Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * |
3 | * Copyright (C) 1991, 1992 Linus Torvalds | |
4 | * | |
5 | * Enhanced CPU detection and feature setting code by Mike Jagdis | |
6 | * and Martin Mares, November 1997. | |
7 | */ | |
8 | ||
9 | .text | |
1da177e4 | 10 | #include <linux/threads.h> |
8b2f7fff | 11 | #include <linux/init.h> |
1da177e4 LT |
12 | #include <linux/linkage.h> |
13 | #include <asm/segment.h> | |
0341c14d JF |
14 | #include <asm/page_types.h> |
15 | #include <asm/pgtable_types.h> | |
1da177e4 LT |
16 | #include <asm/cache.h> |
17 | #include <asm/thread_info.h> | |
86feeaa8 | 18 | #include <asm/asm-offsets.h> |
1da177e4 | 19 | #include <asm/setup.h> |
551889a6 | 20 | #include <asm/processor-flags.h> |
8a50e513 PA |
21 | #include <asm/msr-index.h> |
22 | #include <asm/cpufeature.h> | |
60a5317f | 23 | #include <asm/percpu.h> |
551889a6 IC |
24 | |
25 | /* Physical address */ | |
26 | #define pa(X) ((X) - __PAGE_OFFSET) | |
1da177e4 LT |
27 | |
28 | /* | |
29 | * References to members of the new_cpu_data structure. | |
30 | */ | |
31 | ||
32 | #define X86 new_cpu_data+CPUINFO_x86 | |
33 | #define X86_VENDOR new_cpu_data+CPUINFO_x86_vendor | |
34 | #define X86_MODEL new_cpu_data+CPUINFO_x86_model | |
35 | #define X86_MASK new_cpu_data+CPUINFO_x86_mask | |
36 | #define X86_HARD_MATH new_cpu_data+CPUINFO_hard_math | |
37 | #define X86_CPUID new_cpu_data+CPUINFO_cpuid_level | |
38 | #define X86_CAPABILITY new_cpu_data+CPUINFO_x86_capability | |
39 | #define X86_VENDOR_ID new_cpu_data+CPUINFO_x86_vendor_id | |
40 | ||
41 | /* | |
c090f532 JF |
42 | * This is how much memory in addition to the memory covered up to |
43 | * and including _end we need mapped initially. | |
9ce8c2ed | 44 | * We need: |
2bd2753f YL |
45 | * (KERNEL_IMAGE_SIZE/4096) / 1024 pages (worst case, non PAE) |
46 | * (KERNEL_IMAGE_SIZE/4096) / 512 + 4 pages (worst case for PAE) | |
1da177e4 LT |
47 | * |
48 | * Modulo rounding, each megabyte assigned here requires a kilobyte of | |
49 | * memory, which is currently unreclaimed. | |
50 | * | |
51 | * This should be a multiple of a page. | |
2bd2753f YL |
52 | * |
53 | * KERNEL_IMAGE_SIZE should be greater than pa(_end) | |
54 | * and small than max_low_pfn, otherwise will waste some page table entries | |
1da177e4 | 55 | */ |
1da177e4 | 56 | |
9ce8c2ed | 57 | #if PTRS_PER_PMD > 1 |
c090f532 | 58 | #define PAGE_TABLE_SIZE(pages) (((pages) / PTRS_PER_PMD) + PTRS_PER_PGD) |
9ce8c2ed | 59 | #else |
c090f532 | 60 | #define PAGE_TABLE_SIZE(pages) ((pages) / PTRS_PER_PGD) |
9ce8c2ed | 61 | #endif |
9ce8c2ed | 62 | |
147dd561 PA |
63 | /* Number of possible pages in the lowmem region */ |
64 | LOWMEM_PAGES = (((1<<32) - __PAGE_OFFSET) >> PAGE_SHIFT) | |
65 | ||
c090f532 | 66 | /* Enough space to fit pagetables for the low memory linear map */ |
147dd561 | 67 | MAPPING_BEYOND_END = PAGE_TABLE_SIZE(LOWMEM_PAGES) << PAGE_SHIFT |
c090f532 JF |
68 | |
69 | /* | |
70 | * Worst-case size of the kernel mapping we need to make: | |
147dd561 PA |
71 | * a relocatable kernel can live anywhere in lowmem, so we need to be able |
72 | * to map all of lowmem. | |
c090f532 | 73 | */ |
147dd561 | 74 | KERNEL_PAGES = LOWMEM_PAGES |
c090f532 | 75 | |
b8a22a62 | 76 | INIT_MAP_SIZE = PAGE_TABLE_SIZE(KERNEL_PAGES) * PAGE_SIZE_asm |
2bd2753f | 77 | RESERVE_BRK(pagetables, INIT_MAP_SIZE) |
796216a5 | 78 | |
1da177e4 LT |
79 | /* |
80 | * 32-bit kernel entrypoint; only used by the boot CPU. On entry, | |
81 | * %esi points to the real-mode code as a 32-bit pointer. | |
82 | * CS and DS must be 4 GB flat segments, but we don't depend on | |
83 | * any particular GDT layout, because we load our own as soon as we | |
84 | * can. | |
85 | */ | |
4ae59b91 | 86 | __HEAD |
1da177e4 | 87 | ENTRY(startup_32) |
a24e7851 RR |
88 | /* test KEEP_SEGMENTS flag to see if the bootloader is asking |
89 | us to not reload segments */ | |
90 | testb $(1<<6), BP_loadflags(%esi) | |
91 | jnz 2f | |
1da177e4 LT |
92 | |
93 | /* | |
94 | * Set segments to known values. | |
95 | */ | |
551889a6 | 96 | lgdt pa(boot_gdt_descr) |
1da177e4 LT |
97 | movl $(__BOOT_DS),%eax |
98 | movl %eax,%ds | |
99 | movl %eax,%es | |
100 | movl %eax,%fs | |
101 | movl %eax,%gs | |
a24e7851 | 102 | 2: |
1da177e4 LT |
103 | |
104 | /* | |
105 | * Clear BSS first so that there are no surprises... | |
1da177e4 | 106 | */ |
a24e7851 | 107 | cld |
1da177e4 | 108 | xorl %eax,%eax |
551889a6 IC |
109 | movl $pa(__bss_start),%edi |
110 | movl $pa(__bss_stop),%ecx | |
1da177e4 LT |
111 | subl %edi,%ecx |
112 | shrl $2,%ecx | |
113 | rep ; stosl | |
484b90c4 VG |
114 | /* |
115 | * Copy bootup parameters out of the way. | |
116 | * Note: %esi still has the pointer to the real-mode data. | |
117 | * With the kexec as boot loader, parameter segment might be loaded beyond | |
118 | * kernel image and might not even be addressable by early boot page tables. | |
119 | * (kexec on panic case). Hence copy out the parameters before initializing | |
120 | * page tables. | |
121 | */ | |
551889a6 | 122 | movl $pa(boot_params),%edi |
484b90c4 VG |
123 | movl $(PARAM_SIZE/4),%ecx |
124 | cld | |
125 | rep | |
126 | movsl | |
551889a6 | 127 | movl pa(boot_params) + NEW_CL_POINTER,%esi |
484b90c4 | 128 | andl %esi,%esi |
fa76dab9 | 129 | jz 1f # No comand line |
551889a6 | 130 | movl $pa(boot_command_line),%edi |
484b90c4 VG |
131 | movl $(COMMAND_LINE_SIZE/4),%ecx |
132 | rep | |
133 | movsl | |
134 | 1: | |
1da177e4 | 135 | |
fd699c76 AS |
136 | #ifdef CONFIG_OLPC_OPENFIRMWARE |
137 | /* save OFW's pgdir table for later use when calling into OFW */ | |
138 | movl %cr3, %eax | |
139 | movl %eax, pa(olpc_ofw_pgd) | |
140 | #endif | |
141 | ||
1da177e4 LT |
142 | /* |
143 | * Initialize page tables. This creates a PDE and a set of page | |
2bd2753f | 144 | * tables, which are located immediately beyond __brk_base. The variable |
ccf3fe02 | 145 | * _brk_end is set up to point to the first "safe" location. |
1da177e4 | 146 | * Mappings are created both at virtual address 0 (identity mapping) |
2bd2753f | 147 | * and PAGE_OFFSET for up to _end. |
1da177e4 | 148 | * |
551889a6 | 149 | * Note that the stack is not yet set up! |
1da177e4 | 150 | */ |
551889a6 IC |
151 | #ifdef CONFIG_X86_PAE |
152 | ||
153 | /* | |
b40827fa BP |
154 | * In PAE mode initial_page_table is statically defined to contain |
155 | * enough entries to cover the VMSPLIT option (that is the top 1, 2 or 3 | |
156 | * entries). The identity mapping is handled by pointing two PGD entries | |
157 | * to the first kernel PMD. | |
551889a6 | 158 | * |
b40827fa | 159 | * Note the upper half of each PMD or PTE are always zero at this stage. |
551889a6 IC |
160 | */ |
161 | ||
86b2b70e | 162 | #define KPMDS (((-__PAGE_OFFSET) >> 30) & 3) /* Number of kernel PMDs */ |
551889a6 IC |
163 | |
164 | xorl %ebx,%ebx /* %ebx is kept at zero */ | |
165 | ||
ccf3fe02 | 166 | movl $pa(__brk_base), %edi |
b40827fa | 167 | movl $pa(initial_pg_pmd), %edx |
b2bc2731 | 168 | movl $PTE_IDENT_ATTR, %eax |
551889a6 | 169 | 10: |
b2bc2731 | 170 | leal PDE_IDENT_ATTR(%edi),%ecx /* Create PMD entry */ |
551889a6 IC |
171 | movl %ecx,(%edx) /* Store PMD entry */ |
172 | /* Upper half already zero */ | |
173 | addl $8,%edx | |
174 | movl $512,%ecx | |
175 | 11: | |
176 | stosl | |
177 | xchgl %eax,%ebx | |
178 | stosl | |
179 | xchgl %eax,%ebx | |
180 | addl $0x1000,%eax | |
181 | loop 11b | |
182 | ||
183 | /* | |
c090f532 | 184 | * End condition: we must map up to the end + MAPPING_BEYOND_END. |
551889a6 | 185 | */ |
c090f532 | 186 | movl $pa(_end) + MAPPING_BEYOND_END + PTE_IDENT_ATTR, %ebp |
551889a6 IC |
187 | cmpl %ebp,%eax |
188 | jb 10b | |
189 | 1: | |
ccf3fe02 JF |
190 | addl $__PAGE_OFFSET, %edi |
191 | movl %edi, pa(_brk_end) | |
6af61a76 YL |
192 | shrl $12, %eax |
193 | movl %eax, pa(max_pfn_mapped) | |
551889a6 IC |
194 | |
195 | /* Do early initialization of the fixmap area */ | |
b40827fa BP |
196 | movl $pa(initial_pg_fixmap)+PDE_IDENT_ATTR,%eax |
197 | movl %eax,pa(initial_pg_pmd+0x1000*KPMDS-8) | |
551889a6 IC |
198 | #else /* Not PAE */ |
199 | ||
200 | page_pde_offset = (__PAGE_OFFSET >> 20); | |
201 | ||
ccf3fe02 | 202 | movl $pa(__brk_base), %edi |
b40827fa | 203 | movl $pa(initial_page_table), %edx |
b2bc2731 | 204 | movl $PTE_IDENT_ATTR, %eax |
1da177e4 | 205 | 10: |
b2bc2731 | 206 | leal PDE_IDENT_ATTR(%edi),%ecx /* Create PDE entry */ |
1da177e4 LT |
207 | movl %ecx,(%edx) /* Store identity PDE entry */ |
208 | movl %ecx,page_pde_offset(%edx) /* Store kernel PDE entry */ | |
209 | addl $4,%edx | |
210 | movl $1024, %ecx | |
211 | 11: | |
212 | stosl | |
213 | addl $0x1000,%eax | |
214 | loop 11b | |
551889a6 | 215 | /* |
c090f532 | 216 | * End condition: we must map up to the end + MAPPING_BEYOND_END. |
551889a6 | 217 | */ |
c090f532 | 218 | movl $pa(_end) + MAPPING_BEYOND_END + PTE_IDENT_ATTR, %ebp |
1da177e4 LT |
219 | cmpl %ebp,%eax |
220 | jb 10b | |
ccf3fe02 JF |
221 | addl $__PAGE_OFFSET, %edi |
222 | movl %edi, pa(_brk_end) | |
6af61a76 YL |
223 | shrl $12, %eax |
224 | movl %eax, pa(max_pfn_mapped) | |
17d57a92 | 225 | |
551889a6 | 226 | /* Do early initialization of the fixmap area */ |
b40827fa BP |
227 | movl $pa(initial_pg_fixmap)+PDE_IDENT_ATTR,%eax |
228 | movl %eax,pa(initial_page_table+0xffc) | |
551889a6 | 229 | #endif |
d50d8fe1 RR |
230 | |
231 | #ifdef CONFIG_PARAVIRT | |
232 | /* This is can only trip for a broken bootloader... */ | |
233 | cmpw $0x207, pa(boot_params + BP_version) | |
234 | jb default_entry | |
235 | ||
236 | /* Paravirt-compatible boot parameters. Look to see what architecture | |
237 | we're booting under. */ | |
238 | movl pa(boot_params + BP_hardware_subarch), %eax | |
239 | cmpl $num_subarch_entries, %eax | |
240 | jae bad_subarch | |
241 | ||
242 | movl pa(subarch_entries)(,%eax,4), %eax | |
243 | subl $__PAGE_OFFSET, %eax | |
244 | jmp *%eax | |
245 | ||
246 | bad_subarch: | |
247 | WEAK(lguest_entry) | |
248 | WEAK(xen_entry) | |
249 | /* Unknown implementation; there's really | |
250 | nothing we can do at this point. */ | |
251 | ud2a | |
252 | ||
253 | __INITDATA | |
254 | ||
255 | subarch_entries: | |
256 | .long default_entry /* normal x86/PC */ | |
257 | .long lguest_entry /* lguest hypervisor */ | |
258 | .long xen_entry /* Xen hypervisor */ | |
259 | .long default_entry /* Moorestown MID */ | |
260 | num_subarch_entries = (. - subarch_entries) / 4 | |
261 | .previous | |
262 | #else | |
263 | jmp default_entry | |
264 | #endif /* CONFIG_PARAVIRT */ | |
265 | ||
1da177e4 LT |
266 | /* |
267 | * Non-boot CPU entry point; entered from trampoline.S | |
268 | * We can't lgdt here, because lgdt itself uses a data segment, but | |
52de74dd | 269 | * we know the trampoline has already loaded the boot_gdt for us. |
f8657e1b VG |
270 | * |
271 | * If cpu hotplug is not supported then this code can go in init section | |
272 | * which will be freed later | |
1da177e4 | 273 | */ |
f8657e1b | 274 | |
78b89ecd | 275 | __CPUINIT |
f8657e1b VG |
276 | |
277 | #ifdef CONFIG_SMP | |
1da177e4 LT |
278 | ENTRY(startup_32_smp) |
279 | cld | |
280 | movl $(__BOOT_DS),%eax | |
281 | movl %eax,%ds | |
282 | movl %eax,%es | |
283 | movl %eax,%fs | |
284 | movl %eax,%gs | |
5756dd59 | 285 | #endif /* CONFIG_SMP */ |
d50d8fe1 | 286 | default_entry: |
1da177e4 LT |
287 | |
288 | /* | |
289 | * New page tables may be in 4Mbyte page mode and may | |
290 | * be using the global pages. | |
291 | * | |
292 | * NOTE! If we are on a 486 we may have no cr4 at all! | |
293 | * So we do not try to touch it unless we really have | |
294 | * some bits in it to set. This won't work if the BSP | |
295 | * implements cr4 but this AP does not -- very unlikely | |
296 | * but be warned! The same applies to the pse feature | |
297 | * if not equally supported. --macro | |
298 | * | |
299 | * NOTE! We have to correct for the fact that we're | |
300 | * not yet offset PAGE_OFFSET.. | |
301 | */ | |
551889a6 | 302 | #define cr4_bits pa(mmu_cr4_features) |
1da177e4 LT |
303 | movl cr4_bits,%edx |
304 | andl %edx,%edx | |
305 | jz 6f | |
306 | movl %cr4,%eax # Turn on paging options (PSE,PAE,..) | |
307 | orl %edx,%eax | |
308 | movl %eax,%cr4 | |
309 | ||
8a50e513 PA |
310 | testb $X86_CR4_PAE, %al # check if PAE is enabled |
311 | jz 6f | |
1da177e4 LT |
312 | |
313 | /* Check if extended functions are implemented */ | |
314 | movl $0x80000000, %eax | |
315 | cpuid | |
8a50e513 PA |
316 | /* Value must be in the range 0x80000001 to 0x8000ffff */ |
317 | subl $0x80000001, %eax | |
318 | cmpl $(0x8000ffff-0x80000001), %eax | |
319 | ja 6f | |
1da177e4 LT |
320 | mov $0x80000001, %eax |
321 | cpuid | |
322 | /* Execute Disable bit supported? */ | |
8a50e513 | 323 | btl $(X86_FEATURE_NX & 31), %edx |
1da177e4 LT |
324 | jnc 6f |
325 | ||
326 | /* Setup EFER (Extended Feature Enable Register) */ | |
8a50e513 | 327 | movl $MSR_EFER, %ecx |
1da177e4 LT |
328 | rdmsr |
329 | ||
8a50e513 | 330 | btsl $_EFER_NX, %eax |
1da177e4 LT |
331 | /* Make changes effective */ |
332 | wrmsr | |
333 | ||
334 | 6: | |
1da177e4 LT |
335 | |
336 | /* | |
337 | * Enable paging | |
338 | */ | |
b40827fa | 339 | movl $pa(initial_page_table), %eax |
1da177e4 LT |
340 | movl %eax,%cr3 /* set the page table pointer.. */ |
341 | movl %cr0,%eax | |
551889a6 | 342 | orl $X86_CR0_PG,%eax |
1da177e4 LT |
343 | movl %eax,%cr0 /* ..and set paging (PG) bit */ |
344 | ljmp $__BOOT_CS,$1f /* Clear prefetch and normalize %eip */ | |
345 | 1: | |
346 | /* Set up the stack pointer */ | |
347 | lss stack_start,%esp | |
348 | ||
349 | /* | |
350 | * Initialize eflags. Some BIOS's leave bits like NT set. This would | |
351 | * confuse the debugger if this code is traced. | |
352 | * XXX - best to initialize before switching to protected mode. | |
353 | */ | |
354 | pushl $0 | |
355 | popfl | |
356 | ||
357 | #ifdef CONFIG_SMP | |
50359501 | 358 | cmpb $0, ready |
1da177e4 LT |
359 | jz 1f /* Initial CPU cleans BSS */ |
360 | jmp checkCPUtype | |
361 | 1: | |
362 | #endif /* CONFIG_SMP */ | |
363 | ||
364 | /* | |
365 | * start system 32-bit setup. We need to re-do some of the things done | |
366 | * in 16-bit mode for the "real" operations. | |
367 | */ | |
368 | call setup_idt | |
369 | ||
1da177e4 LT |
370 | checkCPUtype: |
371 | ||
372 | movl $-1,X86_CPUID # -1 for no CPUID initially | |
373 | ||
374 | /* check if it is 486 or 386. */ | |
375 | /* | |
376 | * XXX - this does a lot of unnecessary setup. Alignment checks don't | |
377 | * apply at our cpl of 0 and the stack ought to be aligned already, and | |
378 | * we don't need to preserve eflags. | |
379 | */ | |
380 | ||
381 | movb $3,X86 # at least 386 | |
382 | pushfl # push EFLAGS | |
383 | popl %eax # get EFLAGS | |
384 | movl %eax,%ecx # save original EFLAGS | |
385 | xorl $0x240000,%eax # flip AC and ID bits in EFLAGS | |
386 | pushl %eax # copy to EFLAGS | |
387 | popfl # set EFLAGS | |
388 | pushfl # get new EFLAGS | |
389 | popl %eax # put it in eax | |
390 | xorl %ecx,%eax # change in flags | |
391 | pushl %ecx # restore original EFLAGS | |
392 | popfl | |
393 | testl $0x40000,%eax # check if AC bit changed | |
394 | je is386 | |
395 | ||
396 | movb $4,X86 # at least 486 | |
397 | testl $0x200000,%eax # check if ID bit changed | |
398 | je is486 | |
399 | ||
400 | /* get vendor info */ | |
401 | xorl %eax,%eax # call CPUID with 0 -> return vendor ID | |
402 | cpuid | |
403 | movl %eax,X86_CPUID # save CPUID level | |
404 | movl %ebx,X86_VENDOR_ID # lo 4 chars | |
405 | movl %edx,X86_VENDOR_ID+4 # next 4 chars | |
406 | movl %ecx,X86_VENDOR_ID+8 # last 4 chars | |
407 | ||
408 | orl %eax,%eax # do we have processor info as well? | |
409 | je is486 | |
410 | ||
411 | movl $1,%eax # Use the CPUID instruction to get CPU type | |
412 | cpuid | |
413 | movb %al,%cl # save reg for future use | |
414 | andb $0x0f,%ah # mask processor family | |
415 | movb %ah,X86 | |
416 | andb $0xf0,%al # mask model | |
417 | shrb $4,%al | |
418 | movb %al,X86_MODEL | |
419 | andb $0x0f,%cl # mask mask revision | |
420 | movb %cl,X86_MASK | |
421 | movl %edx,X86_CAPABILITY | |
422 | ||
423 | is486: movl $0x50022,%ecx # set AM, WP, NE and MP | |
424 | jmp 2f | |
425 | ||
426 | is386: movl $2,%ecx # set MP | |
427 | 2: movl %cr0,%eax | |
428 | andl $0x80000011,%eax # Save PG,PE,ET | |
429 | orl %ecx,%eax | |
430 | movl %eax,%cr0 | |
431 | ||
432 | call check_x87 | |
2a57ff1a | 433 | lgdt early_gdt_descr |
1da177e4 LT |
434 | lidt idt_descr |
435 | ljmp $(__KERNEL_CS),$1f | |
436 | 1: movl $(__KERNEL_DS),%eax # reload all the segment registers | |
437 | movl %eax,%ss # after changing gdt. | |
438 | ||
439 | movl $(__USER_DS),%eax # DS/ES contains default USER segment | |
440 | movl %eax,%ds | |
441 | movl %eax,%es | |
442 | ||
0dd76d73 BG |
443 | movl $(__KERNEL_PERCPU), %eax |
444 | movl %eax,%fs # set this cpu's percpu | |
445 | ||
60a5317f TH |
446 | #ifdef CONFIG_CC_STACKPROTECTOR |
447 | /* | |
448 | * The linker can't handle this by relocation. Manually set | |
449 | * base address in stack canary segment descriptor. | |
450 | */ | |
451 | cmpb $0,ready | |
452 | jne 1f | |
dd17c8f7 RR |
453 | movl $gdt_page,%eax |
454 | movl $stack_canary,%ecx | |
60a5317f TH |
455 | movw %cx, 8 * GDT_ENTRY_STACK_CANARY + 2(%eax) |
456 | shrl $16, %ecx | |
457 | movb %cl, 8 * GDT_ENTRY_STACK_CANARY + 4(%eax) | |
458 | movb %ch, 8 * GDT_ENTRY_STACK_CANARY + 7(%eax) | |
459 | 1: | |
460 | #endif | |
461 | movl $(__KERNEL_STACK_CANARY),%eax | |
464d1a78 | 462 | movl %eax,%gs |
60a5317f TH |
463 | |
464 | xorl %eax,%eax # Clear LDT | |
1da177e4 | 465 | lldt %ax |
f95d47ca | 466 | |
1da177e4 | 467 | cld # gcc2 wants the direction flag cleared at all times |
26fd5e08 | 468 | pushl $0 # fake return address for unwinder |
1da177e4 | 469 | #ifdef CONFIG_SMP |
d92de65c SL |
470 | movb ready, %cl |
471 | movb $1, ready | |
29fe5f3b | 472 | cmpb $0,%cl # the first CPU calls start_kernel |
7c3576d2 | 473 | je 1f |
3e970473 | 474 | movl (stack_start), %esp |
7c3576d2 | 475 | 1: |
1da177e4 | 476 | #endif /* CONFIG_SMP */ |
e3f77edf | 477 | jmp *(initial_code) |
1da177e4 LT |
478 | |
479 | /* | |
480 | * We depend on ET to be correct. This checks for 287/387. | |
481 | */ | |
482 | check_x87: | |
483 | movb $0,X86_HARD_MATH | |
484 | clts | |
485 | fninit | |
486 | fstsw %ax | |
487 | cmpb $0,%al | |
488 | je 1f | |
489 | movl %cr0,%eax /* no coprocessor: have to set bits */ | |
490 | xorl $4,%eax /* set EM */ | |
491 | movl %eax,%cr0 | |
492 | ret | |
493 | ALIGN | |
494 | 1: movb $1,X86_HARD_MATH | |
495 | .byte 0xDB,0xE4 /* fsetpm for 287, ignored by 387 */ | |
496 | ret | |
497 | ||
498 | /* | |
499 | * setup_idt | |
500 | * | |
501 | * sets up a idt with 256 entries pointing to | |
502 | * ignore_int, interrupt gates. It doesn't actually load | |
503 | * idt - that can be done only after paging has been enabled | |
504 | * and the kernel moved to PAGE_OFFSET. Interrupts | |
505 | * are enabled elsewhere, when we can be relatively | |
506 | * sure everything is ok. | |
507 | * | |
508 | * Warning: %esi is live across this function. | |
509 | */ | |
510 | setup_idt: | |
511 | lea ignore_int,%edx | |
512 | movl $(__KERNEL_CS << 16),%eax | |
513 | movw %dx,%ax /* selector = 0x0010 = cs */ | |
514 | movw $0x8E00,%dx /* interrupt gate - dpl=0, present */ | |
515 | ||
516 | lea idt_table,%edi | |
517 | mov $256,%ecx | |
518 | rp_sidt: | |
519 | movl %eax,(%edi) | |
520 | movl %edx,4(%edi) | |
521 | addl $8,%edi | |
522 | dec %ecx | |
523 | jne rp_sidt | |
ec5c0926 CE |
524 | |
525 | .macro set_early_handler handler,trapno | |
526 | lea \handler,%edx | |
527 | movl $(__KERNEL_CS << 16),%eax | |
528 | movw %dx,%ax | |
529 | movw $0x8E00,%dx /* interrupt gate - dpl=0, present */ | |
530 | lea idt_table,%edi | |
531 | movl %eax,8*\trapno(%edi) | |
532 | movl %edx,8*\trapno+4(%edi) | |
533 | .endm | |
534 | ||
535 | set_early_handler handler=early_divide_err,trapno=0 | |
536 | set_early_handler handler=early_illegal_opcode,trapno=6 | |
537 | set_early_handler handler=early_protection_fault,trapno=13 | |
538 | set_early_handler handler=early_page_fault,trapno=14 | |
539 | ||
1da177e4 LT |
540 | ret |
541 | ||
ec5c0926 CE |
542 | early_divide_err: |
543 | xor %edx,%edx | |
544 | pushl $0 /* fake errcode */ | |
545 | jmp early_fault | |
546 | ||
547 | early_illegal_opcode: | |
548 | movl $6,%edx | |
549 | pushl $0 /* fake errcode */ | |
550 | jmp early_fault | |
551 | ||
552 | early_protection_fault: | |
553 | movl $13,%edx | |
554 | jmp early_fault | |
555 | ||
556 | early_page_fault: | |
557 | movl $14,%edx | |
558 | jmp early_fault | |
559 | ||
560 | early_fault: | |
561 | cld | |
562 | #ifdef CONFIG_PRINTK | |
382f64ab | 563 | pusha |
ec5c0926 CE |
564 | movl $(__KERNEL_DS),%eax |
565 | movl %eax,%ds | |
566 | movl %eax,%es | |
567 | cmpl $2,early_recursion_flag | |
568 | je hlt_loop | |
569 | incl early_recursion_flag | |
570 | movl %cr2,%eax | |
571 | pushl %eax | |
572 | pushl %edx /* trapno */ | |
573 | pushl $fault_msg | |
ec5c0926 | 574 | call printk |
ec5c0926 | 575 | #endif |
94878efd | 576 | call dump_stack |
ec5c0926 CE |
577 | hlt_loop: |
578 | hlt | |
579 | jmp hlt_loop | |
580 | ||
1da177e4 LT |
581 | /* This is the default interrupt "handler" :-) */ |
582 | ALIGN | |
583 | ignore_int: | |
584 | cld | |
d59745ce | 585 | #ifdef CONFIG_PRINTK |
1da177e4 LT |
586 | pushl %eax |
587 | pushl %ecx | |
588 | pushl %edx | |
589 | pushl %es | |
590 | pushl %ds | |
591 | movl $(__KERNEL_DS),%eax | |
592 | movl %eax,%ds | |
593 | movl %eax,%es | |
ec5c0926 CE |
594 | cmpl $2,early_recursion_flag |
595 | je hlt_loop | |
596 | incl early_recursion_flag | |
1da177e4 LT |
597 | pushl 16(%esp) |
598 | pushl 24(%esp) | |
599 | pushl 32(%esp) | |
600 | pushl 40(%esp) | |
601 | pushl $int_msg | |
602 | call printk | |
d5e397cb IM |
603 | |
604 | call dump_stack | |
605 | ||
1da177e4 LT |
606 | addl $(5*4),%esp |
607 | popl %ds | |
608 | popl %es | |
609 | popl %edx | |
610 | popl %ecx | |
611 | popl %eax | |
d59745ce | 612 | #endif |
1da177e4 LT |
613 | iret |
614 | ||
0e83815b | 615 | __REFDATA |
583323b9 TG |
616 | .align 4 |
617 | ENTRY(initial_code) | |
618 | .long i386_start_kernel | |
619 | ||
1da177e4 LT |
620 | /* |
621 | * BSS section | |
622 | */ | |
02b7da37 | 623 | __PAGE_ALIGNED_BSS |
5ead97c8 | 624 | .align PAGE_SIZE_asm |
551889a6 | 625 | #ifdef CONFIG_X86_PAE |
d50d8fe1 | 626 | initial_pg_pmd: |
551889a6 IC |
627 | .fill 1024*KPMDS,4,0 |
628 | #else | |
b40827fa | 629 | ENTRY(initial_page_table) |
1da177e4 | 630 | .fill 1024,4,0 |
551889a6 | 631 | #endif |
d50d8fe1 | 632 | initial_pg_fixmap: |
b1c931e3 | 633 | .fill 1024,4,0 |
1da177e4 LT |
634 | ENTRY(empty_zero_page) |
635 | .fill 4096,1,0 | |
b40827fa BP |
636 | ENTRY(swapper_pg_dir) |
637 | .fill 1024,4,0 | |
2bd2753f | 638 | |
1da177e4 LT |
639 | /* |
640 | * This starts the data section. | |
641 | */ | |
551889a6 | 642 | #ifdef CONFIG_X86_PAE |
abe1ee3a | 643 | __PAGE_ALIGNED_DATA |
551889a6 IC |
644 | /* Page-aligned for the benefit of paravirt? */ |
645 | .align PAGE_SIZE_asm | |
b40827fa BP |
646 | ENTRY(initial_page_table) |
647 | .long pa(initial_pg_pmd+PGD_IDENT_ATTR),0 /* low identity map */ | |
551889a6 | 648 | # if KPMDS == 3 |
b40827fa BP |
649 | .long pa(initial_pg_pmd+PGD_IDENT_ATTR),0 |
650 | .long pa(initial_pg_pmd+PGD_IDENT_ATTR+0x1000),0 | |
651 | .long pa(initial_pg_pmd+PGD_IDENT_ATTR+0x2000),0 | |
551889a6 IC |
652 | # elif KPMDS == 2 |
653 | .long 0,0 | |
b40827fa BP |
654 | .long pa(initial_pg_pmd+PGD_IDENT_ATTR),0 |
655 | .long pa(initial_pg_pmd+PGD_IDENT_ATTR+0x1000),0 | |
551889a6 IC |
656 | # elif KPMDS == 1 |
657 | .long 0,0 | |
658 | .long 0,0 | |
b40827fa | 659 | .long pa(initial_pg_pmd+PGD_IDENT_ATTR),0 |
551889a6 IC |
660 | # else |
661 | # error "Kernel PMDs should be 1, 2 or 3" | |
662 | # endif | |
663 | .align PAGE_SIZE_asm /* needs to be page-sized too */ | |
664 | #endif | |
665 | ||
1da177e4 | 666 | .data |
1da177e4 LT |
667 | ENTRY(stack_start) |
668 | .long init_thread_union+THREAD_SIZE | |
669 | .long __BOOT_DS | |
670 | ||
671 | ready: .byte 0 | |
672 | ||
ec5c0926 CE |
673 | early_recursion_flag: |
674 | .long 0 | |
675 | ||
1da177e4 | 676 | int_msg: |
d5e397cb | 677 | .asciz "Unknown interrupt or fault at: %p %p %p\n" |
1da177e4 | 678 | |
ec5c0926 | 679 | fault_msg: |
575ca735 VN |
680 | /* fault info: */ |
681 | .ascii "BUG: Int %d: CR2 %p\n" | |
682 | /* pusha regs: */ | |
683 | .ascii " EDI %p ESI %p EBP %p ESP %p\n" | |
684 | .ascii " EBX %p EDX %p ECX %p EAX %p\n" | |
685 | /* fault frame: */ | |
686 | .ascii " err %p EIP %p CS %p flg %p\n" | |
687 | .ascii "Stack: %p %p %p %p %p %p %p %p\n" | |
688 | .ascii " %p %p %p %p %p %p %p %p\n" | |
689 | .asciz " %p %p %p %p %p %p %p %p\n" | |
ec5c0926 | 690 | |
9702785a | 691 | #include "../../x86/xen/xen-head.S" |
5ead97c8 | 692 | |
1da177e4 LT |
693 | /* |
694 | * The IDT and GDT 'descriptors' are a strange 48-bit object | |
695 | * only used by the lidt and lgdt instructions. They are not | |
696 | * like usual segment descriptors - they consist of a 16-bit | |
697 | * segment size, and 32-bit linear address value: | |
698 | */ | |
699 | ||
700 | .globl boot_gdt_descr | |
701 | .globl idt_descr | |
1da177e4 LT |
702 | |
703 | ALIGN | |
704 | # early boot GDT descriptor (must use 1:1 address mapping) | |
705 | .word 0 # 32 bit align gdt_desc.address | |
706 | boot_gdt_descr: | |
707 | .word __BOOT_DS+7 | |
52de74dd | 708 | .long boot_gdt - __PAGE_OFFSET |
1da177e4 LT |
709 | |
710 | .word 0 # 32-bit align idt_desc.address | |
711 | idt_descr: | |
712 | .word IDT_ENTRIES*8-1 # idt contains 256 entries | |
713 | .long idt_table | |
714 | ||
715 | # boot GDT descriptor (later on used by CPU#0): | |
716 | .word 0 # 32 bit align gdt_desc.address | |
2a57ff1a | 717 | ENTRY(early_gdt_descr) |
1da177e4 | 718 | .word GDT_ENTRIES*8-1 |
dd17c8f7 | 719 | .long gdt_page /* Overwritten for secondary CPUs */ |
1da177e4 | 720 | |
1da177e4 | 721 | /* |
52de74dd | 722 | * The boot_gdt must mirror the equivalent in setup.S and is |
1da177e4 LT |
723 | * used only for booting. |
724 | */ | |
725 | .align L1_CACHE_BYTES | |
52de74dd | 726 | ENTRY(boot_gdt) |
1da177e4 LT |
727 | .fill GDT_ENTRY_BOOT_CS,8,0 |
728 | .quad 0x00cf9a000000ffff /* kernel 4GB code at 0x00000000 */ | |
729 | .quad 0x00cf92000000ffff /* kernel 4GB data at 0x00000000 */ |