Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
5b171e82 | 2 | * linux/arch/x86/kernel/head_64.S -- start in 32bit and switch to 64bit |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE | |
5 | * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> | |
6 | * Copyright (C) 2000 Karsten Keil <kkeil@suse.de> | |
7 | * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de> | |
1ab60e0f | 8 | * Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com> |
1da177e4 LT |
9 | */ |
10 | ||
11 | ||
12 | #include <linux/linkage.h> | |
13 | #include <linux/threads.h> | |
f6c2e333 | 14 | #include <linux/init.h> |
1da177e4 | 15 | #include <asm/segment.h> |
67dcbb6b | 16 | #include <asm/pgtable.h> |
1da177e4 LT |
17 | #include <asm/page.h> |
18 | #include <asm/msr.h> | |
19 | #include <asm/cache.h> | |
369101da | 20 | #include <asm/processor-flags.h> |
b12d8db8 | 21 | #include <asm/percpu.h> |
9900aa2f | 22 | #include <asm/nops.h> |
1ab60e0f | 23 | |
49a69787 GOC |
24 | #ifdef CONFIG_PARAVIRT |
25 | #include <asm/asm-offsets.h> | |
26 | #include <asm/paravirt.h> | |
ffc4bc9c | 27 | #define GET_CR2_INTO(reg) GET_CR2_INTO_RAX ; movq %rax, reg |
49a69787 | 28 | #else |
ffc4bc9c | 29 | #define GET_CR2_INTO(reg) movq %cr2, reg |
9900aa2f | 30 | #define INTERRUPT_RETURN iretq |
49a69787 GOC |
31 | #endif |
32 | ||
3ad2f3fb | 33 | /* we are not able to switch in one step to the final KERNEL ADDRESS SPACE |
1ab60e0f VG |
34 | * because we need identity-mapped pages. |
35 | * | |
1da177e4 LT |
36 | */ |
37 | ||
a6523748 EH |
38 | #define pud_index(x) (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) |
39 | ||
40 | L4_PAGE_OFFSET = pgd_index(__PAGE_OFFSET) | |
a6523748 EH |
41 | L4_START_KERNEL = pgd_index(__START_KERNEL_map) |
42 | L3_START_KERNEL = pud_index(__START_KERNEL_map) | |
43 | ||
1da177e4 | 44 | .text |
4ae59b91 | 45 | __HEAD |
1ab60e0f VG |
46 | .code64 |
47 | .globl startup_64 | |
48 | startup_64: | |
1da177e4 | 49 | /* |
1256276c | 50 | * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0, |
1ab60e0f VG |
51 | * and someone has loaded an identity mapped page table |
52 | * for us. These identity mapped page tables map all of the | |
53 | * kernel pages and possibly all of memory. | |
54 | * | |
8170e6be | 55 | * %rsi holds a physical pointer to real_mode_data. |
1ab60e0f VG |
56 | * |
57 | * We come here either directly from a 64bit bootloader, or from | |
5b171e82 | 58 | * arch/x86/boot/compressed/head_64.S. |
1ab60e0f VG |
59 | * |
60 | * We only come here initially at boot nothing else comes here. | |
61 | * | |
62 | * Since we may be loaded at an address different from what we were | |
63 | * compiled to run at we first fixup the physical addresses in our page | |
64 | * tables and then reload them. | |
1da177e4 LT |
65 | */ |
66 | ||
04633df0 BP |
67 | /* Sanitize CPU configuration */ |
68 | call verify_cpu | |
69 | ||
8170e6be PA |
70 | /* |
71 | * Compute the delta between the address I am compiled to run at and the | |
1ab60e0f | 72 | * address I am actually running at. |
1da177e4 | 73 | */ |
1ab60e0f VG |
74 | leaq _text(%rip), %rbp |
75 | subq $_text - __START_KERNEL_map, %rbp | |
76 | ||
77 | /* Is the address not 2M aligned? */ | |
a4733143 | 78 | testl $~PMD_PAGE_MASK, %ebp |
1ab60e0f VG |
79 | jnz bad_address |
80 | ||
8170e6be PA |
81 | /* |
82 | * Is the address too large? | |
1da177e4 | 83 | */ |
8170e6be PA |
84 | leaq _text(%rip), %rax |
85 | shrq $MAX_PHYSMEM_BITS, %rax | |
86 | jnz bad_address | |
1ab60e0f | 87 | |
8170e6be PA |
88 | /* |
89 | * Fixup the physical addresses in the page table | |
90 | */ | |
91 | addq %rbp, early_level4_pgt + (L4_START_KERNEL*8)(%rip) | |
b1c931e3 | 92 | |
1ab60e0f | 93 | addq %rbp, level3_kernel_pgt + (510*8)(%rip) |
b1c931e3 EB |
94 | addq %rbp, level3_kernel_pgt + (511*8)(%rip) |
95 | ||
96 | addq %rbp, level2_fixmap_pgt + (506*8)(%rip) | |
1ab60e0f | 97 | |
8170e6be PA |
98 | /* |
99 | * Set up the identity mapping for the switchover. These | |
100 | * entries should *NOT* have the global bit set! This also | |
101 | * creates a bunch of nonsense entries but that is fine -- | |
102 | * it avoids problems around wraparound. | |
103 | */ | |
1ab60e0f | 104 | leaq _text(%rip), %rdi |
8170e6be | 105 | leaq early_level4_pgt(%rip), %rbx |
1ab60e0f VG |
106 | |
107 | movq %rdi, %rax | |
8170e6be | 108 | shrq $PGDIR_SHIFT, %rax |
1ab60e0f | 109 | |
8170e6be PA |
110 | leaq (4096 + _KERNPG_TABLE)(%rbx), %rdx |
111 | movq %rdx, 0(%rbx,%rax,8) | |
112 | movq %rdx, 8(%rbx,%rax,8) | |
1ab60e0f | 113 | |
8170e6be | 114 | addq $4096, %rdx |
1ab60e0f | 115 | movq %rdi, %rax |
8170e6be PA |
116 | shrq $PUD_SHIFT, %rax |
117 | andl $(PTRS_PER_PUD-1), %eax | |
e9d0626e ZY |
118 | movq %rdx, 4096(%rbx,%rax,8) |
119 | incl %eax | |
120 | andl $(PTRS_PER_PUD-1), %eax | |
121 | movq %rdx, 4096(%rbx,%rax,8) | |
8170e6be PA |
122 | |
123 | addq $8192, %rbx | |
124 | movq %rdi, %rax | |
125 | shrq $PMD_SHIFT, %rdi | |
126 | addq $(__PAGE_KERNEL_LARGE_EXEC & ~_PAGE_GLOBAL), %rax | |
127 | leaq (_end - 1)(%rip), %rcx | |
128 | shrq $PMD_SHIFT, %rcx | |
129 | subq %rdi, %rcx | |
130 | incl %ecx | |
131 | ||
132 | 1: | |
133 | andq $(PTRS_PER_PMD - 1), %rdi | |
134 | movq %rax, (%rbx,%rdi,8) | |
135 | incq %rdi | |
136 | addq $PMD_SIZE, %rax | |
137 | decl %ecx | |
138 | jnz 1b | |
1ab60e0f | 139 | |
31eedd82 TG |
140 | /* |
141 | * Fixup the kernel text+data virtual addresses. Note that | |
142 | * we might write invalid pmds, when the kernel is relocated | |
143 | * cleanup_highmap() fixes this up along with the mappings | |
144 | * beyond _end. | |
1ab60e0f VG |
145 | */ |
146 | leaq level2_kernel_pgt(%rip), %rdi | |
147 | leaq 4096(%rdi), %r8 | |
148 | /* See if it is a valid page table entry */ | |
3e1aa7cb | 149 | 1: testb $1, 0(%rdi) |
1ab60e0f VG |
150 | jz 2f |
151 | addq %rbp, 0(%rdi) | |
152 | /* Go to the next page */ | |
153 | 2: addq $8, %rdi | |
154 | cmp %r8, %rdi | |
155 | jne 1b | |
156 | ||
157 | /* Fixup phys_base */ | |
158 | addq %rbp, phys_base(%rip) | |
1da177e4 | 159 | |
8170e6be PA |
160 | movq $(early_level4_pgt - __START_KERNEL_map), %rax |
161 | jmp 1f | |
90b1c208 | 162 | ENTRY(secondary_startup_64) |
1ab60e0f | 163 | /* |
1256276c | 164 | * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0, |
1ab60e0f VG |
165 | * and someone has loaded a mapped page table. |
166 | * | |
8170e6be | 167 | * %rsi holds a physical pointer to real_mode_data. |
1ab60e0f VG |
168 | * |
169 | * We come here either from startup_64 (using physical addresses) | |
170 | * or from trampoline.S (using virtual addresses). | |
171 | * | |
172 | * Using virtual addresses from trampoline.S removes the need | |
173 | * to have any identity mapped pages in the kernel page table | |
174 | * after the boot processor executes this code. | |
1da177e4 LT |
175 | */ |
176 | ||
04633df0 BP |
177 | /* Sanitize CPU configuration */ |
178 | call verify_cpu | |
179 | ||
8170e6be PA |
180 | movq $(init_level4_pgt - __START_KERNEL_map), %rax |
181 | 1: | |
182 | ||
1da177e4 | 183 | /* Enable PAE mode and PGE */ |
8170e6be PA |
184 | movl $(X86_CR4_PAE | X86_CR4_PGE), %ecx |
185 | movq %rcx, %cr4 | |
1da177e4 LT |
186 | |
187 | /* Setup early boot stage 4 level pagetables. */ | |
1ab60e0f | 188 | addq phys_base(%rip), %rax |
1da177e4 LT |
189 | movq %rax, %cr3 |
190 | ||
1ab60e0f VG |
191 | /* Ensure I am executing from virtual addresses */ |
192 | movq $1f, %rax | |
193 | jmp *%rax | |
194 | 1: | |
195 | ||
1da177e4 LT |
196 | /* Check if nx is implemented */ |
197 | movl $0x80000001, %eax | |
198 | cpuid | |
199 | movl %edx,%edi | |
200 | ||
201 | /* Setup EFER (Extended Feature Enable Register) */ | |
202 | movl $MSR_EFER, %ecx | |
203 | rdmsr | |
1ab60e0f VG |
204 | btsl $_EFER_SCE, %eax /* Enable System Call */ |
205 | btl $20,%edi /* No Execute supported? */ | |
1da177e4 LT |
206 | jnc 1f |
207 | btsl $_EFER_NX, %eax | |
78d77df7 | 208 | btsq $_PAGE_BIT_NX,early_pmd_flags(%rip) |
1ab60e0f | 209 | 1: wrmsr /* Make changes effective */ |
1da177e4 LT |
210 | |
211 | /* Setup cr0 */ | |
369101da CG |
212 | #define CR0_STATE (X86_CR0_PE | X86_CR0_MP | X86_CR0_ET | \ |
213 | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM | \ | |
214 | X86_CR0_PG) | |
215 | movl $CR0_STATE, %eax | |
1da177e4 LT |
216 | /* Make changes effective */ |
217 | movq %rax, %cr0 | |
218 | ||
219 | /* Setup a boot time stack */ | |
8170e6be | 220 | movq stack_start(%rip), %rsp |
1da177e4 LT |
221 | |
222 | /* zero EFLAGS after setting rsp */ | |
223 | pushq $0 | |
224 | popfq | |
225 | ||
226 | /* | |
227 | * We must switch to a new descriptor in kernel space for the GDT | |
228 | * because soon the kernel won't have access anymore to the userspace | |
229 | * addresses where we're currently running on. We have to do that here | |
230 | * because in 32bit we couldn't load a 64bit linear address. | |
231 | */ | |
a939098a | 232 | lgdt early_gdt_descr(%rip) |
1da177e4 | 233 | |
8ec6993d BG |
234 | /* set up data segments */ |
235 | xorl %eax,%eax | |
ffb60175 ZA |
236 | movl %eax,%ds |
237 | movl %eax,%ss | |
238 | movl %eax,%es | |
239 | ||
240 | /* | |
241 | * We don't really need to load %fs or %gs, but load them anyway | |
242 | * to kill any stale realmode selectors. This allows execution | |
243 | * under VT hardware. | |
244 | */ | |
245 | movl %eax,%fs | |
246 | movl %eax,%gs | |
247 | ||
f32ff538 TH |
248 | /* Set up %gs. |
249 | * | |
947e76cd BG |
250 | * The base of %gs always points to the bottom of the irqstack |
251 | * union. If the stack protector canary is enabled, it is | |
252 | * located at %gs:40. Note that, on SMP, the boot cpu uses | |
253 | * init data section till per cpu areas are set up. | |
f32ff538 | 254 | */ |
1da177e4 | 255 | movl $MSR_GS_BASE,%ecx |
650fb439 BG |
256 | movl initial_gs(%rip),%eax |
257 | movl initial_gs+4(%rip),%edx | |
1da177e4 LT |
258 | wrmsr |
259 | ||
8170e6be | 260 | /* rsi is pointer to real mode structure with interesting info. |
1da177e4 | 261 | pass it to C */ |
8170e6be | 262 | movq %rsi, %rdi |
1da177e4 LT |
263 | |
264 | /* Finally jump to run C code and to be on real kernel address | |
265 | * Since we are running on identity-mapped space we have to jump | |
26374c7b EB |
266 | * to the full 64bit address, this is only possible as indirect |
267 | * jump. In addition we need to ensure %cs is set so we make this | |
268 | * a far return. | |
8170e6be PA |
269 | * |
270 | * Note: do not change to far jump indirect with 64bit offset. | |
271 | * | |
272 | * AMD does not support far jump indirect with 64bit offset. | |
273 | * AMD64 Architecture Programmer's Manual, Volume 3: states only | |
274 | * JMP FAR mem16:16 FF /5 Far jump indirect, | |
275 | * with the target specified by a far pointer in memory. | |
276 | * JMP FAR mem16:32 FF /5 Far jump indirect, | |
277 | * with the target specified by a far pointer in memory. | |
278 | * | |
279 | * Intel64 does support 64bit offset. | |
280 | * Software Developer Manual Vol 2: states: | |
281 | * FF /5 JMP m16:16 Jump far, absolute indirect, | |
282 | * address given in m16:16 | |
283 | * FF /5 JMP m16:32 Jump far, absolute indirect, | |
284 | * address given in m16:32. | |
285 | * REX.W + FF /5 JMP m16:64 Jump far, absolute indirect, | |
286 | * address given in m16:64. | |
1da177e4 LT |
287 | */ |
288 | movq initial_code(%rip),%rax | |
26374c7b EB |
289 | pushq $0 # fake return address to stop unwinder |
290 | pushq $__KERNEL_CS # set correct cs | |
291 | pushq %rax # target address in negative space | |
292 | lretq | |
1da177e4 | 293 | |
04633df0 BP |
294 | #include "verify_cpu.S" |
295 | ||
42e78e97 FY |
296 | #ifdef CONFIG_HOTPLUG_CPU |
297 | /* | |
298 | * Boot CPU0 entry point. It's called from play_dead(). Everything has been set | |
299 | * up already except stack. We just set up stack here. Then call | |
300 | * start_secondary(). | |
301 | */ | |
302 | ENTRY(start_cpu0) | |
303 | movq stack_start(%rip),%rsp | |
304 | movq initial_code(%rip),%rax | |
305 | pushq $0 # fake return address to stop unwinder | |
306 | pushq $__KERNEL_CS # set correct cs | |
307 | pushq %rax # target address in negative space | |
308 | lretq | |
309 | ENDPROC(start_cpu0) | |
310 | #endif | |
311 | ||
e57113bc | 312 | /* SMP bootup changes these two */ |
da5968ae | 313 | __REFDATA |
8170e6be PA |
314 | .balign 8 |
315 | GLOBAL(initial_code) | |
1da177e4 | 316 | .quad x86_64_start_kernel |
8170e6be | 317 | GLOBAL(initial_gs) |
2add8e23 | 318 | .quad INIT_PER_CPU_VAR(irq_stack_union) |
f1fbabb3 | 319 | |
8170e6be | 320 | GLOBAL(stack_start) |
1da177e4 | 321 | .quad init_thread_union+THREAD_SIZE-8 |
9cf4f298 | 322 | .word 0 |
b9af7c0d | 323 | __FINITDATA |
1da177e4 | 324 | |
1ab60e0f VG |
325 | bad_address: |
326 | jmp bad_address | |
327 | ||
8170e6be | 328 | __INIT |
cdeb6048 | 329 | ENTRY(early_idt_handler_array) |
9900aa2f PA |
330 | # 104(%rsp) %rflags |
331 | # 96(%rsp) %cs | |
332 | # 88(%rsp) %rip | |
333 | # 80(%rsp) error code | |
749c970a AK |
334 | i = 0 |
335 | .rept NUM_EXCEPTION_VECTORS | |
cdeb6048 | 336 | .ifeq (EXCEPTION_ERRCODE_MASK >> i) & 1 |
9900aa2f PA |
337 | pushq $0 # Dummy error code, to make stack frame uniform |
338 | .endif | |
339 | pushq $i # 72(%rsp) Vector number | |
cdeb6048 | 340 | jmp early_idt_handler_common |
749c970a | 341 | i = i + 1 |
cdeb6048 | 342 | .fill early_idt_handler_array + i*EARLY_IDT_HANDLER_SIZE - ., 1, 0xcc |
749c970a | 343 | .endr |
cdeb6048 | 344 | ENDPROC(early_idt_handler_array) |
8866cd9d | 345 | |
cdeb6048 AL |
346 | early_idt_handler_common: |
347 | /* | |
348 | * The stack is the hardware frame, an error code or zero, and the | |
349 | * vector number. | |
350 | */ | |
9900aa2f PA |
351 | cld |
352 | ||
b01d4e68 | 353 | cmpl $2,(%rsp) # X86_TRAP_NMI |
e839004b | 354 | je .Lis_nmi # Ignore NMI |
5fa10196 | 355 | |
b957591f AK |
356 | cmpl $2,early_recursion_flag(%rip) |
357 | jz 1f | |
358 | incl early_recursion_flag(%rip) | |
9900aa2f PA |
359 | |
360 | pushq %rax # 64(%rsp) | |
361 | pushq %rcx # 56(%rsp) | |
362 | pushq %rdx # 48(%rsp) | |
363 | pushq %rsi # 40(%rsp) | |
364 | pushq %rdi # 32(%rsp) | |
365 | pushq %r8 # 24(%rsp) | |
366 | pushq %r9 # 16(%rsp) | |
367 | pushq %r10 # 8(%rsp) | |
368 | pushq %r11 # 0(%rsp) | |
369 | ||
370 | cmpl $__KERNEL_CS,96(%rsp) | |
8170e6be PA |
371 | jne 11f |
372 | ||
373 | cmpl $14,72(%rsp) # Page fault? | |
374 | jnz 10f | |
375 | GET_CR2_INTO(%rdi) # can clobber any volatile register if pv | |
376 | call early_make_pgtable | |
377 | andl %eax,%eax | |
378 | jz 20f # All good | |
9900aa2f | 379 | |
8170e6be | 380 | 10: |
9900aa2f PA |
381 | leaq 88(%rsp),%rdi # Pointer to %rip |
382 | call early_fixup_exception | |
383 | andl %eax,%eax | |
384 | jnz 20f # Found an exception entry | |
385 | ||
8170e6be | 386 | 11: |
9900aa2f PA |
387 | #ifdef CONFIG_EARLY_PRINTK |
388 | GET_CR2_INTO(%r9) # can clobber any volatile register if pv | |
389 | movl 80(%rsp),%r8d # error code | |
390 | movl 72(%rsp),%esi # vector number | |
391 | movl 96(%rsp),%edx # %cs | |
392 | movq 88(%rsp),%rcx # %rip | |
8866cd9d | 393 | xorl %eax,%eax |
1da177e4 LT |
394 | leaq early_idt_msg(%rip),%rdi |
395 | call early_printk | |
b957591f AK |
396 | cmpl $2,early_recursion_flag(%rip) |
397 | jz 1f | |
398 | call dump_stack | |
6574ffd7 AK |
399 | #ifdef CONFIG_KALLSYMS |
400 | leaq early_idt_ripmsg(%rip),%rdi | |
9900aa2f | 401 | movq 40(%rsp),%rsi # %rip again |
6574ffd7 AK |
402 | call __print_symbol |
403 | #endif | |
076f9776 | 404 | #endif /* EARLY_PRINTK */ |
1da177e4 LT |
405 | 1: hlt |
406 | jmp 1b | |
076f9776 | 407 | |
8170e6be | 408 | 20: # Exception table entry found or page table generated |
9900aa2f PA |
409 | popq %r11 |
410 | popq %r10 | |
411 | popq %r9 | |
412 | popq %r8 | |
413 | popq %rdi | |
414 | popq %rsi | |
415 | popq %rdx | |
416 | popq %rcx | |
417 | popq %rax | |
9900aa2f | 418 | decl early_recursion_flag(%rip) |
e839004b | 419 | .Lis_nmi: |
5fa10196 | 420 | addq $16,%rsp # drop vector number and error code |
9900aa2f | 421 | INTERRUPT_RETURN |
cdeb6048 | 422 | ENDPROC(early_idt_handler_common) |
9900aa2f | 423 | |
8170e6be PA |
424 | __INITDATA |
425 | ||
9900aa2f | 426 | .balign 4 |
b957591f AK |
427 | early_recursion_flag: |
428 | .long 0 | |
1da177e4 | 429 | |
9900aa2f | 430 | #ifdef CONFIG_EARLY_PRINTK |
1da177e4 | 431 | early_idt_msg: |
8866cd9d | 432 | .asciz "PANIC: early exception %02lx rip %lx:%lx error %lx cr2 %lx\n" |
6574ffd7 AK |
433 | early_idt_ripmsg: |
434 | .asciz "RIP %s\n" | |
076f9776 | 435 | #endif /* CONFIG_EARLY_PRINTK */ |
1da177e4 | 436 | |
f0cf5d1a | 437 | #define NEXT_PAGE(name) \ |
67dcbb6b | 438 | .balign PAGE_SIZE; \ |
8170e6be | 439 | GLOBAL(name) |
f0cf5d1a | 440 | |
67dcbb6b | 441 | /* Automate the creation of 1 to 1 mapping pmd entries */ |
0e192b99 CG |
442 | #define PMDS(START, PERM, COUNT) \ |
443 | i = 0 ; \ | |
444 | .rept (COUNT) ; \ | |
445 | .quad (START) + (i << PMD_SHIFT) + (PERM) ; \ | |
446 | i = i + 1 ; \ | |
67dcbb6b VG |
447 | .endr |
448 | ||
8170e6be PA |
449 | __INITDATA |
450 | NEXT_PAGE(early_level4_pgt) | |
451 | .fill 511,8,0 | |
452 | .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE | |
453 | ||
454 | NEXT_PAGE(early_dynamic_pgts) | |
455 | .fill 512*EARLY_DYNAMIC_PAGE_TABLES,8,0 | |
456 | ||
b9af7c0d | 457 | .data |
8170e6be PA |
458 | |
459 | #ifndef CONFIG_XEN | |
f0cf5d1a | 460 | NEXT_PAGE(init_level4_pgt) |
8170e6be PA |
461 | .fill 512,8,0 |
462 | #else | |
463 | NEXT_PAGE(init_level4_pgt) | |
464 | .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE | |
465 | .org init_level4_pgt + L4_PAGE_OFFSET*8, 0 | |
466 | .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE | |
467 | .org init_level4_pgt + L4_START_KERNEL*8, 0 | |
cfd243d4 | 468 | /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */ |
8170e6be | 469 | .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE |
1da177e4 | 470 | |
f0cf5d1a | 471 | NEXT_PAGE(level3_ident_pgt) |
67dcbb6b | 472 | .quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE |
8170e6be PA |
473 | .fill 511, 8, 0 |
474 | NEXT_PAGE(level2_ident_pgt) | |
475 | /* Since I easily can, map the first 1G. | |
476 | * Don't set NX because code runs from these pages. | |
477 | */ | |
478 | PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD) | |
479 | #endif | |
1da177e4 | 480 | |
f0cf5d1a | 481 | NEXT_PAGE(level3_kernel_pgt) |
a6523748 | 482 | .fill L3_START_KERNEL,8,0 |
1da177e4 | 483 | /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */ |
67dcbb6b | 484 | .quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE |
b1c931e3 EB |
485 | .quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE |
486 | ||
f0cf5d1a | 487 | NEXT_PAGE(level2_kernel_pgt) |
88f3aec7 | 488 | /* |
85eb69a1 | 489 | * 512 MB kernel mapping. We spend a full page on this pagetable |
88f3aec7 IM |
490 | * anyway. |
491 | * | |
492 | * The kernel code+data+bss must not be bigger than that. | |
493 | * | |
85eb69a1 | 494 | * (NOTE: at +512MB starts the module area, see MODULES_VADDR. |
88f3aec7 IM |
495 | * If you want to increase this then increase MODULES_VADDR |
496 | * too.) | |
497 | */ | |
8490638c | 498 | PMDS(0, __PAGE_KERNEL_LARGE_EXEC, |
d4afe414 | 499 | KERNEL_IMAGE_SIZE/PMD_SIZE) |
1da177e4 | 500 | |
8170e6be PA |
501 | NEXT_PAGE(level2_fixmap_pgt) |
502 | .fill 506,8,0 | |
503 | .quad level1_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE | |
504 | /* 8MB reserved for vsyscalls + a 2MB hole = 4 + 1 entries */ | |
505 | .fill 5,8,0 | |
506 | ||
507 | NEXT_PAGE(level1_fixmap_pgt) | |
508 | .fill 512,8,0 | |
1ab60e0f | 509 | |
67dcbb6b | 510 | #undef PMDS |
1da177e4 | 511 | |
f0cf5d1a | 512 | .data |
1da177e4 | 513 | .align 16 |
a939098a GC |
514 | .globl early_gdt_descr |
515 | early_gdt_descr: | |
516 | .word GDT_ENTRIES*8-1 | |
3e5d8f97 | 517 | early_gdt_descr_base: |
2add8e23 | 518 | .quad INIT_PER_CPU_VAR(gdt_page) |
1da177e4 | 519 | |
1ab60e0f VG |
520 | ENTRY(phys_base) |
521 | /* This must match the first entry in level2_kernel_pgt */ | |
522 | .quad 0x0000000000000000 | |
523 | ||
8c5e5ac3 | 524 | #include "../../x86/xen/xen-head.S" |
1da177e4 | 525 | |
02b7da37 | 526 | __PAGE_ALIGNED_BSS |
8170e6be | 527 | NEXT_PAGE(empty_zero_page) |
e57113bc | 528 | .skip PAGE_SIZE |
ef7f0d6a | 529 |