[deliverable/linux.git] / arch / x86 / kernel / head_64.S

/*
 *  linux/arch/x86_64/kernel/head.S -- start in 32bit and switch to 64bit
 *
 *  Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
 *  Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
 *  Copyright (C) 2000 Karsten Keil <kkeil@suse.de>
 *  Copyright (C) 2001,2002 Andi Kleen <ak@suse.de>
 *  Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com>
 */


#include <linux/linkage.h>
#include <linux/threads.h>
#include <linux/init.h>
#include <asm/segment.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/msr.h>
#include <asm/cache.h>
#include <asm/processor-flags.h>
#include <asm/percpu.h>

#ifdef CONFIG_PARAVIRT
#include <asm/asm-offsets.h>
#include <asm/paravirt.h>
#else
#define GET_CR2_INTO_RCX movq %cr2, %rcx
#endif

/* we are not able to switch in one step to the final KERNEL ADDRESS SPACE
 * because we need identity-mapped pages.
 *
 */

#define pud_index(x)	(((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1))

L4_PAGE_OFFSET = pgd_index(__PAGE_OFFSET)
L3_PAGE_OFFSET = pud_index(__PAGE_OFFSET)
L4_START_KERNEL = pgd_index(__START_KERNEL_map)
L3_START_KERNEL = pud_index(__START_KERNEL_map)

	.text
	__HEAD
	.code64
	.globl startup_64
startup_64:

	/*
	 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 1,
	 * and someone has loaded an identity mapped page table
	 * for us.  These identity mapped page tables map all of the
	 * kernel pages and possibly all of memory.
	 *
	 * %esi holds a physical pointer to real_mode_data.
	 *
	 * We come here either directly from a 64bit bootloader, or from
	 * arch/x86_64/boot/compressed/head.S.
	 *
	 * We only come here initially at boot nothing else comes here.
	 *
	 * Since we may be loaded at an address different from what we were
	 * compiled to run at we first fixup the physical addresses in our page
	 * tables and then reload them.
	 */

	/* Compute the delta between the address I am compiled to run at and the
	 * address I am actually running at.
	 */
	leaq	_text(%rip), %rbp
	subq	$_text - __START_KERNEL_map, %rbp

	/* Is the address not 2M aligned? */
	movq	%rbp, %rax
	andl	$~PMD_PAGE_MASK, %eax
	testl	%eax, %eax
	jnz	bad_address

	/* Is the address too large? */
	leaq	_text(%rip), %rdx
	movq	$PGDIR_SIZE, %rax
	cmpq	%rax, %rdx
	jae	bad_address

	/* Fixup the physical addresses in the page table
	 */
	addq	%rbp, init_level4_pgt + 0(%rip)
	addq	%rbp, init_level4_pgt + (L4_PAGE_OFFSET*8)(%rip)
	addq	%rbp, init_level4_pgt + (L4_START_KERNEL*8)(%rip)

	addq	%rbp, level3_ident_pgt + 0(%rip)

	addq	%rbp, level3_kernel_pgt + (510*8)(%rip)
	addq	%rbp, level3_kernel_pgt + (511*8)(%rip)

	addq	%rbp, level2_fixmap_pgt + (506*8)(%rip)

	/* Add an Identity mapping if I am above 1G */
	leaq	_text(%rip), %rdi
	andq	$PMD_PAGE_MASK, %rdi

	movq	%rdi, %rax
	shrq	$PUD_SHIFT, %rax
	andq	$(PTRS_PER_PUD - 1), %rax
	jz	ident_complete

	leaq	(level2_spare_pgt - __START_KERNEL_map + _KERNPG_TABLE)(%rbp), %rdx
	leaq	level3_ident_pgt(%rip), %rbx
	movq	%rdx, 0(%rbx, %rax, 8)

	movq	%rdi, %rax
	shrq	$PMD_SHIFT, %rax
	andq	$(PTRS_PER_PMD - 1), %rax
	leaq	__PAGE_KERNEL_IDENT_LARGE_EXEC(%rdi), %rdx
	leaq	level2_spare_pgt(%rip), %rbx
	movq	%rdx, 0(%rbx, %rax, 8)
ident_complete:

	/*
	 * Fixup the kernel text+data virtual addresses. Note that
	 * we might write invalid pmds, when the kernel is relocated
	 * cleanup_highmap() fixes this up along with the mappings
	 * beyond _end.
	 */

	leaq	level2_kernel_pgt(%rip), %rdi
	leaq	4096(%rdi), %r8
	/* See if it is a valid page table entry */
1:	testq	$1, 0(%rdi)
	jz	2f
	addq	%rbp, 0(%rdi)
	/* Go to the next page */
2:	addq	$8, %rdi
	cmp	%r8, %rdi
	jne	1b

	/* Fixup phys_base */
	addq	%rbp, phys_base(%rip)

#ifdef CONFIG_X86_TRAMPOLINE
	addq	%rbp, trampoline_level4_pgt + 0(%rip)
	addq	%rbp, trampoline_level4_pgt + (511*8)(%rip)
#endif

	/* Due to ENTRY(), sometimes the empty space gets filled with
	 * zeros. Better take a jmp than relying on empty space being
	 * filled with 0x90 (nop)
	 */
	jmp secondary_startup_64
ENTRY(secondary_startup_64)
	/*
	 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 1,
	 * and someone has loaded a mapped page table.
	 *
	 * %esi holds a physical pointer to real_mode_data.
	 *
	 * We come here either from startup_64 (using physical addresses)
	 * or from trampoline.S (using virtual addresses).
	 *
	 * Using virtual addresses from trampoline.S removes the need
	 * to have any identity mapped pages in the kernel page table
	 * after the boot processor executes this code.
	 */

	/* Enable PAE mode and PGE */
	movl	$(X86_CR4_PAE | X86_CR4_PGE), %eax
	movq	%rax, %cr4

	/* Setup early boot stage 4 level pagetables. */
	movq	$(init_level4_pgt - __START_KERNEL_map), %rax
	addq	phys_base(%rip), %rax
	movq	%rax, %cr3

	/* Ensure I am executing from virtual addresses */
	movq	$1f, %rax
	jmp	*%rax
1:

	/* Check if nx is implemented */
	movl	$0x80000001, %eax
	cpuid
	movl	%edx,%edi

	/* Setup EFER (Extended Feature Enable Register) */
	movl	$MSR_EFER, %ecx
	rdmsr
	btsl	$_EFER_SCE, %eax	/* Enable System Call */
	btl	$20,%edi		/* No Execute supported? */
	jnc     1f
	btsl	$_EFER_NX, %eax
1:	wrmsr				/* Make changes effective */

	/* Setup cr0 */
#define CR0_STATE	(X86_CR0_PE | X86_CR0_MP | X86_CR0_ET | \
			 X86_CR0_NE | X86_CR0_WP | X86_CR0_AM | \
			 X86_CR0_PG)
	movl	$CR0_STATE, %eax
	/* Make changes effective */
	movq	%rax, %cr0

	/* Setup a boot time stack */
	movq stack_start(%rip),%rsp

	/* zero EFLAGS after setting rsp */
	pushq $0
	popfq

	/*
	 * We must switch to a new descriptor in kernel space for the GDT
	 * because soon the kernel won't have access anymore to the userspace
	 * addresses where we're currently running on. We have to do that here
	 * because in 32bit we couldn't load a 64bit linear address.
	 */
	lgdt	early_gdt_descr(%rip)

	/* set up data segments */
	xorl %eax,%eax
	movl %eax,%ds
	movl %eax,%ss
	movl %eax,%es

	/*
	 * We don't really need to load %fs or %gs, but load them anyway
	 * to kill any stale realmode selectors.  This allows execution
	 * under VT hardware.
	 */
	movl %eax,%fs
	movl %eax,%gs

	/* Set up %gs.
	 *
	 * The base of %gs always points to the bottom of the irqstack
	 * union.  If the stack protector canary is enabled, it is
	 * located at %gs:40.  Note that, on SMP, the boot cpu uses
	 * init data section till per cpu areas are set up.
	 */
	movl	$MSR_GS_BASE,%ecx
	movl	initial_gs(%rip),%eax
	movl	initial_gs+4(%rip),%edx
	wrmsr	

	/* esi is pointer to real mode structure with interesting info.
	   pass it to C */
	movl	%esi, %edi
	
	/* Finally jump to run C code and to be on real kernel address
	 * Since we are running on identity-mapped space we have to jump
	 * to the full 64bit address, this is only possible as indirect
	 * jump.  In addition we need to ensure %cs is set so we make this
	 * a far return.
	 */
	movq	initial_code(%rip),%rax
	pushq	$0		# fake return address to stop unwinder
	pushq	$__KERNEL_CS	# set correct cs
	pushq	%rax		# target address in negative space
	lretq

	/* SMP bootup changes these two */
	__REFDATA
	.align	8
	ENTRY(initial_code)
	.quad	x86_64_start_kernel
	ENTRY(initial_gs)
	.quad	INIT_PER_CPU_VAR(irq_stack_union)

	ENTRY(stack_start)
	.quad  init_thread_union+THREAD_SIZE-8
	.word  0
	__FINITDATA

bad_address:
	jmp bad_address

	.section ".init.text","ax"
#ifdef CONFIG_EARLY_PRINTK
	.globl early_idt_handlers
early_idt_handlers:
	i = 0
	.rept NUM_EXCEPTION_VECTORS
	movl $i, %esi
	jmp early_idt_handler
	i = i + 1
	.endr
#endif

ENTRY(early_idt_handler)
#ifdef CONFIG_EARLY_PRINTK
	cmpl $2,early_recursion_flag(%rip)
	jz  1f
	incl early_recursion_flag(%rip)
	GET_CR2_INTO_RCX
	movq %rcx,%r9
	xorl %r8d,%r8d		# zero for error code
	movl %esi,%ecx		# get vector number
	# Test %ecx against mask of vectors that push error code.
	cmpl $31,%ecx
	ja 0f
	movl $1,%eax
	salq %cl,%rax
	testl $0x27d00,%eax
	je 0f
	popq %r8		# get error code
0:	movq 0(%rsp),%rcx	# get ip
	movq 8(%rsp),%rdx	# get cs
	xorl %eax,%eax
	leaq early_idt_msg(%rip),%rdi
	call early_printk
	cmpl $2,early_recursion_flag(%rip)
	jz  1f
	call dump_stack
#ifdef CONFIG_KALLSYMS	
	leaq early_idt_ripmsg(%rip),%rdi
	movq 0(%rsp),%rsi	# get rip again
	call __print_symbol
#endif
#endif /* EARLY_PRINTK */
1:	hlt
	jmp 1b

#ifdef CONFIG_EARLY_PRINTK
early_recursion_flag:
	.long 0

early_idt_msg:
	.asciz "PANIC: early exception %02lx rip %lx:%lx error %lx cr2 %lx\n"
early_idt_ripmsg:
	.asciz "RIP %s\n"
#endif /* CONFIG_EARLY_PRINTK */
	.previous

#define NEXT_PAGE(name) \
	.balign	PAGE_SIZE; \
ENTRY(name)

/* Automate the creation of 1 to 1 mapping pmd entries */
#define PMDS(START, PERM, COUNT)			\
	i = 0 ;						\
	.rept (COUNT) ;					\
	.quad	(START) + (i << PMD_SHIFT) + (PERM) ;	\
	i = i + 1 ;					\
	.endr

	.data
	/*
	 * This default setting generates an ident mapping at address 0x100000
	 * and a mapping for the kernel that precisely maps virtual address
	 * 0xffffffff80000000 to physical address 0x000000. (always using
	 * 2Mbyte large pages provided by PAE mode)
	 */
NEXT_PAGE(init_level4_pgt)
	.quad	level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
	.org	init_level4_pgt + L4_PAGE_OFFSET*8, 0
	.quad	level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
	.org	init_level4_pgt + L4_START_KERNEL*8, 0
	/* (2^48-(2*1024*1024*1024))/(2^39) = 511 */
	.quad	level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE

NEXT_PAGE(level3_ident_pgt)
	.quad	level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
	.fill	511,8,0

NEXT_PAGE(level3_kernel_pgt)
	.fill	L3_START_KERNEL,8,0
	/* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */
	.quad	level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE
	.quad	level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE

NEXT_PAGE(level2_fixmap_pgt)
	.fill	506,8,0
	.quad	level1_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE
	/* 8MB reserved for vsyscalls + a 2MB hole = 4 + 1 entries */
	.fill	5,8,0

NEXT_PAGE(level1_fixmap_pgt)
	.fill	512,8,0

NEXT_PAGE(level2_ident_pgt)
	/* Since I easily can, map the first 1G.
	 * Don't set NX because code runs from these pages.
	 */
	PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD)

NEXT_PAGE(level2_kernel_pgt)
	/*
	 * 512 MB kernel mapping. We spend a full page on this pagetable
	 * anyway.
	 *
	 * The kernel code+data+bss must not be bigger than that.
	 *
	 * (NOTE: at +512MB starts the module area, see MODULES_VADDR.
	 *  If you want to increase this then increase MODULES_VADDR
	 *  too.)
	 */
	PMDS(0, __PAGE_KERNEL_LARGE_EXEC,
		KERNEL_IMAGE_SIZE/PMD_SIZE)

NEXT_PAGE(level2_spare_pgt)
	.fill   512, 8, 0

#undef PMDS
#undef NEXT_PAGE

	.data
	.align 16
	.globl early_gdt_descr
early_gdt_descr:
	.word	GDT_ENTRIES*8-1
early_gdt_descr_base:
	.quad	INIT_PER_CPU_VAR(gdt_page)

ENTRY(phys_base)
	/* This must match the first entry in level2_kernel_pgt */
	.quad   0x0000000000000000

#include "../../x86/xen/xen-head.S"
	
	.section .bss, "aw", @nobits
	.align L1_CACHE_BYTES
ENTRY(idt_table)
	.skip IDT_ENTRIES * 16

	__PAGE_ALIGNED_BSS
	.align PAGE_SIZE
ENTRY(empty_zero_page)
	.skip PAGE_SIZE
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/x86_64/kernel/head.S -- start in 32bit and switch to 64bit
	3	*
	4	* Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
	5	* Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
	6	* Copyright (C) 2000 Karsten Keil <kkeil@suse.de>
	7	* Copyright (C) 2001,2002 Andi Kleen <ak@suse.de>
1ab60e0f	8	* Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com>
1da177e4 LT	9	*/
	10
	11
	12	#include <linux/linkage.h>
	13	#include <linux/threads.h>
f6c2e333	14	#include <linux/init.h>
1da177e4	15	#include <asm/segment.h>
67dcbb6b	16	#include <asm/pgtable.h>
1da177e4 LT	17	#include <asm/page.h>
	18	#include <asm/msr.h>
	19	#include <asm/cache.h>
369101da	20	#include <asm/processor-flags.h>
b12d8db8	21	#include <asm/percpu.h>
1ab60e0f	22
49a69787 GOC	23	#ifdef CONFIG_PARAVIRT
	24	#include <asm/asm-offsets.h>
	25	#include <asm/paravirt.h>
	26	#else
	27	#define GET_CR2_INTO_RCX movq %cr2, %rcx
	28	#endif
	29
3ad2f3fb	30	/* we are not able to switch in one step to the final KERNEL ADDRESS SPACE
1ab60e0f VG	31	* because we need identity-mapped pages.
1ab60e0f VG	32	*
1da177e4 LT	33	*/
1da177e4 LT	34
a6523748 EH	35	#define pud_index(x) (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
	36
	37	L4_PAGE_OFFSET = pgd_index(__PAGE_OFFSET)
	38	L3_PAGE_OFFSET = pud_index(__PAGE_OFFSET)
	39	L4_START_KERNEL = pgd_index(__START_KERNEL_map)
	40	L3_START_KERNEL = pud_index(__START_KERNEL_map)
	41
1da177e4	42	.text
4ae59b91	43	__HEAD
1ab60e0f VG	44	.code64
	45	.globl startup_64
	46	startup_64:
	47
1da177e4	48	/*
1ab60e0f VG	49	* At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 1,
	50	* and someone has loaded an identity mapped page table
	51	* for us. These identity mapped page tables map all of the
	52	* kernel pages and possibly all of memory.
	53	*
	54	* %esi holds a physical pointer to real_mode_data.
	55	*
	56	* We come here either directly from a 64bit bootloader, or from
	57	* arch/x86_64/boot/compressed/head.S.
	58	*
	59	* We only come here initially at boot nothing else comes here.
	60	*
	61	* Since we may be loaded at an address different from what we were
	62	* compiled to run at we first fixup the physical addresses in our page
	63	* tables and then reload them.
1da177e4 LT	64	*/
1da177e4 LT	65
1ab60e0f VG	66	/* Compute the delta between the address I am compiled to run at and the
1ab60e0f VG	67	* address I am actually running at.
1da177e4	68	*/
1ab60e0f VG	69	leaq _text(%rip), %rbp
	70	subq $_text - __START_KERNEL_map, %rbp
	71
	72	/* Is the address not 2M aligned? */
	73	movq %rbp, %rax
31422c51	74	andl $~PMD_PAGE_MASK, %eax
1ab60e0f VG	75	testl %eax, %eax
	76	jnz bad_address
	77
	78	/* Is the address too large? */
	79	leaq _text(%rip), %rdx
	80	movq $PGDIR_SIZE, %rax
	81	cmpq %rax, %rdx
	82	jae bad_address
	83
	84	/* Fixup the physical addresses in the page table
1da177e4	85	*/
1ab60e0f	86	addq %rbp, init_level4_pgt + 0(%rip)
a6523748 EH	87	addq %rbp, init_level4_pgt + (L4_PAGE_OFFSET*8)(%rip)
a6523748 EH	88	addq %rbp, init_level4_pgt + (L4_START_KERNEL*8)(%rip)
1ab60e0f VG	89
1ab60e0f VG	90	addq %rbp, level3_ident_pgt + 0(%rip)
b1c931e3	91
1ab60e0f	92	addq %rbp, level3_kernel_pgt + (510*8)(%rip)
b1c931e3 EB	93	addq %rbp, level3_kernel_pgt + (511*8)(%rip)
	94
	95	addq %rbp, level2_fixmap_pgt + (506*8)(%rip)
1ab60e0f VG	96
	97	/* Add an Identity mapping if I am above 1G */
	98	leaq _text(%rip), %rdi
31422c51	99	andq $PMD_PAGE_MASK, %rdi
1ab60e0f VG	100
	101	movq %rdi, %rax
	102	shrq $PUD_SHIFT, %rax
	103	andq $(PTRS_PER_PUD - 1), %rax
	104	jz ident_complete
	105
	106	leaq (level2_spare_pgt - __START_KERNEL_map + _KERNPG_TABLE)(%rbp), %rdx
	107	leaq level3_ident_pgt(%rip), %rbx
	108	movq %rdx, 0(%rbx, %rax, 8)
	109
	110	movq %rdi, %rax
	111	shrq $PMD_SHIFT, %rax
	112	andq $(PTRS_PER_PMD - 1), %rax
b2bc2731	113	leaq __PAGE_KERNEL_IDENT_LARGE_EXEC(%rdi), %rdx
1ab60e0f VG	114	leaq level2_spare_pgt(%rip), %rbx
	115	movq %rdx, 0(%rbx, %rax, 8)
	116	ident_complete:
	117
31eedd82 TG	118	/*
	119	* Fixup the kernel text+data virtual addresses. Note that
	120	* we might write invalid pmds, when the kernel is relocated
	121	* cleanup_highmap() fixes this up along with the mappings
	122	* beyond _end.
1ab60e0f	123	*/
31eedd82	124
1ab60e0f VG	125	leaq level2_kernel_pgt(%rip), %rdi
	126	leaq 4096(%rdi), %r8
	127	/* See if it is a valid page table entry */
	128	1: testq $1, 0(%rdi)
	129	jz 2f
	130	addq %rbp, 0(%rdi)
	131	/* Go to the next page */
	132	2: addq $8, %rdi
	133	cmp %r8, %rdi
	134	jne 1b
	135
	136	/* Fixup phys_base */
	137	addq %rbp, phys_base(%rip)
1da177e4	138
64e83b5a	139	#ifdef CONFIG_X86_TRAMPOLINE
1ab60e0f VG	140	addq %rbp, trampoline_level4_pgt + 0(%rip)
	141	addq %rbp, trampoline_level4_pgt + (511*8)(%rip)
	142	#endif
1da177e4	143
1ab60e0f VG	144	/* Due to ENTRY(), sometimes the empty space gets filled with
	145	* zeros. Better take a jmp than relying on empty space being
	146	* filled with 0x90 (nop)
1da177e4	147	*/
1ab60e0f	148	jmp secondary_startup_64
90b1c208	149	ENTRY(secondary_startup_64)
1ab60e0f VG	150	/*
	151	* At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 1,
	152	* and someone has loaded a mapped page table.
	153	*
	154	* %esi holds a physical pointer to real_mode_data.
	155	*
	156	* We come here either from startup_64 (using physical addresses)
	157	* or from trampoline.S (using virtual addresses).
	158	*
	159	* Using virtual addresses from trampoline.S removes the need
	160	* to have any identity mapped pages in the kernel page table
	161	* after the boot processor executes this code.
1da177e4 LT	162	*/
	163
	164	/* Enable PAE mode and PGE */
05139d8f	165	movl $(X86_CR4_PAE \| X86_CR4_PGE), %eax
1da177e4 LT	166	movq %rax, %cr4
	167
	168	/* Setup early boot stage 4 level pagetables. */
cfd243d4	169	movq $(init_level4_pgt - __START_KERNEL_map), %rax
1ab60e0f	170	addq phys_base(%rip), %rax
1da177e4 LT	171	movq %rax, %cr3
1da177e4 LT	172
1ab60e0f VG	173	/* Ensure I am executing from virtual addresses */
	174	movq $1f, %rax
	175	jmp *%rax
	176	1:
	177
1da177e4 LT	178	/* Check if nx is implemented */
	179	movl $0x80000001, %eax
	180	cpuid
	181	movl %edx,%edi
	182
	183	/* Setup EFER (Extended Feature Enable Register) */
	184	movl $MSR_EFER, %ecx
	185	rdmsr
1ab60e0f VG	186	btsl $_EFER_SCE, %eax /* Enable System Call */
1ab60e0f VG	187	btl $20,%edi /* No Execute supported? */
1da177e4 LT	188	jnc 1f
1da177e4 LT	189	btsl $_EFER_NX, %eax
1ab60e0f	190	1: wrmsr /* Make changes effective */
1da177e4 LT	191
1da177e4 LT	192	/* Setup cr0 */
369101da CG	193	#define CR0_STATE (X86_CR0_PE \| X86_CR0_MP \| X86_CR0_ET \| \
	194	X86_CR0_NE \| X86_CR0_WP \| X86_CR0_AM \| \
	195	X86_CR0_PG)
	196	movl $CR0_STATE, %eax
1da177e4 LT	197	/* Make changes effective */
	198	movq %rax, %cr0
	199
	200	/* Setup a boot time stack */
9cf4f298	201	movq stack_start(%rip),%rsp
1da177e4 LT	202
	203	/* zero EFLAGS after setting rsp */
	204	pushq $0
	205	popfq
	206
	207	/*
	208	* We must switch to a new descriptor in kernel space for the GDT
	209	* because soon the kernel won't have access anymore to the userspace
	210	* addresses where we're currently running on. We have to do that here
	211	* because in 32bit we couldn't load a 64bit linear address.
	212	*/
a939098a	213	lgdt early_gdt_descr(%rip)
1da177e4	214
8ec6993d BG	215	/* set up data segments */
8ec6993d BG	216	xorl %eax,%eax
ffb60175 ZA	217	movl %eax,%ds
	218	movl %eax,%ss
	219	movl %eax,%es
	220
	221	/*
	222	* We don't really need to load %fs or %gs, but load them anyway
	223	* to kill any stale realmode selectors. This allows execution
	224	* under VT hardware.
	225	*/
	226	movl %eax,%fs
	227	movl %eax,%gs
	228
f32ff538 TH	229	/* Set up %gs.
f32ff538 TH	230	*
947e76cd BG	231	* The base of %gs always points to the bottom of the irqstack
	232	* union. If the stack protector canary is enabled, it is
	233	* located at %gs:40. Note that, on SMP, the boot cpu uses
	234	* init data section till per cpu areas are set up.
f32ff538	235	*/
1da177e4	236	movl $MSR_GS_BASE,%ecx
650fb439 BG	237	movl initial_gs(%rip),%eax
650fb439 BG	238	movl initial_gs+4(%rip),%edx
1da177e4 LT	239	wrmsr
1da177e4 LT	240
1da177e4 LT	241	/* esi is pointer to real mode structure with interesting info.
	242	pass it to C */
	243	movl %esi, %edi
	244
	245	/* Finally jump to run C code and to be on real kernel address
	246	* Since we are running on identity-mapped space we have to jump
26374c7b EB	247	* to the full 64bit address, this is only possible as indirect
	248	* jump. In addition we need to ensure %cs is set so we make this
	249	* a far return.
1da177e4 LT	250	*/
1da177e4 LT	251	movq initial_code(%rip),%rax
26374c7b EB	252	pushq $0 # fake return address to stop unwinder
	253	pushq $__KERNEL_CS # set correct cs
	254	pushq %rax # target address in negative space
	255	lretq
1da177e4	256
e57113bc	257	/* SMP bootup changes these two */
da5968ae	258	__REFDATA
e57113bc	259	.align 8
f1fbabb3	260	ENTRY(initial_code)
1da177e4	261	.quad x86_64_start_kernel
f32ff538	262	ENTRY(initial_gs)
2add8e23	263	.quad INIT_PER_CPU_VAR(irq_stack_union)
f1fbabb3	264
9cf4f298	265	ENTRY(stack_start)
1da177e4	266	.quad init_thread_union+THREAD_SIZE-8
9cf4f298	267	.word 0
b9af7c0d	268	__FINITDATA
1da177e4	269
1ab60e0f VG	270	bad_address:
	271	jmp bad_address
	272
41bd4eac	273	.section ".init.text","ax"
076f9776	274	#ifdef CONFIG_EARLY_PRINTK
8866cd9d RM	275	.globl early_idt_handlers
8866cd9d RM	276	early_idt_handlers:
749c970a AK	277	i = 0
	278	.rept NUM_EXCEPTION_VECTORS
	279	movl $i, %esi
	280	jmp early_idt_handler
	281	i = i + 1
	282	.endr
076f9776	283	#endif
8866cd9d	284
1da177e4	285	ENTRY(early_idt_handler)
076f9776	286	#ifdef CONFIG_EARLY_PRINTK
b957591f AK	287	cmpl $2,early_recursion_flag(%rip)
	288	jz 1f
	289	incl early_recursion_flag(%rip)
49a69787	290	GET_CR2_INTO_RCX
8866cd9d RM	291	movq %rcx,%r9
	292	xorl %r8d,%r8d # zero for error code
	293	movl %esi,%ecx # get vector number
	294	# Test %ecx against mask of vectors that push error code.
	295	cmpl $31,%ecx
	296	ja 0f
	297	movl $1,%eax
	298	salq %cl,%rax
	299	testl $0x27d00,%eax
	300	je 0f
	301	popq %r8 # get error code
	302	0: movq 0(%rsp),%rcx # get ip
	303	movq 8(%rsp),%rdx # get cs
	304	xorl %eax,%eax
1da177e4 LT	305	leaq early_idt_msg(%rip),%rdi
1da177e4 LT	306	call early_printk
b957591f AK	307	cmpl $2,early_recursion_flag(%rip)
	308	jz 1f
	309	call dump_stack
6574ffd7 AK	310	#ifdef CONFIG_KALLSYMS
6574ffd7 AK	311	leaq early_idt_ripmsg(%rip),%rdi
7aed55d1	312	movq 0(%rsp),%rsi # get rip again
6574ffd7 AK	313	call __print_symbol
6574ffd7 AK	314	#endif
076f9776	315	#endif /* EARLY_PRINTK */
1da177e4 LT	316	1: hlt
1da177e4 LT	317	jmp 1b
076f9776 IM	318
076f9776 IM	319	#ifdef CONFIG_EARLY_PRINTK
b957591f AK	320	early_recursion_flag:
b957591f AK	321	.long 0
1da177e4 LT	322
1da177e4 LT	323	early_idt_msg:
8866cd9d	324	.asciz "PANIC: early exception %02lx rip %lx:%lx error %lx cr2 %lx\n"
6574ffd7 AK	325	early_idt_ripmsg:
6574ffd7 AK	326	.asciz "RIP %s\n"
076f9776	327	#endif /* CONFIG_EARLY_PRINTK */
41bd4eac	328	.previous
1da177e4	329
f0cf5d1a	330	#define NEXT_PAGE(name) \
67dcbb6b	331	.balign PAGE_SIZE; \
f0cf5d1a JB	332	ENTRY(name)
f0cf5d1a JB	333
67dcbb6b	334	/* Automate the creation of 1 to 1 mapping pmd entries */
0e192b99 CG	335	#define PMDS(START, PERM, COUNT) \
	336	i = 0 ; \
	337	.rept (COUNT) ; \
	338	.quad (START) + (i << PMD_SHIFT) + (PERM) ; \
	339	i = i + 1 ; \
67dcbb6b VG	340	.endr
67dcbb6b VG	341
b9af7c0d	342	.data
cfd243d4 VG	343	/*
	344	* This default setting generates an ident mapping at address 0x100000
	345	* and a mapping for the kernel that precisely maps virtual address
	346	* 0xffffffff80000000 to physical address 0x000000. (always using
	347	* 2Mbyte large pages provided by PAE mode)
	348	*/
f0cf5d1a	349	NEXT_PAGE(init_level4_pgt)
cfd243d4	350	.quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
a6523748	351	.org init_level4_pgt + L4_PAGE_OFFSET*8, 0
cfd243d4	352	.quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
a6523748	353	.org init_level4_pgt + L4_START_KERNEL*8, 0
cfd243d4 VG	354	/* (2^48-(2102410241024))/(2^39) = 511 /
cfd243d4 VG	355	.quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE
1da177e4	356
f0cf5d1a	357	NEXT_PAGE(level3_ident_pgt)
67dcbb6b	358	.quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
1da177e4 LT	359	.fill 511,8,0
1da177e4 LT	360
f0cf5d1a	361	NEXT_PAGE(level3_kernel_pgt)
a6523748	362	.fill L3_START_KERNEL,8,0
1da177e4	363	/* (2^48-(2102410241024)-((2^39)511))/(2^30) = 510 */
67dcbb6b	364	.quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE
b1c931e3 EB	365	.quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE
	366
	367	NEXT_PAGE(level2_fixmap_pgt)
6596f242 IM	368	.fill 506,8,0
	369	.quad level1_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE
	370	/* 8MB reserved for vsyscalls + a 2MB hole = 4 + 1 entries */
	371	.fill 5,8,0
	372
	373	NEXT_PAGE(level1_fixmap_pgt)
b1c931e3	374	.fill 512,8,0
1da177e4	375
f0cf5d1a	376	NEXT_PAGE(level2_ident_pgt)
67dcbb6b VG	377	/* Since I easily can, map the first 1G.
	378	* Don't set NX because code runs from these pages.
	379	*/
b2bc2731	380	PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD)
1ab60e0f	381
f0cf5d1a	382	NEXT_PAGE(level2_kernel_pgt)
88f3aec7	383	/*
85eb69a1	384	* 512 MB kernel mapping. We spend a full page on this pagetable
88f3aec7 IM	385	* anyway.
	386	*
	387	* The kernel code+data+bss must not be bigger than that.
	388	*
85eb69a1	389	* (NOTE: at +512MB starts the module area, see MODULES_VADDR.
88f3aec7 IM	390	* If you want to increase this then increase MODULES_VADDR
	391	* too.)
	392	*/
8490638c	393	PMDS(0, __PAGE_KERNEL_LARGE_EXEC,
d4afe414	394	KERNEL_IMAGE_SIZE/PMD_SIZE)
1da177e4	395
1ab60e0f	396	NEXT_PAGE(level2_spare_pgt)
88f3aec7	397	.fill 512, 8, 0
1ab60e0f	398
67dcbb6b	399	#undef PMDS
f0cf5d1a	400	#undef NEXT_PAGE
1da177e4	401
f0cf5d1a	402	.data
1da177e4	403	.align 16
a939098a GC	404	.globl early_gdt_descr
	405	early_gdt_descr:
	406	.word GDT_ENTRIES*8-1
3e5d8f97	407	early_gdt_descr_base:
2add8e23	408	.quad INIT_PER_CPU_VAR(gdt_page)
1da177e4	409
1ab60e0f VG	410	ENTRY(phys_base)
	411	/* This must match the first entry in level2_kernel_pgt */
	412	.quad 0x0000000000000000
	413
8c5e5ac3	414	#include "../../x86/xen/xen-head.S"
1da177e4	415
e57113bc JB	416	.section .bss, "aw", @nobits
	417	.align L1_CACHE_BYTES
	418	ENTRY(idt_table)
5e112ae2	419	.skip IDT_ENTRIES * 16
1da177e4	420
02b7da37	421	__PAGE_ALIGNED_BSS
e57113bc JB	422	.align PAGE_SIZE
	423	ENTRY(empty_zero_page)
	424	.skip PAGE_SIZE