Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/arch/x86_64/kernel/head.S -- start in 32bit and switch to 64bit | |
3 | * | |
4 | * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE | |
5 | * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> | |
6 | * Copyright (C) 2000 Karsten Keil <kkeil@suse.de> | |
7 | * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de> | |
1ab60e0f | 8 | * Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com> |
1da177e4 LT |
9 | */ |
10 | ||
11 | ||
12 | #include <linux/linkage.h> | |
13 | #include <linux/threads.h> | |
f6c2e333 | 14 | #include <linux/init.h> |
1da177e4 LT |
15 | #include <asm/desc.h> |
16 | #include <asm/segment.h> | |
67dcbb6b | 17 | #include <asm/pgtable.h> |
1da177e4 LT |
18 | #include <asm/page.h> |
19 | #include <asm/msr.h> | |
20 | #include <asm/cache.h> | |
369101da | 21 | #include <asm/processor-flags.h> |
b12d8db8 | 22 | #include <asm/percpu.h> |
1ab60e0f | 23 | |
49a69787 GOC |
24 | #ifdef CONFIG_PARAVIRT |
25 | #include <asm/asm-offsets.h> | |
26 | #include <asm/paravirt.h> | |
27 | #else | |
28 | #define GET_CR2_INTO_RCX movq %cr2, %rcx | |
29 | #endif | |
30 | ||
1da177e4 | 31 | /* we are not able to switch in one step to the final KERNEL ADRESS SPACE |
1ab60e0f VG |
32 | * because we need identity-mapped pages. |
33 | * | |
1da177e4 LT |
34 | */ |
35 | ||
a6523748 EH |
36 | #define pud_index(x) (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) |
37 | ||
38 | L4_PAGE_OFFSET = pgd_index(__PAGE_OFFSET) | |
39 | L3_PAGE_OFFSET = pud_index(__PAGE_OFFSET) | |
40 | L4_START_KERNEL = pgd_index(__START_KERNEL_map) | |
41 | L3_START_KERNEL = pud_index(__START_KERNEL_map) | |
42 | ||
1da177e4 | 43 | .text |
92417df0 | 44 | .section .text.head |
1ab60e0f VG |
45 | .code64 |
46 | .globl startup_64 | |
47 | startup_64: | |
48 | ||
1da177e4 | 49 | /* |
1ab60e0f VG |
50 | * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 1, |
51 | * and someone has loaded an identity mapped page table | |
52 | * for us. These identity mapped page tables map all of the | |
53 | * kernel pages and possibly all of memory. | |
54 | * | |
55 | * %esi holds a physical pointer to real_mode_data. | |
56 | * | |
57 | * We come here either directly from a 64bit bootloader, or from | |
58 | * arch/x86_64/boot/compressed/head.S. | |
59 | * | |
60 | * We only come here initially at boot nothing else comes here. | |
61 | * | |
62 | * Since we may be loaded at an address different from what we were | |
63 | * compiled to run at we first fixup the physical addresses in our page | |
64 | * tables and then reload them. | |
1da177e4 LT |
65 | */ |
66 | ||
1ab60e0f VG |
67 | /* Compute the delta between the address I am compiled to run at and the |
68 | * address I am actually running at. | |
1da177e4 | 69 | */ |
1ab60e0f VG |
70 | leaq _text(%rip), %rbp |
71 | subq $_text - __START_KERNEL_map, %rbp | |
72 | ||
73 | /* Is the address not 2M aligned? */ | |
74 | movq %rbp, %rax | |
31422c51 | 75 | andl $~PMD_PAGE_MASK, %eax |
1ab60e0f VG |
76 | testl %eax, %eax |
77 | jnz bad_address | |
78 | ||
79 | /* Is the address too large? */ | |
80 | leaq _text(%rip), %rdx | |
81 | movq $PGDIR_SIZE, %rax | |
82 | cmpq %rax, %rdx | |
83 | jae bad_address | |
84 | ||
85 | /* Fixup the physical addresses in the page table | |
1da177e4 | 86 | */ |
1ab60e0f | 87 | addq %rbp, init_level4_pgt + 0(%rip) |
a6523748 EH |
88 | addq %rbp, init_level4_pgt + (L4_PAGE_OFFSET*8)(%rip) |
89 | addq %rbp, init_level4_pgt + (L4_START_KERNEL*8)(%rip) | |
1ab60e0f VG |
90 | |
91 | addq %rbp, level3_ident_pgt + 0(%rip) | |
b1c931e3 | 92 | |
1ab60e0f | 93 | addq %rbp, level3_kernel_pgt + (510*8)(%rip) |
b1c931e3 EB |
94 | addq %rbp, level3_kernel_pgt + (511*8)(%rip) |
95 | ||
96 | addq %rbp, level2_fixmap_pgt + (506*8)(%rip) | |
1ab60e0f VG |
97 | |
98 | /* Add an Identity mapping if I am above 1G */ | |
99 | leaq _text(%rip), %rdi | |
31422c51 | 100 | andq $PMD_PAGE_MASK, %rdi |
1ab60e0f VG |
101 | |
102 | movq %rdi, %rax | |
103 | shrq $PUD_SHIFT, %rax | |
104 | andq $(PTRS_PER_PUD - 1), %rax | |
105 | jz ident_complete | |
106 | ||
107 | leaq (level2_spare_pgt - __START_KERNEL_map + _KERNPG_TABLE)(%rbp), %rdx | |
108 | leaq level3_ident_pgt(%rip), %rbx | |
109 | movq %rdx, 0(%rbx, %rax, 8) | |
110 | ||
111 | movq %rdi, %rax | |
112 | shrq $PMD_SHIFT, %rax | |
113 | andq $(PTRS_PER_PMD - 1), %rax | |
b2bc2731 | 114 | leaq __PAGE_KERNEL_IDENT_LARGE_EXEC(%rdi), %rdx |
1ab60e0f VG |
115 | leaq level2_spare_pgt(%rip), %rbx |
116 | movq %rdx, 0(%rbx, %rax, 8) | |
117 | ident_complete: | |
118 | ||
31eedd82 TG |
119 | /* |
120 | * Fixup the kernel text+data virtual addresses. Note that | |
121 | * we might write invalid pmds, when the kernel is relocated | |
122 | * cleanup_highmap() fixes this up along with the mappings | |
123 | * beyond _end. | |
1ab60e0f | 124 | */ |
31eedd82 | 125 | |
1ab60e0f VG |
126 | leaq level2_kernel_pgt(%rip), %rdi |
127 | leaq 4096(%rdi), %r8 | |
128 | /* See if it is a valid page table entry */ | |
129 | 1: testq $1, 0(%rdi) | |
130 | jz 2f | |
131 | addq %rbp, 0(%rdi) | |
132 | /* Go to the next page */ | |
133 | 2: addq $8, %rdi | |
134 | cmp %r8, %rdi | |
135 | jne 1b | |
136 | ||
137 | /* Fixup phys_base */ | |
138 | addq %rbp, phys_base(%rip) | |
1da177e4 | 139 | |
64e83b5a | 140 | #ifdef CONFIG_X86_TRAMPOLINE |
1ab60e0f VG |
141 | addq %rbp, trampoline_level4_pgt + 0(%rip) |
142 | addq %rbp, trampoline_level4_pgt + (511*8)(%rip) | |
143 | #endif | |
1da177e4 | 144 | |
1ab60e0f VG |
145 | /* Due to ENTRY(), sometimes the empty space gets filled with |
146 | * zeros. Better take a jmp than relying on empty space being | |
147 | * filled with 0x90 (nop) | |
1da177e4 | 148 | */ |
1ab60e0f | 149 | jmp secondary_startup_64 |
90b1c208 | 150 | ENTRY(secondary_startup_64) |
1ab60e0f VG |
151 | /* |
152 | * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 1, | |
153 | * and someone has loaded a mapped page table. | |
154 | * | |
155 | * %esi holds a physical pointer to real_mode_data. | |
156 | * | |
157 | * We come here either from startup_64 (using physical addresses) | |
158 | * or from trampoline.S (using virtual addresses). | |
159 | * | |
160 | * Using virtual addresses from trampoline.S removes the need | |
161 | * to have any identity mapped pages in the kernel page table | |
162 | * after the boot processor executes this code. | |
1da177e4 LT |
163 | */ |
164 | ||
165 | /* Enable PAE mode and PGE */ | |
05139d8f | 166 | movl $(X86_CR4_PAE | X86_CR4_PGE), %eax |
1da177e4 LT |
167 | movq %rax, %cr4 |
168 | ||
169 | /* Setup early boot stage 4 level pagetables. */ | |
cfd243d4 | 170 | movq $(init_level4_pgt - __START_KERNEL_map), %rax |
1ab60e0f | 171 | addq phys_base(%rip), %rax |
1da177e4 LT |
172 | movq %rax, %cr3 |
173 | ||
1ab60e0f VG |
174 | /* Ensure I am executing from virtual addresses */ |
175 | movq $1f, %rax | |
176 | jmp *%rax | |
177 | 1: | |
178 | ||
1da177e4 LT |
179 | /* Check if nx is implemented */ |
180 | movl $0x80000001, %eax | |
181 | cpuid | |
182 | movl %edx,%edi | |
183 | ||
184 | /* Setup EFER (Extended Feature Enable Register) */ | |
185 | movl $MSR_EFER, %ecx | |
186 | rdmsr | |
1ab60e0f VG |
187 | btsl $_EFER_SCE, %eax /* Enable System Call */ |
188 | btl $20,%edi /* No Execute supported? */ | |
1da177e4 LT |
189 | jnc 1f |
190 | btsl $_EFER_NX, %eax | |
1ab60e0f | 191 | 1: wrmsr /* Make changes effective */ |
1da177e4 LT |
192 | |
193 | /* Setup cr0 */ | |
369101da CG |
194 | #define CR0_STATE (X86_CR0_PE | X86_CR0_MP | X86_CR0_ET | \ |
195 | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM | \ | |
196 | X86_CR0_PG) | |
197 | movl $CR0_STATE, %eax | |
1da177e4 LT |
198 | /* Make changes effective */ |
199 | movq %rax, %cr0 | |
200 | ||
201 | /* Setup a boot time stack */ | |
9cf4f298 | 202 | movq stack_start(%rip),%rsp |
1da177e4 LT |
203 | |
204 | /* zero EFLAGS after setting rsp */ | |
205 | pushq $0 | |
206 | popfq | |
207 | ||
3e5d8f97 TH |
208 | #ifdef CONFIG_SMP |
209 | /* | |
8c7e58e6 BG |
210 | * Fix up static pointers that need __per_cpu_load added. The assembler |
211 | * is unable to do this directly. This is only needed for the boot cpu. | |
212 | * These values are set up with the correct base addresses by C code for | |
213 | * secondary cpus. | |
3e5d8f97 | 214 | */ |
8c7e58e6 BG |
215 | movq initial_gs(%rip), %rax |
216 | cmpl $0, per_cpu__cpu_number(%rax) | |
217 | jne 1f | |
218 | addq %rax, early_gdt_descr_base(%rip) | |
3e5d8f97 TH |
219 | 1: |
220 | #endif | |
1da177e4 LT |
221 | /* |
222 | * We must switch to a new descriptor in kernel space for the GDT | |
223 | * because soon the kernel won't have access anymore to the userspace | |
224 | * addresses where we're currently running on. We have to do that here | |
225 | * because in 32bit we couldn't load a 64bit linear address. | |
226 | */ | |
a939098a | 227 | lgdt early_gdt_descr(%rip) |
1da177e4 | 228 | |
ffb60175 ZA |
229 | /* set up data segments. actually 0 would do too */ |
230 | movl $__KERNEL_DS,%eax | |
231 | movl %eax,%ds | |
232 | movl %eax,%ss | |
233 | movl %eax,%es | |
234 | ||
235 | /* | |
236 | * We don't really need to load %fs or %gs, but load them anyway | |
237 | * to kill any stale realmode selectors. This allows execution | |
238 | * under VT hardware. | |
239 | */ | |
240 | movl %eax,%fs | |
241 | movl %eax,%gs | |
242 | ||
f32ff538 TH |
243 | /* Set up %gs. |
244 | * | |
947e76cd BG |
245 | * The base of %gs always points to the bottom of the irqstack |
246 | * union. If the stack protector canary is enabled, it is | |
247 | * located at %gs:40. Note that, on SMP, the boot cpu uses | |
248 | * init data section till per cpu areas are set up. | |
f32ff538 | 249 | */ |
1da177e4 | 250 | movl $MSR_GS_BASE,%ecx |
f32ff538 | 251 | movq initial_gs(%rip),%rax |
1da177e4 LT |
252 | movq %rax,%rdx |
253 | shrq $32,%rdx | |
254 | wrmsr | |
255 | ||
1da177e4 LT |
256 | /* esi is pointer to real mode structure with interesting info. |
257 | pass it to C */ | |
258 | movl %esi, %edi | |
259 | ||
260 | /* Finally jump to run C code and to be on real kernel address | |
261 | * Since we are running on identity-mapped space we have to jump | |
26374c7b EB |
262 | * to the full 64bit address, this is only possible as indirect |
263 | * jump. In addition we need to ensure %cs is set so we make this | |
264 | * a far return. | |
1da177e4 LT |
265 | */ |
266 | movq initial_code(%rip),%rax | |
26374c7b EB |
267 | pushq $0 # fake return address to stop unwinder |
268 | pushq $__KERNEL_CS # set correct cs | |
269 | pushq %rax # target address in negative space | |
270 | lretq | |
1da177e4 | 271 | |
e57113bc | 272 | /* SMP bootup changes these two */ |
da5968ae | 273 | __REFDATA |
e57113bc | 274 | .align 8 |
f1fbabb3 | 275 | ENTRY(initial_code) |
1da177e4 | 276 | .quad x86_64_start_kernel |
f32ff538 | 277 | ENTRY(initial_gs) |
1a51e3a0 TH |
278 | #ifdef CONFIG_SMP |
279 | .quad __per_cpu_load | |
280 | #else | |
947e76cd | 281 | .quad PER_CPU_VAR(irq_stack_union) |
1a51e3a0 | 282 | #endif |
f1fbabb3 SR |
283 | __FINITDATA |
284 | ||
9cf4f298 | 285 | ENTRY(stack_start) |
1da177e4 | 286 | .quad init_thread_union+THREAD_SIZE-8 |
9cf4f298 | 287 | .word 0 |
1da177e4 | 288 | |
1ab60e0f VG |
289 | bad_address: |
290 | jmp bad_address | |
291 | ||
41bd4eac | 292 | .section ".init.text","ax" |
076f9776 | 293 | #ifdef CONFIG_EARLY_PRINTK |
8866cd9d RM |
294 | .globl early_idt_handlers |
295 | early_idt_handlers: | |
749c970a AK |
296 | i = 0 |
297 | .rept NUM_EXCEPTION_VECTORS | |
298 | movl $i, %esi | |
299 | jmp early_idt_handler | |
300 | i = i + 1 | |
301 | .endr | |
076f9776 | 302 | #endif |
8866cd9d | 303 | |
1da177e4 | 304 | ENTRY(early_idt_handler) |
076f9776 | 305 | #ifdef CONFIG_EARLY_PRINTK |
b957591f AK |
306 | cmpl $2,early_recursion_flag(%rip) |
307 | jz 1f | |
308 | incl early_recursion_flag(%rip) | |
49a69787 | 309 | GET_CR2_INTO_RCX |
8866cd9d RM |
310 | movq %rcx,%r9 |
311 | xorl %r8d,%r8d # zero for error code | |
312 | movl %esi,%ecx # get vector number | |
313 | # Test %ecx against mask of vectors that push error code. | |
314 | cmpl $31,%ecx | |
315 | ja 0f | |
316 | movl $1,%eax | |
317 | salq %cl,%rax | |
318 | testl $0x27d00,%eax | |
319 | je 0f | |
320 | popq %r8 # get error code | |
321 | 0: movq 0(%rsp),%rcx # get ip | |
322 | movq 8(%rsp),%rdx # get cs | |
323 | xorl %eax,%eax | |
1da177e4 LT |
324 | leaq early_idt_msg(%rip),%rdi |
325 | call early_printk | |
b957591f AK |
326 | cmpl $2,early_recursion_flag(%rip) |
327 | jz 1f | |
328 | call dump_stack | |
6574ffd7 AK |
329 | #ifdef CONFIG_KALLSYMS |
330 | leaq early_idt_ripmsg(%rip),%rdi | |
7aed55d1 | 331 | movq 0(%rsp),%rsi # get rip again |
6574ffd7 AK |
332 | call __print_symbol |
333 | #endif | |
076f9776 | 334 | #endif /* EARLY_PRINTK */ |
1da177e4 LT |
335 | 1: hlt |
336 | jmp 1b | |
076f9776 IM |
337 | |
338 | #ifdef CONFIG_EARLY_PRINTK | |
b957591f AK |
339 | early_recursion_flag: |
340 | .long 0 | |
1da177e4 LT |
341 | |
342 | early_idt_msg: | |
8866cd9d | 343 | .asciz "PANIC: early exception %02lx rip %lx:%lx error %lx cr2 %lx\n" |
6574ffd7 AK |
344 | early_idt_ripmsg: |
345 | .asciz "RIP %s\n" | |
076f9776 | 346 | #endif /* CONFIG_EARLY_PRINTK */ |
41bd4eac | 347 | .previous |
1da177e4 | 348 | |
1ab60e0f | 349 | .balign PAGE_SIZE |
1da177e4 | 350 | |
f0cf5d1a | 351 | #define NEXT_PAGE(name) \ |
67dcbb6b | 352 | .balign PAGE_SIZE; \ |
f0cf5d1a JB |
353 | ENTRY(name) |
354 | ||
67dcbb6b | 355 | /* Automate the creation of 1 to 1 mapping pmd entries */ |
0e192b99 CG |
356 | #define PMDS(START, PERM, COUNT) \ |
357 | i = 0 ; \ | |
358 | .rept (COUNT) ; \ | |
359 | .quad (START) + (i << PMD_SHIFT) + (PERM) ; \ | |
360 | i = i + 1 ; \ | |
67dcbb6b VG |
361 | .endr |
362 | ||
cfd243d4 VG |
363 | /* |
364 | * This default setting generates an ident mapping at address 0x100000 | |
365 | * and a mapping for the kernel that precisely maps virtual address | |
366 | * 0xffffffff80000000 to physical address 0x000000. (always using | |
367 | * 2Mbyte large pages provided by PAE mode) | |
368 | */ | |
f0cf5d1a | 369 | NEXT_PAGE(init_level4_pgt) |
cfd243d4 | 370 | .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE |
a6523748 | 371 | .org init_level4_pgt + L4_PAGE_OFFSET*8, 0 |
cfd243d4 | 372 | .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE |
a6523748 | 373 | .org init_level4_pgt + L4_START_KERNEL*8, 0 |
cfd243d4 VG |
374 | /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */ |
375 | .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE | |
1da177e4 | 376 | |
f0cf5d1a | 377 | NEXT_PAGE(level3_ident_pgt) |
67dcbb6b | 378 | .quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE |
1da177e4 LT |
379 | .fill 511,8,0 |
380 | ||
f0cf5d1a | 381 | NEXT_PAGE(level3_kernel_pgt) |
a6523748 | 382 | .fill L3_START_KERNEL,8,0 |
1da177e4 | 383 | /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */ |
67dcbb6b | 384 | .quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE |
b1c931e3 EB |
385 | .quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE |
386 | ||
387 | NEXT_PAGE(level2_fixmap_pgt) | |
6596f242 IM |
388 | .fill 506,8,0 |
389 | .quad level1_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE | |
390 | /* 8MB reserved for vsyscalls + a 2MB hole = 4 + 1 entries */ | |
391 | .fill 5,8,0 | |
392 | ||
393 | NEXT_PAGE(level1_fixmap_pgt) | |
b1c931e3 | 394 | .fill 512,8,0 |
1da177e4 | 395 | |
f0cf5d1a | 396 | NEXT_PAGE(level2_ident_pgt) |
67dcbb6b VG |
397 | /* Since I easily can, map the first 1G. |
398 | * Don't set NX because code runs from these pages. | |
399 | */ | |
b2bc2731 | 400 | PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD) |
1ab60e0f | 401 | |
f0cf5d1a | 402 | NEXT_PAGE(level2_kernel_pgt) |
88f3aec7 | 403 | /* |
85eb69a1 | 404 | * 512 MB kernel mapping. We spend a full page on this pagetable |
88f3aec7 IM |
405 | * anyway. |
406 | * | |
407 | * The kernel code+data+bss must not be bigger than that. | |
408 | * | |
85eb69a1 | 409 | * (NOTE: at +512MB starts the module area, see MODULES_VADDR. |
88f3aec7 IM |
410 | * If you want to increase this then increase MODULES_VADDR |
411 | * too.) | |
412 | */ | |
8490638c | 413 | PMDS(0, __PAGE_KERNEL_LARGE_EXEC, |
d4afe414 | 414 | KERNEL_IMAGE_SIZE/PMD_SIZE) |
1da177e4 | 415 | |
1ab60e0f | 416 | NEXT_PAGE(level2_spare_pgt) |
88f3aec7 | 417 | .fill 512, 8, 0 |
1ab60e0f | 418 | |
67dcbb6b | 419 | #undef PMDS |
f0cf5d1a | 420 | #undef NEXT_PAGE |
1da177e4 | 421 | |
f0cf5d1a | 422 | .data |
1da177e4 | 423 | .align 16 |
a939098a GC |
424 | .globl early_gdt_descr |
425 | early_gdt_descr: | |
426 | .word GDT_ENTRIES*8-1 | |
3e5d8f97 | 427 | early_gdt_descr_base: |
3e5d8f97 | 428 | .quad per_cpu__gdt_page |
1da177e4 | 429 | |
1ab60e0f VG |
430 | ENTRY(phys_base) |
431 | /* This must match the first entry in level2_kernel_pgt */ | |
432 | .quad 0x0000000000000000 | |
433 | ||
8c5e5ac3 | 434 | #include "../../x86/xen/xen-head.S" |
1da177e4 | 435 | |
e57113bc JB |
436 | .section .bss, "aw", @nobits |
437 | .align L1_CACHE_BYTES | |
438 | ENTRY(idt_table) | |
439 | .skip 256 * 16 | |
1da177e4 | 440 | |
e57113bc JB |
441 | .section .bss.page_aligned, "aw", @nobits |
442 | .align PAGE_SIZE | |
443 | ENTRY(empty_zero_page) | |
444 | .skip PAGE_SIZE |