Commit | Line | Data |
---|---|---|
5d0cf410 | 1 | #include <linux/clocksource.h> |
e9e2cdb4 | 2 | #include <linux/clockchips.h> |
4588c1f0 IM |
3 | #include <linux/interrupt.h> |
4 | #include <linux/sysdev.h> | |
28769149 | 5 | #include <linux/delay.h> |
5d0cf410 | 6 | #include <linux/errno.h> |
5a0e3ad6 | 7 | #include <linux/slab.h> |
5d0cf410 | 8 | #include <linux/hpet.h> |
9 | #include <linux/init.h> | |
58ac1e76 | 10 | #include <linux/cpu.h> |
4588c1f0 IM |
11 | #include <linux/pm.h> |
12 | #include <linux/io.h> | |
5d0cf410 | 13 | |
28769149 | 14 | #include <asm/fixmap.h> |
06a24dec | 15 | #include <asm/i8253.h> |
4588c1f0 | 16 | #include <asm/hpet.h> |
5d0cf410 | 17 | |
4588c1f0 | 18 | #define HPET_MASK CLOCKSOURCE_MASK(32) |
5d0cf410 | 19 | |
b10db7f0 PM |
20 | /* FSEC = 10^-15 |
21 | NSEC = 10^-9 */ | |
4588c1f0 | 22 | #define FSEC_PER_NSEC 1000000L |
5d0cf410 | 23 | |
26afe5f2 | 24 | #define HPET_DEV_USED_BIT 2 |
25 | #define HPET_DEV_USED (1 << HPET_DEV_USED_BIT) | |
26 | #define HPET_DEV_VALID 0x8 | |
27 | #define HPET_DEV_FSB_CAP 0x1000 | |
28 | #define HPET_DEV_PERI_CAP 0x2000 | |
29 | ||
f1c18071 TG |
30 | #define HPET_MIN_CYCLES 128 |
31 | #define HPET_MIN_PROG_DELTA (HPET_MIN_CYCLES + (HPET_MIN_CYCLES >> 1)) | |
32 | ||
26afe5f2 | 33 | #define EVT_TO_HPET_DEV(evt) container_of(evt, struct hpet_dev, evt) |
34 | ||
e9e2cdb4 TG |
35 | /* |
36 | * HPET address is set in acpi/boot.c, when an ACPI entry exists | |
37 | */ | |
4588c1f0 | 38 | unsigned long hpet_address; |
c8bc6f3c | 39 | u8 hpet_blockid; /* OS timer block num */ |
73472a46 PV |
40 | u8 hpet_msi_disable; |
41 | ||
e951e4af | 42 | #ifdef CONFIG_PCI_MSI |
3b71e9e3 | 43 | static unsigned long hpet_num_timers; |
e951e4af | 44 | #endif |
4588c1f0 | 45 | static void __iomem *hpet_virt_address; |
e9e2cdb4 | 46 | |
58ac1e76 | 47 | struct hpet_dev { |
4588c1f0 IM |
48 | struct clock_event_device evt; |
49 | unsigned int num; | |
50 | int cpu; | |
51 | unsigned int irq; | |
52 | unsigned int flags; | |
53 | char name[10]; | |
58ac1e76 | 54 | }; |
55 | ||
5946fa3d | 56 | inline unsigned int hpet_readl(unsigned int a) |
e9e2cdb4 TG |
57 | { |
58 | return readl(hpet_virt_address + a); | |
59 | } | |
60 | ||
5946fa3d | 61 | static inline void hpet_writel(unsigned int d, unsigned int a) |
e9e2cdb4 TG |
62 | { |
63 | writel(d, hpet_virt_address + a); | |
64 | } | |
65 | ||
28769149 | 66 | #ifdef CONFIG_X86_64 |
28769149 | 67 | #include <asm/pgtable.h> |
2387ce57 | 68 | #endif |
28769149 | 69 | |
06a24dec TG |
70 | static inline void hpet_set_mapping(void) |
71 | { | |
72 | hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE); | |
2387ce57 YL |
73 | #ifdef CONFIG_X86_64 |
74 | __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VSYSCALL_NOCACHE); | |
75 | #endif | |
06a24dec TG |
76 | } |
77 | ||
78 | static inline void hpet_clear_mapping(void) | |
79 | { | |
80 | iounmap(hpet_virt_address); | |
81 | hpet_virt_address = NULL; | |
82 | } | |
83 | ||
e9e2cdb4 TG |
84 | /* |
85 | * HPET command line enable / disable | |
86 | */ | |
87 | static int boot_hpet_disable; | |
b17530bd | 88 | int hpet_force_user; |
b98103a5 | 89 | static int hpet_verbose; |
e9e2cdb4 | 90 | |
4588c1f0 | 91 | static int __init hpet_setup(char *str) |
e9e2cdb4 TG |
92 | { |
93 | if (str) { | |
94 | if (!strncmp("disable", str, 7)) | |
95 | boot_hpet_disable = 1; | |
b17530bd TG |
96 | if (!strncmp("force", str, 5)) |
97 | hpet_force_user = 1; | |
b98103a5 AH |
98 | if (!strncmp("verbose", str, 7)) |
99 | hpet_verbose = 1; | |
e9e2cdb4 TG |
100 | } |
101 | return 1; | |
102 | } | |
103 | __setup("hpet=", hpet_setup); | |
104 | ||
28769149 TG |
105 | static int __init disable_hpet(char *str) |
106 | { | |
107 | boot_hpet_disable = 1; | |
108 | return 1; | |
109 | } | |
110 | __setup("nohpet", disable_hpet); | |
111 | ||
e9e2cdb4 TG |
112 | static inline int is_hpet_capable(void) |
113 | { | |
4588c1f0 | 114 | return !boot_hpet_disable && hpet_address; |
e9e2cdb4 TG |
115 | } |
116 | ||
117 | /* | |
118 | * HPET timer interrupt enable / disable | |
119 | */ | |
120 | static int hpet_legacy_int_enabled; | |
121 | ||
122 | /** | |
123 | * is_hpet_enabled - check whether the hpet timer interrupt is enabled | |
124 | */ | |
125 | int is_hpet_enabled(void) | |
126 | { | |
127 | return is_hpet_capable() && hpet_legacy_int_enabled; | |
128 | } | |
1bdbdaac | 129 | EXPORT_SYMBOL_GPL(is_hpet_enabled); |
e9e2cdb4 | 130 | |
b98103a5 AH |
131 | static void _hpet_print_config(const char *function, int line) |
132 | { | |
133 | u32 i, timers, l, h; | |
134 | printk(KERN_INFO "hpet: %s(%d):\n", function, line); | |
135 | l = hpet_readl(HPET_ID); | |
136 | h = hpet_readl(HPET_PERIOD); | |
137 | timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1; | |
138 | printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h); | |
139 | l = hpet_readl(HPET_CFG); | |
140 | h = hpet_readl(HPET_STATUS); | |
141 | printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h); | |
142 | l = hpet_readl(HPET_COUNTER); | |
143 | h = hpet_readl(HPET_COUNTER+4); | |
144 | printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h); | |
145 | ||
146 | for (i = 0; i < timers; i++) { | |
147 | l = hpet_readl(HPET_Tn_CFG(i)); | |
148 | h = hpet_readl(HPET_Tn_CFG(i)+4); | |
149 | printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n", | |
150 | i, l, h); | |
151 | l = hpet_readl(HPET_Tn_CMP(i)); | |
152 | h = hpet_readl(HPET_Tn_CMP(i)+4); | |
153 | printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n", | |
154 | i, l, h); | |
155 | l = hpet_readl(HPET_Tn_ROUTE(i)); | |
156 | h = hpet_readl(HPET_Tn_ROUTE(i)+4); | |
157 | printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n", | |
158 | i, l, h); | |
159 | } | |
160 | } | |
161 | ||
162 | #define hpet_print_config() \ | |
163 | do { \ | |
164 | if (hpet_verbose) \ | |
165 | _hpet_print_config(__FUNCTION__, __LINE__); \ | |
166 | } while (0) | |
167 | ||
e9e2cdb4 TG |
168 | /* |
169 | * When the hpet driver (/dev/hpet) is enabled, we need to reserve | |
170 | * timer 0 and timer 1 in case of RTC emulation. | |
171 | */ | |
172 | #ifdef CONFIG_HPET | |
f0ed4e69 | 173 | |
5f79f2f2 | 174 | static void hpet_reserve_msi_timers(struct hpet_data *hd); |
f0ed4e69 | 175 | |
5946fa3d | 176 | static void hpet_reserve_platform_timers(unsigned int id) |
e9e2cdb4 TG |
177 | { |
178 | struct hpet __iomem *hpet = hpet_virt_address; | |
37a47db8 BR |
179 | struct hpet_timer __iomem *timer = &hpet->hpet_timers[2]; |
180 | unsigned int nrtimers, i; | |
e9e2cdb4 TG |
181 | struct hpet_data hd; |
182 | ||
183 | nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1; | |
184 | ||
4588c1f0 IM |
185 | memset(&hd, 0, sizeof(hd)); |
186 | hd.hd_phys_address = hpet_address; | |
187 | hd.hd_address = hpet; | |
188 | hd.hd_nirqs = nrtimers; | |
e9e2cdb4 TG |
189 | hpet_reserve_timer(&hd, 0); |
190 | ||
191 | #ifdef CONFIG_HPET_EMULATE_RTC | |
192 | hpet_reserve_timer(&hd, 1); | |
193 | #endif | |
5761d64b | 194 | |
64a76f66 DB |
195 | /* |
196 | * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254 | |
197 | * is wrong for i8259!) not the output IRQ. Many BIOS writers | |
198 | * don't bother configuring *any* comparator interrupts. | |
199 | */ | |
e9e2cdb4 TG |
200 | hd.hd_irq[0] = HPET_LEGACY_8254; |
201 | hd.hd_irq[1] = HPET_LEGACY_RTC; | |
202 | ||
fc3fbc45 | 203 | for (i = 2; i < nrtimers; timer++, i++) { |
4588c1f0 IM |
204 | hd.hd_irq[i] = (readl(&timer->hpet_config) & |
205 | Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT; | |
fc3fbc45 | 206 | } |
5761d64b | 207 | |
f0ed4e69 | 208 | hpet_reserve_msi_timers(&hd); |
26afe5f2 | 209 | |
e9e2cdb4 | 210 | hpet_alloc(&hd); |
5761d64b | 211 | |
e9e2cdb4 TG |
212 | } |
213 | #else | |
5946fa3d | 214 | static void hpet_reserve_platform_timers(unsigned int id) { } |
e9e2cdb4 TG |
215 | #endif |
216 | ||
217 | /* | |
218 | * Common hpet info | |
219 | */ | |
220 | static unsigned long hpet_period; | |
221 | ||
610bf2f1 | 222 | static void hpet_legacy_set_mode(enum clock_event_mode mode, |
e9e2cdb4 | 223 | struct clock_event_device *evt); |
610bf2f1 | 224 | static int hpet_legacy_next_event(unsigned long delta, |
e9e2cdb4 TG |
225 | struct clock_event_device *evt); |
226 | ||
227 | /* | |
228 | * The hpet clock event device | |
229 | */ | |
230 | static struct clock_event_device hpet_clockevent = { | |
231 | .name = "hpet", | |
232 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | |
610bf2f1 VP |
233 | .set_mode = hpet_legacy_set_mode, |
234 | .set_next_event = hpet_legacy_next_event, | |
e9e2cdb4 TG |
235 | .shift = 32, |
236 | .irq = 0, | |
59c69f2a | 237 | .rating = 50, |
e9e2cdb4 TG |
238 | }; |
239 | ||
8d6f0c82 | 240 | static void hpet_stop_counter(void) |
e9e2cdb4 TG |
241 | { |
242 | unsigned long cfg = hpet_readl(HPET_CFG); | |
e9e2cdb4 TG |
243 | cfg &= ~HPET_CFG_ENABLE; |
244 | hpet_writel(cfg, HPET_CFG); | |
7a6f9cbb AH |
245 | } |
246 | ||
247 | static void hpet_reset_counter(void) | |
248 | { | |
e9e2cdb4 TG |
249 | hpet_writel(0, HPET_COUNTER); |
250 | hpet_writel(0, HPET_COUNTER + 4); | |
8d6f0c82 AH |
251 | } |
252 | ||
253 | static void hpet_start_counter(void) | |
254 | { | |
5946fa3d | 255 | unsigned int cfg = hpet_readl(HPET_CFG); |
e9e2cdb4 TG |
256 | cfg |= HPET_CFG_ENABLE; |
257 | hpet_writel(cfg, HPET_CFG); | |
258 | } | |
259 | ||
8d6f0c82 AH |
260 | static void hpet_restart_counter(void) |
261 | { | |
262 | hpet_stop_counter(); | |
7a6f9cbb | 263 | hpet_reset_counter(); |
8d6f0c82 AH |
264 | hpet_start_counter(); |
265 | } | |
266 | ||
59c69f2a VP |
267 | static void hpet_resume_device(void) |
268 | { | |
bfe0c1cc | 269 | force_hpet_resume(); |
59c69f2a VP |
270 | } |
271 | ||
17622339 | 272 | static void hpet_resume_counter(struct clocksource *cs) |
59c69f2a VP |
273 | { |
274 | hpet_resume_device(); | |
8d6f0c82 | 275 | hpet_restart_counter(); |
59c69f2a VP |
276 | } |
277 | ||
610bf2f1 | 278 | static void hpet_enable_legacy_int(void) |
e9e2cdb4 | 279 | { |
5946fa3d | 280 | unsigned int cfg = hpet_readl(HPET_CFG); |
e9e2cdb4 TG |
281 | |
282 | cfg |= HPET_CFG_LEGACY; | |
283 | hpet_writel(cfg, HPET_CFG); | |
284 | hpet_legacy_int_enabled = 1; | |
285 | } | |
286 | ||
610bf2f1 VP |
287 | static void hpet_legacy_clockevent_register(void) |
288 | { | |
610bf2f1 VP |
289 | /* Start HPET legacy interrupts */ |
290 | hpet_enable_legacy_int(); | |
291 | ||
292 | /* | |
6fd592da CM |
293 | * The mult factor is defined as (include/linux/clockchips.h) |
294 | * mult/2^shift = cyc/ns (in contrast to ns/cyc in clocksource.h) | |
295 | * hpet_period is in units of femtoseconds (per cycle), so | |
296 | * mult/2^shift = cyc/ns = 10^6/hpet_period | |
297 | * mult = (10^6 * 2^shift)/hpet_period | |
298 | * mult = (FSEC_PER_NSEC << hpet_clockevent.shift)/hpet_period | |
610bf2f1 | 299 | */ |
6fd592da CM |
300 | hpet_clockevent.mult = div_sc((unsigned long) FSEC_PER_NSEC, |
301 | hpet_period, hpet_clockevent.shift); | |
610bf2f1 VP |
302 | /* Calculate the min / max delta */ |
303 | hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF, | |
304 | &hpet_clockevent); | |
f1c18071 TG |
305 | /* Setup minimum reprogramming delta. */ |
306 | hpet_clockevent.min_delta_ns = clockevent_delta2ns(HPET_MIN_PROG_DELTA, | |
307 | &hpet_clockevent); | |
610bf2f1 VP |
308 | |
309 | /* | |
310 | * Start hpet with the boot cpu mask and make it | |
311 | * global after the IO_APIC has been initialized. | |
312 | */ | |
320ab2b0 | 313 | hpet_clockevent.cpumask = cpumask_of(smp_processor_id()); |
610bf2f1 VP |
314 | clockevents_register_device(&hpet_clockevent); |
315 | global_clock_event = &hpet_clockevent; | |
316 | printk(KERN_DEBUG "hpet clockevent registered\n"); | |
317 | } | |
318 | ||
26afe5f2 | 319 | static int hpet_setup_msi_irq(unsigned int irq); |
320 | ||
b40d575b | 321 | static void hpet_set_mode(enum clock_event_mode mode, |
322 | struct clock_event_device *evt, int timer) | |
e9e2cdb4 | 323 | { |
5946fa3d | 324 | unsigned int cfg, cmp, now; |
e9e2cdb4 TG |
325 | uint64_t delta; |
326 | ||
4588c1f0 | 327 | switch (mode) { |
e9e2cdb4 | 328 | case CLOCK_EVT_MODE_PERIODIC: |
c23e253e | 329 | hpet_stop_counter(); |
b40d575b | 330 | delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult; |
331 | delta >>= evt->shift; | |
7a6f9cbb | 332 | now = hpet_readl(HPET_COUNTER); |
5946fa3d | 333 | cmp = now + (unsigned int) delta; |
b40d575b | 334 | cfg = hpet_readl(HPET_Tn_CFG(timer)); |
b13e2464 | 335 | /* Make sure we use edge triggered interrupts */ |
336 | cfg &= ~HPET_TN_LEVEL; | |
e9e2cdb4 TG |
337 | cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | |
338 | HPET_TN_SETVAL | HPET_TN_32BIT; | |
b40d575b | 339 | hpet_writel(cfg, HPET_Tn_CFG(timer)); |
7a6f9cbb AH |
340 | hpet_writel(cmp, HPET_Tn_CMP(timer)); |
341 | udelay(1); | |
342 | /* | |
343 | * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL | |
344 | * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL | |
345 | * bit is automatically cleared after the first write. | |
346 | * (See AMD-8111 HyperTransport I/O Hub Data Sheet, | |
347 | * Publication # 24674) | |
348 | */ | |
5946fa3d | 349 | hpet_writel((unsigned int) delta, HPET_Tn_CMP(timer)); |
c23e253e | 350 | hpet_start_counter(); |
b98103a5 | 351 | hpet_print_config(); |
e9e2cdb4 TG |
352 | break; |
353 | ||
354 | case CLOCK_EVT_MODE_ONESHOT: | |
b40d575b | 355 | cfg = hpet_readl(HPET_Tn_CFG(timer)); |
e9e2cdb4 TG |
356 | cfg &= ~HPET_TN_PERIODIC; |
357 | cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; | |
b40d575b | 358 | hpet_writel(cfg, HPET_Tn_CFG(timer)); |
e9e2cdb4 TG |
359 | break; |
360 | ||
361 | case CLOCK_EVT_MODE_UNUSED: | |
362 | case CLOCK_EVT_MODE_SHUTDOWN: | |
b40d575b | 363 | cfg = hpet_readl(HPET_Tn_CFG(timer)); |
e9e2cdb4 | 364 | cfg &= ~HPET_TN_ENABLE; |
b40d575b | 365 | hpet_writel(cfg, HPET_Tn_CFG(timer)); |
e9e2cdb4 | 366 | break; |
18de5bc4 TG |
367 | |
368 | case CLOCK_EVT_MODE_RESUME: | |
26afe5f2 | 369 | if (timer == 0) { |
370 | hpet_enable_legacy_int(); | |
371 | } else { | |
372 | struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); | |
373 | hpet_setup_msi_irq(hdev->irq); | |
374 | disable_irq(hdev->irq); | |
0de26520 | 375 | irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu)); |
26afe5f2 | 376 | enable_irq(hdev->irq); |
377 | } | |
b98103a5 | 378 | hpet_print_config(); |
18de5bc4 | 379 | break; |
e9e2cdb4 TG |
380 | } |
381 | } | |
382 | ||
b40d575b | 383 | static int hpet_next_event(unsigned long delta, |
384 | struct clock_event_device *evt, int timer) | |
e9e2cdb4 | 385 | { |
f7676254 | 386 | u32 cnt; |
995bd3bb | 387 | s32 res; |
e9e2cdb4 TG |
388 | |
389 | cnt = hpet_readl(HPET_COUNTER); | |
f7676254 | 390 | cnt += (u32) delta; |
b40d575b | 391 | hpet_writel(cnt, HPET_Tn_CMP(timer)); |
e9e2cdb4 | 392 | |
72d43d9b | 393 | /* |
995bd3bb TG |
394 | * HPETs are a complete disaster. The compare register is |
395 | * based on a equal comparison and neither provides a less | |
396 | * than or equal functionality (which would require to take | |
397 | * the wraparound into account) nor a simple count down event | |
398 | * mode. Further the write to the comparator register is | |
399 | * delayed internally up to two HPET clock cycles in certain | |
f1c18071 TG |
400 | * chipsets (ATI, ICH9,10). Some newer AMD chipsets have even |
401 | * longer delays. We worked around that by reading back the | |
402 | * compare register, but that required another workaround for | |
403 | * ICH9,10 chips where the first readout after write can | |
404 | * return the old stale value. We already had a minimum | |
405 | * programming delta of 5us enforced, but a NMI or SMI hitting | |
995bd3bb TG |
406 | * between the counter readout and the comparator write can |
407 | * move us behind that point easily. Now instead of reading | |
408 | * the compare register back several times, we make the ETIME | |
409 | * decision based on the following: Return ETIME if the | |
f1c18071 | 410 | * counter value after the write is less than HPET_MIN_CYCLES |
995bd3bb | 411 | * away from the event or if the counter is already ahead of |
f1c18071 TG |
412 | * the event. The minimum programming delta for the generic |
413 | * clockevents code is set to 1.5 * HPET_MIN_CYCLES. | |
72d43d9b | 414 | */ |
995bd3bb | 415 | res = (s32)(cnt - hpet_readl(HPET_COUNTER)); |
72d43d9b | 416 | |
f1c18071 | 417 | return res < HPET_MIN_CYCLES ? -ETIME : 0; |
e9e2cdb4 TG |
418 | } |
419 | ||
b40d575b | 420 | static void hpet_legacy_set_mode(enum clock_event_mode mode, |
421 | struct clock_event_device *evt) | |
422 | { | |
423 | hpet_set_mode(mode, evt, 0); | |
424 | } | |
425 | ||
426 | static int hpet_legacy_next_event(unsigned long delta, | |
427 | struct clock_event_device *evt) | |
428 | { | |
429 | return hpet_next_event(delta, evt, 0); | |
430 | } | |
431 | ||
58ac1e76 | 432 | /* |
433 | * HPET MSI Support | |
434 | */ | |
26afe5f2 | 435 | #ifdef CONFIG_PCI_MSI |
5f79f2f2 VP |
436 | |
437 | static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev); | |
438 | static struct hpet_dev *hpet_devs; | |
439 | ||
d0fbca8f | 440 | void hpet_msi_unmask(struct irq_data *data) |
58ac1e76 | 441 | { |
d0fbca8f | 442 | struct hpet_dev *hdev = data->handler_data; |
5946fa3d | 443 | unsigned int cfg; |
58ac1e76 | 444 | |
445 | /* unmask it */ | |
446 | cfg = hpet_readl(HPET_Tn_CFG(hdev->num)); | |
447 | cfg |= HPET_TN_FSB; | |
448 | hpet_writel(cfg, HPET_Tn_CFG(hdev->num)); | |
449 | } | |
450 | ||
d0fbca8f | 451 | void hpet_msi_mask(struct irq_data *data) |
58ac1e76 | 452 | { |
d0fbca8f | 453 | struct hpet_dev *hdev = data->handler_data; |
5946fa3d | 454 | unsigned int cfg; |
58ac1e76 | 455 | |
456 | /* mask it */ | |
457 | cfg = hpet_readl(HPET_Tn_CFG(hdev->num)); | |
458 | cfg &= ~HPET_TN_FSB; | |
459 | hpet_writel(cfg, HPET_Tn_CFG(hdev->num)); | |
460 | } | |
461 | ||
d0fbca8f | 462 | void hpet_msi_write(struct hpet_dev *hdev, struct msi_msg *msg) |
58ac1e76 | 463 | { |
58ac1e76 | 464 | hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num)); |
465 | hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4); | |
466 | } | |
467 | ||
d0fbca8f | 468 | void hpet_msi_read(struct hpet_dev *hdev, struct msi_msg *msg) |
58ac1e76 | 469 | { |
58ac1e76 | 470 | msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num)); |
471 | msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4); | |
472 | msg->address_hi = 0; | |
473 | } | |
474 | ||
26afe5f2 | 475 | static void hpet_msi_set_mode(enum clock_event_mode mode, |
476 | struct clock_event_device *evt) | |
477 | { | |
478 | struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); | |
479 | hpet_set_mode(mode, evt, hdev->num); | |
480 | } | |
481 | ||
482 | static int hpet_msi_next_event(unsigned long delta, | |
483 | struct clock_event_device *evt) | |
484 | { | |
485 | struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); | |
486 | return hpet_next_event(delta, evt, hdev->num); | |
487 | } | |
488 | ||
489 | static int hpet_setup_msi_irq(unsigned int irq) | |
490 | { | |
c8bc6f3c | 491 | if (arch_setup_hpet_msi(irq, hpet_blockid)) { |
26afe5f2 | 492 | destroy_irq(irq); |
493 | return -EINVAL; | |
494 | } | |
495 | return 0; | |
496 | } | |
497 | ||
498 | static int hpet_assign_irq(struct hpet_dev *dev) | |
499 | { | |
500 | unsigned int irq; | |
501 | ||
02198962 | 502 | irq = create_irq_nr(0, -1); |
26afe5f2 | 503 | if (!irq) |
504 | return -EINVAL; | |
505 | ||
2c778651 | 506 | irq_set_handler_data(irq, dev); |
26afe5f2 | 507 | |
508 | if (hpet_setup_msi_irq(irq)) | |
509 | return -EINVAL; | |
510 | ||
511 | dev->irq = irq; | |
512 | return 0; | |
513 | } | |
514 | ||
515 | static irqreturn_t hpet_interrupt_handler(int irq, void *data) | |
516 | { | |
517 | struct hpet_dev *dev = (struct hpet_dev *)data; | |
518 | struct clock_event_device *hevt = &dev->evt; | |
519 | ||
520 | if (!hevt->event_handler) { | |
521 | printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n", | |
522 | dev->num); | |
523 | return IRQ_HANDLED; | |
524 | } | |
525 | ||
526 | hevt->event_handler(hevt); | |
527 | return IRQ_HANDLED; | |
528 | } | |
529 | ||
530 | static int hpet_setup_irq(struct hpet_dev *dev) | |
531 | { | |
532 | ||
533 | if (request_irq(dev->irq, hpet_interrupt_handler, | |
507fa3a3 TG |
534 | IRQF_TIMER | IRQF_DISABLED | IRQF_NOBALANCING, |
535 | dev->name, dev)) | |
26afe5f2 | 536 | return -1; |
537 | ||
538 | disable_irq(dev->irq); | |
0de26520 | 539 | irq_set_affinity(dev->irq, cpumask_of(dev->cpu)); |
26afe5f2 | 540 | enable_irq(dev->irq); |
541 | ||
c81bba49 YL |
542 | printk(KERN_DEBUG "hpet: %s irq %d for MSI\n", |
543 | dev->name, dev->irq); | |
544 | ||
26afe5f2 | 545 | return 0; |
546 | } | |
547 | ||
548 | /* This should be called in specific @cpu */ | |
549 | static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu) | |
550 | { | |
551 | struct clock_event_device *evt = &hdev->evt; | |
552 | uint64_t hpet_freq; | |
553 | ||
554 | WARN_ON(cpu != smp_processor_id()); | |
555 | if (!(hdev->flags & HPET_DEV_VALID)) | |
556 | return; | |
557 | ||
558 | if (hpet_setup_msi_irq(hdev->irq)) | |
559 | return; | |
560 | ||
561 | hdev->cpu = cpu; | |
562 | per_cpu(cpu_hpet_dev, cpu) = hdev; | |
563 | evt->name = hdev->name; | |
564 | hpet_setup_irq(hdev); | |
565 | evt->irq = hdev->irq; | |
566 | ||
567 | evt->rating = 110; | |
568 | evt->features = CLOCK_EVT_FEAT_ONESHOT; | |
569 | if (hdev->flags & HPET_DEV_PERI_CAP) | |
570 | evt->features |= CLOCK_EVT_FEAT_PERIODIC; | |
571 | ||
572 | evt->set_mode = hpet_msi_set_mode; | |
573 | evt->set_next_event = hpet_msi_next_event; | |
574 | evt->shift = 32; | |
575 | ||
576 | /* | |
577 | * The period is a femto seconds value. We need to calculate the | |
578 | * scaled math multiplication factor for nanosecond to hpet tick | |
579 | * conversion. | |
580 | */ | |
4936a3b9 | 581 | hpet_freq = FSEC_PER_SEC; |
26afe5f2 | 582 | do_div(hpet_freq, hpet_period); |
583 | evt->mult = div_sc((unsigned long) hpet_freq, | |
584 | NSEC_PER_SEC, evt->shift); | |
585 | /* Calculate the max delta */ | |
586 | evt->max_delta_ns = clockevent_delta2ns(0x7FFFFFFF, evt); | |
587 | /* 5 usec minimum reprogramming delta. */ | |
588 | evt->min_delta_ns = 5000; | |
589 | ||
320ab2b0 | 590 | evt->cpumask = cpumask_of(hdev->cpu); |
26afe5f2 | 591 | clockevents_register_device(evt); |
592 | } | |
593 | ||
594 | #ifdef CONFIG_HPET | |
595 | /* Reserve at least one timer for userspace (/dev/hpet) */ | |
596 | #define RESERVE_TIMERS 1 | |
597 | #else | |
598 | #define RESERVE_TIMERS 0 | |
599 | #endif | |
5f79f2f2 VP |
600 | |
601 | static void hpet_msi_capability_lookup(unsigned int start_timer) | |
26afe5f2 | 602 | { |
603 | unsigned int id; | |
604 | unsigned int num_timers; | |
605 | unsigned int num_timers_used = 0; | |
606 | int i; | |
607 | ||
73472a46 PV |
608 | if (hpet_msi_disable) |
609 | return; | |
610 | ||
39fe05e5 SL |
611 | if (boot_cpu_has(X86_FEATURE_ARAT)) |
612 | return; | |
26afe5f2 | 613 | id = hpet_readl(HPET_ID); |
614 | ||
615 | num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT); | |
616 | num_timers++; /* Value read out starts from 0 */ | |
b98103a5 | 617 | hpet_print_config(); |
26afe5f2 | 618 | |
619 | hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL); | |
620 | if (!hpet_devs) | |
621 | return; | |
622 | ||
623 | hpet_num_timers = num_timers; | |
624 | ||
625 | for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) { | |
626 | struct hpet_dev *hdev = &hpet_devs[num_timers_used]; | |
5946fa3d | 627 | unsigned int cfg = hpet_readl(HPET_Tn_CFG(i)); |
26afe5f2 | 628 | |
629 | /* Only consider HPET timer with MSI support */ | |
630 | if (!(cfg & HPET_TN_FSB_CAP)) | |
631 | continue; | |
632 | ||
633 | hdev->flags = 0; | |
634 | if (cfg & HPET_TN_PERIODIC_CAP) | |
635 | hdev->flags |= HPET_DEV_PERI_CAP; | |
636 | hdev->num = i; | |
637 | ||
638 | sprintf(hdev->name, "hpet%d", i); | |
639 | if (hpet_assign_irq(hdev)) | |
640 | continue; | |
641 | ||
642 | hdev->flags |= HPET_DEV_FSB_CAP; | |
643 | hdev->flags |= HPET_DEV_VALID; | |
644 | num_timers_used++; | |
645 | if (num_timers_used == num_possible_cpus()) | |
646 | break; | |
647 | } | |
648 | ||
649 | printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n", | |
650 | num_timers, num_timers_used); | |
651 | } | |
652 | ||
5f79f2f2 VP |
653 | #ifdef CONFIG_HPET |
654 | static void hpet_reserve_msi_timers(struct hpet_data *hd) | |
655 | { | |
656 | int i; | |
657 | ||
658 | if (!hpet_devs) | |
659 | return; | |
660 | ||
661 | for (i = 0; i < hpet_num_timers; i++) { | |
662 | struct hpet_dev *hdev = &hpet_devs[i]; | |
663 | ||
664 | if (!(hdev->flags & HPET_DEV_VALID)) | |
665 | continue; | |
666 | ||
667 | hd->hd_irq[hdev->num] = hdev->irq; | |
668 | hpet_reserve_timer(hd, hdev->num); | |
669 | } | |
670 | } | |
671 | #endif | |
672 | ||
26afe5f2 | 673 | static struct hpet_dev *hpet_get_unused_timer(void) |
674 | { | |
675 | int i; | |
676 | ||
677 | if (!hpet_devs) | |
678 | return NULL; | |
679 | ||
680 | for (i = 0; i < hpet_num_timers; i++) { | |
681 | struct hpet_dev *hdev = &hpet_devs[i]; | |
682 | ||
683 | if (!(hdev->flags & HPET_DEV_VALID)) | |
684 | continue; | |
685 | if (test_and_set_bit(HPET_DEV_USED_BIT, | |
686 | (unsigned long *)&hdev->flags)) | |
687 | continue; | |
688 | return hdev; | |
689 | } | |
690 | return NULL; | |
691 | } | |
692 | ||
693 | struct hpet_work_struct { | |
694 | struct delayed_work work; | |
695 | struct completion complete; | |
696 | }; | |
697 | ||
698 | static void hpet_work(struct work_struct *w) | |
699 | { | |
700 | struct hpet_dev *hdev; | |
701 | int cpu = smp_processor_id(); | |
702 | struct hpet_work_struct *hpet_work; | |
703 | ||
704 | hpet_work = container_of(w, struct hpet_work_struct, work.work); | |
705 | ||
706 | hdev = hpet_get_unused_timer(); | |
707 | if (hdev) | |
708 | init_one_hpet_msi_clockevent(hdev, cpu); | |
709 | ||
710 | complete(&hpet_work->complete); | |
711 | } | |
712 | ||
713 | static int hpet_cpuhp_notify(struct notifier_block *n, | |
714 | unsigned long action, void *hcpu) | |
715 | { | |
716 | unsigned long cpu = (unsigned long)hcpu; | |
717 | struct hpet_work_struct work; | |
718 | struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu); | |
719 | ||
720 | switch (action & 0xf) { | |
721 | case CPU_ONLINE: | |
ca1cab37 | 722 | INIT_DELAYED_WORK_ONSTACK(&work.work, hpet_work); |
26afe5f2 | 723 | init_completion(&work.complete); |
724 | /* FIXME: add schedule_work_on() */ | |
725 | schedule_delayed_work_on(cpu, &work.work, 0); | |
726 | wait_for_completion(&work.complete); | |
336f6c32 | 727 | destroy_timer_on_stack(&work.work.timer); |
26afe5f2 | 728 | break; |
729 | case CPU_DEAD: | |
730 | if (hdev) { | |
731 | free_irq(hdev->irq, hdev); | |
732 | hdev->flags &= ~HPET_DEV_USED; | |
733 | per_cpu(cpu_hpet_dev, cpu) = NULL; | |
734 | } | |
735 | break; | |
736 | } | |
737 | return NOTIFY_OK; | |
738 | } | |
739 | #else | |
740 | ||
ba374c9b SN |
741 | static int hpet_setup_msi_irq(unsigned int irq) |
742 | { | |
743 | return 0; | |
744 | } | |
5f79f2f2 VP |
745 | static void hpet_msi_capability_lookup(unsigned int start_timer) |
746 | { | |
747 | return; | |
748 | } | |
749 | ||
750 | #ifdef CONFIG_HPET | |
751 | static void hpet_reserve_msi_timers(struct hpet_data *hd) | |
26afe5f2 | 752 | { |
753 | return; | |
754 | } | |
5f79f2f2 | 755 | #endif |
26afe5f2 | 756 | |
757 | static int hpet_cpuhp_notify(struct notifier_block *n, | |
758 | unsigned long action, void *hcpu) | |
759 | { | |
760 | return NOTIFY_OK; | |
761 | } | |
762 | ||
763 | #endif | |
764 | ||
6bb74df4 | 765 | /* |
766 | * Clock source related code | |
767 | */ | |
8e19608e | 768 | static cycle_t read_hpet(struct clocksource *cs) |
6bb74df4 | 769 | { |
770 | return (cycle_t)hpet_readl(HPET_COUNTER); | |
771 | } | |
772 | ||
28769149 TG |
773 | #ifdef CONFIG_X86_64 |
774 | static cycle_t __vsyscall_fn vread_hpet(void) | |
775 | { | |
776 | return readl((const void __iomem *)fix_to_virt(VSYSCALL_HPET) + 0xf0); | |
777 | } | |
778 | #endif | |
779 | ||
6bb74df4 | 780 | static struct clocksource clocksource_hpet = { |
781 | .name = "hpet", | |
782 | .rating = 250, | |
783 | .read = read_hpet, | |
784 | .mask = HPET_MASK, | |
6bb74df4 | 785 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
8d6f0c82 | 786 | .resume = hpet_resume_counter, |
28769149 TG |
787 | #ifdef CONFIG_X86_64 |
788 | .vread = vread_hpet, | |
789 | #endif | |
6bb74df4 | 790 | }; |
791 | ||
610bf2f1 | 792 | static int hpet_clocksource_register(void) |
e9e2cdb4 | 793 | { |
6fd592da | 794 | u64 start, now; |
f12a15be | 795 | u64 hpet_freq; |
075bcd1f | 796 | cycle_t t1; |
e9e2cdb4 | 797 | |
e9e2cdb4 | 798 | /* Start the counter */ |
8d6f0c82 | 799 | hpet_restart_counter(); |
e9e2cdb4 | 800 | |
075bcd1f | 801 | /* Verify whether hpet counter works */ |
8e19608e | 802 | t1 = hpet_readl(HPET_COUNTER); |
075bcd1f TG |
803 | rdtscll(start); |
804 | ||
805 | /* | |
806 | * We don't know the TSC frequency yet, but waiting for | |
807 | * 200000 TSC cycles is safe: | |
808 | * 4 GHz == 50us | |
809 | * 1 GHz == 200us | |
810 | */ | |
811 | do { | |
812 | rep_nop(); | |
813 | rdtscll(now); | |
814 | } while ((now - start) < 200000UL); | |
815 | ||
8e19608e | 816 | if (t1 == hpet_readl(HPET_COUNTER)) { |
075bcd1f TG |
817 | printk(KERN_WARNING |
818 | "HPET counter not counting. HPET disabled\n"); | |
610bf2f1 | 819 | return -ENODEV; |
075bcd1f TG |
820 | } |
821 | ||
6fd592da CM |
822 | /* |
823 | * The definition of mult is (include/linux/clocksource.h) | |
824 | * mult/2^shift = ns/cyc and hpet_period is in units of fsec/cyc | |
825 | * so we first need to convert hpet_period to ns/cyc units: | |
826 | * mult/2^shift = ns/cyc = hpet_period/10^6 | |
827 | * mult = (hpet_period * 2^shift)/10^6 | |
828 | * mult = (hpet_period << shift)/FSEC_PER_NSEC | |
6bb74df4 | 829 | */ |
6bb74df4 | 830 | |
f12a15be JS |
831 | /* Need to convert hpet_period (fsec/cyc) to cyc/sec: |
832 | * | |
833 | * cyc/sec = FSEC_PER_SEC/hpet_period(fsec/cyc) | |
834 | * cyc/sec = (FSEC_PER_NSEC * NSEC_PER_SEC)/hpet_period | |
835 | */ | |
4936a3b9 | 836 | hpet_freq = FSEC_PER_SEC; |
f12a15be JS |
837 | do_div(hpet_freq, hpet_period); |
838 | clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq); | |
6bb74df4 | 839 | |
610bf2f1 VP |
840 | return 0; |
841 | } | |
842 | ||
b02a7f22 PM |
843 | /** |
844 | * hpet_enable - Try to setup the HPET timer. Returns 1 on success. | |
610bf2f1 VP |
845 | */ |
846 | int __init hpet_enable(void) | |
847 | { | |
5946fa3d | 848 | unsigned int id; |
a6825f1c | 849 | int i; |
610bf2f1 VP |
850 | |
851 | if (!is_hpet_capable()) | |
852 | return 0; | |
853 | ||
854 | hpet_set_mapping(); | |
855 | ||
856 | /* | |
857 | * Read the period and check for a sane value: | |
858 | */ | |
859 | hpet_period = hpet_readl(HPET_PERIOD); | |
a6825f1c TG |
860 | |
861 | /* | |
862 | * AMD SB700 based systems with spread spectrum enabled use a | |
863 | * SMM based HPET emulation to provide proper frequency | |
864 | * setting. The SMM code is initialized with the first HPET | |
865 | * register access and takes some time to complete. During | |
866 | * this time the config register reads 0xffffffff. We check | |
867 | * for max. 1000 loops whether the config register reads a non | |
868 | * 0xffffffff value to make sure that HPET is up and running | |
869 | * before we go further. A counting loop is safe, as the HPET | |
870 | * access takes thousands of CPU cycles. On non SB700 based | |
871 | * machines this check is only done once and has no side | |
872 | * effects. | |
873 | */ | |
874 | for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) { | |
875 | if (i == 1000) { | |
876 | printk(KERN_WARNING | |
877 | "HPET config register value = 0xFFFFFFFF. " | |
878 | "Disabling HPET\n"); | |
879 | goto out_nohpet; | |
880 | } | |
881 | } | |
882 | ||
610bf2f1 VP |
883 | if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD) |
884 | goto out_nohpet; | |
885 | ||
886 | /* | |
887 | * Read the HPET ID register to retrieve the IRQ routing | |
888 | * information and the number of channels | |
889 | */ | |
890 | id = hpet_readl(HPET_ID); | |
b98103a5 | 891 | hpet_print_config(); |
610bf2f1 VP |
892 | |
893 | #ifdef CONFIG_HPET_EMULATE_RTC | |
894 | /* | |
895 | * The legacy routing mode needs at least two channels, tick timer | |
896 | * and the rtc emulation channel. | |
897 | */ | |
898 | if (!(id & HPET_ID_NUMBER)) | |
899 | goto out_nohpet; | |
900 | #endif | |
901 | ||
902 | if (hpet_clocksource_register()) | |
903 | goto out_nohpet; | |
904 | ||
e9e2cdb4 | 905 | if (id & HPET_ID_LEGSUP) { |
610bf2f1 | 906 | hpet_legacy_clockevent_register(); |
e9e2cdb4 TG |
907 | return 1; |
908 | } | |
909 | return 0; | |
5d0cf410 | 910 | |
e9e2cdb4 | 911 | out_nohpet: |
06a24dec | 912 | hpet_clear_mapping(); |
bacbe999 | 913 | hpet_address = 0; |
e9e2cdb4 TG |
914 | return 0; |
915 | } | |
916 | ||
28769149 TG |
917 | /* |
918 | * Needs to be late, as the reserve_timer code calls kalloc ! | |
919 | * | |
920 | * Not a problem on i386 as hpet_enable is called from late_time_init, | |
921 | * but on x86_64 it is necessary ! | |
922 | */ | |
923 | static __init int hpet_late_init(void) | |
924 | { | |
26afe5f2 | 925 | int cpu; |
926 | ||
59c69f2a | 927 | if (boot_hpet_disable) |
28769149 TG |
928 | return -ENODEV; |
929 | ||
59c69f2a VP |
930 | if (!hpet_address) { |
931 | if (!force_hpet_address) | |
932 | return -ENODEV; | |
933 | ||
934 | hpet_address = force_hpet_address; | |
935 | hpet_enable(); | |
59c69f2a VP |
936 | } |
937 | ||
39c04b55 JF |
938 | if (!hpet_virt_address) |
939 | return -ENODEV; | |
940 | ||
39fe05e5 SL |
941 | if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP) |
942 | hpet_msi_capability_lookup(2); | |
943 | else | |
944 | hpet_msi_capability_lookup(0); | |
945 | ||
28769149 | 946 | hpet_reserve_platform_timers(hpet_readl(HPET_ID)); |
b98103a5 | 947 | hpet_print_config(); |
59c69f2a | 948 | |
73472a46 PV |
949 | if (hpet_msi_disable) |
950 | return 0; | |
951 | ||
39fe05e5 SL |
952 | if (boot_cpu_has(X86_FEATURE_ARAT)) |
953 | return 0; | |
954 | ||
26afe5f2 | 955 | for_each_online_cpu(cpu) { |
956 | hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu); | |
957 | } | |
958 | ||
959 | /* This notifier should be called after workqueue is ready */ | |
960 | hotcpu_notifier(hpet_cpuhp_notify, -20); | |
961 | ||
28769149 TG |
962 | return 0; |
963 | } | |
964 | fs_initcall(hpet_late_init); | |
965 | ||
c86c7fbc OH |
966 | void hpet_disable(void) |
967 | { | |
ff487808 | 968 | if (is_hpet_capable() && hpet_virt_address) { |
5946fa3d | 969 | unsigned int cfg = hpet_readl(HPET_CFG); |
c86c7fbc OH |
970 | |
971 | if (hpet_legacy_int_enabled) { | |
972 | cfg &= ~HPET_CFG_LEGACY; | |
973 | hpet_legacy_int_enabled = 0; | |
974 | } | |
975 | cfg &= ~HPET_CFG_ENABLE; | |
976 | hpet_writel(cfg, HPET_CFG); | |
977 | } | |
978 | } | |
979 | ||
e9e2cdb4 TG |
980 | #ifdef CONFIG_HPET_EMULATE_RTC |
981 | ||
982 | /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET | |
983 | * is enabled, we support RTC interrupt functionality in software. | |
984 | * RTC has 3 kinds of interrupts: | |
985 | * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock | |
986 | * is updated | |
987 | * 2) Alarm Interrupt - generate an interrupt at a specific time of day | |
988 | * 3) Periodic Interrupt - generate periodic interrupt, with frequencies | |
989 | * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2) | |
990 | * (1) and (2) above are implemented using polling at a frequency of | |
991 | * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt | |
992 | * overhead. (DEFAULT_RTC_INT_FREQ) | |
993 | * For (3), we use interrupts at 64Hz or user specified periodic | |
994 | * frequency, whichever is higher. | |
995 | */ | |
996 | #include <linux/mc146818rtc.h> | |
997 | #include <linux/rtc.h> | |
1bdbdaac | 998 | #include <asm/rtc.h> |
e9e2cdb4 TG |
999 | |
1000 | #define DEFAULT_RTC_INT_FREQ 64 | |
1001 | #define DEFAULT_RTC_SHIFT 6 | |
1002 | #define RTC_NUM_INTS 1 | |
1003 | ||
1004 | static unsigned long hpet_rtc_flags; | |
7e2a31da | 1005 | static int hpet_prev_update_sec; |
e9e2cdb4 TG |
1006 | static struct rtc_time hpet_alarm_time; |
1007 | static unsigned long hpet_pie_count; | |
ff08f76d | 1008 | static u32 hpet_t1_cmp; |
5946fa3d JB |
1009 | static u32 hpet_default_delta; |
1010 | static u32 hpet_pie_delta; | |
e9e2cdb4 TG |
1011 | static unsigned long hpet_pie_limit; |
1012 | ||
1bdbdaac BW |
1013 | static rtc_irq_handler irq_handler; |
1014 | ||
ff08f76d PE |
1015 | /* |
1016 | * Check that the hpet counter c1 is ahead of the c2 | |
1017 | */ | |
1018 | static inline int hpet_cnt_ahead(u32 c1, u32 c2) | |
1019 | { | |
1020 | return (s32)(c2 - c1) < 0; | |
1021 | } | |
1022 | ||
1bdbdaac BW |
1023 | /* |
1024 | * Registers a IRQ handler. | |
1025 | */ | |
1026 | int hpet_register_irq_handler(rtc_irq_handler handler) | |
1027 | { | |
1028 | if (!is_hpet_enabled()) | |
1029 | return -ENODEV; | |
1030 | if (irq_handler) | |
1031 | return -EBUSY; | |
1032 | ||
1033 | irq_handler = handler; | |
1034 | ||
1035 | return 0; | |
1036 | } | |
1037 | EXPORT_SYMBOL_GPL(hpet_register_irq_handler); | |
1038 | ||
1039 | /* | |
1040 | * Deregisters the IRQ handler registered with hpet_register_irq_handler() | |
1041 | * and does cleanup. | |
1042 | */ | |
1043 | void hpet_unregister_irq_handler(rtc_irq_handler handler) | |
1044 | { | |
1045 | if (!is_hpet_enabled()) | |
1046 | return; | |
1047 | ||
1048 | irq_handler = NULL; | |
1049 | hpet_rtc_flags = 0; | |
1050 | } | |
1051 | EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler); | |
1052 | ||
e9e2cdb4 TG |
1053 | /* |
1054 | * Timer 1 for RTC emulation. We use one shot mode, as periodic mode | |
1055 | * is not supported by all HPET implementations for timer 1. | |
1056 | * | |
1057 | * hpet_rtc_timer_init() is called when the rtc is initialized. | |
1058 | */ | |
1059 | int hpet_rtc_timer_init(void) | |
1060 | { | |
5946fa3d JB |
1061 | unsigned int cfg, cnt, delta; |
1062 | unsigned long flags; | |
e9e2cdb4 TG |
1063 | |
1064 | if (!is_hpet_enabled()) | |
1065 | return 0; | |
1066 | ||
1067 | if (!hpet_default_delta) { | |
1068 | uint64_t clc; | |
1069 | ||
1070 | clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; | |
1071 | clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT; | |
5946fa3d | 1072 | hpet_default_delta = clc; |
e9e2cdb4 TG |
1073 | } |
1074 | ||
1075 | if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) | |
1076 | delta = hpet_default_delta; | |
1077 | else | |
1078 | delta = hpet_pie_delta; | |
1079 | ||
1080 | local_irq_save(flags); | |
1081 | ||
1082 | cnt = delta + hpet_readl(HPET_COUNTER); | |
1083 | hpet_writel(cnt, HPET_T1_CMP); | |
1084 | hpet_t1_cmp = cnt; | |
1085 | ||
1086 | cfg = hpet_readl(HPET_T1_CFG); | |
1087 | cfg &= ~HPET_TN_PERIODIC; | |
1088 | cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; | |
1089 | hpet_writel(cfg, HPET_T1_CFG); | |
1090 | ||
1091 | local_irq_restore(flags); | |
1092 | ||
1093 | return 1; | |
1094 | } | |
1bdbdaac | 1095 | EXPORT_SYMBOL_GPL(hpet_rtc_timer_init); |
e9e2cdb4 TG |
1096 | |
1097 | /* | |
1098 | * The functions below are called from rtc driver. | |
1099 | * Return 0 if HPET is not being used. | |
1100 | * Otherwise do the necessary changes and return 1. | |
1101 | */ | |
1102 | int hpet_mask_rtc_irq_bit(unsigned long bit_mask) | |
1103 | { | |
1104 | if (!is_hpet_enabled()) | |
1105 | return 0; | |
1106 | ||
1107 | hpet_rtc_flags &= ~bit_mask; | |
1108 | return 1; | |
1109 | } | |
1bdbdaac | 1110 | EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit); |
e9e2cdb4 TG |
1111 | |
1112 | int hpet_set_rtc_irq_bit(unsigned long bit_mask) | |
1113 | { | |
1114 | unsigned long oldbits = hpet_rtc_flags; | |
1115 | ||
1116 | if (!is_hpet_enabled()) | |
1117 | return 0; | |
1118 | ||
1119 | hpet_rtc_flags |= bit_mask; | |
1120 | ||
7e2a31da DB |
1121 | if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE)) |
1122 | hpet_prev_update_sec = -1; | |
1123 | ||
e9e2cdb4 TG |
1124 | if (!oldbits) |
1125 | hpet_rtc_timer_init(); | |
1126 | ||
1127 | return 1; | |
1128 | } | |
1bdbdaac | 1129 | EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit); |
e9e2cdb4 TG |
1130 | |
1131 | int hpet_set_alarm_time(unsigned char hrs, unsigned char min, | |
1132 | unsigned char sec) | |
1133 | { | |
1134 | if (!is_hpet_enabled()) | |
1135 | return 0; | |
1136 | ||
1137 | hpet_alarm_time.tm_hour = hrs; | |
1138 | hpet_alarm_time.tm_min = min; | |
1139 | hpet_alarm_time.tm_sec = sec; | |
1140 | ||
1141 | return 1; | |
1142 | } | |
1bdbdaac | 1143 | EXPORT_SYMBOL_GPL(hpet_set_alarm_time); |
e9e2cdb4 TG |
1144 | |
1145 | int hpet_set_periodic_freq(unsigned long freq) | |
1146 | { | |
1147 | uint64_t clc; | |
1148 | ||
1149 | if (!is_hpet_enabled()) | |
1150 | return 0; | |
1151 | ||
1152 | if (freq <= DEFAULT_RTC_INT_FREQ) | |
1153 | hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq; | |
1154 | else { | |
1155 | clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; | |
1156 | do_div(clc, freq); | |
1157 | clc >>= hpet_clockevent.shift; | |
5946fa3d | 1158 | hpet_pie_delta = clc; |
b4a5e8a1 | 1159 | hpet_pie_limit = 0; |
e9e2cdb4 TG |
1160 | } |
1161 | return 1; | |
1162 | } | |
1bdbdaac | 1163 | EXPORT_SYMBOL_GPL(hpet_set_periodic_freq); |
e9e2cdb4 TG |
1164 | |
1165 | int hpet_rtc_dropped_irq(void) | |
1166 | { | |
1167 | return is_hpet_enabled(); | |
1168 | } | |
1bdbdaac | 1169 | EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq); |
e9e2cdb4 TG |
1170 | |
1171 | static void hpet_rtc_timer_reinit(void) | |
1172 | { | |
5946fa3d | 1173 | unsigned int cfg, delta; |
e9e2cdb4 TG |
1174 | int lost_ints = -1; |
1175 | ||
1176 | if (unlikely(!hpet_rtc_flags)) { | |
1177 | cfg = hpet_readl(HPET_T1_CFG); | |
1178 | cfg &= ~HPET_TN_ENABLE; | |
1179 | hpet_writel(cfg, HPET_T1_CFG); | |
1180 | return; | |
1181 | } | |
1182 | ||
1183 | if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) | |
1184 | delta = hpet_default_delta; | |
1185 | else | |
1186 | delta = hpet_pie_delta; | |
1187 | ||
1188 | /* | |
1189 | * Increment the comparator value until we are ahead of the | |
1190 | * current count. | |
1191 | */ | |
1192 | do { | |
1193 | hpet_t1_cmp += delta; | |
1194 | hpet_writel(hpet_t1_cmp, HPET_T1_CMP); | |
1195 | lost_ints++; | |
ff08f76d | 1196 | } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER))); |
e9e2cdb4 TG |
1197 | |
1198 | if (lost_ints) { | |
1199 | if (hpet_rtc_flags & RTC_PIE) | |
1200 | hpet_pie_count += lost_ints; | |
1201 | if (printk_ratelimit()) | |
7e2a31da | 1202 | printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n", |
e9e2cdb4 TG |
1203 | lost_ints); |
1204 | } | |
1205 | } | |
1206 | ||
1207 | irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id) | |
1208 | { | |
1209 | struct rtc_time curr_time; | |
1210 | unsigned long rtc_int_flag = 0; | |
1211 | ||
1212 | hpet_rtc_timer_reinit(); | |
1bdbdaac | 1213 | memset(&curr_time, 0, sizeof(struct rtc_time)); |
e9e2cdb4 TG |
1214 | |
1215 | if (hpet_rtc_flags & (RTC_UIE | RTC_AIE)) | |
1bdbdaac | 1216 | get_rtc_time(&curr_time); |
e9e2cdb4 TG |
1217 | |
1218 | if (hpet_rtc_flags & RTC_UIE && | |
1219 | curr_time.tm_sec != hpet_prev_update_sec) { | |
7e2a31da DB |
1220 | if (hpet_prev_update_sec >= 0) |
1221 | rtc_int_flag = RTC_UF; | |
e9e2cdb4 TG |
1222 | hpet_prev_update_sec = curr_time.tm_sec; |
1223 | } | |
1224 | ||
1225 | if (hpet_rtc_flags & RTC_PIE && | |
1226 | ++hpet_pie_count >= hpet_pie_limit) { | |
1227 | rtc_int_flag |= RTC_PF; | |
1228 | hpet_pie_count = 0; | |
1229 | } | |
1230 | ||
8ee291f8 | 1231 | if (hpet_rtc_flags & RTC_AIE && |
e9e2cdb4 TG |
1232 | (curr_time.tm_sec == hpet_alarm_time.tm_sec) && |
1233 | (curr_time.tm_min == hpet_alarm_time.tm_min) && | |
1234 | (curr_time.tm_hour == hpet_alarm_time.tm_hour)) | |
1235 | rtc_int_flag |= RTC_AF; | |
1236 | ||
1237 | if (rtc_int_flag) { | |
1238 | rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8)); | |
1bdbdaac BW |
1239 | if (irq_handler) |
1240 | irq_handler(rtc_int_flag, dev_id); | |
e9e2cdb4 TG |
1241 | } |
1242 | return IRQ_HANDLED; | |
1243 | } | |
1bdbdaac | 1244 | EXPORT_SYMBOL_GPL(hpet_rtc_interrupt); |
e9e2cdb4 | 1245 | #endif |