[deliverable/linux.git] / arch / x86 / kernel / hw_breakpoint.c

/*
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 *
 * Copyright (C) 2007 Alan Stern
 * Copyright (C) 2009 IBM Corporation
 * Copyright (C) 2009 Frederic Weisbecker <fweisbec@gmail.com>
 *
 * Authors: Alan Stern <stern@rowland.harvard.edu>
 *          K.Prasad <prasad@linux.vnet.ibm.com>
 *          Frederic Weisbecker <fweisbec@gmail.com>
 */

/*
 * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
 * using the CPU's debug registers.
 */

#include <linux/perf_event.h>
#include <linux/hw_breakpoint.h>
#include <linux/irqflags.h>
#include <linux/notifier.h>
#include <linux/kallsyms.h>
#include <linux/kprobes.h>
#include <linux/percpu.h>
#include <linux/kdebug.h>
#include <linux/kernel.h>
#include <linux/export.h>
#include <linux/sched.h>
#include <linux/smp.h>

#include <asm/hw_breakpoint.h>
#include <asm/processor.h>
#include <asm/debugreg.h>
#include <asm/user.h>

/* Per cpu debug control register value */
DEFINE_PER_CPU(unsigned long, cpu_dr7);
EXPORT_PER_CPU_SYMBOL(cpu_dr7);

/* Per cpu debug address registers values */
static DEFINE_PER_CPU(unsigned long, cpu_debugreg[HBP_NUM]);

/*
 * Stores the breakpoints currently in use on each breakpoint address
 * register for each cpus
 */
static DEFINE_PER_CPU(struct perf_event *, bp_per_reg[HBP_NUM]);


static inline unsigned long
__encode_dr7(int drnum, unsigned int len, unsigned int type)
{
	unsigned long bp_info;

	bp_info = (len | type) & 0xf;
	bp_info <<= (DR_CONTROL_SHIFT + drnum * DR_CONTROL_SIZE);
	bp_info |= (DR_GLOBAL_ENABLE << (drnum * DR_ENABLE_SIZE));

	return bp_info;
}

/*
 * Encode the length, type, Exact, and Enable bits for a particular breakpoint
 * as stored in debug register 7.
 */
unsigned long encode_dr7(int drnum, unsigned int len, unsigned int type)
{
	return __encode_dr7(drnum, len, type) | DR_GLOBAL_SLOWDOWN;
}

/*
 * Decode the length and type bits for a particular breakpoint as
 * stored in debug register 7.  Return the "enabled" status.
 */
int decode_dr7(unsigned long dr7, int bpnum, unsigned *len, unsigned *type)
{
	int bp_info = dr7 >> (DR_CONTROL_SHIFT + bpnum * DR_CONTROL_SIZE);

	*len = (bp_info & 0xc) | 0x40;
	*type = (bp_info & 0x3) | 0x80;

	return (dr7 >> (bpnum * DR_ENABLE_SIZE)) & 0x3;
}

/*
 * Install a perf counter breakpoint.
 *
 * We seek a free debug address register and use it for this
 * breakpoint. Eventually we enable it in the debug control register.
 *
 * Atomic: we hold the counter->ctx->lock and we only handle variables
 * and registers local to this cpu.
 */
int arch_install_hw_breakpoint(struct perf_event *bp)
{
	struct arch_hw_breakpoint *info = counter_arch_bp(bp);
	unsigned long *dr7;
	int i;

	for (i = 0; i < HBP_NUM; i++) {
		struct perf_event **slot = this_cpu_ptr(&bp_per_reg[i]);

		if (!*slot) {
			*slot = bp;
			break;
		}
	}

	if (WARN_ONCE(i == HBP_NUM, "Can't find any breakpoint slot"))
		return -EBUSY;

	set_debugreg(info->address, i);
	__this_cpu_write(cpu_debugreg[i], info->address);

	dr7 = this_cpu_ptr(&cpu_dr7);
	*dr7 |= encode_dr7(i, info->len, info->type);

	set_debugreg(*dr7, 7);
	if (info->mask)
		set_dr_addr_mask(info->mask, i);

	return 0;
}

/*
 * Uninstall the breakpoint contained in the given counter.
 *
 * First we search the debug address register it uses and then we disable
 * it.
 *
 * Atomic: we hold the counter->ctx->lock and we only handle variables
 * and registers local to this cpu.
 */
void arch_uninstall_hw_breakpoint(struct perf_event *bp)
{
	struct arch_hw_breakpoint *info = counter_arch_bp(bp);
	unsigned long *dr7;
	int i;

	for (i = 0; i < HBP_NUM; i++) {
		struct perf_event **slot = this_cpu_ptr(&bp_per_reg[i]);

		if (*slot == bp) {
			*slot = NULL;
			break;
		}
	}

	if (WARN_ONCE(i == HBP_NUM, "Can't find any breakpoint slot"))
		return;

	dr7 = this_cpu_ptr(&cpu_dr7);
	*dr7 &= ~__encode_dr7(i, info->len, info->type);

	set_debugreg(*dr7, 7);
	if (info->mask)
		set_dr_addr_mask(0, i);
}

/*
 * Check for virtual address in kernel space.
 */
int arch_check_bp_in_kernelspace(struct perf_event *bp)
{
	unsigned int len;
	unsigned long va;
	struct arch_hw_breakpoint *info = counter_arch_bp(bp);

	va = info->address;
	len = bp->attr.bp_len;

	/*
	 * We don't need to worry about va + len - 1 overflowing:
	 * we already require that va is aligned to a multiple of len.
	 */
	return (va >= TASK_SIZE_MAX) || ((va + len - 1) >= TASK_SIZE_MAX);
}

int arch_bp_generic_fields(int x86_len, int x86_type,
			   int *gen_len, int *gen_type)
{
	/* Type */
	switch (x86_type) {
	case X86_BREAKPOINT_EXECUTE:
		if (x86_len != X86_BREAKPOINT_LEN_X)
			return -EINVAL;

		*gen_type = HW_BREAKPOINT_X;
		*gen_len = sizeof(long);
		return 0;
	case X86_BREAKPOINT_WRITE:
		*gen_type = HW_BREAKPOINT_W;
		break;
	case X86_BREAKPOINT_RW:
		*gen_type = HW_BREAKPOINT_W | HW_BREAKPOINT_R;
		break;
	default:
		return -EINVAL;
	}

	/* Len */
	switch (x86_len) {
	case X86_BREAKPOINT_LEN_1:
		*gen_len = HW_BREAKPOINT_LEN_1;
		break;
	case X86_BREAKPOINT_LEN_2:
		*gen_len = HW_BREAKPOINT_LEN_2;
		break;
	case X86_BREAKPOINT_LEN_4:
		*gen_len = HW_BREAKPOINT_LEN_4;
		break;
#ifdef CONFIG_X86_64
	case X86_BREAKPOINT_LEN_8:
		*gen_len = HW_BREAKPOINT_LEN_8;
		break;
#endif
	default:
		return -EINVAL;
	}

	return 0;
}


static int arch_build_bp_info(struct perf_event *bp)
{
	struct arch_hw_breakpoint *info = counter_arch_bp(bp);

	info->address = bp->attr.bp_addr;

	/* Type */
	switch (bp->attr.bp_type) {
	case HW_BREAKPOINT_W:
		info->type = X86_BREAKPOINT_WRITE;
		break;
	case HW_BREAKPOINT_W | HW_BREAKPOINT_R:
		info->type = X86_BREAKPOINT_RW;
		break;
	case HW_BREAKPOINT_X:
		/*
		 * We don't allow kernel breakpoints in places that are not
		 * acceptable for kprobes.  On non-kprobes kernels, we don't
		 * allow kernel breakpoints at all.
		 */
		if (bp->attr.bp_addr >= TASK_SIZE_MAX) {
#ifdef CONFIG_KPROBES
			if (within_kprobe_blacklist(bp->attr.bp_addr))
				return -EINVAL;
#else
			return -EINVAL;
#endif
		}

		info->type = X86_BREAKPOINT_EXECUTE;
		/*
		 * x86 inst breakpoints need to have a specific undefined len.
		 * But we still need to check userspace is not trying to setup
		 * an unsupported length, to get a range breakpoint for example.
		 */
		if (bp->attr.bp_len == sizeof(long)) {
			info->len = X86_BREAKPOINT_LEN_X;
			return 0;
		}
	default:
		return -EINVAL;
	}

	/* Len */
	info->mask = 0;

	switch (bp->attr.bp_len) {
	case HW_BREAKPOINT_LEN_1:
		info->len = X86_BREAKPOINT_LEN_1;
		break;
	case HW_BREAKPOINT_LEN_2:
		info->len = X86_BREAKPOINT_LEN_2;
		break;
	case HW_BREAKPOINT_LEN_4:
		info->len = X86_BREAKPOINT_LEN_4;
		break;
#ifdef CONFIG_X86_64
	case HW_BREAKPOINT_LEN_8:
		info->len = X86_BREAKPOINT_LEN_8;
		break;
#endif
	default:
		/* AMD range breakpoint */
		if (!is_power_of_2(bp->attr.bp_len))
			return -EINVAL;
		if (bp->attr.bp_addr & (bp->attr.bp_len - 1))
			return -EINVAL;

		if (!boot_cpu_has(X86_FEATURE_BPEXT))
			return -EOPNOTSUPP;

		/*
		 * It's impossible to use a range breakpoint to fake out
		 * user vs kernel detection because bp_len - 1 can't
		 * have the high bit set.  If we ever allow range instruction
		 * breakpoints, then we'll have to check for kprobe-blacklisted
		 * addresses anywhere in the range.
		 */
		info->mask = bp->attr.bp_len - 1;
		info->len = X86_BREAKPOINT_LEN_1;
	}

	return 0;
}

/*
 * Validate the arch-specific HW Breakpoint register settings
 */
int arch_validate_hwbkpt_settings(struct perf_event *bp)
{
	struct arch_hw_breakpoint *info = counter_arch_bp(bp);
	unsigned int align;
	int ret;


	ret = arch_build_bp_info(bp);
	if (ret)
		return ret;

	switch (info->len) {
	case X86_BREAKPOINT_LEN_1:
		align = 0;
		if (info->mask)
			align = info->mask;
		break;
	case X86_BREAKPOINT_LEN_2:
		align = 1;
		break;
	case X86_BREAKPOINT_LEN_4:
		align = 3;
		break;
#ifdef CONFIG_X86_64
	case X86_BREAKPOINT_LEN_8:
		align = 7;
		break;
#endif
	default:
		WARN_ON_ONCE(1);
	}

	/*
	 * Check that the low-order bits of the address are appropriate
	 * for the alignment implied by len.
	 */
	if (info->address & align)
		return -EINVAL;

	return 0;
}

/*
 * Dump the debug register contents to the user.
 * We can't dump our per cpu values because it
 * may contain cpu wide breakpoint, something that
 * doesn't belong to the current task.
 *
 * TODO: include non-ptrace user breakpoints (perf)
 */
void aout_dump_debugregs(struct user *dump)
{
	int i;
	int dr7 = 0;
	struct perf_event *bp;
	struct arch_hw_breakpoint *info;
	struct thread_struct *thread = &current->thread;

	for (i = 0; i < HBP_NUM; i++) {
		bp = thread->ptrace_bps[i];

		if (bp && !bp->attr.disabled) {
			dump->u_debugreg[i] = bp->attr.bp_addr;
			info = counter_arch_bp(bp);
			dr7 |= encode_dr7(i, info->len, info->type);
		} else {
			dump->u_debugreg[i] = 0;
		}
	}

	dump->u_debugreg[4] = 0;
	dump->u_debugreg[5] = 0;
	dump->u_debugreg[6] = current->thread.debugreg6;

	dump->u_debugreg[7] = dr7;
}
EXPORT_SYMBOL_GPL(aout_dump_debugregs);

/*
 * Release the user breakpoints used by ptrace
 */
void flush_ptrace_hw_breakpoint(struct task_struct *tsk)
{
	int i;
	struct thread_struct *t = &tsk->thread;

	for (i = 0; i < HBP_NUM; i++) {
		unregister_hw_breakpoint(t->ptrace_bps[i]);
		t->ptrace_bps[i] = NULL;
	}

	t->debugreg6 = 0;
	t->ptrace_dr7 = 0;
}

void hw_breakpoint_restore(void)
{
	set_debugreg(__this_cpu_read(cpu_debugreg[0]), 0);
	set_debugreg(__this_cpu_read(cpu_debugreg[1]), 1);
	set_debugreg(__this_cpu_read(cpu_debugreg[2]), 2);
	set_debugreg(__this_cpu_read(cpu_debugreg[3]), 3);
	set_debugreg(current->thread.debugreg6, 6);
	set_debugreg(__this_cpu_read(cpu_dr7), 7);
}
EXPORT_SYMBOL_GPL(hw_breakpoint_restore);

/*
 * Handle debug exception notifications.
 *
 * Return value is either NOTIFY_STOP or NOTIFY_DONE as explained below.
 *
 * NOTIFY_DONE returned if one of the following conditions is true.
 * i) When the causative address is from user-space and the exception
 * is a valid one, i.e. not triggered as a result of lazy debug register
 * switching
 * ii) When there are more bits than trap<n> set in DR6 register (such
 * as BD, BS or BT) indicating that more than one debug condition is
 * met and requires some more action in do_debug().
 *
 * NOTIFY_STOP returned for all other cases
 *
 */
static int hw_breakpoint_handler(struct die_args *args)
{
	int i, cpu, rc = NOTIFY_STOP;
	struct perf_event *bp;
	unsigned long dr7, dr6;
	unsigned long *dr6_p;

	/* The DR6 value is pointed by args->err */
	dr6_p = (unsigned long *)ERR_PTR(args->err);
	dr6 = *dr6_p;

	/* If it's a single step, TRAP bits are random */
	if (dr6 & DR_STEP)
		return NOTIFY_DONE;

	/* Do an early return if no trap bits are set in DR6 */
	if ((dr6 & DR_TRAP_BITS) == 0)
		return NOTIFY_DONE;

	get_debugreg(dr7, 7);
	/* Disable breakpoints during exception handling */
	set_debugreg(0UL, 7);
	/*
	 * Assert that local interrupts are disabled
	 * Reset the DRn bits in the virtualized register value.
	 * The ptrace trigger routine will add in whatever is needed.
	 */
	current->thread.debugreg6 &= ~DR_TRAP_BITS;
	cpu = get_cpu();

	/* Handle all the breakpoints that were triggered */
	for (i = 0; i < HBP_NUM; ++i) {
		if (likely(!(dr6 & (DR_TRAP0 << i))))
			continue;

		/*
		 * The counter may be concurrently released but that can only
		 * occur from a call_rcu() path. We can then safely fetch
		 * the breakpoint, use its callback, touch its counter
		 * while we are in an rcu_read_lock() path.
		 */
		rcu_read_lock();

		bp = per_cpu(bp_per_reg[i], cpu);
		/*
		 * Reset the 'i'th TRAP bit in dr6 to denote completion of
		 * exception handling
		 */
		(*dr6_p) &= ~(DR_TRAP0 << i);
		/*
		 * bp can be NULL due to lazy debug register switching
		 * or due to concurrent perf counter removing.
		 */
		if (!bp) {
			rcu_read_unlock();
			break;
		}

		perf_bp_event(bp, args->regs);

		/*
		 * Set up resume flag to avoid breakpoint recursion when
		 * returning back to origin.
		 */
		if (bp->hw.info.type == X86_BREAKPOINT_EXECUTE)
			args->regs->flags |= X86_EFLAGS_RF;

		rcu_read_unlock();
	}
	/*
	 * Further processing in do_debug() is needed for a) user-space
	 * breakpoints (to generate signals) and b) when the system has
	 * taken exception due to multiple causes
	 */
	if ((current->thread.debugreg6 & DR_TRAP_BITS) ||
	    (dr6 & (~DR_TRAP_BITS)))
		rc = NOTIFY_DONE;

	set_debugreg(dr7, 7);
	put_cpu();

	return rc;
}

/*
 * Handle debug exception notifications.
 */
int hw_breakpoint_exceptions_notify(
		struct notifier_block *unused, unsigned long val, void *data)
{
	if (val != DIE_DEBUG)
		return NOTIFY_DONE;

	return hw_breakpoint_handler(data);
}

void hw_breakpoint_pmu_read(struct perf_event *bp)
{
	/* TODO */
}
Commit	Line	Data
0067f129 P	1	/*
	2	* This program is free software; you can redistribute it and/or modify
	3	* it under the terms of the GNU General Public License as published by
	4	* the Free Software Foundation; either version 2 of the License, or
	5	* (at your option) any later version.
	6	*
	7	* This program is distributed in the hope that it will be useful,
	8	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	9	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	10	* GNU General Public License for more details.
	11	*
	12	* You should have received a copy of the GNU General Public License
	13	* along with this program; if not, write to the Free Software
	14	* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	15	*
	16	* Copyright (C) 2007 Alan Stern
	17	* Copyright (C) 2009 IBM Corporation
24f1e32c	18	* Copyright (C) 2009 Frederic Weisbecker <fweisbec@gmail.com>
ba6909b7 P	19	*
	20	* Authors: Alan Stern <stern@rowland.harvard.edu>
	21	* K.Prasad <prasad@linux.vnet.ibm.com>
	22	* Frederic Weisbecker <fweisbec@gmail.com>
0067f129 P	23	*/
	24
	25	/*
	26	* HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
	27	* using the CPU's debug registers.
	28	*/
	29
24f1e32c FW	30	#include <linux/perf_event.h>
24f1e32c FW	31	#include <linux/hw_breakpoint.h>
0067f129 P	32	#include <linux/irqflags.h>
	33	#include <linux/notifier.h>
	34	#include <linux/kallsyms.h>
e5779e8e	35	#include <linux/kprobes.h>
0067f129 P	36	#include <linux/percpu.h>
	37	#include <linux/kdebug.h>
	38	#include <linux/kernel.h>
186f4360	39	#include <linux/export.h>
0067f129	40	#include <linux/sched.h>
0067f129 P	41	#include <linux/smp.h>
	42
	43	#include <asm/hw_breakpoint.h>
	44	#include <asm/processor.h>
	45	#include <asm/debugreg.h>
186f4360	46	#include <asm/user.h>
0067f129	47
24f1e32c	48	/* Per cpu debug control register value */
28b4e0d8 TH	49	DEFINE_PER_CPU(unsigned long, cpu_dr7);
28b4e0d8 TH	50	EXPORT_PER_CPU_SYMBOL(cpu_dr7);
24f1e32c FW	51
	52	/* Per cpu debug address registers values */
	53	static DEFINE_PER_CPU(unsigned long, cpu_debugreg[HBP_NUM]);
0067f129 P	54
0067f129 P	55	/*
24f1e32c FW	56	* Stores the breakpoints currently in use on each breakpoint address
24f1e32c FW	57	* register for each cpus
0067f129	58	*/
24f1e32c	59	static DEFINE_PER_CPU(struct perf_event *, bp_per_reg[HBP_NUM]);
0067f129 P	60
0067f129 P	61
2c31b795 FW	62	static inline unsigned long
2c31b795 FW	63	__encode_dr7(int drnum, unsigned int len, unsigned int type)
0067f129 P	64	{
	65	unsigned long bp_info;
	66
	67	bp_info = (len \| type) & 0xf;
	68	bp_info <<= (DR_CONTROL_SHIFT + drnum * DR_CONTROL_SIZE);
2c31b795 FW	69	bp_info \|= (DR_GLOBAL_ENABLE << (drnum * DR_ENABLE_SIZE));
2c31b795 FW	70
0067f129 P	71	return bp_info;
	72	}
	73
2c31b795 FW	74	/*
	75	* Encode the length, type, Exact, and Enable bits for a particular breakpoint
	76	* as stored in debug register 7.
	77	*/
	78	unsigned long encode_dr7(int drnum, unsigned int len, unsigned int type)
	79	{
	80	return __encode_dr7(drnum, len, type) \| DR_GLOBAL_SLOWDOWN;
	81	}
	82
24f1e32c FW	83	/*
	84	* Decode the length and type bits for a particular breakpoint as
	85	* stored in debug register 7. Return the "enabled" status.
	86	*/
	87	int decode_dr7(unsigned long dr7, int bpnum, unsigned len, unsigned type)
0067f129	88	{
24f1e32c	89	int bp_info = dr7 >> (DR_CONTROL_SHIFT + bpnum * DR_CONTROL_SIZE);
0067f129	90
24f1e32c FW	91	*len = (bp_info & 0xc) \| 0x40;
24f1e32c FW	92	*type = (bp_info & 0x3) \| 0x80;
0067f129	93
24f1e32c	94	return (dr7 >> (bpnum * DR_ENABLE_SIZE)) & 0x3;
0067f129 P	95	}
	96
	97	/*
24f1e32c FW	98	* Install a perf counter breakpoint.
	99	*
	100	* We seek a free debug address register and use it for this
	101	* breakpoint. Eventually we enable it in the debug control register.
	102	*
	103	* Atomic: we hold the counter->ctx->lock and we only handle variables
	104	* and registers local to this cpu.
0067f129	105	*/
24f1e32c	106	int arch_install_hw_breakpoint(struct perf_event *bp)
0067f129	107	{
24f1e32c FW	108	struct arch_hw_breakpoint *info = counter_arch_bp(bp);
	109	unsigned long *dr7;
	110	int i;
	111
	112	for (i = 0; i < HBP_NUM; i++) {
89cbc767	113	struct perf_event **slot = this_cpu_ptr(&bp_per_reg[i]);
24f1e32c FW	114
	115	if (!*slot) {
	116	*slot = bp;
	117	break;
	118	}
0067f129 P	119	}
0067f129 P	120
24f1e32c FW	121	if (WARN_ONCE(i == HBP_NUM, "Can't find any breakpoint slot"))
	122	return -EBUSY;
	123
	124	set_debugreg(info->address, i);
0a3aee0d	125	__this_cpu_write(cpu_debugreg[i], info->address);
24f1e32c	126
89cbc767	127	dr7 = this_cpu_ptr(&cpu_dr7);
24f1e32c FW	128	*dr7 \|= encode_dr7(i, info->len, info->type);
	129
	130	set_debugreg(*dr7, 7);
d6d55f0b JS	131	if (info->mask)
d6d55f0b JS	132	set_dr_addr_mask(info->mask, i);
24f1e32c FW	133
24f1e32c FW	134	return 0;
0067f129 P	135	}
	136
	137	/*
24f1e32c FW	138	* Uninstall the breakpoint contained in the given counter.
	139	*
	140	* First we search the debug address register it uses and then we disable
	141	* it.
	142	*
	143	* Atomic: we hold the counter->ctx->lock and we only handle variables
	144	* and registers local to this cpu.
0067f129	145	*/
24f1e32c	146	void arch_uninstall_hw_breakpoint(struct perf_event *bp)
0067f129	147	{
24f1e32c FW	148	struct arch_hw_breakpoint *info = counter_arch_bp(bp);
	149	unsigned long *dr7;
	150	int i;
	151
	152	for (i = 0; i < HBP_NUM; i++) {
89cbc767	153	struct perf_event **slot = this_cpu_ptr(&bp_per_reg[i]);
24f1e32c FW	154
	155	if (*slot == bp) {
	156	*slot = NULL;
	157	break;
	158	}
	159	}
	160
	161	if (WARN_ONCE(i == HBP_NUM, "Can't find any breakpoint slot"))
	162	return;
0067f129	163
89cbc767	164	dr7 = this_cpu_ptr(&cpu_dr7);
2c31b795	165	*dr7 &= ~__encode_dr7(i, info->len, info->type);
24f1e32c FW	166
24f1e32c FW	167	set_debugreg(*dr7, 7);
d6d55f0b JS	168	if (info->mask)
d6d55f0b JS	169	set_dr_addr_mask(0, i);
0067f129 P	170	}
0067f129 P	171
0067f129 P	172	/*
	173	* Check for virtual address in kernel space.
	174	*/
b2812d03	175	int arch_check_bp_in_kernelspace(struct perf_event *bp)
0067f129 P	176	{
0067f129 P	177	unsigned int len;
b2812d03 FW	178	unsigned long va;
b2812d03 FW	179	struct arch_hw_breakpoint *info = counter_arch_bp(bp);
0067f129	180
b2812d03	181	va = info->address;
36748b95	182	len = bp->attr.bp_len;
0067f129	183
27747f8b AL	184	/*
	185	* We don't need to worry about va + len - 1 overflowing:
	186	* we already require that va is aligned to a multiple of len.
	187	*/
	188	return (va >= TASK_SIZE_MAX) \|\| ((va + len - 1) >= TASK_SIZE_MAX);
0067f129 P	189	}
0067f129 P	190
24f1e32c FW	191	int arch_bp_generic_fields(int x86_len, int x86_type,
24f1e32c FW	192	int gen_len, int gen_type)
0067f129	193	{
89e45aac FW	194	/* Type */
	195	switch (x86_type) {
	196	case X86_BREAKPOINT_EXECUTE:
	197	if (x86_len != X86_BREAKPOINT_LEN_X)
	198	return -EINVAL;
	199
	200	*gen_type = HW_BREAKPOINT_X;
f7809daf	201	*gen_len = sizeof(long);
89e45aac FW	202	return 0;
	203	case X86_BREAKPOINT_WRITE:
	204	*gen_type = HW_BREAKPOINT_W;
f7809daf	205	break;
89e45aac FW	206	case X86_BREAKPOINT_RW:
	207	*gen_type = HW_BREAKPOINT_W \| HW_BREAKPOINT_R;
	208	break;
	209	default:
	210	return -EINVAL;
	211	}
	212
	213	/* Len */
	214	switch (x86_len) {
24f1e32c FW	215	case X86_BREAKPOINT_LEN_1:
	216	*gen_len = HW_BREAKPOINT_LEN_1;
	217	break;
	218	case X86_BREAKPOINT_LEN_2:
	219	*gen_len = HW_BREAKPOINT_LEN_2;
	220	break;
	221	case X86_BREAKPOINT_LEN_4:
	222	*gen_len = HW_BREAKPOINT_LEN_4;
	223	break;
	224	#ifdef CONFIG_X86_64
	225	case X86_BREAKPOINT_LEN_8:
	226	*gen_len = HW_BREAKPOINT_LEN_8;
	227	break;
	228	#endif
	229	default:
	230	return -EINVAL;
	231	}
0067f129	232
24f1e32c FW	233	return 0;
	234	}
	235
	236
	237	static int arch_build_bp_info(struct perf_event *bp)
	238	{
	239	struct arch_hw_breakpoint *info = counter_arch_bp(bp);
	240
	241	info->address = bp->attr.bp_addr;
	242
f7809daf FW	243	/* Type */
	244	switch (bp->attr.bp_type) {
	245	case HW_BREAKPOINT_W:
	246	info->type = X86_BREAKPOINT_WRITE;
	247	break;
	248	case HW_BREAKPOINT_W \| HW_BREAKPOINT_R:
	249	info->type = X86_BREAKPOINT_RW;
	250	break;
	251	case HW_BREAKPOINT_X:
e5779e8e AL	252	/*
	253	* We don't allow kernel breakpoints in places that are not
	254	* acceptable for kprobes. On non-kprobes kernels, we don't
	255	* allow kernel breakpoints at all.
	256	*/
	257	if (bp->attr.bp_addr >= TASK_SIZE_MAX) {
	258	#ifdef CONFIG_KPROBES
	259	if (within_kprobe_blacklist(bp->attr.bp_addr))
	260	return -EINVAL;
	261	#else
	262	return -EINVAL;
	263	#endif
	264	}
	265
f7809daf FW	266	info->type = X86_BREAKPOINT_EXECUTE;
	267	/*
	268	* x86 inst breakpoints need to have a specific undefined len.
	269	* But we still need to check userspace is not trying to setup
	270	* an unsupported length, to get a range breakpoint for example.
	271	*/
	272	if (bp->attr.bp_len == sizeof(long)) {
	273	info->len = X86_BREAKPOINT_LEN_X;
	274	return 0;
	275	}
	276	default:
	277	return -EINVAL;
	278	}
	279
24f1e32c	280	/* Len */
d6d55f0b JS	281	info->mask = 0;
d6d55f0b JS	282
24f1e32c	283	switch (bp->attr.bp_len) {
0067f129	284	case HW_BREAKPOINT_LEN_1:
24f1e32c	285	info->len = X86_BREAKPOINT_LEN_1;
0067f129 P	286	break;
0067f129 P	287	case HW_BREAKPOINT_LEN_2:
24f1e32c	288	info->len = X86_BREAKPOINT_LEN_2;
0067f129 P	289	break;
0067f129 P	290	case HW_BREAKPOINT_LEN_4:
24f1e32c	291	info->len = X86_BREAKPOINT_LEN_4;
0067f129 P	292	break;
	293	#ifdef CONFIG_X86_64
	294	case HW_BREAKPOINT_LEN_8:
24f1e32c FW	295	info->len = X86_BREAKPOINT_LEN_8;
	296	break;
	297	#endif
	298	default:
ab513927	299	/* AMD range breakpoint */
d6d55f0b JS	300	if (!is_power_of_2(bp->attr.bp_len))
d6d55f0b JS	301	return -EINVAL;
ab513927 AL	302	if (bp->attr.bp_addr & (bp->attr.bp_len - 1))
ab513927 AL	303	return -EINVAL;
362f924b BP	304
	305	if (!boot_cpu_has(X86_FEATURE_BPEXT))
	306	return -EOPNOTSUPP;
	307
ab513927 AL	308	/*
	309	* It's impossible to use a range breakpoint to fake out
	310	* user vs kernel detection because bp_len - 1 can't
	311	* have the high bit set. If we ever allow range instruction
	312	* breakpoints, then we'll have to check for kprobe-blacklisted
	313	* addresses anywhere in the range.
	314	*/
d6d55f0b JS	315	info->mask = bp->attr.bp_len - 1;
d6d55f0b JS	316	info->len = X86_BREAKPOINT_LEN_1;
24f1e32c FW	317	}
24f1e32c FW	318
24f1e32c FW	319	return 0;
24f1e32c FW	320	}
d6d55f0b	321
24f1e32c FW	322	/*
	323	* Validate the arch-specific HW Breakpoint register settings
	324	*/
b2812d03	325	int arch_validate_hwbkpt_settings(struct perf_event *bp)
24f1e32c FW	326	{
	327	struct arch_hw_breakpoint *info = counter_arch_bp(bp);
	328	unsigned int align;
	329	int ret;
	330
	331
	332	ret = arch_build_bp_info(bp);
	333	if (ret)
	334	return ret;
	335
24f1e32c FW	336	switch (info->len) {
	337	case X86_BREAKPOINT_LEN_1:
	338	align = 0;
d6d55f0b JS	339	if (info->mask)
d6d55f0b JS	340	align = info->mask;
24f1e32c FW	341	break;
	342	case X86_BREAKPOINT_LEN_2:
	343	align = 1;
	344	break;
	345	case X86_BREAKPOINT_LEN_4:
	346	align = 3;
	347	break;
	348	#ifdef CONFIG_X86_64
	349	case X86_BREAKPOINT_LEN_8:
0067f129 P	350	align = 7;
	351	break;
	352	#endif
	353	default:
d6d55f0b	354	WARN_ON_ONCE(1);
0067f129 P	355	}
0067f129 P	356
0067f129 P	357	/*
	358	* Check that the low-order bits of the address are appropriate
	359	* for the alignment implied by len.
	360	*/
24f1e32c	361	if (info->address & align)
0067f129 P	362	return -EINVAL;
0067f129 P	363
0067f129 P	364	return 0;
	365	}
	366
9f6b3c2c FW	367	/*
	368	* Dump the debug register contents to the user.
	369	* We can't dump our per cpu values because it
	370	* may contain cpu wide breakpoint, something that
	371	* doesn't belong to the current task.
	372	*
	373	* TODO: include non-ptrace user breakpoints (perf)
	374	*/
	375	void aout_dump_debugregs(struct user *dump)
	376	{
	377	int i;
	378	int dr7 = 0;
	379	struct perf_event *bp;
	380	struct arch_hw_breakpoint *info;
	381	struct thread_struct *thread = &current->thread;
	382
	383	for (i = 0; i < HBP_NUM; i++) {
	384	bp = thread->ptrace_bps[i];
	385
	386	if (bp && !bp->attr.disabled) {
	387	dump->u_debugreg[i] = bp->attr.bp_addr;
	388	info = counter_arch_bp(bp);
	389	dr7 \|= encode_dr7(i, info->len, info->type);
	390	} else {
	391	dump->u_debugreg[i] = 0;
	392	}
	393	}
	394
	395	dump->u_debugreg[4] = 0;
	396	dump->u_debugreg[5] = 0;
	397	dump->u_debugreg[6] = current->thread.debugreg6;
	398
	399	dump->u_debugreg[7] = dr7;
	400	}
68efa37d	401	EXPORT_SYMBOL_GPL(aout_dump_debugregs);
9f6b3c2c	402
24f1e32c FW	403	/*
	404	* Release the user breakpoints used by ptrace
	405	*/
	406	void flush_ptrace_hw_breakpoint(struct task_struct *tsk)
0067f129	407	{
24f1e32c FW	408	int i;
	409	struct thread_struct *t = &tsk->thread;
	410
	411	for (i = 0; i < HBP_NUM; i++) {
	412	unregister_hw_breakpoint(t->ptrace_bps[i]);
	413	t->ptrace_bps[i] = NULL;
	414	}
f7da04c9 ON	415
	416	t->debugreg6 = 0;
	417	t->ptrace_dr7 = 0;
0067f129 P	418	}
0067f129 P	419
24f1e32c	420	void hw_breakpoint_restore(void)
0067f129	421	{
0a3aee0d TH	422	set_debugreg(__this_cpu_read(cpu_debugreg[0]), 0);
	423	set_debugreg(__this_cpu_read(cpu_debugreg[1]), 1);
	424	set_debugreg(__this_cpu_read(cpu_debugreg[2]), 2);
	425	set_debugreg(__this_cpu_read(cpu_debugreg[3]), 3);
24f1e32c	426	set_debugreg(current->thread.debugreg6, 6);
0a3aee0d	427	set_debugreg(__this_cpu_read(cpu_dr7), 7);
0067f129	428	}
24f1e32c	429	EXPORT_SYMBOL_GPL(hw_breakpoint_restore);
0067f129 P	430
	431	/*
	432	* Handle debug exception notifications.
	433	*
	434	* Return value is either NOTIFY_STOP or NOTIFY_DONE as explained below.
	435	*
	436	* NOTIFY_DONE returned if one of the following conditions is true.
	437	* i) When the causative address is from user-space and the exception
	438	* is a valid one, i.e. not triggered as a result of lazy debug register
	439	* switching
	440	* ii) When there are more bits than trap<n> set in DR6 register (such
	441	* as BD, BS or BT) indicating that more than one debug condition is
	442	* met and requires some more action in do_debug().
	443	*
	444	* NOTIFY_STOP returned for all other cases
	445	*
	446	*/
9c54b616	447	static int hw_breakpoint_handler(struct die_args *args)
0067f129 P	448	{
0067f129 P	449	int i, cpu, rc = NOTIFY_STOP;
24f1e32c	450	struct perf_event *bp;
62edab90 P	451	unsigned long dr7, dr6;
	452	unsigned long *dr6_p;
	453
	454	/* The DR6 value is pointed by args->err */
	455	dr6_p = (unsigned long *)ERR_PTR(args->err);
	456	dr6 = *dr6_p;
0067f129	457
6c0aca28 FW	458	/* If it's a single step, TRAP bits are random */
	459	if (dr6 & DR_STEP)
	460	return NOTIFY_DONE;
	461
0067f129 P	462	/* Do an early return if no trap bits are set in DR6 */
	463	if ((dr6 & DR_TRAP_BITS) == 0)
	464	return NOTIFY_DONE;
	465
0067f129 P	466	get_debugreg(dr7, 7);
	467	/* Disable breakpoints during exception handling */
	468	set_debugreg(0UL, 7);
	469	/*
	470	* Assert that local interrupts are disabled
	471	* Reset the DRn bits in the virtualized register value.
	472	* The ptrace trigger routine will add in whatever is needed.
	473	*/
	474	current->thread.debugreg6 &= ~DR_TRAP_BITS;
	475	cpu = get_cpu();
	476
	477	/* Handle all the breakpoints that were triggered */
	478	for (i = 0; i < HBP_NUM; ++i) {
	479	if (likely(!(dr6 & (DR_TRAP0 << i))))
	480	continue;
24f1e32c	481
0067f129	482	/*
24f1e32c FW	483	* The counter may be concurrently released but that can only
	484	* occur from a call_rcu() path. We can then safely fetch
	485	* the breakpoint, use its callback, touch its counter
	486	* while we are in an rcu_read_lock() path.
0067f129	487	*/
24f1e32c FW	488	rcu_read_lock();
	489
	490	bp = per_cpu(bp_per_reg[i], cpu);
62edab90 P	491	/*
	492	* Reset the 'i'th TRAP bit in dr6 to denote completion of
	493	* exception handling
	494	*/
	495	(*dr6_p) &= ~(DR_TRAP0 << i);
0067f129 P	496	/*
0067f129 P	497	* bp can be NULL due to lazy debug register switching
24f1e32c	498	* or due to concurrent perf counter removing.
0067f129	499	*/
24f1e32c FW	500	if (!bp) {
	501	rcu_read_unlock();
	502	break;
	503	}
	504
b326e956	505	perf_bp_event(bp, args->regs);
0067f129	506
0c4519e8 FW	507	/*
	508	* Set up resume flag to avoid breakpoint recursion when
	509	* returning back to origin.
	510	*/
	511	if (bp->hw.info.type == X86_BREAKPOINT_EXECUTE)
	512	args->regs->flags \|= X86_EFLAGS_RF;
	513
24f1e32c	514	rcu_read_unlock();
0067f129	515	}
e0e53db6 P	516	/*
	517	* Further processing in do_debug() is needed for a) user-space
	518	* breakpoints (to generate signals) and b) when the system has
	519	* taken exception due to multiple causes
	520	*/
	521	if ((current->thread.debugreg6 & DR_TRAP_BITS) \|\|
	522	(dr6 & (~DR_TRAP_BITS)))
0067f129 P	523	rc = NOTIFY_DONE;
	524
	525	set_debugreg(dr7, 7);
eadb8a09	526	put_cpu();
24f1e32c	527
0067f129 P	528	return rc;
	529	}
	530
	531	/*
	532	* Handle debug exception notifications.
	533	*/
9c54b616	534	int hw_breakpoint_exceptions_notify(
0067f129 P	535	struct notifier_block unused, unsigned long val, void data)
	536	{
	537	if (val != DIE_DEBUG)
	538	return NOTIFY_DONE;
	539
	540	return hw_breakpoint_handler(data);
	541	}
24f1e32c FW	542
	543	void hw_breakpoint_pmu_read(struct perf_event *bp)
	544	{
	545	/* TODO */
	546	}