Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Copyright (C) 1994 Linus Torvalds |
3 | * | |
4 | * Pentium III FXSR, SSE support | |
5 | * General FPU state handling cleanups | |
6 | * Gareth Hughes <gareth@valinux.com>, May 2000 | |
7 | */ | |
129f6946 | 8 | #include <linux/module.h> |
44210111 | 9 | #include <linux/regset.h> |
f668964e | 10 | #include <linux/sched.h> |
5a0e3ad6 | 11 | #include <linux/slab.h> |
f668964e IM |
12 | |
13 | #include <asm/sigcontext.h> | |
1da177e4 | 14 | #include <asm/processor.h> |
1da177e4 | 15 | #include <asm/math_emu.h> |
375074cc | 16 | #include <asm/tlbflush.h> |
1da177e4 | 17 | #include <asm/uaccess.h> |
f668964e IM |
18 | #include <asm/ptrace.h> |
19 | #include <asm/i387.h> | |
1361b83a | 20 | #include <asm/fpu-internal.h> |
f668964e | 21 | #include <asm/user.h> |
1da177e4 | 22 | |
14e153ef ON |
23 | static DEFINE_PER_CPU(bool, in_kernel_fpu); |
24 | ||
7575637a ON |
25 | void kernel_fpu_disable(void) |
26 | { | |
27 | WARN_ON(this_cpu_read(in_kernel_fpu)); | |
28 | this_cpu_write(in_kernel_fpu, true); | |
29 | } | |
30 | ||
31 | void kernel_fpu_enable(void) | |
32 | { | |
33 | this_cpu_write(in_kernel_fpu, false); | |
34 | } | |
35 | ||
8546c008 LT |
36 | /* |
37 | * Were we in an interrupt that interrupted kernel mode? | |
38 | * | |
304bceda | 39 | * On others, we can do a kernel_fpu_begin/end() pair *ONLY* if that |
8546c008 LT |
40 | * pair does nothing at all: the thread must not have fpu (so |
41 | * that we don't try to save the FPU state), and TS must | |
42 | * be set (so that the clts/stts pair does nothing that is | |
43 | * visible in the interrupted kernel thread). | |
5187b28f | 44 | * |
4b2e762e ON |
45 | * Except for the eagerfpu case when we return true; in the likely case |
46 | * the thread has FPU but we are not going to set/clear TS. | |
8546c008 LT |
47 | */ |
48 | static inline bool interrupted_kernel_fpu_idle(void) | |
49 | { | |
14e153ef ON |
50 | if (this_cpu_read(in_kernel_fpu)) |
51 | return false; | |
52 | ||
5d2bd700 | 53 | if (use_eager_fpu()) |
4b2e762e | 54 | return true; |
304bceda | 55 | |
8546c008 LT |
56 | return !__thread_has_fpu(current) && |
57 | (read_cr0() & X86_CR0_TS); | |
58 | } | |
59 | ||
60 | /* | |
61 | * Were we in user mode (or vm86 mode) when we were | |
62 | * interrupted? | |
63 | * | |
64 | * Doing kernel_fpu_begin/end() is ok if we are running | |
65 | * in an interrupt context from user mode - we'll just | |
66 | * save the FPU state as required. | |
67 | */ | |
68 | static inline bool interrupted_user_mode(void) | |
69 | { | |
70 | struct pt_regs *regs = get_irq_regs(); | |
f39b6f0e | 71 | return regs && user_mode(regs); |
8546c008 LT |
72 | } |
73 | ||
74 | /* | |
75 | * Can we use the FPU in kernel mode with the | |
76 | * whole "kernel_fpu_begin/end()" sequence? | |
77 | * | |
78 | * It's always ok in process context (ie "not interrupt") | |
79 | * but it is sometimes ok even from an irq. | |
80 | */ | |
81 | bool irq_fpu_usable(void) | |
82 | { | |
83 | return !in_interrupt() || | |
84 | interrupted_user_mode() || | |
85 | interrupted_kernel_fpu_idle(); | |
86 | } | |
87 | EXPORT_SYMBOL(irq_fpu_usable); | |
88 | ||
b1a74bf8 | 89 | void __kernel_fpu_begin(void) |
8546c008 LT |
90 | { |
91 | struct task_struct *me = current; | |
92 | ||
14e153ef ON |
93 | this_cpu_write(in_kernel_fpu, true); |
94 | ||
8546c008 | 95 | if (__thread_has_fpu(me)) { |
5187b28f | 96 | __save_init_fpu(me); |
7aeccb83 | 97 | } else { |
c6ae41e7 | 98 | this_cpu_write(fpu_owner_task, NULL); |
7aeccb83 ON |
99 | if (!use_eager_fpu()) |
100 | clts(); | |
8546c008 LT |
101 | } |
102 | } | |
b1a74bf8 | 103 | EXPORT_SYMBOL(__kernel_fpu_begin); |
8546c008 | 104 | |
b1a74bf8 | 105 | void __kernel_fpu_end(void) |
8546c008 | 106 | { |
33a3ebdc ON |
107 | struct task_struct *me = current; |
108 | ||
109 | if (__thread_has_fpu(me)) { | |
110 | if (WARN_ON(restore_fpu_checking(me))) | |
b85e67d1 | 111 | fpu_reset_state(me); |
33a3ebdc | 112 | } else if (!use_eager_fpu()) { |
304bceda | 113 | stts(); |
731bd6a9 | 114 | } |
14e153ef ON |
115 | |
116 | this_cpu_write(in_kernel_fpu, false); | |
8546c008 | 117 | } |
b1a74bf8 | 118 | EXPORT_SYMBOL(__kernel_fpu_end); |
8546c008 LT |
119 | |
120 | void unlazy_fpu(struct task_struct *tsk) | |
121 | { | |
122 | preempt_disable(); | |
123 | if (__thread_has_fpu(tsk)) { | |
1a2a7f4e ON |
124 | if (use_eager_fpu()) { |
125 | __save_fpu(tsk); | |
126 | } else { | |
127 | __save_init_fpu(tsk); | |
128 | __thread_fpu_end(tsk); | |
129 | } | |
a9241ea5 | 130 | } |
8546c008 LT |
131 | preempt_enable(); |
132 | } | |
133 | EXPORT_SYMBOL(unlazy_fpu); | |
134 | ||
72a671ce | 135 | unsigned int mxcsr_feature_mask __read_mostly = 0xffffffffu; |
61c4628b | 136 | unsigned int xstate_size; |
f45755b8 | 137 | EXPORT_SYMBOL_GPL(xstate_size); |
148f9bb8 | 138 | static struct i387_fxsave_struct fx_scratch; |
1da177e4 | 139 | |
148f9bb8 | 140 | static void mxcsr_feature_mask_init(void) |
1da177e4 LT |
141 | { |
142 | unsigned long mask = 0; | |
f668964e | 143 | |
1da177e4 | 144 | if (cpu_has_fxsr) { |
61c4628b | 145 | memset(&fx_scratch, 0, sizeof(struct i387_fxsave_struct)); |
eaa5a990 | 146 | asm volatile("fxsave %0" : "+m" (fx_scratch)); |
61c4628b | 147 | mask = fx_scratch.mxcsr_mask; |
3b095a04 CG |
148 | if (mask == 0) |
149 | mask = 0x0000ffbf; | |
150 | } | |
1da177e4 | 151 | mxcsr_feature_mask &= mask; |
1da177e4 LT |
152 | } |
153 | ||
148f9bb8 | 154 | static void init_thread_xstate(void) |
61c4628b | 155 | { |
0e49bf66 RR |
156 | /* |
157 | * Note that xstate_size might be overwriten later during | |
158 | * xsave_init(). | |
159 | */ | |
160 | ||
60e019eb | 161 | if (!cpu_has_fpu) { |
1f999ab5 RR |
162 | /* |
163 | * Disable xsave as we do not support it if i387 | |
164 | * emulation is enabled. | |
165 | */ | |
166 | setup_clear_cpu_cap(X86_FEATURE_XSAVE); | |
167 | setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); | |
e8a496ac SS |
168 | xstate_size = sizeof(struct i387_soft_struct); |
169 | return; | |
170 | } | |
171 | ||
61c4628b SS |
172 | if (cpu_has_fxsr) |
173 | xstate_size = sizeof(struct i387_fxsave_struct); | |
61c4628b SS |
174 | else |
175 | xstate_size = sizeof(struct i387_fsave_struct); | |
e88221c5 IM |
176 | |
177 | /* | |
178 | * Quirk: we don't yet handle the XSAVES* instructions | |
179 | * correctly, as we don't correctly convert between | |
180 | * standard and compacted format when interfacing | |
181 | * with user-space - so disable it for now. | |
182 | * | |
183 | * The difference is small: with recent CPUs the | |
184 | * compacted format is only marginally smaller than | |
185 | * the standard FPU state format. | |
186 | * | |
187 | * ( This is easy to backport while we are fixing | |
188 | * XSAVES* support. ) | |
189 | */ | |
190 | setup_clear_cpu_cap(X86_FEATURE_XSAVES); | |
61c4628b SS |
191 | } |
192 | ||
44210111 RM |
193 | /* |
194 | * Called at bootup to set up the initial FPU state that is later cloned | |
195 | * into all processes. | |
196 | */ | |
0e49bf66 | 197 | |
148f9bb8 | 198 | void fpu_init(void) |
44210111 | 199 | { |
6ac8bac2 BG |
200 | unsigned long cr0; |
201 | unsigned long cr4_mask = 0; | |
44210111 | 202 | |
60e019eb PA |
203 | #ifndef CONFIG_MATH_EMULATION |
204 | if (!cpu_has_fpu) { | |
205 | pr_emerg("No FPU found and no math emulation present\n"); | |
206 | pr_emerg("Giving up\n"); | |
207 | for (;;) | |
208 | asm volatile("hlt"); | |
209 | } | |
210 | #endif | |
6ac8bac2 BG |
211 | if (cpu_has_fxsr) |
212 | cr4_mask |= X86_CR4_OSFXSR; | |
213 | if (cpu_has_xmm) | |
214 | cr4_mask |= X86_CR4_OSXMMEXCPT; | |
215 | if (cr4_mask) | |
375074cc | 216 | cr4_set_bits(cr4_mask); |
6ac8bac2 BG |
217 | |
218 | cr0 = read_cr0(); | |
219 | cr0 &= ~(X86_CR0_TS|X86_CR0_EM); /* clear TS and EM */ | |
60e019eb | 220 | if (!cpu_has_fpu) |
6ac8bac2 BG |
221 | cr0 |= X86_CR0_EM; |
222 | write_cr0(cr0); | |
44210111 | 223 | |
6f5298c2 FY |
224 | /* |
225 | * init_thread_xstate is only called once to avoid overriding | |
226 | * xstate_size during boot time or during CPU hotplug. | |
227 | */ | |
228 | if (xstate_size == 0) | |
dc1e35c6 | 229 | init_thread_xstate(); |
dc1e35c6 | 230 | |
44210111 | 231 | mxcsr_feature_mask_init(); |
5d2bd700 SS |
232 | xsave_init(); |
233 | eager_fpu_init(); | |
44210111 | 234 | } |
0e49bf66 | 235 | |
5ee481da | 236 | void fpu_finit(struct fpu *fpu) |
1da177e4 | 237 | { |
60e019eb | 238 | if (!cpu_has_fpu) { |
86603283 AK |
239 | finit_soft_fpu(&fpu->state->soft); |
240 | return; | |
e8a496ac | 241 | } |
e8a496ac | 242 | |
1d23c451 ON |
243 | memset(fpu->state, 0, xstate_size); |
244 | ||
1da177e4 | 245 | if (cpu_has_fxsr) { |
5d2bd700 | 246 | fx_finit(&fpu->state->fxsave); |
1da177e4 | 247 | } else { |
86603283 | 248 | struct i387_fsave_struct *fp = &fpu->state->fsave; |
61c4628b SS |
249 | fp->cwd = 0xffff037fu; |
250 | fp->swd = 0xffff0000u; | |
251 | fp->twd = 0xffffffffu; | |
252 | fp->fos = 0xffff0000u; | |
1da177e4 | 253 | } |
86603283 | 254 | } |
5ee481da | 255 | EXPORT_SYMBOL_GPL(fpu_finit); |
86603283 AK |
256 | |
257 | /* | |
258 | * The _current_ task is using the FPU for the first time | |
259 | * so initialize it and set the mxcsr to its default | |
260 | * value at reset if we support XMM instructions and then | |
0d2eb44f | 261 | * remember the current task has used the FPU. |
86603283 AK |
262 | */ |
263 | int init_fpu(struct task_struct *tsk) | |
264 | { | |
265 | int ret; | |
266 | ||
267 | if (tsk_used_math(tsk)) { | |
60e019eb | 268 | if (cpu_has_fpu && tsk == current) |
86603283 | 269 | unlazy_fpu(tsk); |
6a5fe895 | 270 | task_disable_lazy_fpu_restore(tsk); |
86603283 AK |
271 | return 0; |
272 | } | |
273 | ||
44210111 | 274 | /* |
86603283 | 275 | * Memory allocation at the first usage of the FPU and other state. |
44210111 | 276 | */ |
86603283 AK |
277 | ret = fpu_alloc(&tsk->thread.fpu); |
278 | if (ret) | |
279 | return ret; | |
280 | ||
281 | fpu_finit(&tsk->thread.fpu); | |
282 | ||
1da177e4 | 283 | set_stopped_child_used_math(tsk); |
aa283f49 | 284 | return 0; |
1da177e4 | 285 | } |
e5c30142 | 286 | EXPORT_SYMBOL_GPL(init_fpu); |
1da177e4 | 287 | |
5b3efd50 SS |
288 | /* |
289 | * The xstateregs_active() routine is the same as the fpregs_active() routine, | |
290 | * as the "regset->n" for the xstate regset will be updated based on the feature | |
291 | * capabilites supported by the xsave. | |
292 | */ | |
44210111 RM |
293 | int fpregs_active(struct task_struct *target, const struct user_regset *regset) |
294 | { | |
295 | return tsk_used_math(target) ? regset->n : 0; | |
296 | } | |
1da177e4 | 297 | |
44210111 | 298 | int xfpregs_active(struct task_struct *target, const struct user_regset *regset) |
1da177e4 | 299 | { |
44210111 RM |
300 | return (cpu_has_fxsr && tsk_used_math(target)) ? regset->n : 0; |
301 | } | |
1da177e4 | 302 | |
44210111 RM |
303 | int xfpregs_get(struct task_struct *target, const struct user_regset *regset, |
304 | unsigned int pos, unsigned int count, | |
305 | void *kbuf, void __user *ubuf) | |
306 | { | |
aa283f49 SS |
307 | int ret; |
308 | ||
44210111 RM |
309 | if (!cpu_has_fxsr) |
310 | return -ENODEV; | |
311 | ||
aa283f49 SS |
312 | ret = init_fpu(target); |
313 | if (ret) | |
314 | return ret; | |
44210111 | 315 | |
29104e10 SS |
316 | sanitize_i387_state(target); |
317 | ||
44210111 | 318 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, |
86603283 | 319 | &target->thread.fpu.state->fxsave, 0, -1); |
1da177e4 | 320 | } |
44210111 RM |
321 | |
322 | int xfpregs_set(struct task_struct *target, const struct user_regset *regset, | |
323 | unsigned int pos, unsigned int count, | |
324 | const void *kbuf, const void __user *ubuf) | |
325 | { | |
326 | int ret; | |
327 | ||
328 | if (!cpu_has_fxsr) | |
329 | return -ENODEV; | |
330 | ||
aa283f49 SS |
331 | ret = init_fpu(target); |
332 | if (ret) | |
333 | return ret; | |
334 | ||
29104e10 SS |
335 | sanitize_i387_state(target); |
336 | ||
44210111 | 337 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, |
86603283 | 338 | &target->thread.fpu.state->fxsave, 0, -1); |
44210111 RM |
339 | |
340 | /* | |
341 | * mxcsr reserved bits must be masked to zero for security reasons. | |
342 | */ | |
86603283 | 343 | target->thread.fpu.state->fxsave.mxcsr &= mxcsr_feature_mask; |
44210111 | 344 | |
42deec6f SS |
345 | /* |
346 | * update the header bits in the xsave header, indicating the | |
347 | * presence of FP and SSE state. | |
348 | */ | |
349 | if (cpu_has_xsave) | |
86603283 | 350 | target->thread.fpu.state->xsave.xsave_hdr.xstate_bv |= XSTATE_FPSSE; |
42deec6f | 351 | |
44210111 RM |
352 | return ret; |
353 | } | |
354 | ||
5b3efd50 SS |
355 | int xstateregs_get(struct task_struct *target, const struct user_regset *regset, |
356 | unsigned int pos, unsigned int count, | |
357 | void *kbuf, void __user *ubuf) | |
358 | { | |
18ecb3bf | 359 | struct xsave_struct *xsave; |
5b3efd50 SS |
360 | int ret; |
361 | ||
362 | if (!cpu_has_xsave) | |
363 | return -ENODEV; | |
364 | ||
365 | ret = init_fpu(target); | |
366 | if (ret) | |
367 | return ret; | |
368 | ||
18ecb3bf BP |
369 | xsave = &target->thread.fpu.state->xsave; |
370 | ||
5b3efd50 | 371 | /* |
ff7fbc72 SS |
372 | * Copy the 48bytes defined by the software first into the xstate |
373 | * memory layout in the thread struct, so that we can copy the entire | |
374 | * xstateregs to the user using one user_regset_copyout(). | |
5b3efd50 | 375 | */ |
e7f180dc ON |
376 | memcpy(&xsave->i387.sw_reserved, |
377 | xstate_fx_sw_bytes, sizeof(xstate_fx_sw_bytes)); | |
5b3efd50 | 378 | /* |
ff7fbc72 | 379 | * Copy the xstate memory layout. |
5b3efd50 | 380 | */ |
e7f180dc | 381 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, xsave, 0, -1); |
5b3efd50 SS |
382 | return ret; |
383 | } | |
384 | ||
385 | int xstateregs_set(struct task_struct *target, const struct user_regset *regset, | |
386 | unsigned int pos, unsigned int count, | |
387 | const void *kbuf, const void __user *ubuf) | |
388 | { | |
18ecb3bf | 389 | struct xsave_struct *xsave; |
5b3efd50 | 390 | int ret; |
5b3efd50 SS |
391 | |
392 | if (!cpu_has_xsave) | |
393 | return -ENODEV; | |
394 | ||
395 | ret = init_fpu(target); | |
396 | if (ret) | |
397 | return ret; | |
398 | ||
18ecb3bf BP |
399 | xsave = &target->thread.fpu.state->xsave; |
400 | ||
e7f180dc | 401 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, xsave, 0, -1); |
5b3efd50 SS |
402 | /* |
403 | * mxcsr reserved bits must be masked to zero for security reasons. | |
404 | */ | |
e7f180dc ON |
405 | xsave->i387.mxcsr &= mxcsr_feature_mask; |
406 | xsave->xsave_hdr.xstate_bv &= pcntxt_mask; | |
5b3efd50 SS |
407 | /* |
408 | * These bits must be zero. | |
409 | */ | |
e7f180dc | 410 | memset(&xsave->xsave_hdr.reserved, 0, 48); |
5b3efd50 SS |
411 | return ret; |
412 | } | |
413 | ||
44210111 | 414 | #if defined CONFIG_X86_32 || defined CONFIG_IA32_EMULATION |
1da177e4 | 415 | |
1da177e4 LT |
416 | /* |
417 | * FPU tag word conversions. | |
418 | */ | |
419 | ||
3b095a04 | 420 | static inline unsigned short twd_i387_to_fxsr(unsigned short twd) |
1da177e4 LT |
421 | { |
422 | unsigned int tmp; /* to avoid 16 bit prefixes in the code */ | |
3b095a04 | 423 | |
1da177e4 | 424 | /* Transform each pair of bits into 01 (valid) or 00 (empty) */ |
3b095a04 | 425 | tmp = ~twd; |
44210111 | 426 | tmp = (tmp | (tmp>>1)) & 0x5555; /* 0V0V0V0V0V0V0V0V */ |
3b095a04 CG |
427 | /* and move the valid bits to the lower byte. */ |
428 | tmp = (tmp | (tmp >> 1)) & 0x3333; /* 00VV00VV00VV00VV */ | |
429 | tmp = (tmp | (tmp >> 2)) & 0x0f0f; /* 0000VVVV0000VVVV */ | |
430 | tmp = (tmp | (tmp >> 4)) & 0x00ff; /* 00000000VVVVVVVV */ | |
f668964e | 431 | |
3b095a04 | 432 | return tmp; |
1da177e4 LT |
433 | } |
434 | ||
497888cf | 435 | #define FPREG_ADDR(f, n) ((void *)&(f)->st_space + (n) * 16) |
44210111 RM |
436 | #define FP_EXP_TAG_VALID 0 |
437 | #define FP_EXP_TAG_ZERO 1 | |
438 | #define FP_EXP_TAG_SPECIAL 2 | |
439 | #define FP_EXP_TAG_EMPTY 3 | |
440 | ||
441 | static inline u32 twd_fxsr_to_i387(struct i387_fxsave_struct *fxsave) | |
442 | { | |
443 | struct _fpxreg *st; | |
444 | u32 tos = (fxsave->swd >> 11) & 7; | |
445 | u32 twd = (unsigned long) fxsave->twd; | |
446 | u32 tag; | |
447 | u32 ret = 0xffff0000u; | |
448 | int i; | |
1da177e4 | 449 | |
44210111 | 450 | for (i = 0; i < 8; i++, twd >>= 1) { |
3b095a04 CG |
451 | if (twd & 0x1) { |
452 | st = FPREG_ADDR(fxsave, (i - tos) & 7); | |
1da177e4 | 453 | |
3b095a04 | 454 | switch (st->exponent & 0x7fff) { |
1da177e4 | 455 | case 0x7fff: |
44210111 | 456 | tag = FP_EXP_TAG_SPECIAL; |
1da177e4 LT |
457 | break; |
458 | case 0x0000: | |
3b095a04 CG |
459 | if (!st->significand[0] && |
460 | !st->significand[1] && | |
461 | !st->significand[2] && | |
44210111 RM |
462 | !st->significand[3]) |
463 | tag = FP_EXP_TAG_ZERO; | |
464 | else | |
465 | tag = FP_EXP_TAG_SPECIAL; | |
1da177e4 LT |
466 | break; |
467 | default: | |
44210111 RM |
468 | if (st->significand[3] & 0x8000) |
469 | tag = FP_EXP_TAG_VALID; | |
470 | else | |
471 | tag = FP_EXP_TAG_SPECIAL; | |
1da177e4 LT |
472 | break; |
473 | } | |
474 | } else { | |
44210111 | 475 | tag = FP_EXP_TAG_EMPTY; |
1da177e4 | 476 | } |
44210111 | 477 | ret |= tag << (2 * i); |
1da177e4 LT |
478 | } |
479 | return ret; | |
480 | } | |
481 | ||
482 | /* | |
44210111 | 483 | * FXSR floating point environment conversions. |
1da177e4 LT |
484 | */ |
485 | ||
72a671ce | 486 | void |
f668964e | 487 | convert_from_fxsr(struct user_i387_ia32_struct *env, struct task_struct *tsk) |
1da177e4 | 488 | { |
86603283 | 489 | struct i387_fxsave_struct *fxsave = &tsk->thread.fpu.state->fxsave; |
44210111 RM |
490 | struct _fpreg *to = (struct _fpreg *) &env->st_space[0]; |
491 | struct _fpxreg *from = (struct _fpxreg *) &fxsave->st_space[0]; | |
492 | int i; | |
1da177e4 | 493 | |
44210111 RM |
494 | env->cwd = fxsave->cwd | 0xffff0000u; |
495 | env->swd = fxsave->swd | 0xffff0000u; | |
496 | env->twd = twd_fxsr_to_i387(fxsave); | |
497 | ||
498 | #ifdef CONFIG_X86_64 | |
499 | env->fip = fxsave->rip; | |
500 | env->foo = fxsave->rdp; | |
10c11f30 BG |
501 | /* |
502 | * should be actually ds/cs at fpu exception time, but | |
503 | * that information is not available in 64bit mode. | |
504 | */ | |
505 | env->fcs = task_pt_regs(tsk)->cs; | |
44210111 | 506 | if (tsk == current) { |
10c11f30 | 507 | savesegment(ds, env->fos); |
1da177e4 | 508 | } else { |
10c11f30 | 509 | env->fos = tsk->thread.ds; |
1da177e4 | 510 | } |
10c11f30 | 511 | env->fos |= 0xffff0000; |
44210111 RM |
512 | #else |
513 | env->fip = fxsave->fip; | |
609b5297 | 514 | env->fcs = (u16) fxsave->fcs | ((u32) fxsave->fop << 16); |
44210111 RM |
515 | env->foo = fxsave->foo; |
516 | env->fos = fxsave->fos; | |
517 | #endif | |
1da177e4 | 518 | |
44210111 RM |
519 | for (i = 0; i < 8; ++i) |
520 | memcpy(&to[i], &from[i], sizeof(to[0])); | |
1da177e4 LT |
521 | } |
522 | ||
72a671ce SS |
523 | void convert_to_fxsr(struct task_struct *tsk, |
524 | const struct user_i387_ia32_struct *env) | |
1da177e4 | 525 | |
1da177e4 | 526 | { |
86603283 | 527 | struct i387_fxsave_struct *fxsave = &tsk->thread.fpu.state->fxsave; |
44210111 RM |
528 | struct _fpreg *from = (struct _fpreg *) &env->st_space[0]; |
529 | struct _fpxreg *to = (struct _fpxreg *) &fxsave->st_space[0]; | |
530 | int i; | |
1da177e4 | 531 | |
44210111 RM |
532 | fxsave->cwd = env->cwd; |
533 | fxsave->swd = env->swd; | |
534 | fxsave->twd = twd_i387_to_fxsr(env->twd); | |
535 | fxsave->fop = (u16) ((u32) env->fcs >> 16); | |
536 | #ifdef CONFIG_X86_64 | |
537 | fxsave->rip = env->fip; | |
538 | fxsave->rdp = env->foo; | |
539 | /* cs and ds ignored */ | |
540 | #else | |
541 | fxsave->fip = env->fip; | |
542 | fxsave->fcs = (env->fcs & 0xffff); | |
543 | fxsave->foo = env->foo; | |
544 | fxsave->fos = env->fos; | |
545 | #endif | |
1da177e4 | 546 | |
44210111 RM |
547 | for (i = 0; i < 8; ++i) |
548 | memcpy(&to[i], &from[i], sizeof(from[0])); | |
1da177e4 LT |
549 | } |
550 | ||
44210111 RM |
551 | int fpregs_get(struct task_struct *target, const struct user_regset *regset, |
552 | unsigned int pos, unsigned int count, | |
553 | void *kbuf, void __user *ubuf) | |
1da177e4 | 554 | { |
44210111 | 555 | struct user_i387_ia32_struct env; |
aa283f49 | 556 | int ret; |
1da177e4 | 557 | |
aa283f49 SS |
558 | ret = init_fpu(target); |
559 | if (ret) | |
560 | return ret; | |
1da177e4 | 561 | |
60e019eb | 562 | if (!static_cpu_has(X86_FEATURE_FPU)) |
e8a496ac SS |
563 | return fpregs_soft_get(target, regset, pos, count, kbuf, ubuf); |
564 | ||
60e019eb | 565 | if (!cpu_has_fxsr) |
44210111 | 566 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, |
86603283 | 567 | &target->thread.fpu.state->fsave, 0, |
61c4628b | 568 | -1); |
1da177e4 | 569 | |
29104e10 SS |
570 | sanitize_i387_state(target); |
571 | ||
44210111 RM |
572 | if (kbuf && pos == 0 && count == sizeof(env)) { |
573 | convert_from_fxsr(kbuf, target); | |
574 | return 0; | |
1da177e4 | 575 | } |
44210111 RM |
576 | |
577 | convert_from_fxsr(&env, target); | |
f668964e | 578 | |
44210111 | 579 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, &env, 0, -1); |
1da177e4 LT |
580 | } |
581 | ||
44210111 RM |
582 | int fpregs_set(struct task_struct *target, const struct user_regset *regset, |
583 | unsigned int pos, unsigned int count, | |
584 | const void *kbuf, const void __user *ubuf) | |
1da177e4 | 585 | { |
44210111 RM |
586 | struct user_i387_ia32_struct env; |
587 | int ret; | |
1da177e4 | 588 | |
aa283f49 SS |
589 | ret = init_fpu(target); |
590 | if (ret) | |
591 | return ret; | |
592 | ||
29104e10 SS |
593 | sanitize_i387_state(target); |
594 | ||
60e019eb | 595 | if (!static_cpu_has(X86_FEATURE_FPU)) |
e8a496ac SS |
596 | return fpregs_soft_set(target, regset, pos, count, kbuf, ubuf); |
597 | ||
60e019eb | 598 | if (!cpu_has_fxsr) |
44210111 | 599 | return user_regset_copyin(&pos, &count, &kbuf, &ubuf, |
60e019eb PA |
600 | &target->thread.fpu.state->fsave, 0, |
601 | -1); | |
44210111 RM |
602 | |
603 | if (pos > 0 || count < sizeof(env)) | |
604 | convert_from_fxsr(&env, target); | |
605 | ||
606 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &env, 0, -1); | |
607 | if (!ret) | |
608 | convert_to_fxsr(target, &env); | |
609 | ||
42deec6f SS |
610 | /* |
611 | * update the header bit in the xsave header, indicating the | |
612 | * presence of FP. | |
613 | */ | |
614 | if (cpu_has_xsave) | |
86603283 | 615 | target->thread.fpu.state->xsave.xsave_hdr.xstate_bv |= XSTATE_FP; |
44210111 | 616 | return ret; |
1da177e4 LT |
617 | } |
618 | ||
1da177e4 LT |
619 | /* |
620 | * FPU state for core dumps. | |
60b3b9af RM |
621 | * This is only used for a.out dumps now. |
622 | * It is declared generically using elf_fpregset_t (which is | |
623 | * struct user_i387_struct) but is in fact only used for 32-bit | |
624 | * dumps, so on 64-bit it is really struct user_i387_ia32_struct. | |
1da177e4 | 625 | */ |
3b095a04 | 626 | int dump_fpu(struct pt_regs *regs, struct user_i387_struct *fpu) |
1da177e4 | 627 | { |
1da177e4 | 628 | struct task_struct *tsk = current; |
f668964e | 629 | int fpvalid; |
1da177e4 LT |
630 | |
631 | fpvalid = !!used_math(); | |
60b3b9af RM |
632 | if (fpvalid) |
633 | fpvalid = !fpregs_get(tsk, NULL, | |
634 | 0, sizeof(struct user_i387_ia32_struct), | |
635 | fpu, NULL); | |
1da177e4 LT |
636 | |
637 | return fpvalid; | |
638 | } | |
129f6946 | 639 | EXPORT_SYMBOL(dump_fpu); |
1da177e4 | 640 | |
60b3b9af | 641 | #endif /* CONFIG_X86_32 || CONFIG_IA32_EMULATION */ |
60e019eb PA |
642 | |
643 | static int __init no_387(char *s) | |
644 | { | |
645 | setup_clear_cpu_cap(X86_FEATURE_FPU); | |
646 | return 1; | |
647 | } | |
648 | ||
649 | __setup("no387", no_387); | |
650 | ||
148f9bb8 | 651 | void fpu_detect(struct cpuinfo_x86 *c) |
60e019eb PA |
652 | { |
653 | unsigned long cr0; | |
654 | u16 fsw, fcw; | |
655 | ||
656 | fsw = fcw = 0xffff; | |
657 | ||
658 | cr0 = read_cr0(); | |
659 | cr0 &= ~(X86_CR0_TS | X86_CR0_EM); | |
660 | write_cr0(cr0); | |
661 | ||
662 | asm volatile("fninit ; fnstsw %0 ; fnstcw %1" | |
663 | : "+m" (fsw), "+m" (fcw)); | |
664 | ||
665 | if (fsw == 0 && (fcw & 0x103f) == 0x003f) | |
666 | set_cpu_cap(c, X86_FEATURE_FPU); | |
667 | else | |
668 | clear_cpu_cap(c, X86_FEATURE_FPU); | |
669 | ||
670 | /* The final cr0 value is set in fpu_init() */ | |
671 | } |