[deliverable/linux.git] / arch / x86 / kernel / i387.c

/*
 *  Copyright (C) 1994 Linus Torvalds
 *
 *  Pentium III FXSR, SSE support
 *  General FPU state handling cleanups
 *	Gareth Hughes <gareth@valinux.com>, May 2000
 */
#include <linux/module.h>
#include <linux/regset.h>
#include <linux/sched.h>

#include <asm/sigcontext.h>
#include <asm/processor.h>
#include <asm/math_emu.h>
#include <asm/uaccess.h>
#include <asm/ptrace.h>
#include <asm/i387.h>
#include <asm/user.h>

#ifdef CONFIG_X86_64
# include <asm/sigcontext32.h>
# include <asm/user32.h>
#else
# define save_i387_ia32		save_i387
# define restore_i387_ia32	restore_i387
# define _fpstate_ia32		_fpstate
# define user_i387_ia32_struct	user_i387_struct
# define user32_fxsr_struct	user_fxsr_struct
#endif

#ifdef CONFIG_MATH_EMULATION
# define HAVE_HWFP		(boot_cpu_data.hard_math)
#else
# define HAVE_HWFP		1
#endif

static unsigned int		mxcsr_feature_mask __read_mostly = 0xffffffffu;

void mxcsr_feature_mask_init(void)
{
	unsigned long mask = 0;

	clts();
	if (cpu_has_fxsr) {
		memset(&current->thread.i387.fxsave, 0,
		       sizeof(struct i387_fxsave_struct));
		asm volatile("fxsave %0" : : "m" (current->thread.i387.fxsave));
		mask = current->thread.i387.fxsave.mxcsr_mask;
		if (mask == 0)
			mask = 0x0000ffbf;
	}
	mxcsr_feature_mask &= mask;
	stts();
}

#ifdef CONFIG_X86_64
/*
 * Called at bootup to set up the initial FPU state that is later cloned
 * into all processes.
 */
void __cpuinit fpu_init(void)
{
	unsigned long oldcr0 = read_cr0();
	extern void __bad_fxsave_alignment(void);

	if (offsetof(struct task_struct, thread.i387.fxsave) & 15)
		__bad_fxsave_alignment();

	set_in_cr4(X86_CR4_OSFXSR);
	set_in_cr4(X86_CR4_OSXMMEXCPT);

	write_cr0(oldcr0 & ~(X86_CR0_TS|X86_CR0_EM)); /* clear TS and EM */

	mxcsr_feature_mask_init();
	/* clean state in init */
	current_thread_info()->status = 0;
	clear_used_math();
}
#endif	/* CONFIG_X86_64 */

/*
 * The _current_ task is using the FPU for the first time
 * so initialize it and set the mxcsr to its default
 * value at reset if we support XMM instructions and then
 * remeber the current task has used the FPU.
 */
void init_fpu(struct task_struct *tsk)
{
	if (tsk_used_math(tsk)) {
		if (tsk == current)
			unlazy_fpu(tsk);
		return;
	}

	if (cpu_has_fxsr) {
		memset(&tsk->thread.i387.fxsave, 0,
		       sizeof(struct i387_fxsave_struct));
		tsk->thread.i387.fxsave.cwd = 0x37f;
		if (cpu_has_xmm)
			tsk->thread.i387.fxsave.mxcsr = MXCSR_DEFAULT;
	} else {
		memset(&tsk->thread.i387.fsave, 0,
		       sizeof(struct i387_fsave_struct));
		tsk->thread.i387.fsave.cwd = 0xffff037fu;
		tsk->thread.i387.fsave.swd = 0xffff0000u;
		tsk->thread.i387.fsave.twd = 0xffffffffu;
		tsk->thread.i387.fsave.fos = 0xffff0000u;
	}
	/*
	 * Only the device not available exception or ptrace can call init_fpu.
	 */
	set_stopped_child_used_math(tsk);
}

int fpregs_active(struct task_struct *target, const struct user_regset *regset)
{
	return tsk_used_math(target) ? regset->n : 0;
}

int xfpregs_active(struct task_struct *target, const struct user_regset *regset)
{
	return (cpu_has_fxsr && tsk_used_math(target)) ? regset->n : 0;
}

int xfpregs_get(struct task_struct *target, const struct user_regset *regset,
		unsigned int pos, unsigned int count,
		void *kbuf, void __user *ubuf)
{
	if (!cpu_has_fxsr)
		return -ENODEV;

	init_fpu(target);

	return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
				   &target->thread.i387.fxsave, 0, -1);
}

int xfpregs_set(struct task_struct *target, const struct user_regset *regset,
		unsigned int pos, unsigned int count,
		const void *kbuf, const void __user *ubuf)
{
	int ret;

	if (!cpu_has_fxsr)
		return -ENODEV;

	init_fpu(target);
	set_stopped_child_used_math(target);

	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
				 &target->thread.i387.fxsave, 0, -1);

	/*
	 * mxcsr reserved bits must be masked to zero for security reasons.
	 */
	target->thread.i387.fxsave.mxcsr &= mxcsr_feature_mask;

	return ret;
}

#if defined CONFIG_X86_32 || defined CONFIG_IA32_EMULATION

/*
 * FPU tag word conversions.
 */

static inline unsigned short twd_i387_to_fxsr(unsigned short twd)
{
	unsigned int tmp; /* to avoid 16 bit prefixes in the code */

	/* Transform each pair of bits into 01 (valid) or 00 (empty) */
	tmp = ~twd;
	tmp = (tmp | (tmp>>1)) & 0x5555; /* 0V0V0V0V0V0V0V0V */
	/* and move the valid bits to the lower byte. */
	tmp = (tmp | (tmp >> 1)) & 0x3333; /* 00VV00VV00VV00VV */
	tmp = (tmp | (tmp >> 2)) & 0x0f0f; /* 0000VVVV0000VVVV */
	tmp = (tmp | (tmp >> 4)) & 0x00ff; /* 00000000VVVVVVVV */

	return tmp;
}

#define FPREG_ADDR(f, n)	((void *)&(f)->st_space + (n) * 16);
#define FP_EXP_TAG_VALID	0
#define FP_EXP_TAG_ZERO		1
#define FP_EXP_TAG_SPECIAL	2
#define FP_EXP_TAG_EMPTY	3

static inline u32 twd_fxsr_to_i387(struct i387_fxsave_struct *fxsave)
{
	struct _fpxreg *st;
	u32 tos = (fxsave->swd >> 11) & 7;
	u32 twd = (unsigned long) fxsave->twd;
	u32 tag;
	u32 ret = 0xffff0000u;
	int i;

	for (i = 0; i < 8; i++, twd >>= 1) {
		if (twd & 0x1) {
			st = FPREG_ADDR(fxsave, (i - tos) & 7);

			switch (st->exponent & 0x7fff) {
			case 0x7fff:
				tag = FP_EXP_TAG_SPECIAL;
				break;
			case 0x0000:
				if (!st->significand[0] &&
				    !st->significand[1] &&
				    !st->significand[2] &&
				    !st->significand[3])
					tag = FP_EXP_TAG_ZERO;
				else
					tag = FP_EXP_TAG_SPECIAL;
				break;
			default:
				if (st->significand[3] & 0x8000)
					tag = FP_EXP_TAG_VALID;
				else
					tag = FP_EXP_TAG_SPECIAL;
				break;
			}
		} else {
			tag = FP_EXP_TAG_EMPTY;
		}
		ret |= tag << (2 * i);
	}
	return ret;
}

/*
 * FXSR floating point environment conversions.
 */

static void
convert_from_fxsr(struct user_i387_ia32_struct *env, struct task_struct *tsk)
{
	struct i387_fxsave_struct *fxsave = &tsk->thread.i387.fxsave;
	struct _fpreg *to = (struct _fpreg *) &env->st_space[0];
	struct _fpxreg *from = (struct _fpxreg *) &fxsave->st_space[0];
	int i;

	env->cwd = fxsave->cwd | 0xffff0000u;
	env->swd = fxsave->swd | 0xffff0000u;
	env->twd = twd_fxsr_to_i387(fxsave);

#ifdef CONFIG_X86_64
	env->fip = fxsave->rip;
	env->foo = fxsave->rdp;
	if (tsk == current) {
		/*
		 * should be actually ds/cs at fpu exception time, but
		 * that information is not available in 64bit mode.
		 */
		asm("mov %%ds, %[fos]" : [fos] "=r" (env->fos));
		asm("mov %%cs, %[fcs]" : [fcs] "=r" (env->fcs));
	} else {
		struct pt_regs *regs = task_pt_regs(tsk);

		env->fos = 0xffff0000 | tsk->thread.ds;
		env->fcs = regs->cs;
	}
#else
	env->fip = fxsave->fip;
	env->fcs = (u16) fxsave->fcs | ((u32) fxsave->fop << 16);
	env->foo = fxsave->foo;
	env->fos = fxsave->fos;
#endif

	for (i = 0; i < 8; ++i)
		memcpy(&to[i], &from[i], sizeof(to[0]));
}

static void convert_to_fxsr(struct task_struct *tsk,
			    const struct user_i387_ia32_struct *env)

{
	struct i387_fxsave_struct *fxsave = &tsk->thread.i387.fxsave;
	struct _fpreg *from = (struct _fpreg *) &env->st_space[0];
	struct _fpxreg *to = (struct _fpxreg *) &fxsave->st_space[0];
	int i;

	fxsave->cwd = env->cwd;
	fxsave->swd = env->swd;
	fxsave->twd = twd_i387_to_fxsr(env->twd);
	fxsave->fop = (u16) ((u32) env->fcs >> 16);
#ifdef CONFIG_X86_64
	fxsave->rip = env->fip;
	fxsave->rdp = env->foo;
	/* cs and ds ignored */
#else
	fxsave->fip = env->fip;
	fxsave->fcs = (env->fcs & 0xffff);
	fxsave->foo = env->foo;
	fxsave->fos = env->fos;
#endif

	for (i = 0; i < 8; ++i)
		memcpy(&to[i], &from[i], sizeof(from[0]));
}

int fpregs_get(struct task_struct *target, const struct user_regset *regset,
	       unsigned int pos, unsigned int count,
	       void *kbuf, void __user *ubuf)
{
	struct user_i387_ia32_struct env;

	if (!HAVE_HWFP)
		return fpregs_soft_get(target, regset, pos, count, kbuf, ubuf);

	init_fpu(target);

	if (!cpu_has_fxsr) {
		return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
					   &target->thread.i387.fsave, 0, -1);
	}

	if (kbuf && pos == 0 && count == sizeof(env)) {
		convert_from_fxsr(kbuf, target);
		return 0;
	}

	convert_from_fxsr(&env, target);

	return user_regset_copyout(&pos, &count, &kbuf, &ubuf, &env, 0, -1);
}

int fpregs_set(struct task_struct *target, const struct user_regset *regset,
	       unsigned int pos, unsigned int count,
	       const void *kbuf, const void __user *ubuf)
{
	struct user_i387_ia32_struct env;
	int ret;

	if (!HAVE_HWFP)
		return fpregs_soft_set(target, regset, pos, count, kbuf, ubuf);

	init_fpu(target);
	set_stopped_child_used_math(target);

	if (!cpu_has_fxsr) {
		return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
					  &target->thread.i387.fsave, 0, -1);
	}

	if (pos > 0 || count < sizeof(env))
		convert_from_fxsr(&env, target);

	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &env, 0, -1);
	if (!ret)
		convert_to_fxsr(target, &env);

	return ret;
}

/*
 * Signal frame handlers.
 */

static inline int save_i387_fsave(struct _fpstate_ia32 __user *buf)
{
	struct task_struct *tsk = current;

	unlazy_fpu(tsk);
	tsk->thread.i387.fsave.status = tsk->thread.i387.fsave.swd;
	if (__copy_to_user(buf, &tsk->thread.i387.fsave,
			   sizeof(struct i387_fsave_struct)))
		return -1;
	return 1;
}

static int save_i387_fxsave(struct _fpstate_ia32 __user *buf)
{
	struct task_struct *tsk = current;
	struct user_i387_ia32_struct env;
	int err = 0;

	unlazy_fpu(tsk);

	convert_from_fxsr(&env, tsk);
	if (__copy_to_user(buf, &env, sizeof(env)))
		return -1;

	err |= __put_user(tsk->thread.i387.fxsave.swd, &buf->status);
	err |= __put_user(X86_FXSR_MAGIC, &buf->magic);
	if (err)
		return -1;

	if (__copy_to_user(&buf->_fxsr_env[0], &tsk->thread.i387.fxsave,
			   sizeof(struct i387_fxsave_struct)))
		return -1;
	return 1;
}

int save_i387_ia32(struct _fpstate_ia32 __user *buf)
{
	if (!used_math())
		return 0;
	/*
	 * This will cause a "finit" to be triggered by the next
	 * attempted FPU operation by the 'current' process.
	 */
	clear_used_math();

	if (!HAVE_HWFP) {
		return fpregs_soft_get(current, NULL,
				       0, sizeof(struct user_i387_ia32_struct),
				       NULL, buf) ? -1 : 1;
	}

	if (cpu_has_fxsr)
		return save_i387_fxsave(buf);
	else
		return save_i387_fsave(buf);
}

static inline int restore_i387_fsave(struct _fpstate_ia32 __user *buf)
{
	struct task_struct *tsk = current;

	clear_fpu(tsk);
	return __copy_from_user(&tsk->thread.i387.fsave, buf,
				sizeof(struct i387_fsave_struct));
}

static int restore_i387_fxsave(struct _fpstate_ia32 __user *buf)
{
	struct task_struct *tsk = current;
	struct user_i387_ia32_struct env;
	int err;

	clear_fpu(tsk);
	err = __copy_from_user(&tsk->thread.i387.fxsave, &buf->_fxsr_env[0],
			       sizeof(struct i387_fxsave_struct));
	/* mxcsr reserved bits must be masked to zero for security reasons */
	tsk->thread.i387.fxsave.mxcsr &= mxcsr_feature_mask;
	if (err || __copy_from_user(&env, buf, sizeof(env)))
		return 1;
	convert_to_fxsr(tsk, &env);

	return 0;
}

int restore_i387_ia32(struct _fpstate_ia32 __user *buf)
{
	int err;

	if (HAVE_HWFP) {
		if (cpu_has_fxsr)
			err = restore_i387_fxsave(buf);
		else
			err = restore_i387_fsave(buf);
	} else {
		err = fpregs_soft_set(current, NULL,
				      0, sizeof(struct user_i387_ia32_struct),
				      NULL, buf) != 0;
	}
	set_used_math();

	return err;
}

/*
 * FPU state for core dumps.
 * This is only used for a.out dumps now.
 * It is declared generically using elf_fpregset_t (which is
 * struct user_i387_struct) but is in fact only used for 32-bit
 * dumps, so on 64-bit it is really struct user_i387_ia32_struct.
 */
int dump_fpu(struct pt_regs *regs, struct user_i387_struct *fpu)
{
	struct task_struct *tsk = current;
	int fpvalid;

	fpvalid = !!used_math();
	if (fpvalid)
		fpvalid = !fpregs_get(tsk, NULL,
				      0, sizeof(struct user_i387_ia32_struct),
				      fpu, NULL);

	return fpvalid;
}
EXPORT_SYMBOL(dump_fpu);

#endif	/* CONFIG_X86_32 || CONFIG_IA32_EMULATION */
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* Copyright (C) 1994 Linus Torvalds
	3	*
	4	* Pentium III FXSR, SSE support
	5	* General FPU state handling cleanups
	6	* Gareth Hughes <gareth@valinux.com>, May 2000
	7	*/
129f6946	8	#include <linux/module.h>
44210111	9	#include <linux/regset.h>
f668964e IM	10	#include <linux/sched.h>
	11
	12	#include <asm/sigcontext.h>
1da177e4	13	#include <asm/processor.h>
1da177e4	14	#include <asm/math_emu.h>
1da177e4	15	#include <asm/uaccess.h>
f668964e IM	16	#include <asm/ptrace.h>
	17	#include <asm/i387.h>
	18	#include <asm/user.h>
1da177e4	19
44210111	20	#ifdef CONFIG_X86_64
f668964e IM	21	# include <asm/sigcontext32.h>
f668964e IM	22	# include <asm/user32.h>
44210111	23	#else
f668964e IM	24	# define save_i387_ia32 save_i387
	25	# define restore_i387_ia32 restore_i387
	26	# define _fpstate_ia32 _fpstate
	27	# define user_i387_ia32_struct user_i387_struct
	28	# define user32_fxsr_struct user_fxsr_struct
44210111 RM	29	#endif
44210111 RM	30
1da177e4	31	#ifdef CONFIG_MATH_EMULATION
f668964e	32	# define HAVE_HWFP (boot_cpu_data.hard_math)
1da177e4	33	#else
f668964e	34	# define HAVE_HWFP 1
1da177e4 LT	35	#endif
1da177e4 LT	36
f668964e	37	static unsigned int mxcsr_feature_mask __read_mostly = 0xffffffffu;
1da177e4 LT	38
	39	void mxcsr_feature_mask_init(void)
	40	{
	41	unsigned long mask = 0;
f668964e	42
1da177e4 LT	43	clts();
1da177e4 LT	44	if (cpu_has_fxsr) {
3b095a04 CG	45	memset(&current->thread.i387.fxsave, 0,
	46	sizeof(struct i387_fxsave_struct));
	47	asm volatile("fxsave %0" : : "m" (current->thread.i387.fxsave));
1da177e4	48	mask = current->thread.i387.fxsave.mxcsr_mask;
3b095a04 CG	49	if (mask == 0)
	50	mask = 0x0000ffbf;
	51	}
1da177e4 LT	52	mxcsr_feature_mask &= mask;
	53	stts();
	54	}
	55
44210111 RM	56	#ifdef CONFIG_X86_64
	57	/*
	58	* Called at bootup to set up the initial FPU state that is later cloned
	59	* into all processes.
	60	*/
	61	void __cpuinit fpu_init(void)
	62	{
	63	unsigned long oldcr0 = read_cr0();
	64	extern void __bad_fxsave_alignment(void);
	65
	66	if (offsetof(struct task_struct, thread.i387.fxsave) & 15)
	67	__bad_fxsave_alignment();
f668964e	68
44210111 RM	69	set_in_cr4(X86_CR4_OSFXSR);
	70	set_in_cr4(X86_CR4_OSXMMEXCPT);
	71
f668964e	72	write_cr0(oldcr0 & ~(X86_CR0_TS\|X86_CR0_EM)); /* clear TS and EM */
44210111 RM	73
	74	mxcsr_feature_mask_init();
	75	/* clean state in init */
	76	current_thread_info()->status = 0;
	77	clear_used_math();
	78	}
	79	#endif /* CONFIG_X86_64 */
	80
1da177e4 LT	81	/*
	82	* The _current_ task is using the FPU for the first time
	83	* so initialize it and set the mxcsr to its default
	84	* value at reset if we support XMM instructions and then
	85	* remeber the current task has used the FPU.
	86	*/
	87	void init_fpu(struct task_struct *tsk)
	88	{
44210111 RM	89	if (tsk_used_math(tsk)) {
	90	if (tsk == current)
	91	unlazy_fpu(tsk);
	92	return;
	93	}
	94
1da177e4	95	if (cpu_has_fxsr) {
3b095a04 CG	96	memset(&tsk->thread.i387.fxsave, 0,
3b095a04 CG	97	sizeof(struct i387_fxsave_struct));
1da177e4 LT	98	tsk->thread.i387.fxsave.cwd = 0x37f;
1da177e4 LT	99	if (cpu_has_xmm)
44210111	100	tsk->thread.i387.fxsave.mxcsr = MXCSR_DEFAULT;
1da177e4	101	} else {
3b095a04 CG	102	memset(&tsk->thread.i387.fsave, 0,
3b095a04 CG	103	sizeof(struct i387_fsave_struct));
1da177e4 LT	104	tsk->thread.i387.fsave.cwd = 0xffff037fu;
	105	tsk->thread.i387.fsave.swd = 0xffff0000u;
	106	tsk->thread.i387.fsave.twd = 0xffffffffu;
	107	tsk->thread.i387.fsave.fos = 0xffff0000u;
	108	}
44210111 RM	109	/*
	110	* Only the device not available exception or ptrace can call init_fpu.
	111	*/
1da177e4 LT	112	set_stopped_child_used_math(tsk);
	113	}
	114
44210111 RM	115	int fpregs_active(struct task_struct target, const struct user_regset regset)
	116	{
	117	return tsk_used_math(target) ? regset->n : 0;
	118	}
1da177e4	119
44210111	120	int xfpregs_active(struct task_struct target, const struct user_regset regset)
1da177e4	121	{
44210111 RM	122	return (cpu_has_fxsr && tsk_used_math(target)) ? regset->n : 0;
44210111 RM	123	}
1da177e4	124
44210111 RM	125	int xfpregs_get(struct task_struct target, const struct user_regset regset,
	126	unsigned int pos, unsigned int count,
	127	void kbuf, void __user ubuf)
	128	{
	129	if (!cpu_has_fxsr)
	130	return -ENODEV;
	131
18a86221	132	init_fpu(target);
44210111 RM	133
	134	return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
	135	&target->thread.i387.fxsave, 0, -1);
1da177e4	136	}
44210111 RM	137
	138	int xfpregs_set(struct task_struct target, const struct user_regset regset,
	139	unsigned int pos, unsigned int count,
	140	const void kbuf, const void __user ubuf)
	141	{
	142	int ret;
	143
	144	if (!cpu_has_fxsr)
	145	return -ENODEV;
	146
18a86221	147	init_fpu(target);
44210111 RM	148	set_stopped_child_used_math(target);
	149
	150	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
	151	&target->thread.i387.fxsave, 0, -1);
	152
	153	/*
	154	* mxcsr reserved bits must be masked to zero for security reasons.
	155	*/
	156	target->thread.i387.fxsave.mxcsr &= mxcsr_feature_mask;
	157
	158	return ret;
	159	}
	160
	161	#if defined CONFIG_X86_32 \|\| defined CONFIG_IA32_EMULATION
1da177e4	162
1da177e4 LT	163	/*
	164	* FPU tag word conversions.
	165	*/
	166
3b095a04	167	static inline unsigned short twd_i387_to_fxsr(unsigned short twd)
1da177e4 LT	168	{
1da177e4 LT	169	unsigned int tmp; /* to avoid 16 bit prefixes in the code */
3b095a04	170
1da177e4	171	/* Transform each pair of bits into 01 (valid) or 00 (empty) */
3b095a04	172	tmp = ~twd;
44210111	173	tmp = (tmp \| (tmp>>1)) & 0x5555; /* 0V0V0V0V0V0V0V0V */
3b095a04 CG	174	/* and move the valid bits to the lower byte. */
	175	tmp = (tmp \| (tmp >> 1)) & 0x3333; /* 00VV00VV00VV00VV */
	176	tmp = (tmp \| (tmp >> 2)) & 0x0f0f; /* 0000VVVV0000VVVV */
	177	tmp = (tmp \| (tmp >> 4)) & 0x00ff; /* 00000000VVVVVVVV */
f668964e	178
3b095a04	179	return tmp;
1da177e4 LT	180	}
1da177e4 LT	181
1da177e4	182	#define FPREG_ADDR(f, n) ((void )&(f)->st_space + (n) 16);
44210111 RM	183	#define FP_EXP_TAG_VALID 0
	184	#define FP_EXP_TAG_ZERO 1
	185	#define FP_EXP_TAG_SPECIAL 2
	186	#define FP_EXP_TAG_EMPTY 3
	187
	188	static inline u32 twd_fxsr_to_i387(struct i387_fxsave_struct *fxsave)
	189	{
	190	struct _fpxreg *st;
	191	u32 tos = (fxsave->swd >> 11) & 7;
	192	u32 twd = (unsigned long) fxsave->twd;
	193	u32 tag;
	194	u32 ret = 0xffff0000u;
	195	int i;
1da177e4	196
44210111	197	for (i = 0; i < 8; i++, twd >>= 1) {
3b095a04 CG	198	if (twd & 0x1) {
3b095a04 CG	199	st = FPREG_ADDR(fxsave, (i - tos) & 7);
1da177e4	200
3b095a04	201	switch (st->exponent & 0x7fff) {
1da177e4	202	case 0x7fff:
44210111	203	tag = FP_EXP_TAG_SPECIAL;
1da177e4 LT	204	break;
1da177e4 LT	205	case 0x0000:
3b095a04 CG	206	if (!st->significand[0] &&
	207	!st->significand[1] &&
	208	!st->significand[2] &&
44210111 RM	209	!st->significand[3])
	210	tag = FP_EXP_TAG_ZERO;
	211	else
	212	tag = FP_EXP_TAG_SPECIAL;
1da177e4 LT	213	break;
1da177e4 LT	214	default:
44210111 RM	215	if (st->significand[3] & 0x8000)
	216	tag = FP_EXP_TAG_VALID;
	217	else
	218	tag = FP_EXP_TAG_SPECIAL;
1da177e4 LT	219	break;
	220	}
	221	} else {
44210111	222	tag = FP_EXP_TAG_EMPTY;
1da177e4	223	}
44210111	224	ret \|= tag << (2 * i);
1da177e4 LT	225	}
	226	return ret;
	227	}
	228
	229	/*
44210111	230	* FXSR floating point environment conversions.
1da177e4 LT	231	*/
1da177e4 LT	232
f668964e IM	233	static void
f668964e IM	234	convert_from_fxsr(struct user_i387_ia32_struct env, struct task_struct tsk)
1da177e4	235	{
44210111 RM	236	struct i387_fxsave_struct *fxsave = &tsk->thread.i387.fxsave;
	237	struct _fpreg to = (struct _fpreg ) &env->st_space[0];
	238	struct _fpxreg from = (struct _fpxreg ) &fxsave->st_space[0];
	239	int i;
1da177e4	240
44210111 RM	241	env->cwd = fxsave->cwd \| 0xffff0000u;
	242	env->swd = fxsave->swd \| 0xffff0000u;
	243	env->twd = twd_fxsr_to_i387(fxsave);
	244
	245	#ifdef CONFIG_X86_64
	246	env->fip = fxsave->rip;
	247	env->foo = fxsave->rdp;
	248	if (tsk == current) {
	249	/*
	250	* should be actually ds/cs at fpu exception time, but
	251	* that information is not available in 64bit mode.
	252	*/
f668964e IM	253	asm("mov %%ds, %[fos]" : [fos] "=r" (env->fos));
f668964e IM	254	asm("mov %%cs, %[fcs]" : [fcs] "=r" (env->fcs));
1da177e4	255	} else {
44210111	256	struct pt_regs *regs = task_pt_regs(tsk);
f668964e	257
44210111 RM	258	env->fos = 0xffff0000 \| tsk->thread.ds;
44210111 RM	259	env->fcs = regs->cs;
1da177e4	260	}
44210111 RM	261	#else
44210111 RM	262	env->fip = fxsave->fip;
609b5297	263	env->fcs = (u16) fxsave->fcs \| ((u32) fxsave->fop << 16);
44210111 RM	264	env->foo = fxsave->foo;
	265	env->fos = fxsave->fos;
	266	#endif
1da177e4	267
44210111 RM	268	for (i = 0; i < 8; ++i)
44210111 RM	269	memcpy(&to[i], &from[i], sizeof(to[0]));
1da177e4 LT	270	}
1da177e4 LT	271
44210111 RM	272	static void convert_to_fxsr(struct task_struct *tsk,
44210111 RM	273	const struct user_i387_ia32_struct *env)
1da177e4	274
1da177e4	275	{
44210111 RM	276	struct i387_fxsave_struct *fxsave = &tsk->thread.i387.fxsave;
	277	struct _fpreg from = (struct _fpreg ) &env->st_space[0];
	278	struct _fpxreg to = (struct _fpxreg ) &fxsave->st_space[0];
	279	int i;
1da177e4	280
44210111 RM	281	fxsave->cwd = env->cwd;
	282	fxsave->swd = env->swd;
	283	fxsave->twd = twd_i387_to_fxsr(env->twd);
	284	fxsave->fop = (u16) ((u32) env->fcs >> 16);
	285	#ifdef CONFIG_X86_64
	286	fxsave->rip = env->fip;
	287	fxsave->rdp = env->foo;
	288	/* cs and ds ignored */
	289	#else
	290	fxsave->fip = env->fip;
	291	fxsave->fcs = (env->fcs & 0xffff);
	292	fxsave->foo = env->foo;
	293	fxsave->fos = env->fos;
	294	#endif
1da177e4	295
44210111 RM	296	for (i = 0; i < 8; ++i)
44210111 RM	297	memcpy(&to[i], &from[i], sizeof(from[0]));
1da177e4 LT	298	}
1da177e4 LT	299
44210111 RM	300	int fpregs_get(struct task_struct target, const struct user_regset regset,
	301	unsigned int pos, unsigned int count,
	302	void kbuf, void __user ubuf)
1da177e4	303	{
44210111	304	struct user_i387_ia32_struct env;
1da177e4	305
44210111 RM	306	if (!HAVE_HWFP)
44210111 RM	307	return fpregs_soft_get(target, regset, pos, count, kbuf, ubuf);
1da177e4	308
18a86221	309	init_fpu(target);
1da177e4	310
f668964e	311	if (!cpu_has_fxsr) {
44210111 RM	312	return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
44210111 RM	313	&target->thread.i387.fsave, 0, -1);
f668964e	314	}
1da177e4	315
44210111 RM	316	if (kbuf && pos == 0 && count == sizeof(env)) {
	317	convert_from_fxsr(kbuf, target);
	318	return 0;
1da177e4	319	}
44210111 RM	320
44210111 RM	321	convert_from_fxsr(&env, target);
f668964e	322
44210111	323	return user_regset_copyout(&pos, &count, &kbuf, &ubuf, &env, 0, -1);
1da177e4 LT	324	}
1da177e4 LT	325
44210111 RM	326	int fpregs_set(struct task_struct target, const struct user_regset regset,
	327	unsigned int pos, unsigned int count,
	328	const void kbuf, const void __user ubuf)
1da177e4	329	{
44210111 RM	330	struct user_i387_ia32_struct env;
44210111 RM	331	int ret;
1da177e4	332
44210111 RM	333	if (!HAVE_HWFP)
44210111 RM	334	return fpregs_soft_set(target, regset, pos, count, kbuf, ubuf);
1da177e4	335
18a86221	336	init_fpu(target);
44210111 RM	337	set_stopped_child_used_math(target);
44210111 RM	338
f668964e	339	if (!cpu_has_fxsr) {
44210111 RM	340	return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
44210111 RM	341	&target->thread.i387.fsave, 0, -1);
f668964e	342	}
44210111 RM	343
	344	if (pos > 0 \|\| count < sizeof(env))
	345	convert_from_fxsr(&env, target);
	346
	347	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &env, 0, -1);
	348	if (!ret)
	349	convert_to_fxsr(target, &env);
	350
	351	return ret;
1da177e4 LT	352	}
	353
	354	/*
	355	* Signal frame handlers.
	356	*/
	357
44210111	358	static inline int save_i387_fsave(struct _fpstate_ia32 __user *buf)
1da177e4 LT	359	{
	360	struct task_struct *tsk = current;
	361
3b095a04	362	unlazy_fpu(tsk);
1da177e4	363	tsk->thread.i387.fsave.status = tsk->thread.i387.fsave.swd;
3b095a04 CG	364	if (__copy_to_user(buf, &tsk->thread.i387.fsave,
3b095a04 CG	365	sizeof(struct i387_fsave_struct)))
1da177e4 LT	366	return -1;
	367	return 1;
	368	}
	369
44210111	370	static int save_i387_fxsave(struct _fpstate_ia32 __user *buf)
1da177e4 LT	371	{
1da177e4 LT	372	struct task_struct *tsk = current;
44210111	373	struct user_i387_ia32_struct env;
1da177e4 LT	374	int err = 0;
1da177e4 LT	375
3b095a04	376	unlazy_fpu(tsk);
1da177e4	377
44210111 RM	378	convert_from_fxsr(&env, tsk);
44210111 RM	379	if (__copy_to_user(buf, &env, sizeof(env)))
1da177e4 LT	380	return -1;
1da177e4 LT	381
3b095a04 CG	382	err \|= __put_user(tsk->thread.i387.fxsave.swd, &buf->status);
	383	err \|= __put_user(X86_FXSR_MAGIC, &buf->magic);
	384	if (err)
1da177e4 LT	385	return -1;
1da177e4 LT	386
3b095a04 CG	387	if (__copy_to_user(&buf->_fxsr_env[0], &tsk->thread.i387.fxsave,
3b095a04 CG	388	sizeof(struct i387_fxsave_struct)))
1da177e4 LT	389	return -1;
	390	return 1;
	391	}
	392
44210111	393	int save_i387_ia32(struct _fpstate_ia32 __user *buf)
1da177e4	394	{
3b095a04	395	if (!used_math())
1da177e4	396	return 0;
f668964e IM	397	/*
f668964e IM	398	* This will cause a "finit" to be triggered by the next
1da177e4 LT	399	* attempted FPU operation by the 'current' process.
	400	*/
	401	clear_used_math();
	402
f668964e	403	if (!HAVE_HWFP) {
44210111 RM	404	return fpregs_soft_get(current, NULL,
	405	0, sizeof(struct user_i387_ia32_struct),
	406	NULL, buf) ? -1 : 1;
1da177e4	407	}
f668964e IM	408
	409	if (cpu_has_fxsr)
	410	return save_i387_fxsave(buf);
	411	else
	412	return save_i387_fsave(buf);
1da177e4 LT	413	}
1da177e4 LT	414
44210111	415	static inline int restore_i387_fsave(struct _fpstate_ia32 __user *buf)
1da177e4 LT	416	{
1da177e4 LT	417	struct task_struct *tsk = current;
f668964e	418
3b095a04 CG	419	clear_fpu(tsk);
	420	return __copy_from_user(&tsk->thread.i387.fsave, buf,
	421	sizeof(struct i387_fsave_struct));
1da177e4 LT	422	}
1da177e4 LT	423
44210111	424	static int restore_i387_fxsave(struct _fpstate_ia32 __user *buf)
1da177e4	425	{
1da177e4	426	struct task_struct *tsk = current;
44210111	427	struct user_i387_ia32_struct env;
f668964e IM	428	int err;
f668964e IM	429
3b095a04 CG	430	clear_fpu(tsk);
	431	err = __copy_from_user(&tsk->thread.i387.fxsave, &buf->_fxsr_env[0],
	432	sizeof(struct i387_fxsave_struct));
1da177e4 LT	433	/* mxcsr reserved bits must be masked to zero for security reasons */
1da177e4 LT	434	tsk->thread.i387.fxsave.mxcsr &= mxcsr_feature_mask;
44210111 RM	435	if (err \|\| __copy_from_user(&env, buf, sizeof(env)))
	436	return 1;
	437	convert_to_fxsr(tsk, &env);
f668964e	438
44210111	439	return 0;
1da177e4 LT	440	}
1da177e4 LT	441
44210111	442	int restore_i387_ia32(struct _fpstate_ia32 __user *buf)
1da177e4 LT	443	{
	444	int err;
	445
3b095a04	446	if (HAVE_HWFP) {
f668964e	447	if (cpu_has_fxsr)
3b095a04	448	err = restore_i387_fxsave(buf);
f668964e	449	else
3b095a04	450	err = restore_i387_fsave(buf);
1da177e4	451	} else {
44210111 RM	452	err = fpregs_soft_set(current, NULL,
	453	0, sizeof(struct user_i387_ia32_struct),
	454	NULL, buf) != 0;
1da177e4 LT	455	}
1da177e4 LT	456	set_used_math();
f668964e	457
1da177e4 LT	458	return err;
	459	}
	460
1da177e4 LT	461	/*
1da177e4 LT	462	* FPU state for core dumps.
60b3b9af RM	463	* This is only used for a.out dumps now.
	464	* It is declared generically using elf_fpregset_t (which is
	465	* struct user_i387_struct) but is in fact only used for 32-bit
	466	* dumps, so on 64-bit it is really struct user_i387_ia32_struct.
1da177e4	467	*/
3b095a04	468	int dump_fpu(struct pt_regs regs, struct user_i387_struct fpu)
1da177e4	469	{
1da177e4	470	struct task_struct *tsk = current;
f668964e	471	int fpvalid;
1da177e4 LT	472
1da177e4 LT	473	fpvalid = !!used_math();
60b3b9af RM	474	if (fpvalid)
	475	fpvalid = !fpregs_get(tsk, NULL,
	476	0, sizeof(struct user_i387_ia32_struct),
	477	fpu, NULL);
1da177e4 LT	478
	479	return fpvalid;
	480	}
129f6946	481	EXPORT_SYMBOL(dump_fpu);
1da177e4	482
60b3b9af	483	#endif /* CONFIG_X86_32 \|\| CONFIG_IA32_EMULATION */