Commit | Line | Data |
---|---|---|
8d016ef1 | 1 | /* |
835c34a1 | 2 | * 8253/PIT functions |
8d016ef1 | 3 | * |
4 | */ | |
e9e2cdb4 | 5 | #include <linux/clockchips.h> |
18de5bc4 TG |
6 | #include <linux/init.h> |
7 | #include <linux/interrupt.h> | |
8d016ef1 | 8 | #include <linux/jiffies.h> |
8d016ef1 | 9 | #include <linux/module.h> |
18de5bc4 | 10 | #include <linux/spinlock.h> |
8d016ef1 | 11 | |
12 | #include <asm/smp.h> | |
13 | #include <asm/delay.h> | |
14 | #include <asm/i8253.h> | |
15 | #include <asm/io.h> | |
4713e22c | 16 | #include <asm/hpet.h> |
8d016ef1 | 17 | |
8d016ef1 | 18 | DEFINE_SPINLOCK(i8253_lock); |
19 | EXPORT_SYMBOL(i8253_lock); | |
20 | ||
1a0c009a TG |
21 | #ifdef CONFIG_X86_32 |
22 | static void pit_disable_clocksource(void); | |
23 | #else | |
24 | static inline void pit_disable_clocksource(void) { } | |
25 | #endif | |
26 | ||
e9e2cdb4 TG |
27 | /* |
28 | * HPET replaces the PIT, when enabled. So we need to know, which of | |
29 | * the two timers is used | |
30 | */ | |
31 | struct clock_event_device *global_clock_event; | |
32 | ||
33 | /* | |
34 | * Initialize the PIT timer. | |
35 | * | |
36 | * This is also called after resume to bring the PIT into operation again. | |
37 | */ | |
38 | static void init_pit_timer(enum clock_event_mode mode, | |
39 | struct clock_event_device *evt) | |
40 | { | |
5f627f8e | 41 | spin_lock(&i8253_lock); |
e9e2cdb4 TG |
42 | |
43 | switch(mode) { | |
44 | case CLOCK_EVT_MODE_PERIODIC: | |
45 | /* binary, mode 2, LSB/MSB, ch 0 */ | |
466eed22 AC |
46 | outb_pit(0x34, PIT_MODE); |
47 | outb_pit(LATCH & 0xff , PIT_CH0); /* LSB */ | |
48 | outb_pit(LATCH >> 8 , PIT_CH0); /* MSB */ | |
e9e2cdb4 TG |
49 | break; |
50 | ||
e9e2cdb4 TG |
51 | case CLOCK_EVT_MODE_SHUTDOWN: |
52 | case CLOCK_EVT_MODE_UNUSED: | |
7671988b TG |
53 | if (evt->mode == CLOCK_EVT_MODE_PERIODIC || |
54 | evt->mode == CLOCK_EVT_MODE_ONESHOT) { | |
466eed22 AC |
55 | outb_pit(0x30, PIT_MODE); |
56 | outb_pit(0, PIT_CH0); | |
57 | outb_pit(0, PIT_CH0); | |
7671988b | 58 | } |
1a0c009a | 59 | pit_disable_clocksource(); |
18de5bc4 TG |
60 | break; |
61 | ||
6b3964cd | 62 | case CLOCK_EVT_MODE_ONESHOT: |
e9e2cdb4 | 63 | /* One shot setup */ |
1a0c009a | 64 | pit_disable_clocksource(); |
466eed22 | 65 | outb_pit(0x38, PIT_MODE); |
18de5bc4 TG |
66 | break; |
67 | ||
68 | case CLOCK_EVT_MODE_RESUME: | |
69 | /* Nothing to do here */ | |
e9e2cdb4 TG |
70 | break; |
71 | } | |
5f627f8e | 72 | spin_unlock(&i8253_lock); |
e9e2cdb4 TG |
73 | } |
74 | ||
75 | /* | |
76 | * Program the next event in oneshot mode | |
77 | * | |
78 | * Delta is given in PIT ticks | |
79 | */ | |
80 | static int pit_next_event(unsigned long delta, struct clock_event_device *evt) | |
8d016ef1 | 81 | { |
5f627f8e | 82 | spin_lock(&i8253_lock); |
466eed22 AC |
83 | outb_pit(delta & 0xff , PIT_CH0); /* LSB */ |
84 | outb_pit(delta >> 8 , PIT_CH0); /* MSB */ | |
5f627f8e | 85 | spin_unlock(&i8253_lock); |
e9e2cdb4 TG |
86 | |
87 | return 0; | |
88 | } | |
89 | ||
90 | /* | |
91 | * On UP the PIT can serve all of the possible timer functions. On SMP systems | |
92 | * it can be solely used for the global tick. | |
93 | * | |
27b46d76 | 94 | * The profiling and update capabilities are switched off once the local apic is |
e9e2cdb4 TG |
95 | * registered. This mechanism replaces the previous #ifdef LOCAL_APIC - |
96 | * !using_apic_timer decisions in do_timer_interrupt_hook() | |
97 | */ | |
98 | struct clock_event_device pit_clockevent = { | |
99 | .name = "pit", | |
100 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | |
101 | .set_mode = init_pit_timer, | |
102 | .set_next_event = pit_next_event, | |
103 | .shift = 32, | |
104 | .irq = 0, | |
105 | }; | |
106 | ||
107 | /* | |
108 | * Initialize the conversion factor and the min/max deltas of the clock event | |
109 | * structure and register the clock event source with the framework. | |
110 | */ | |
111 | void __init setup_pit_timer(void) | |
112 | { | |
113 | /* | |
114 | * Start pit with the boot cpu mask and make it global after the | |
115 | * IO_APIC has been initialized. | |
116 | */ | |
2feae215 | 117 | pit_clockevent.cpumask = cpumask_of_cpu(smp_processor_id()); |
e9e2cdb4 TG |
118 | pit_clockevent.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, 32); |
119 | pit_clockevent.max_delta_ns = | |
120 | clockevent_delta2ns(0x7FFF, &pit_clockevent); | |
121 | pit_clockevent.min_delta_ns = | |
122 | clockevent_delta2ns(0xF, &pit_clockevent); | |
123 | clockevents_register_device(&pit_clockevent); | |
124 | global_clock_event = &pit_clockevent; | |
8d016ef1 | 125 | } |
5d0cf410 | 126 | |
f5e0e93f | 127 | #ifndef CONFIG_X86_64 |
5d0cf410 | 128 | /* |
129 | * Since the PIT overflows every tick, its not very useful | |
130 | * to just read by itself. So use jiffies to emulate a free | |
131 | * running counter: | |
132 | */ | |
133 | static cycle_t pit_read(void) | |
134 | { | |
135 | unsigned long flags; | |
136 | int count; | |
6415ce9a | 137 | u32 jifs; |
138 | static int old_count; | |
139 | static u32 old_jifs; | |
5d0cf410 | 140 | |
141 | spin_lock_irqsave(&i8253_lock, flags); | |
e9e2cdb4 | 142 | /* |
6415ce9a | 143 | * Although our caller may have the read side of xtime_lock, |
144 | * this is now a seqlock, and we are cheating in this routine | |
145 | * by having side effects on state that we cannot undo if | |
146 | * there is a collision on the seqlock and our caller has to | |
147 | * retry. (Namely, old_jifs and old_count.) So we must treat | |
148 | * jiffies as volatile despite the lock. We read jiffies | |
149 | * before latching the timer count to guarantee that although | |
150 | * the jiffies value might be older than the count (that is, | |
151 | * the counter may underflow between the last point where | |
152 | * jiffies was incremented and the point where we latch the | |
153 | * count), it cannot be newer. | |
154 | */ | |
155 | jifs = jiffies; | |
466eed22 AC |
156 | outb_pit(0x00, PIT_MODE); /* latch the count ASAP */ |
157 | count = inb_pit(PIT_CH0); /* read the latched count */ | |
158 | count |= inb_pit(PIT_CH0) << 8; | |
5d0cf410 | 159 | |
160 | /* VIA686a test code... reset the latch if count > max + 1 */ | |
161 | if (count > LATCH) { | |
466eed22 AC |
162 | outb_pit(0x34, PIT_MODE); |
163 | outb_pit(LATCH & 0xff, PIT_CH0); | |
164 | outb_pit(LATCH >> 8, PIT_CH0); | |
5d0cf410 | 165 | count = LATCH - 1; |
166 | } | |
5d0cf410 | 167 | |
6415ce9a | 168 | /* |
169 | * It's possible for count to appear to go the wrong way for a | |
170 | * couple of reasons: | |
171 | * | |
172 | * 1. The timer counter underflows, but we haven't handled the | |
173 | * resulting interrupt and incremented jiffies yet. | |
174 | * 2. Hardware problem with the timer, not giving us continuous time, | |
175 | * the counter does small "jumps" upwards on some Pentium systems, | |
176 | * (see c't 95/10 page 335 for Neptun bug.) | |
177 | * | |
178 | * Previous attempts to handle these cases intelligently were | |
179 | * buggy, so we just do the simple thing now. | |
180 | */ | |
181 | if (count > old_count && jifs == old_jifs) { | |
182 | count = old_count; | |
183 | } | |
184 | old_count = count; | |
185 | old_jifs = jifs; | |
186 | ||
187 | spin_unlock_irqrestore(&i8253_lock, flags); | |
5d0cf410 | 188 | |
6415ce9a | 189 | count = (LATCH - 1) - count; |
5d0cf410 | 190 | |
191 | return (cycle_t)(jifs * LATCH) + count; | |
192 | } | |
193 | ||
194 | static struct clocksource clocksource_pit = { | |
195 | .name = "pit", | |
196 | .rating = 110, | |
197 | .read = pit_read, | |
6415ce9a | 198 | .mask = CLOCKSOURCE_MASK(32), |
5d0cf410 | 199 | .mult = 0, |
200 | .shift = 20, | |
201 | }; | |
202 | ||
1a0c009a TG |
203 | static void pit_disable_clocksource(void) |
204 | { | |
205 | /* | |
206 | * Use mult to check whether it is registered or not | |
207 | */ | |
208 | if (clocksource_pit.mult) { | |
209 | clocksource_unregister(&clocksource_pit); | |
210 | clocksource_pit.mult = 0; | |
211 | } | |
212 | } | |
213 | ||
5d0cf410 | 214 | static int __init init_pit_clocksource(void) |
215 | { | |
316da3b3 TG |
216 | /* |
217 | * Several reasons not to register PIT as a clocksource: | |
218 | * | |
219 | * - On SMP PIT does not scale due to i8253_lock | |
220 | * - when HPET is enabled | |
221 | * - when local APIC timer is active (PIT is switched off) | |
222 | */ | |
223 | if (num_possible_cpus() > 1 || is_hpet_enabled() || | |
224 | pit_clockevent.mode != CLOCK_EVT_MODE_PERIODIC) | |
5d0cf410 | 225 | return 0; |
226 | ||
227 | clocksource_pit.mult = clocksource_hz2mult(CLOCK_TICK_RATE, 20); | |
a2752549 | 228 | return clocksource_register(&clocksource_pit); |
5d0cf410 | 229 | } |
6bb74df4 | 230 | arch_initcall(init_pit_clocksource); |
f5e0e93f TG |
231 | |
232 | #endif |