[deliverable/linux.git] / arch / x86 / kernel / i8259.c

#include <linux/linkage.h>
#include <linux/errno.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/timex.h>
#include <linux/random.h>
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/sysdev.h>
#include <linux/bitops.h>
#include <linux/acpi.h>
#include <linux/io.h>
#include <linux/delay.h>

#include <asm/atomic.h>
#include <asm/system.h>
#include <asm/timer.h>
#include <asm/hw_irq.h>
#include <asm/pgtable.h>
#include <asm/desc.h>
#include <asm/apic.h>
#include <asm/i8259.h>

/*
 * This is the 'legacy' 8259A Programmable Interrupt Controller,
 * present in the majority of PC/AT boxes.
 * plus some generic x86 specific things if generic specifics makes
 * any sense at all.
 */

static int i8259A_auto_eoi;
DEFINE_RAW_SPINLOCK(i8259A_lock);
static void mask_and_ack_8259A(unsigned int);
static void mask_8259A(void);
static void unmask_8259A(void);
static void disable_8259A_irq(unsigned int irq);
static void enable_8259A_irq(unsigned int irq);
static void init_8259A(int auto_eoi);
static int i8259A_irq_pending(unsigned int irq);

struct irq_chip i8259A_chip = {
	.name		= "XT-PIC",
	.mask		= disable_8259A_irq,
	.disable	= disable_8259A_irq,
	.unmask		= enable_8259A_irq,
	.mask_ack	= mask_and_ack_8259A,
};

/*
 * 8259A PIC functions to handle ISA devices:
 */

/*
 * This contains the irq mask for both 8259A irq controllers,
 */
unsigned int cached_irq_mask = 0xffff;

/*
 * Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
 * boards the timer interrupt is not really connected to any IO-APIC pin,
 * it's fed to the master 8259A's IR0 line only.
 *
 * Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
 * this 'mixed mode' IRQ handling costs nothing because it's only used
 * at IRQ setup time.
 */
unsigned long io_apic_irqs;

static void disable_8259A_irq(unsigned int irq)
{
	unsigned int mask = 1 << irq;
	unsigned long flags;

	raw_spin_lock_irqsave(&i8259A_lock, flags);
	cached_irq_mask |= mask;
	if (irq & 8)
		outb(cached_slave_mask, PIC_SLAVE_IMR);
	else
		outb(cached_master_mask, PIC_MASTER_IMR);
	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
}

static void enable_8259A_irq(unsigned int irq)
{
	unsigned int mask = ~(1 << irq);
	unsigned long flags;

	raw_spin_lock_irqsave(&i8259A_lock, flags);
	cached_irq_mask &= mask;
	if (irq & 8)
		outb(cached_slave_mask, PIC_SLAVE_IMR);
	else
		outb(cached_master_mask, PIC_MASTER_IMR);
	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
}

static int i8259A_irq_pending(unsigned int irq)
{
	unsigned int mask = 1<<irq;
	unsigned long flags;
	int ret;

	raw_spin_lock_irqsave(&i8259A_lock, flags);
	if (irq < 8)
		ret = inb(PIC_MASTER_CMD) & mask;
	else
		ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
	raw_spin_unlock_irqrestore(&i8259A_lock, flags);

	return ret;
}

static void make_8259A_irq(unsigned int irq)
{
	disable_irq_nosync(irq);
	io_apic_irqs &= ~(1<<irq);
	set_irq_chip_and_handler_name(irq, &i8259A_chip, handle_level_irq,
				      "XT");
	enable_irq(irq);
}

/*
 * This function assumes to be called rarely. Switching between
 * 8259A registers is slow.
 * This has to be protected by the irq controller spinlock
 * before being called.
 */
static inline int i8259A_irq_real(unsigned int irq)
{
	int value;
	int irqmask = 1<<irq;

	if (irq < 8) {
		outb(0x0B, PIC_MASTER_CMD);	/* ISR register */
		value = inb(PIC_MASTER_CMD) & irqmask;
		outb(0x0A, PIC_MASTER_CMD);	/* back to the IRR register */
		return value;
	}
	outb(0x0B, PIC_SLAVE_CMD);	/* ISR register */
	value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
	outb(0x0A, PIC_SLAVE_CMD);	/* back to the IRR register */
	return value;
}

/*
 * Careful! The 8259A is a fragile beast, it pretty
 * much _has_ to be done exactly like this (mask it
 * first, _then_ send the EOI, and the order of EOI
 * to the two 8259s is important!
 */
static void mask_and_ack_8259A(unsigned int irq)
{
	unsigned int irqmask = 1 << irq;
	unsigned long flags;

	raw_spin_lock_irqsave(&i8259A_lock, flags);
	/*
	 * Lightweight spurious IRQ detection. We do not want
	 * to overdo spurious IRQ handling - it's usually a sign
	 * of hardware problems, so we only do the checks we can
	 * do without slowing down good hardware unnecessarily.
	 *
	 * Note that IRQ7 and IRQ15 (the two spurious IRQs
	 * usually resulting from the 8259A-1|2 PICs) occur
	 * even if the IRQ is masked in the 8259A. Thus we
	 * can check spurious 8259A IRQs without doing the
	 * quite slow i8259A_irq_real() call for every IRQ.
	 * This does not cover 100% of spurious interrupts,
	 * but should be enough to warn the user that there
	 * is something bad going on ...
	 */
	if (cached_irq_mask & irqmask)
		goto spurious_8259A_irq;
	cached_irq_mask |= irqmask;

handle_real_irq:
	if (irq & 8) {
		inb(PIC_SLAVE_IMR);	/* DUMMY - (do we need this?) */
		outb(cached_slave_mask, PIC_SLAVE_IMR);
		/* 'Specific EOI' to slave */
		outb(0x60+(irq&7), PIC_SLAVE_CMD);
		 /* 'Specific EOI' to master-IRQ2 */
		outb(0x60+PIC_CASCADE_IR, PIC_MASTER_CMD);
	} else {
		inb(PIC_MASTER_IMR);	/* DUMMY - (do we need this?) */
		outb(cached_master_mask, PIC_MASTER_IMR);
		outb(0x60+irq, PIC_MASTER_CMD);	/* 'Specific EOI to master */
	}
	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
	return;

spurious_8259A_irq:
	/*
	 * this is the slow path - should happen rarely.
	 */
	if (i8259A_irq_real(irq))
		/*
		 * oops, the IRQ _is_ in service according to the
		 * 8259A - not spurious, go handle it.
		 */
		goto handle_real_irq;

	{
		static int spurious_irq_mask;
		/*
		 * At this point we can be sure the IRQ is spurious,
		 * lets ACK and report it. [once per IRQ]
		 */
		if (!(spurious_irq_mask & irqmask)) {
			printk(KERN_DEBUG
			       "spurious 8259A interrupt: IRQ%d.\n", irq);
			spurious_irq_mask |= irqmask;
		}
		atomic_inc(&irq_err_count);
		/*
		 * Theoretically we do not have to handle this IRQ,
		 * but in Linux this does not cause problems and is
		 * simpler for us.
		 */
		goto handle_real_irq;
	}
}

static char irq_trigger[2];
/**
 * ELCR registers (0x4d0, 0x4d1) control edge/level of IRQ
 */
static void restore_ELCR(char *trigger)
{
	outb(trigger[0], 0x4d0);
	outb(trigger[1], 0x4d1);
}

static void save_ELCR(char *trigger)
{
	/* IRQ 0,1,2,8,13 are marked as reserved */
	trigger[0] = inb(0x4d0) & 0xF8;
	trigger[1] = inb(0x4d1) & 0xDE;
}

static int i8259A_resume(struct sys_device *dev)
{
	init_8259A(i8259A_auto_eoi);
	restore_ELCR(irq_trigger);
	return 0;
}

static int i8259A_suspend(struct sys_device *dev, pm_message_t state)
{
	save_ELCR(irq_trigger);
	return 0;
}

static int i8259A_shutdown(struct sys_device *dev)
{
	/* Put the i8259A into a quiescent state that
	 * the kernel initialization code can get it
	 * out of.
	 */
	outb(0xff, PIC_MASTER_IMR);	/* mask all of 8259A-1 */
	outb(0xff, PIC_SLAVE_IMR);	/* mask all of 8259A-1 */
	return 0;
}

static struct sysdev_class i8259_sysdev_class = {
	.name = "i8259",
	.suspend = i8259A_suspend,
	.resume = i8259A_resume,
	.shutdown = i8259A_shutdown,
};

static struct sys_device device_i8259A = {
	.id	= 0,
	.cls	= &i8259_sysdev_class,
};

static void mask_8259A(void)
{
	unsigned long flags;

	raw_spin_lock_irqsave(&i8259A_lock, flags);

	outb(0xff, PIC_MASTER_IMR);	/* mask all of 8259A-1 */
	outb(0xff, PIC_SLAVE_IMR);	/* mask all of 8259A-2 */

	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
}

static void unmask_8259A(void)
{
	unsigned long flags;

	raw_spin_lock_irqsave(&i8259A_lock, flags);

	outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
	outb(cached_slave_mask, PIC_SLAVE_IMR);	  /* restore slave IRQ mask */

	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
}

static void init_8259A(int auto_eoi)
{
	unsigned long flags;

	i8259A_auto_eoi = auto_eoi;

	raw_spin_lock_irqsave(&i8259A_lock, flags);

	outb(0xff, PIC_MASTER_IMR);	/* mask all of 8259A-1 */
	outb(0xff, PIC_SLAVE_IMR);	/* mask all of 8259A-2 */

	/*
	 * outb_pic - this has to work on a wide range of PC hardware.
	 */
	outb_pic(0x11, PIC_MASTER_CMD);	/* ICW1: select 8259A-1 init */

	/* ICW2: 8259A-1 IR0-7 mapped to 0x30-0x37 on x86-64,
	   to 0x20-0x27 on i386 */
	outb_pic(IRQ0_VECTOR, PIC_MASTER_IMR);

	/* 8259A-1 (the master) has a slave on IR2 */
	outb_pic(1U << PIC_CASCADE_IR, PIC_MASTER_IMR);

	if (auto_eoi)	/* master does Auto EOI */
		outb_pic(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);
	else		/* master expects normal EOI */
		outb_pic(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);

	outb_pic(0x11, PIC_SLAVE_CMD);	/* ICW1: select 8259A-2 init */

	/* ICW2: 8259A-2 IR0-7 mapped to IRQ8_VECTOR */
	outb_pic(IRQ8_VECTOR, PIC_SLAVE_IMR);
	/* 8259A-2 is a slave on master's IR2 */
	outb_pic(PIC_CASCADE_IR, PIC_SLAVE_IMR);
	/* (slave's support for AEOI in flat mode is to be investigated) */
	outb_pic(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR);

	if (auto_eoi)
		/*
		 * In AEOI mode we just have to mask the interrupt
		 * when acking.
		 */
		i8259A_chip.mask_ack = disable_8259A_irq;
	else
		i8259A_chip.mask_ack = mask_and_ack_8259A;

	udelay(100);		/* wait for 8259A to initialize */

	outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
	outb(cached_slave_mask, PIC_SLAVE_IMR);	  /* restore slave IRQ mask */

	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
}

/*
 * make i8259 a driver so that we can select pic functions at run time. the goal
 * is to make x86 binary compatible among pc compatible and non-pc compatible
 * platforms, such as x86 MID.
 */

static void legacy_pic_noop(void) { };
static void legacy_pic_uint_noop(unsigned int unused) { };
static void legacy_pic_int_noop(int unused) { };

static struct irq_chip dummy_pic_chip  = {
	.name = "dummy pic",
	.mask = legacy_pic_uint_noop,
	.unmask = legacy_pic_uint_noop,
	.disable = legacy_pic_uint_noop,
	.mask_ack = legacy_pic_uint_noop,
};
static int legacy_pic_irq_pending_noop(unsigned int irq)
{
	return 0;
}

struct legacy_pic null_legacy_pic = {
	.nr_legacy_irqs = 0,
	.chip = &dummy_pic_chip,
	.mask_all = legacy_pic_noop,
	.restore_mask = legacy_pic_noop,
	.init = legacy_pic_int_noop,
	.irq_pending = legacy_pic_irq_pending_noop,
	.make_irq = legacy_pic_uint_noop,
};

struct legacy_pic default_legacy_pic = {
	.nr_legacy_irqs = NR_IRQS_LEGACY,
	.chip  = &i8259A_chip,
	.mask_all  = mask_8259A,
	.restore_mask = unmask_8259A,
	.init = init_8259A,
	.irq_pending = i8259A_irq_pending,
	.make_irq = make_8259A_irq,
};

struct legacy_pic *legacy_pic = &default_legacy_pic;

static int __init i8259A_init_sysfs(void)
{
	int error;

	if (legacy_pic != &default_legacy_pic)
		return 0;

	error = sysdev_class_register(&i8259_sysdev_class);
	if (!error)
		error = sysdev_register(&device_i8259A);
	return error;
}

device_initcall(i8259A_init_sysfs);
Commit	Line	Data
21fd5132	1	#include <linux/linkage.h>
21fd5132 PM	2	#include <linux/errno.h>
	3	#include <linux/signal.h>
	4	#include <linux/sched.h>
	5	#include <linux/ioport.h>
	6	#include <linux/interrupt.h>
21fd5132	7	#include <linux/timex.h>
21fd5132 PM	8	#include <linux/random.h>
	9	#include <linux/init.h>
	10	#include <linux/kernel_stat.h>
	11	#include <linux/sysdev.h>
	12	#include <linux/bitops.h>
7bafaf30 JSR	13	#include <linux/acpi.h>
	14	#include <linux/io.h>
	15	#include <linux/delay.h>
21fd5132	16
21fd5132 PM	17	#include <asm/atomic.h>
21fd5132 PM	18	#include <asm/system.h>
21fd5132	19	#include <asm/timer.h>
21fd5132	20	#include <asm/hw_irq.h>
21fd5132	21	#include <asm/pgtable.h>
21fd5132 PM	22	#include <asm/desc.h>
21fd5132 PM	23	#include <asm/apic.h>
21fd5132 PM	24	#include <asm/i8259.h>
	25
	26	/*
	27	* This is the 'legacy' 8259A Programmable Interrupt Controller,
	28	* present in the majority of PC/AT boxes.
	29	* plus some generic x86 specific things if generic specifics makes
	30	* any sense at all.
	31	*/
	32
	33	static int i8259A_auto_eoi;
5619c280	34	DEFINE_RAW_SPINLOCK(i8259A_lock);
21fd5132	35	static void mask_and_ack_8259A(unsigned int);
b81bb373 JP	36	static void mask_8259A(void);
	37	static void unmask_8259A(void);
	38	static void disable_8259A_irq(unsigned int irq);
	39	static void enable_8259A_irq(unsigned int irq);
	40	static void init_8259A(int auto_eoi);
	41	static int i8259A_irq_pending(unsigned int irq);
21fd5132 PM	42
	43	struct irq_chip i8259A_chip = {
	44	.name = "XT-PIC",
	45	.mask = disable_8259A_irq,
	46	.disable = disable_8259A_irq,
	47	.unmask = enable_8259A_irq,
	48	.mask_ack = mask_and_ack_8259A,
	49	};
	50
	51	/*
	52	* 8259A PIC functions to handle ISA devices:
	53	*/
	54
	55	/*
	56	* This contains the irq mask for both 8259A irq controllers,
	57	*/
	58	unsigned int cached_irq_mask = 0xffff;
	59
	60	/*
	61	* Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
	62	* boards the timer interrupt is not really connected to any IO-APIC pin,
	63	* it's fed to the master 8259A's IR0 line only.
	64	*
	65	* Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
	66	* this 'mixed mode' IRQ handling costs nothing because it's only used
	67	* at IRQ setup time.
	68	*/
	69	unsigned long io_apic_irqs;
	70
b81bb373	71	static void disable_8259A_irq(unsigned int irq)
21fd5132 PM	72	{
	73	unsigned int mask = 1 << irq;
	74	unsigned long flags;
	75
5619c280	76	raw_spin_lock_irqsave(&i8259A_lock, flags);
21fd5132 PM	77	cached_irq_mask \|= mask;
	78	if (irq & 8)
	79	outb(cached_slave_mask, PIC_SLAVE_IMR);
	80	else
	81	outb(cached_master_mask, PIC_MASTER_IMR);
5619c280	82	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
21fd5132 PM	83	}
21fd5132 PM	84
b81bb373	85	static void enable_8259A_irq(unsigned int irq)
21fd5132 PM	86	{
	87	unsigned int mask = ~(1 << irq);
	88	unsigned long flags;
	89
5619c280	90	raw_spin_lock_irqsave(&i8259A_lock, flags);
21fd5132 PM	91	cached_irq_mask &= mask;
	92	if (irq & 8)
	93	outb(cached_slave_mask, PIC_SLAVE_IMR);
	94	else
	95	outb(cached_master_mask, PIC_MASTER_IMR);
5619c280	96	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
21fd5132 PM	97	}
21fd5132 PM	98
b81bb373	99	static int i8259A_irq_pending(unsigned int irq)
21fd5132 PM	100	{
	101	unsigned int mask = 1<<irq;
	102	unsigned long flags;
	103	int ret;
	104
5619c280	105	raw_spin_lock_irqsave(&i8259A_lock, flags);
21fd5132 PM	106	if (irq < 8)
	107	ret = inb(PIC_MASTER_CMD) & mask;
	108	else
	109	ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
5619c280	110	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
21fd5132 PM	111
	112	return ret;
	113	}
	114
b81bb373	115	static void make_8259A_irq(unsigned int irq)
21fd5132 PM	116	{
	117	disable_irq_nosync(irq);
	118	io_apic_irqs &= ~(1<<irq);
	119	set_irq_chip_and_handler_name(irq, &i8259A_chip, handle_level_irq,
	120	"XT");
	121	enable_irq(irq);
	122	}
	123
	124	/*
	125	* This function assumes to be called rarely. Switching between
	126	* 8259A registers is slow.
	127	* This has to be protected by the irq controller spinlock
	128	* before being called.
	129	*/
	130	static inline int i8259A_irq_real(unsigned int irq)
	131	{
	132	int value;
	133	int irqmask = 1<<irq;
	134
	135	if (irq < 8) {
680afbf9	136	outb(0x0B, PIC_MASTER_CMD); /* ISR register */
21fd5132	137	value = inb(PIC_MASTER_CMD) & irqmask;
680afbf9	138	outb(0x0A, PIC_MASTER_CMD); /* back to the IRR register */
21fd5132 PM	139	return value;
21fd5132 PM	140	}
680afbf9	141	outb(0x0B, PIC_SLAVE_CMD); /* ISR register */
21fd5132	142	value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
680afbf9	143	outb(0x0A, PIC_SLAVE_CMD); /* back to the IRR register */
21fd5132 PM	144	return value;
	145	}
	146
	147	/*
	148	* Careful! The 8259A is a fragile beast, it pretty
	149	* much _has_ to be done exactly like this (mask it
	150	* first, _then_ send the EOI, and the order of EOI
	151	* to the two 8259s is important!
	152	*/
	153	static void mask_and_ack_8259A(unsigned int irq)
	154	{
	155	unsigned int irqmask = 1 << irq;
	156	unsigned long flags;
	157
5619c280	158	raw_spin_lock_irqsave(&i8259A_lock, flags);
21fd5132 PM	159	/*
	160	* Lightweight spurious IRQ detection. We do not want
	161	* to overdo spurious IRQ handling - it's usually a sign
	162	* of hardware problems, so we only do the checks we can
	163	* do without slowing down good hardware unnecessarily.
	164	*
	165	* Note that IRQ7 and IRQ15 (the two spurious IRQs
	166	* usually resulting from the 8259A-1\|2 PICs) occur
	167	* even if the IRQ is masked in the 8259A. Thus we
	168	* can check spurious 8259A IRQs without doing the
	169	* quite slow i8259A_irq_real() call for every IRQ.
	170	* This does not cover 100% of spurious interrupts,
	171	* but should be enough to warn the user that there
	172	* is something bad going on ...
	173	*/
	174	if (cached_irq_mask & irqmask)
	175	goto spurious_8259A_irq;
	176	cached_irq_mask \|= irqmask;
	177
	178	handle_real_irq:
	179	if (irq & 8) {
	180	inb(PIC_SLAVE_IMR); /* DUMMY - (do we need this?) */
	181	outb(cached_slave_mask, PIC_SLAVE_IMR);
21fd5132	182	/* 'Specific EOI' to slave */
3e8631d2	183	outb(0x60+(irq&7), PIC_SLAVE_CMD);
21fd5132	184	/* 'Specific EOI' to master-IRQ2 */
3e8631d2	185	outb(0x60+PIC_CASCADE_IR, PIC_MASTER_CMD);
21fd5132 PM	186	} else {
	187	inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */
	188	outb(cached_master_mask, PIC_MASTER_IMR);
3e8631d2	189	outb(0x60+irq, PIC_MASTER_CMD); /* 'Specific EOI to master */
21fd5132	190	}
5619c280	191	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
21fd5132 PM	192	return;
	193
	194	spurious_8259A_irq:
	195	/*
	196	* this is the slow path - should happen rarely.
	197	*/
	198	if (i8259A_irq_real(irq))
	199	/*
	200	* oops, the IRQ _is_ in service according to the
	201	* 8259A - not spurious, go handle it.
	202	*/
	203	goto handle_real_irq;
	204
	205	{
	206	static int spurious_irq_mask;
	207	/*
	208	* At this point we can be sure the IRQ is spurious,
	209	* lets ACK and report it. [once per IRQ]
	210	*/
	211	if (!(spurious_irq_mask & irqmask)) {
21fd5132 PM	212	printk(KERN_DEBUG
21fd5132 PM	213	"spurious 8259A interrupt: IRQ%d.\n", irq);
21fd5132 PM	214	spurious_irq_mask \|= irqmask;
	215	}
	216	atomic_inc(&irq_err_count);
	217	/*
	218	* Theoretically we do not have to handle this IRQ,
	219	* but in Linux this does not cause problems and is
	220	* simpler for us.
	221	*/
	222	goto handle_real_irq;
	223	}
	224	}
	225
	226	static char irq_trigger[2];
	227	/**
	228	* ELCR registers (0x4d0, 0x4d1) control edge/level of IRQ
	229	*/
	230	static void restore_ELCR(char *trigger)
	231	{
	232	outb(trigger[0], 0x4d0);
	233	outb(trigger[1], 0x4d1);
	234	}
	235
	236	static void save_ELCR(char *trigger)
	237	{
	238	/* IRQ 0,1,2,8,13 are marked as reserved */
	239	trigger[0] = inb(0x4d0) & 0xF8;
	240	trigger[1] = inb(0x4d1) & 0xDE;
	241	}
	242
	243	static int i8259A_resume(struct sys_device *dev)
	244	{
	245	init_8259A(i8259A_auto_eoi);
	246	restore_ELCR(irq_trigger);
	247	return 0;
	248	}
	249
	250	static int i8259A_suspend(struct sys_device *dev, pm_message_t state)
	251	{
	252	save_ELCR(irq_trigger);
	253	return 0;
	254	}
	255
	256	static int i8259A_shutdown(struct sys_device *dev)
	257	{
	258	/* Put the i8259A into a quiescent state that
	259	* the kernel initialization code can get it
	260	* out of.
	261	*/
	262	outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
	263	outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-1 */
	264	return 0;
	265	}
	266
	267	static struct sysdev_class i8259_sysdev_class = {
	268	.name = "i8259",
	269	.suspend = i8259A_suspend,
	270	.resume = i8259A_resume,
	271	.shutdown = i8259A_shutdown,
	272	};
	273
	274	static struct sys_device device_i8259A = {
	275	.id = 0,
	276	.cls = &i8259_sysdev_class,
	277	};
278
b81bb373	279	static void mask_8259A(void)
d94d93ca SS	280	{
	281	unsigned long flags;
	282
5619c280	283	raw_spin_lock_irqsave(&i8259A_lock, flags);
d94d93ca SS	284
	285	outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
	286	outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
	287
5619c280	288	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
d94d93ca SS	289	}
d94d93ca SS	290
b81bb373	291	static void unmask_8259A(void)
d94d93ca SS	292	{
	293	unsigned long flags;
	294
5619c280	295	raw_spin_lock_irqsave(&i8259A_lock, flags);
d94d93ca SS	296
	297	outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
	298	outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */
	299
5619c280	300	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
d94d93ca SS	301	}
d94d93ca SS	302
b81bb373	303	static void init_8259A(int auto_eoi)
21fd5132 PM	304	{
	305	unsigned long flags;
	306
	307	i8259A_auto_eoi = auto_eoi;
	308
5619c280	309	raw_spin_lock_irqsave(&i8259A_lock, flags);
21fd5132 PM	310
	311	outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
	312	outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
	313
	314	/*
	315	* outb_pic - this has to work on a wide range of PC hardware.
	316	*/
	317	outb_pic(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */
c46e62f7 PM	318
c46e62f7 PM	319	/* ICW2: 8259A-1 IR0-7 mapped to 0x30-0x37 on x86-64,
7bafaf30	320	to 0x20-0x27 on i386 */
21fd5132	321	outb_pic(IRQ0_VECTOR, PIC_MASTER_IMR);
c46e62f7	322
21fd5132	323	/* 8259A-1 (the master) has a slave on IR2 */
c46e62f7 PM	324	outb_pic(1U << PIC_CASCADE_IR, PIC_MASTER_IMR);
c46e62f7 PM	325
21fd5132 PM	326	if (auto_eoi) /* master does Auto EOI */
	327	outb_pic(MASTER_ICW4_DEFAULT \| PIC_ICW4_AEOI, PIC_MASTER_IMR);
	328	else /* master expects normal EOI */
	329	outb_pic(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);
	330
	331	outb_pic(0x11, PIC_SLAVE_CMD); /* ICW1: select 8259A-2 init */
c46e62f7 PM	332
c46e62f7 PM	333	/* ICW2: 8259A-2 IR0-7 mapped to IRQ8_VECTOR */
21fd5132 PM	334	outb_pic(IRQ8_VECTOR, PIC_SLAVE_IMR);
	335	/* 8259A-2 is a slave on master's IR2 */
	336	outb_pic(PIC_CASCADE_IR, PIC_SLAVE_IMR);
	337	/* (slave's support for AEOI in flat mode is to be investigated) */
	338	outb_pic(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR);
	339
21fd5132 PM	340	if (auto_eoi)
	341	/*
	342	* In AEOI mode we just have to mask the interrupt
	343	* when acking.
	344	*/
	345	i8259A_chip.mask_ack = disable_8259A_irq;
	346	else
	347	i8259A_chip.mask_ack = mask_and_ack_8259A;
	348
	349	udelay(100); /* wait for 8259A to initialize */
	350
	351	outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
	352	outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */
	353
5619c280	354	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
21fd5132	355	}
b81bb373	356
ef354866 JP	357	/*
	358	* make i8259 a driver so that we can select pic functions at run time. the goal
	359	* is to make x86 binary compatible among pc compatible and non-pc compatible
	360	* platforms, such as x86 MID.
	361	*/
	362
28a3c93d JP	363	static void legacy_pic_noop(void) { };
	364	static void legacy_pic_uint_noop(unsigned int unused) { };
	365	static void legacy_pic_int_noop(int unused) { };
ef354866 JP	366
	367	static struct irq_chip dummy_pic_chip = {
	368	.name = "dummy pic",
	369	.mask = legacy_pic_uint_noop,
	370	.unmask = legacy_pic_uint_noop,
	371	.disable = legacy_pic_uint_noop,
	372	.mask_ack = legacy_pic_uint_noop,
	373	};
	374	static int legacy_pic_irq_pending_noop(unsigned int irq)
	375	{
	376	return 0;
	377	}
	378
	379	struct legacy_pic null_legacy_pic = {
	380	.nr_legacy_irqs = 0,
	381	.chip = &dummy_pic_chip,
	382	.mask_all = legacy_pic_noop,
	383	.restore_mask = legacy_pic_noop,
	384	.init = legacy_pic_int_noop,
	385	.irq_pending = legacy_pic_irq_pending_noop,
	386	.make_irq = legacy_pic_uint_noop,
	387	};
	388
	389	struct legacy_pic default_legacy_pic = {
	390	.nr_legacy_irqs = NR_IRQS_LEGACY,
	391	.chip = &i8259A_chip,
	392	.mask_all = mask_8259A,
	393	.restore_mask = unmask_8259A,
	394	.init = init_8259A,
	395	.irq_pending = i8259A_irq_pending,
	396	.make_irq = make_8259A_irq,
	397	};
	398
	399	struct legacy_pic *legacy_pic = &default_legacy_pic;
087b255a AL	400
	401	static int __init i8259A_init_sysfs(void)
	402	{
	403	int error;
	404
	405	if (legacy_pic != &default_legacy_pic)
	406	return 0;
	407
	408	error = sysdev_class_register(&i8259_sysdev_class);
	409	if (!error)
	410	error = sysdev_register(&device_i8259A);
	411	return error;
	412	}
	413
	414	device_initcall(i8259A_init_sysfs);