[deliverable/linux.git] / arch / x86 / kernel / i8259_32.c

#include <linux/errno.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/slab.h>
#include <linux/random.h>
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/sysdev.h>
#include <linux/bitops.h>

#include <asm/atomic.h>
#include <asm/system.h>
#include <asm/io.h>
#include <asm/timer.h>
#include <asm/pgtable.h>
#include <asm/delay.h>
#include <asm/desc.h>
#include <asm/apic.h>
#include <asm/arch_hooks.h>
#include <asm/i8259.h>

/*
 * This is the 'legacy' 8259A Programmable Interrupt Controller,
 * present in the majority of PC/AT boxes.
 * plus some generic x86 specific things if generic specifics makes
 * any sense at all.
 * this file should become arch/i386/kernel/irq.c when the old irq.c
 * moves to arch independent land
 */

static int i8259A_auto_eoi;
DEFINE_SPINLOCK(i8259A_lock);
static void mask_and_ack_8259A(unsigned int);

static struct irq_chip i8259A_chip = {
	.name		= "XT-PIC",
	.mask		= disable_8259A_irq,
	.disable	= disable_8259A_irq,
	.unmask		= enable_8259A_irq,
	.mask_ack	= mask_and_ack_8259A,
};

/*
 * 8259A PIC functions to handle ISA devices:
 */

/*
 * This contains the irq mask for both 8259A irq controllers,
 */
unsigned int cached_irq_mask = 0xffff;

/*
 * Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
 * boards the timer interrupt is not really connected to any IO-APIC pin,
 * it's fed to the master 8259A's IR0 line only.
 *
 * Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
 * this 'mixed mode' IRQ handling costs nothing because it's only used
 * at IRQ setup time.
 */
unsigned long io_apic_irqs;

void disable_8259A_irq(unsigned int irq)
{
	unsigned int mask = 1 << irq;
	unsigned long flags;

	spin_lock_irqsave(&i8259A_lock, flags);
	cached_irq_mask |= mask;
	if (irq & 8)
		outb(cached_slave_mask, PIC_SLAVE_IMR);
	else
		outb(cached_master_mask, PIC_MASTER_IMR);
	spin_unlock_irqrestore(&i8259A_lock, flags);
}

void enable_8259A_irq(unsigned int irq)
{
	unsigned int mask = ~(1 << irq);
	unsigned long flags;

	spin_lock_irqsave(&i8259A_lock, flags);
	cached_irq_mask &= mask;
	if (irq & 8)
		outb(cached_slave_mask, PIC_SLAVE_IMR);
	else
		outb(cached_master_mask, PIC_MASTER_IMR);
	spin_unlock_irqrestore(&i8259A_lock, flags);
}

int i8259A_irq_pending(unsigned int irq)
{
	unsigned int mask = 1<<irq;
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&i8259A_lock, flags);
	if (irq < 8)
		ret = inb(PIC_MASTER_CMD) & mask;
	else
		ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
	spin_unlock_irqrestore(&i8259A_lock, flags);

	return ret;
}

void make_8259A_irq(unsigned int irq)
{
	disable_irq_nosync(irq);
	io_apic_irqs &= ~(1<<irq);
	set_irq_chip_and_handler_name(irq, &i8259A_chip, handle_level_irq,
				      "XT");
	enable_irq(irq);
}

/*
 * This function assumes to be called rarely. Switching between
 * 8259A registers is slow.
 * This has to be protected by the irq controller spinlock
 * before being called.
 */
static inline int i8259A_irq_real(unsigned int irq)
{
	int value;
	int irqmask = 1<<irq;

	if (irq < 8) {
		outb(0x0B,PIC_MASTER_CMD);	/* ISR register */
		value = inb(PIC_MASTER_CMD) & irqmask;
		outb(0x0A,PIC_MASTER_CMD);	/* back to the IRR register */
		return value;
	}
	outb(0x0B,PIC_SLAVE_CMD);	/* ISR register */
	value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
	outb(0x0A,PIC_SLAVE_CMD);	/* back to the IRR register */
	return value;
}

/*
 * Careful! The 8259A is a fragile beast, it pretty
 * much _has_ to be done exactly like this (mask it
 * first, _then_ send the EOI, and the order of EOI
 * to the two 8259s is important!
 */
static void mask_and_ack_8259A(unsigned int irq)
{
	unsigned int irqmask = 1 << irq;
	unsigned long flags;

	spin_lock_irqsave(&i8259A_lock, flags);
	/*
	 * Lightweight spurious IRQ detection. We do not want
	 * to overdo spurious IRQ handling - it's usually a sign
	 * of hardware problems, so we only do the checks we can
	 * do without slowing down good hardware unnecessarily.
	 *
	 * Note that IRQ7 and IRQ15 (the two spurious IRQs
	 * usually resulting from the 8259A-1|2 PICs) occur
	 * even if the IRQ is masked in the 8259A. Thus we
	 * can check spurious 8259A IRQs without doing the
	 * quite slow i8259A_irq_real() call for every IRQ.
	 * This does not cover 100% of spurious interrupts,
	 * but should be enough to warn the user that there
	 * is something bad going on ...
	 */
	if (cached_irq_mask & irqmask)
		goto spurious_8259A_irq;
	cached_irq_mask |= irqmask;

handle_real_irq:
	if (irq & 8) {
		inb(PIC_SLAVE_IMR);	/* DUMMY - (do we need this?) */
		outb(cached_slave_mask, PIC_SLAVE_IMR);
		outb(0x60+(irq&7),PIC_SLAVE_CMD);/* 'Specific EOI' to slave */
		outb(0x60+PIC_CASCADE_IR,PIC_MASTER_CMD); /* 'Specific EOI' to master-IRQ2 */
	} else {
		inb(PIC_MASTER_IMR);	/* DUMMY - (do we need this?) */
		outb(cached_master_mask, PIC_MASTER_IMR);
		outb(0x60+irq,PIC_MASTER_CMD);	/* 'Specific EOI to master */
	}
	spin_unlock_irqrestore(&i8259A_lock, flags);
	return;

spurious_8259A_irq:
	/*
	 * this is the slow path - should happen rarely.
	 */
	if (i8259A_irq_real(irq))
		/*
		 * oops, the IRQ _is_ in service according to the
		 * 8259A - not spurious, go handle it.
		 */
		goto handle_real_irq;

	{
		static int spurious_irq_mask;
		/*
		 * At this point we can be sure the IRQ is spurious,
		 * lets ACK and report it. [once per IRQ]
		 */
		if (!(spurious_irq_mask & irqmask)) {
			printk(KERN_DEBUG "spurious 8259A interrupt: IRQ%d.\n", irq);
			spurious_irq_mask |= irqmask;
		}
		atomic_inc(&irq_err_count);
		/*
		 * Theoretically we do not have to handle this IRQ,
		 * but in Linux this does not cause problems and is
		 * simpler for us.
		 */
		goto handle_real_irq;
	}
}

static char irq_trigger[2];
/**
 * ELCR registers (0x4d0, 0x4d1) control edge/level of IRQ
 */
static void restore_ELCR(char *trigger)
{
	outb(trigger[0], 0x4d0);
	outb(trigger[1], 0x4d1);
}

static void save_ELCR(char *trigger)
{
	/* IRQ 0,1,2,8,13 are marked as reserved */
	trigger[0] = inb(0x4d0) & 0xF8;
	trigger[1] = inb(0x4d1) & 0xDE;
}

static int i8259A_resume(struct sys_device *dev)
{
	init_8259A(i8259A_auto_eoi);
	restore_ELCR(irq_trigger);
	return 0;
}

static int i8259A_suspend(struct sys_device *dev, pm_message_t state)
{
	save_ELCR(irq_trigger);
	return 0;
}

static int i8259A_shutdown(struct sys_device *dev)
{
	/* Put the i8259A into a quiescent state that
	 * the kernel initialization code can get it
	 * out of.
	 */
	outb(0xff, PIC_MASTER_IMR);	/* mask all of 8259A-1 */
	outb(0xff, PIC_SLAVE_IMR);	/* mask all of 8259A-1 */
	return 0;
}

static struct sysdev_class i8259_sysdev_class = {
	.name = "i8259",
	.suspend = i8259A_suspend,
	.resume = i8259A_resume,
	.shutdown = i8259A_shutdown,
};

static struct sys_device device_i8259A = {
	.id	= 0,
	.cls	= &i8259_sysdev_class,
};

static int __init i8259A_init_sysfs(void)
{
	int error = sysdev_class_register(&i8259_sysdev_class);
	if (!error)
		error = sysdev_register(&device_i8259A);
	return error;
}

device_initcall(i8259A_init_sysfs);

void init_8259A(int auto_eoi)
{
	unsigned long flags;

	i8259A_auto_eoi = auto_eoi;

	spin_lock_irqsave(&i8259A_lock, flags);

	outb(0xff, PIC_MASTER_IMR);	/* mask all of 8259A-1 */
	outb(0xff, PIC_SLAVE_IMR);	/* mask all of 8259A-2 */

	/*
	 * outb_pic - this has to work on a wide range of PC hardware.
	 */
	outb_pic(0x11, PIC_MASTER_CMD);	/* ICW1: select 8259A-1 init */
	outb_pic(0x20 + 0, PIC_MASTER_IMR);	/* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */
	outb_pic(1U << PIC_CASCADE_IR, PIC_MASTER_IMR);	/* 8259A-1 (the master) has a slave on IR2 */
	if (auto_eoi)	/* master does Auto EOI */
		outb_pic(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);
	else		/* master expects normal EOI */
		outb_pic(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);

	outb_pic(0x11, PIC_SLAVE_CMD);	/* ICW1: select 8259A-2 init */
	outb_pic(0x20 + 8, PIC_SLAVE_IMR);	/* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */
	outb_pic(PIC_CASCADE_IR, PIC_SLAVE_IMR);	/* 8259A-2 is a slave on master's IR2 */
	outb_pic(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR); /* (slave's support for AEOI in flat mode is to be investigated) */
	if (auto_eoi)
		/*
		 * In AEOI mode we just have to mask the interrupt
		 * when acking.
		 */
		i8259A_chip.mask_ack = disable_8259A_irq;
	else
		i8259A_chip.mask_ack = mask_and_ack_8259A;

	udelay(100);		/* wait for 8259A to initialize */

	outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
	outb(cached_slave_mask, PIC_SLAVE_IMR);	  /* restore slave IRQ mask */

	spin_unlock_irqrestore(&i8259A_lock, flags);
}

/*
 * Note that on a 486, we don't want to do a SIGFPE on an irq13
 * as the irq is unreliable, and exception 16 works correctly
 * (ie as explained in the intel literature). On a 386, you
 * can't use exception 16 due to bad IBM design, so we have to
 * rely on the less exact irq13.
 *
 * Careful.. Not only is IRQ13 unreliable, but it is also
 * leads to races. IBM designers who came up with it should
 * be shot.
 */
 

static irqreturn_t math_error_irq(int cpl, void *dev_id)
{
	extern void math_error(void __user *);
	outb(0,0xF0);
	if (ignore_fpu_irq || !boot_cpu_data.hard_math)
		return IRQ_NONE;
	math_error((void __user *)get_irq_regs()->ip);
	return IRQ_HANDLED;
}

/*
 * New motherboards sometimes make IRQ 13 be a PCI interrupt,
 * so allow interrupt sharing.
 */
static struct irqaction fpu_irq = {
	.handler = math_error_irq,
	.mask = CPU_MASK_NONE,
	.name = "fpu",
};

void __init init_ISA_irqs (void)
{
	int i;

#ifdef CONFIG_X86_LOCAL_APIC
	init_bsp_APIC();
#endif
	init_8259A(0);

	for (i = 0; i < NR_IRQS; i++) {
		irq_desc[i].status = IRQ_DISABLED;
		irq_desc[i].action = NULL;
		irq_desc[i].depth = 1;

		if (i < 16) {
			/*
			 * 16 old-style INTA-cycle interrupts:
			 */
			set_irq_chip_and_handler_name(i, &i8259A_chip,
						      handle_level_irq, "XT");
		} else {
			/*
			 * 'high' PCI IRQs filled in on demand
			 */
			irq_desc[i].chip = &no_irq_chip;
		}
	}
}

/* Overridden in paravirt.c */
void init_IRQ(void) __attribute__((weak, alias("native_init_IRQ")));

void __init native_init_IRQ(void)
{
	int i;

	/* all the set up before the call gates are initialised */
	pre_intr_init_hook();

	/*
	 * Cover the whole vector space, no vector can escape
	 * us. (some of these will be overridden and become
	 * 'special' SMP interrupts)
	 */
	for (i = 0; i < (NR_VECTORS - FIRST_EXTERNAL_VECTOR); i++) {
		int vector = FIRST_EXTERNAL_VECTOR + i;
		if (i >= NR_IRQS)
			break;
		/* SYSCALL_VECTOR was reserved in trap_init. */
		if (!test_bit(vector, used_vectors))
			set_intr_gate(vector, interrupt[i]);
	}

	/* setup after call gates are initialised (usually add in
	 * the architecture specific gates)
	 */
	intr_init_hook();

	/*
	 * External FPU? Set up irq13 if so, for
	 * original braindamaged IBM FERR coupling.
	 */
	if (boot_cpu_data.hard_math && !cpu_has_fpu)
		setup_irq(FPU_IRQ, &fpu_irq);

	irq_ctx_init(smp_processor_id());
}
Commit	Line	Data
1da177e4 LT	1	#include <linux/errno.h>
	2	#include <linux/signal.h>
	3	#include <linux/sched.h>
	4	#include <linux/ioport.h>
	5	#include <linux/interrupt.h>
	6	#include <linux/slab.h>
	7	#include <linux/random.h>
1da177e4 LT	8	#include <linux/init.h>
	9	#include <linux/kernel_stat.h>
	10	#include <linux/sysdev.h>
	11	#include <linux/bitops.h>
	12
1da177e4 LT	13	#include <asm/atomic.h>
	14	#include <asm/system.h>
	15	#include <asm/io.h>
1da177e4 LT	16	#include <asm/timer.h>
	17	#include <asm/pgtable.h>
	18	#include <asm/delay.h>
	19	#include <asm/desc.h>
	20	#include <asm/apic.h>
	21	#include <asm/arch_hooks.h>
	22	#include <asm/i8259.h>
	23
1da177e4 LT	24	/*
	25	* This is the 'legacy' 8259A Programmable Interrupt Controller,
	26	* present in the majority of PC/AT boxes.
	27	* plus some generic x86 specific things if generic specifics makes
	28	* any sense at all.
	29	* this file should become arch/i386/kernel/irq.c when the old irq.c
	30	* moves to arch independent land
	31	*/
	32
35d534a3	33	static int i8259A_auto_eoi;
f5b9ed7a	34	DEFINE_SPINLOCK(i8259A_lock);
1da177e4 LT	35	static void mask_and_ack_8259A(unsigned int);
1da177e4 LT	36
f5b9ed7a IM	37	static struct irq_chip i8259A_chip = {
	38	.name = "XT-PIC",
	39	.mask = disable_8259A_irq,
76d21601	40	.disable = disable_8259A_irq,
f5b9ed7a IM	41	.unmask = enable_8259A_irq,
f5b9ed7a IM	42	.mask_ack = mask_and_ack_8259A,
1da177e4 LT	43	};
	44
	45	/*
	46	* 8259A PIC functions to handle ISA devices:
	47	*/
	48
	49	/*
	50	* This contains the irq mask for both 8259A irq controllers,
	51	*/
	52	unsigned int cached_irq_mask = 0xffff;
	53
	54	/*
	55	* Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
	56	* boards the timer interrupt is not really connected to any IO-APIC pin,
	57	* it's fed to the master 8259A's IR0 line only.
	58	*
	59	* Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
	60	* this 'mixed mode' IRQ handling costs nothing because it's only used
	61	* at IRQ setup time.
	62	*/
	63	unsigned long io_apic_irqs;
	64
	65	void disable_8259A_irq(unsigned int irq)
	66	{
	67	unsigned int mask = 1 << irq;
	68	unsigned long flags;
	69
	70	spin_lock_irqsave(&i8259A_lock, flags);
	71	cached_irq_mask \|= mask;
	72	if (irq & 8)
	73	outb(cached_slave_mask, PIC_SLAVE_IMR);
	74	else
	75	outb(cached_master_mask, PIC_MASTER_IMR);
	76	spin_unlock_irqrestore(&i8259A_lock, flags);
	77	}
	78
	79	void enable_8259A_irq(unsigned int irq)
	80	{
	81	unsigned int mask = ~(1 << irq);
	82	unsigned long flags;
	83
	84	spin_lock_irqsave(&i8259A_lock, flags);
	85	cached_irq_mask &= mask;
	86	if (irq & 8)
	87	outb(cached_slave_mask, PIC_SLAVE_IMR);
	88	else
	89	outb(cached_master_mask, PIC_MASTER_IMR);
	90	spin_unlock_irqrestore(&i8259A_lock, flags);
	91	}
	92
	93	int i8259A_irq_pending(unsigned int irq)
	94	{
	95	unsigned int mask = 1<<irq;
	96	unsigned long flags;
	97	int ret;
	98
	99	spin_lock_irqsave(&i8259A_lock, flags);
	100	if (irq < 8)
	101	ret = inb(PIC_MASTER_CMD) & mask;
	102	else
	103	ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
	104	spin_unlock_irqrestore(&i8259A_lock, flags);
	105
	106	return ret;
107	}
108
109	void make_8259A_irq(unsigned int irq)
110	{
111	disable_irq_nosync(irq);
112	io_apic_irqs &= ~(1<<irq);
a460e745 IM	113	set_irq_chip_and_handler_name(irq, &i8259A_chip, handle_level_irq,
a460e745 IM	114	"XT");
1da177e4 LT	115	enable_irq(irq);
	116	}
	117
	118	/*
	119	* This function assumes to be called rarely. Switching between
	120	* 8259A registers is slow.
	121	* This has to be protected by the irq controller spinlock
	122	* before being called.
	123	*/
	124	static inline int i8259A_irq_real(unsigned int irq)
	125	{
	126	int value;
	127	int irqmask = 1<<irq;
	128
	129	if (irq < 8) {
	130	outb(0x0B,PIC_MASTER_CMD); /* ISR register */
	131	value = inb(PIC_MASTER_CMD) & irqmask;
	132	outb(0x0A,PIC_MASTER_CMD); /* back to the IRR register */
	133	return value;
	134	}
	135	outb(0x0B,PIC_SLAVE_CMD); /* ISR register */
	136	value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
	137	outb(0x0A,PIC_SLAVE_CMD); /* back to the IRR register */
	138	return value;
	139	}
	140
	141	/*
	142	* Careful! The 8259A is a fragile beast, it pretty
	143	* much _has_ to be done exactly like this (mask it
	144	* first, _then_ send the EOI, and the order of EOI
	145	* to the two 8259s is important!
	146	*/
	147	static void mask_and_ack_8259A(unsigned int irq)
	148	{
	149	unsigned int irqmask = 1 << irq;
	150	unsigned long flags;
	151
	152	spin_lock_irqsave(&i8259A_lock, flags);
	153	/*
	154	* Lightweight spurious IRQ detection. We do not want
	155	* to overdo spurious IRQ handling - it's usually a sign
	156	* of hardware problems, so we only do the checks we can
d6e05edc	157	* do without slowing down good hardware unnecessarily.
1da177e4 LT	158	*
	159	* Note that IRQ7 and IRQ15 (the two spurious IRQs
	160	* usually resulting from the 8259A-1\|2 PICs) occur
	161	* even if the IRQ is masked in the 8259A. Thus we
	162	* can check spurious 8259A IRQs without doing the
	163	* quite slow i8259A_irq_real() call for every IRQ.
	164	* This does not cover 100% of spurious interrupts,
	165	* but should be enough to warn the user that there
	166	* is something bad going on ...
	167	*/
	168	if (cached_irq_mask & irqmask)
	169	goto spurious_8259A_irq;
	170	cached_irq_mask \|= irqmask;
	171
	172	handle_real_irq:
	173	if (irq & 8) {
	174	inb(PIC_SLAVE_IMR); /* DUMMY - (do we need this?) */
	175	outb(cached_slave_mask, PIC_SLAVE_IMR);
	176	outb(0x60+(irq&7),PIC_SLAVE_CMD);/* 'Specific EOI' to slave */
	177	outb(0x60+PIC_CASCADE_IR,PIC_MASTER_CMD); /* 'Specific EOI' to master-IRQ2 */
	178	} else {
	179	inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */
	180	outb(cached_master_mask, PIC_MASTER_IMR);
	181	outb(0x60+irq,PIC_MASTER_CMD); /* 'Specific EOI to master */
	182	}
	183	spin_unlock_irqrestore(&i8259A_lock, flags);
	184	return;
	185
	186	spurious_8259A_irq:
	187	/*
	188	* this is the slow path - should happen rarely.
	189	*/
	190	if (i8259A_irq_real(irq))
	191	/*
	192	* oops, the IRQ _is_ in service according to the
	193	* 8259A - not spurious, go handle it.
	194	*/
	195	goto handle_real_irq;
	196
	197	{
	198	static int spurious_irq_mask;
	199	/*
	200	* At this point we can be sure the IRQ is spurious,
	201	* lets ACK and report it. [once per IRQ]
	202	*/
	203	if (!(spurious_irq_mask & irqmask)) {
	204	printk(KERN_DEBUG "spurious 8259A interrupt: IRQ%d.\n", irq);
	205	spurious_irq_mask \|= irqmask;
	206	}
	207	atomic_inc(&irq_err_count);
	208	/*
	209	* Theoretically we do not have to handle this IRQ,
	210	* but in Linux this does not cause problems and is
	211	* simpler for us.
	212	*/
	213	goto handle_real_irq;
	214	}
	215	}
	216
	217	static char irq_trigger[2];
	218	/**
	219	* ELCR registers (0x4d0, 0x4d1) control edge/level of IRQ
	220	*/
	221	static void restore_ELCR(char *trigger)
222	{
223	outb(trigger[0], 0x4d0);
224	outb(trigger[1], 0x4d1);
225	}
226
227	static void save_ELCR(char *trigger)
228	{
229	/* IRQ 0,1,2,8,13 are marked as reserved */
230	trigger[0] = inb(0x4d0) & 0xF8;
231	trigger[1] = inb(0x4d1) & 0xDE;
232	}
233
234	static int i8259A_resume(struct sys_device *dev)
235	{
35d534a3	236	init_8259A(i8259A_auto_eoi);
1da177e4 LT	237	restore_ELCR(irq_trigger);
	238	return 0;
	239	}
	240
438510f6	241	static int i8259A_suspend(struct sys_device *dev, pm_message_t state)
1da177e4 LT	242	{
	243	save_ELCR(irq_trigger);
	244	return 0;
	245	}
	246
cee5dab4 EB	247	static int i8259A_shutdown(struct sys_device *dev)
	248	{
	249	/* Put the i8259A into a quiescent state that
	250	* the kernel initialization code can get it
	251	* out of.
	252	*/
110cb1d2 AM	253	outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
110cb1d2 AM	254	outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-1 */
cee5dab4 EB	255	return 0;
	256	}
	257
1da177e4	258	static struct sysdev_class i8259_sysdev_class = {
af5ca3f4	259	.name = "i8259",
1da177e4 LT	260	.suspend = i8259A_suspend,
1da177e4 LT	261	.resume = i8259A_resume,
cee5dab4	262	.shutdown = i8259A_shutdown,
1da177e4 LT	263	};
	264
	265	static struct sys_device device_i8259A = {
	266	.id = 0,
	267	.cls = &i8259_sysdev_class,
	268	};
	269
	270	static int __init i8259A_init_sysfs(void)
	271	{
	272	int error = sysdev_class_register(&i8259_sysdev_class);
	273	if (!error)
	274	error = sysdev_register(&device_i8259A);
	275	return error;
	276	}
	277
	278	device_initcall(i8259A_init_sysfs);
	279
	280	void init_8259A(int auto_eoi)
	281	{
	282	unsigned long flags;
	283
35d534a3 MG	284	i8259A_auto_eoi = auto_eoi;
35d534a3 MG	285
1da177e4 LT	286	spin_lock_irqsave(&i8259A_lock, flags);
	287
	288	outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
	289	outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
	290
	291	/*
466eed22	292	* outb_pic - this has to work on a wide range of PC hardware.
1da177e4	293	*/
466eed22 AC	294	outb_pic(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */
	295	outb_pic(0x20 + 0, PIC_MASTER_IMR); /* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */
	296	outb_pic(1U << PIC_CASCADE_IR, PIC_MASTER_IMR); /* 8259A-1 (the master) has a slave on IR2 */
1da177e4	297	if (auto_eoi) /* master does Auto EOI */
466eed22	298	outb_pic(MASTER_ICW4_DEFAULT \| PIC_ICW4_AEOI, PIC_MASTER_IMR);
1da177e4	299	else /* master expects normal EOI */
466eed22	300	outb_pic(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);
1da177e4	301
466eed22 AC	302	outb_pic(0x11, PIC_SLAVE_CMD); /* ICW1: select 8259A-2 init */
	303	outb_pic(0x20 + 8, PIC_SLAVE_IMR); /* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */
	304	outb_pic(PIC_CASCADE_IR, PIC_SLAVE_IMR); /* 8259A-2 is a slave on master's IR2 */
	305	outb_pic(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR); /* (slave's support for AEOI in flat mode is to be investigated) */
1da177e4 LT	306	if (auto_eoi)
1da177e4 LT	307	/*
f5b9ed7a	308	* In AEOI mode we just have to mask the interrupt
1da177e4 LT	309	* when acking.
1da177e4 LT	310	*/
f5b9ed7a	311	i8259A_chip.mask_ack = disable_8259A_irq;
1da177e4	312	else
f5b9ed7a	313	i8259A_chip.mask_ack = mask_and_ack_8259A;
1da177e4 LT	314
	315	udelay(100); /* wait for 8259A to initialize */
	316
	317	outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
	318	outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */
	319
	320	spin_unlock_irqrestore(&i8259A_lock, flags);
	321	}
	322
	323	/*
	324	* Note that on a 486, we don't want to do a SIGFPE on an irq13
	325	* as the irq is unreliable, and exception 16 works correctly
	326	* (ie as explained in the intel literature). On a 386, you
	327	* can't use exception 16 due to bad IBM design, so we have to
	328	* rely on the less exact irq13.
	329	*
	330	* Careful.. Not only is IRQ13 unreliable, but it is also
	331	* leads to races. IBM designers who came up with it should
	332	* be shot.
	333	*/
	334
	335
7d12e780	336	static irqreturn_t math_error_irq(int cpl, void *dev_id)
1da177e4 LT	337	{
	338	extern void math_error(void __user *);
	339	outb(0,0xF0);
	340	if (ignore_fpu_irq \|\| !boot_cpu_data.hard_math)
	341	return IRQ_NONE;
65ea5b03	342	math_error((void __user *)get_irq_regs()->ip);
1da177e4 LT	343	return IRQ_HANDLED;
	344	}
	345
	346	/*
	347	* New motherboards sometimes make IRQ 13 be a PCI interrupt,
	348	* so allow interrupt sharing.
	349	*/
6a61f6a5 TG	350	static struct irqaction fpu_irq = {
	351	.handler = math_error_irq,
	352	.mask = CPU_MASK_NONE,
	353	.name = "fpu",
	354	};
1da177e4 LT	355
	356	void __init init_ISA_irqs (void)
	357	{
	358	int i;
	359
	360	#ifdef CONFIG_X86_LOCAL_APIC
	361	init_bsp_APIC();
	362	#endif
	363	init_8259A(0);
	364
	365	for (i = 0; i < NR_IRQS; i++) {
	366	irq_desc[i].status = IRQ_DISABLED;
	367	irq_desc[i].action = NULL;
	368	irq_desc[i].depth = 1;
	369
	370	if (i < 16) {
	371	/*
	372	* 16 old-style INTA-cycle interrupts:
	373	*/
a460e745 IM	374	set_irq_chip_and_handler_name(i, &i8259A_chip,
a460e745 IM	375	handle_level_irq, "XT");
1da177e4 LT	376	} else {
	377	/*
	378	* 'high' PCI IRQs filled in on demand
	379	*/
f5b9ed7a	380	irq_desc[i].chip = &no_irq_chip;
1da177e4 LT	381	}
	382	}
	383	}
	384
d3561b7f RR	385	/* Overridden in paravirt.c */
	386	void init_IRQ(void) __attribute__((weak, alias("native_init_IRQ")));
	387
	388	void __init native_init_IRQ(void)
1da177e4 LT	389	{
	390	int i;
	391
	392	/* all the set up before the call gates are initialised */
	393	pre_intr_init_hook();
	394
	395	/*
	396	* Cover the whole vector space, no vector can escape
	397	* us. (some of these will be overridden and become
	398	* 'special' SMP interrupts)
	399	*/
	400	for (i = 0; i < (NR_VECTORS - FIRST_EXTERNAL_VECTOR); i++) {
	401	int vector = FIRST_EXTERNAL_VECTOR + i;
	402	if (i >= NR_IRQS)
	403	break;
dbeb2be2 RR	404	/* SYSCALL_VECTOR was reserved in trap_init. */
dbeb2be2 RR	405	if (!test_bit(vector, used_vectors))
1da177e4 LT	406	set_intr_gate(vector, interrupt[i]);
	407	}
	408
	409	/* setup after call gates are initialised (usually add in
	410	* the architecture specific gates)
	411	*/
	412	intr_init_hook();
	413
1da177e4 LT	414	/*
	415	* External FPU? Set up irq13 if so, for
	416	* original braindamaged IBM FERR coupling.
	417	*/
	418	if (boot_cpu_data.hard_math && !cpu_has_fpu)
	419	setup_irq(FPU_IRQ, &fpu_irq);
	420
	421	irq_ctx_init(smp_processor_id());
	422	}