Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
4 | * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo | |
5 | * | |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
d4057bdb | 28 | #include <linux/pci.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
1da177e4 | 33 | #include <linux/sysdev.h> |
3b7d1921 | 34 | #include <linux/msi.h> |
95d77884 | 35 | #include <linux/htirq.h> |
7dfb7103 | 36 | #include <linux/freezer.h> |
f26d6a2b | 37 | #include <linux/kthread.h> |
54168ed7 | 38 | #include <linux/jiffies.h> /* time_after() */ |
d4057bdb YL |
39 | #ifdef CONFIG_ACPI |
40 | #include <acpi/acpi_bus.h> | |
41 | #endif | |
42 | #include <linux/bootmem.h> | |
43 | #include <linux/dmar.h> | |
58ac1e76 | 44 | #include <linux/hpet.h> |
54d5d424 | 45 | |
d4057bdb | 46 | #include <asm/idle.h> |
1da177e4 LT |
47 | #include <asm/io.h> |
48 | #include <asm/smp.h> | |
49 | #include <asm/desc.h> | |
d4057bdb YL |
50 | #include <asm/proto.h> |
51 | #include <asm/acpi.h> | |
52 | #include <asm/dma.h> | |
1da177e4 | 53 | #include <asm/timer.h> |
306e440d | 54 | #include <asm/i8259.h> |
3e4ff115 | 55 | #include <asm/nmi.h> |
2d3fcc1c | 56 | #include <asm/msidef.h> |
8b955b0d | 57 | #include <asm/hypertransport.h> |
a4dbc34d | 58 | #include <asm/setup.h> |
d4057bdb | 59 | #include <asm/irq_remapping.h> |
58ac1e76 | 60 | #include <asm/hpet.h> |
4173a0e7 DN |
61 | #include <asm/uv/uv_hub.h> |
62 | #include <asm/uv/uv_irq.h> | |
1da177e4 | 63 | |
497c9a19 | 64 | #include <mach_ipi.h> |
1da177e4 | 65 | #include <mach_apic.h> |
874c4fe3 | 66 | #include <mach_apicdef.h> |
1da177e4 | 67 | |
32f71aff MR |
68 | #define __apicdebuginit(type) static type __init |
69 | ||
1da177e4 | 70 | /* |
54168ed7 IM |
71 | * Is the SiS APIC rmw bug present ? |
72 | * -1 = don't know, 0 = no, 1 = yes | |
1da177e4 LT |
73 | */ |
74 | int sis_apic_bug = -1; | |
75 | ||
efa2559f YL |
76 | static DEFINE_SPINLOCK(ioapic_lock); |
77 | static DEFINE_SPINLOCK(vector_lock); | |
78 | ||
1da177e4 LT |
79 | /* |
80 | * # of IRQ routing registers | |
81 | */ | |
82 | int nr_ioapic_registers[MAX_IO_APICS]; | |
83 | ||
9f640ccb | 84 | /* I/O APIC entries */ |
ec2cd0a2 | 85 | struct mp_config_ioapic mp_ioapics[MAX_IO_APICS]; |
9f640ccb AS |
86 | int nr_ioapics; |
87 | ||
584f734d | 88 | /* MP IRQ source entries */ |
2fddb6e2 | 89 | struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
90 | |
91 | /* # of MP IRQ source entries */ | |
92 | int mp_irq_entries; | |
93 | ||
8732fc4b AS |
94 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
95 | int mp_bus_id_to_type[MAX_MP_BUSSES]; | |
96 | #endif | |
97 | ||
98 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
99 | ||
efa2559f YL |
100 | int skip_ioapic_setup; |
101 | ||
54168ed7 | 102 | static int __init parse_noapic(char *str) |
efa2559f YL |
103 | { |
104 | /* disable IO-APIC */ | |
105 | disable_ioapic_setup(); | |
106 | return 0; | |
107 | } | |
108 | early_param("noapic", parse_noapic); | |
66759a01 | 109 | |
0f978f45 | 110 | struct irq_pin_list; |
0b8f1efa YL |
111 | |
112 | /* | |
113 | * This is performance-critical, we want to do it O(1) | |
114 | * | |
115 | * the indexing order of this array favors 1:1 mappings | |
116 | * between pins and IRQs. | |
117 | */ | |
118 | ||
119 | struct irq_pin_list { | |
120 | int apic, pin; | |
121 | struct irq_pin_list *next; | |
122 | }; | |
123 | ||
124 | static struct irq_pin_list *get_one_free_irq_2_pin(int cpu) | |
125 | { | |
126 | struct irq_pin_list *pin; | |
127 | int node; | |
128 | ||
129 | node = cpu_to_node(cpu); | |
130 | ||
131 | pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node); | |
132 | printk(KERN_DEBUG " alloc irq_2_pin on cpu %d node %d\n", cpu, node); | |
133 | ||
134 | return pin; | |
135 | } | |
136 | ||
a1420f39 | 137 | struct irq_cfg { |
0f978f45 | 138 | struct irq_pin_list *irq_2_pin; |
497c9a19 YL |
139 | cpumask_t domain; |
140 | cpumask_t old_domain; | |
141 | unsigned move_cleanup_count; | |
a1420f39 | 142 | u8 vector; |
497c9a19 | 143 | u8 move_in_progress : 1; |
a1420f39 YL |
144 | }; |
145 | ||
a1420f39 | 146 | /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */ |
0b8f1efa YL |
147 | #ifdef CONFIG_SPARSE_IRQ |
148 | static struct irq_cfg irq_cfgx[] = { | |
149 | #else | |
d6c88a50 | 150 | static struct irq_cfg irq_cfgx[NR_IRQS] = { |
0b8f1efa YL |
151 | #endif |
152 | [0] = { .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, }, | |
153 | [1] = { .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, }, | |
154 | [2] = { .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, }, | |
155 | [3] = { .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, }, | |
156 | [4] = { .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, }, | |
157 | [5] = { .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, }, | |
158 | [6] = { .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, }, | |
159 | [7] = { .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, }, | |
160 | [8] = { .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, }, | |
161 | [9] = { .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, }, | |
162 | [10] = { .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, }, | |
163 | [11] = { .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, }, | |
164 | [12] = { .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, }, | |
165 | [13] = { .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, }, | |
166 | [14] = { .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, }, | |
167 | [15] = { .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, }, | |
a1420f39 YL |
168 | }; |
169 | ||
0b8f1efa | 170 | void __init arch_early_irq_init(void) |
8f09cd20 | 171 | { |
0b8f1efa YL |
172 | struct irq_cfg *cfg; |
173 | struct irq_desc *desc; | |
174 | int count; | |
175 | int i; | |
d6c88a50 | 176 | |
0b8f1efa YL |
177 | cfg = irq_cfgx; |
178 | count = ARRAY_SIZE(irq_cfgx); | |
8f09cd20 | 179 | |
0b8f1efa YL |
180 | for (i = 0; i < count; i++) { |
181 | desc = irq_to_desc(i); | |
182 | desc->chip_data = &cfg[i]; | |
183 | } | |
184 | } | |
d6c88a50 | 185 | |
0b8f1efa YL |
186 | #ifdef CONFIG_SPARSE_IRQ |
187 | static struct irq_cfg *irq_cfg(unsigned int irq) | |
188 | { | |
189 | struct irq_cfg *cfg = NULL; | |
190 | struct irq_desc *desc; | |
1da177e4 | 191 | |
0b8f1efa YL |
192 | desc = irq_to_desc(irq); |
193 | if (desc) | |
194 | cfg = desc->chip_data; | |
0f978f45 | 195 | |
0b8f1efa YL |
196 | return cfg; |
197 | } | |
d6c88a50 | 198 | |
0b8f1efa | 199 | static struct irq_cfg *get_one_free_irq_cfg(int cpu) |
0f978f45 | 200 | { |
0b8f1efa YL |
201 | struct irq_cfg *cfg; |
202 | int node; | |
203 | ||
204 | node = cpu_to_node(cpu); | |
0f978f45 | 205 | |
0b8f1efa YL |
206 | cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node); |
207 | printk(KERN_DEBUG " alloc irq_cfg on cpu %d node %d\n", cpu, node); | |
0f978f45 | 208 | |
0b8f1efa | 209 | return cfg; |
0f978f45 | 210 | } |
0f978f45 | 211 | |
0b8f1efa | 212 | void arch_init_chip_data(struct irq_desc *desc, int cpu) |
0f978f45 | 213 | { |
0b8f1efa | 214 | struct irq_cfg *cfg; |
0f978f45 | 215 | |
0b8f1efa YL |
216 | cfg = desc->chip_data; |
217 | if (!cfg) { | |
218 | desc->chip_data = get_one_free_irq_cfg(cpu); | |
219 | if (!desc->chip_data) { | |
220 | printk(KERN_ERR "can not alloc irq_cfg\n"); | |
221 | BUG_ON(1); | |
222 | } | |
223 | } | |
224 | } | |
301e6190 | 225 | |
0b8f1efa YL |
226 | #else |
227 | static struct irq_cfg *irq_cfg(unsigned int irq) | |
228 | { | |
229 | return irq < nr_irqs ? irq_cfgx + irq : NULL; | |
0f978f45 | 230 | } |
1da177e4 | 231 | |
0b8f1efa YL |
232 | #endif |
233 | ||
130fe05d LT |
234 | struct io_apic { |
235 | unsigned int index; | |
236 | unsigned int unused[3]; | |
237 | unsigned int data; | |
238 | }; | |
239 | ||
240 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
241 | { | |
242 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
ec2cd0a2 | 243 | + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK); |
130fe05d LT |
244 | } |
245 | ||
246 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) | |
247 | { | |
248 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
249 | writel(reg, &io_apic->index); | |
250 | return readl(&io_apic->data); | |
251 | } | |
252 | ||
253 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) | |
254 | { | |
255 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
256 | writel(reg, &io_apic->index); | |
257 | writel(value, &io_apic->data); | |
258 | } | |
259 | ||
260 | /* | |
261 | * Re-write a value: to be used for read-modify-write | |
262 | * cycles where the read already set up the index register. | |
263 | * | |
264 | * Older SiS APIC requires we rewrite the index register | |
265 | */ | |
266 | static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) | |
267 | { | |
54168ed7 | 268 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
d6c88a50 TG |
269 | |
270 | if (sis_apic_bug) | |
271 | writel(reg, &io_apic->index); | |
130fe05d LT |
272 | writel(value, &io_apic->data); |
273 | } | |
274 | ||
047c8fdb YL |
275 | static bool io_apic_level_ack_pending(unsigned int irq) |
276 | { | |
277 | struct irq_pin_list *entry; | |
278 | unsigned long flags; | |
279 | struct irq_cfg *cfg = irq_cfg(irq); | |
280 | ||
281 | spin_lock_irqsave(&ioapic_lock, flags); | |
282 | entry = cfg->irq_2_pin; | |
283 | for (;;) { | |
284 | unsigned int reg; | |
285 | int pin; | |
286 | ||
287 | if (!entry) | |
288 | break; | |
289 | pin = entry->pin; | |
290 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
291 | /* Is the remote IRR bit set? */ | |
292 | if (reg & IO_APIC_REDIR_REMOTE_IRR) { | |
293 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
294 | return true; | |
295 | } | |
296 | if (!entry->next) | |
297 | break; | |
298 | entry = entry->next; | |
299 | } | |
300 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
301 | ||
302 | return false; | |
303 | } | |
047c8fdb | 304 | |
cf4c6a2f AK |
305 | union entry_union { |
306 | struct { u32 w1, w2; }; | |
307 | struct IO_APIC_route_entry entry; | |
308 | }; | |
309 | ||
310 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) | |
311 | { | |
312 | union entry_union eu; | |
313 | unsigned long flags; | |
314 | spin_lock_irqsave(&ioapic_lock, flags); | |
315 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); | |
316 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
317 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
318 | return eu.entry; | |
319 | } | |
320 | ||
f9dadfa7 LT |
321 | /* |
322 | * When we write a new IO APIC routing entry, we need to write the high | |
323 | * word first! If the mask bit in the low word is clear, we will enable | |
324 | * the interrupt, and we need to make sure the entry is fully populated | |
325 | * before that happens. | |
326 | */ | |
d15512f4 AK |
327 | static void |
328 | __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
cf4c6a2f | 329 | { |
cf4c6a2f AK |
330 | union entry_union eu; |
331 | eu.entry = e; | |
f9dadfa7 LT |
332 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
333 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
334 | } |
335 | ||
336 | static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
337 | { | |
338 | unsigned long flags; | |
339 | spin_lock_irqsave(&ioapic_lock, flags); | |
340 | __ioapic_write_entry(apic, pin, e); | |
f9dadfa7 LT |
341 | spin_unlock_irqrestore(&ioapic_lock, flags); |
342 | } | |
343 | ||
344 | /* | |
345 | * When we mask an IO APIC routing entry, we need to write the low | |
346 | * word first, in order to set the mask bit before we change the | |
347 | * high bits! | |
348 | */ | |
349 | static void ioapic_mask_entry(int apic, int pin) | |
350 | { | |
351 | unsigned long flags; | |
352 | union entry_union eu = { .entry.mask = 1 }; | |
353 | ||
cf4c6a2f AK |
354 | spin_lock_irqsave(&ioapic_lock, flags); |
355 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
356 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
357 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
358 | } | |
359 | ||
497c9a19 YL |
360 | #ifdef CONFIG_SMP |
361 | static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector) | |
362 | { | |
363 | int apic, pin; | |
364 | struct irq_cfg *cfg; | |
365 | struct irq_pin_list *entry; | |
366 | ||
367 | cfg = irq_cfg(irq); | |
368 | entry = cfg->irq_2_pin; | |
369 | for (;;) { | |
370 | unsigned int reg; | |
371 | ||
372 | if (!entry) | |
373 | break; | |
374 | ||
375 | apic = entry->apic; | |
376 | pin = entry->pin; | |
54168ed7 IM |
377 | #ifdef CONFIG_INTR_REMAP |
378 | /* | |
379 | * With interrupt-remapping, destination information comes | |
380 | * from interrupt-remapping table entry. | |
381 | */ | |
382 | if (!irq_remapped(irq)) | |
383 | io_apic_write(apic, 0x11 + pin*2, dest); | |
384 | #else | |
497c9a19 | 385 | io_apic_write(apic, 0x11 + pin*2, dest); |
54168ed7 | 386 | #endif |
497c9a19 YL |
387 | reg = io_apic_read(apic, 0x10 + pin*2); |
388 | reg &= ~IO_APIC_REDIR_VECTOR_MASK; | |
389 | reg |= vector; | |
54168ed7 | 390 | io_apic_modify(apic, 0x10 + pin*2, reg); |
497c9a19 YL |
391 | if (!entry->next) |
392 | break; | |
393 | entry = entry->next; | |
394 | } | |
395 | } | |
efa2559f YL |
396 | |
397 | static int assign_irq_vector(int irq, cpumask_t mask); | |
398 | ||
497c9a19 YL |
399 | static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask) |
400 | { | |
401 | struct irq_cfg *cfg; | |
402 | unsigned long flags; | |
403 | unsigned int dest; | |
404 | cpumask_t tmp; | |
54168ed7 | 405 | struct irq_desc *desc; |
497c9a19 | 406 | |
497c9a19 YL |
407 | cpus_and(tmp, mask, cpu_online_map); |
408 | if (cpus_empty(tmp)) | |
409 | return; | |
410 | ||
047c8fdb | 411 | cfg = irq_cfg(irq); |
497c9a19 YL |
412 | if (assign_irq_vector(irq, mask)) |
413 | return; | |
414 | ||
415 | cpus_and(tmp, cfg->domain, mask); | |
497c9a19 YL |
416 | dest = cpu_mask_to_apicid(tmp); |
417 | /* | |
418 | * Only the high 8 bits are valid. | |
419 | */ | |
420 | dest = SET_APIC_LOGICAL_ID(dest); | |
421 | ||
54168ed7 | 422 | desc = irq_to_desc(irq); |
497c9a19 YL |
423 | spin_lock_irqsave(&ioapic_lock, flags); |
424 | __target_IO_APIC_irq(irq, dest, cfg->vector); | |
54168ed7 | 425 | desc->affinity = mask; |
497c9a19 YL |
426 | spin_unlock_irqrestore(&ioapic_lock, flags); |
427 | } | |
497c9a19 YL |
428 | #endif /* CONFIG_SMP */ |
429 | ||
1da177e4 LT |
430 | /* |
431 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
432 | * shared ISA-space IRQs, so we have to support them. We are super | |
433 | * fast in the common case, and fast for shared ISA-space IRQs. | |
434 | */ | |
0b8f1efa | 435 | static void add_pin_to_irq_cpu(unsigned int irq, int cpu, int apic, int pin) |
1da177e4 | 436 | { |
0f978f45 | 437 | struct irq_pin_list *entry; |
0b8f1efa | 438 | struct irq_cfg *cfg = irq_cfg(irq); |
0f978f45 | 439 | |
0f978f45 YL |
440 | entry = cfg->irq_2_pin; |
441 | if (!entry) { | |
0b8f1efa YL |
442 | entry = get_one_free_irq_2_pin(cpu); |
443 | if (!entry) { | |
444 | printk(KERN_ERR "can not alloc irq_2_pin to add %d - %d\n", | |
445 | apic, pin); | |
446 | return; | |
447 | } | |
0f978f45 YL |
448 | cfg->irq_2_pin = entry; |
449 | entry->apic = apic; | |
450 | entry->pin = pin; | |
0f978f45 YL |
451 | return; |
452 | } | |
1da177e4 | 453 | |
0f978f45 YL |
454 | while (entry->next) { |
455 | /* not again, please */ | |
456 | if (entry->apic == apic && entry->pin == pin) | |
457 | return; | |
1da177e4 | 458 | |
0f978f45 | 459 | entry = entry->next; |
1da177e4 | 460 | } |
0f978f45 | 461 | |
0b8f1efa | 462 | entry->next = get_one_free_irq_2_pin(cpu); |
0f978f45 | 463 | entry = entry->next; |
1da177e4 LT |
464 | entry->apic = apic; |
465 | entry->pin = pin; | |
466 | } | |
467 | ||
468 | /* | |
469 | * Reroute an IRQ to a different pin. | |
470 | */ | |
0b8f1efa | 471 | static void __init replace_pin_at_irq(unsigned int irq, int cpu, |
1da177e4 LT |
472 | int oldapic, int oldpin, |
473 | int newapic, int newpin) | |
474 | { | |
0f978f45 YL |
475 | struct irq_cfg *cfg = irq_cfg(irq); |
476 | struct irq_pin_list *entry = cfg->irq_2_pin; | |
477 | int replaced = 0; | |
1da177e4 | 478 | |
0f978f45 | 479 | while (entry) { |
1da177e4 LT |
480 | if (entry->apic == oldapic && entry->pin == oldpin) { |
481 | entry->apic = newapic; | |
482 | entry->pin = newpin; | |
0f978f45 YL |
483 | replaced = 1; |
484 | /* every one is different, right? */ | |
1da177e4 | 485 | break; |
0f978f45 YL |
486 | } |
487 | entry = entry->next; | |
1da177e4 | 488 | } |
0f978f45 YL |
489 | |
490 | /* why? call replace before add? */ | |
491 | if (!replaced) | |
0b8f1efa | 492 | add_pin_to_irq_cpu(irq, cpu, newapic, newpin); |
1da177e4 LT |
493 | } |
494 | ||
87783be4 CG |
495 | static inline void io_apic_modify_irq(unsigned int irq, |
496 | int mask_and, int mask_or, | |
497 | void (*final)(struct irq_pin_list *entry)) | |
498 | { | |
499 | int pin; | |
500 | struct irq_cfg *cfg; | |
501 | struct irq_pin_list *entry; | |
047c8fdb | 502 | |
87783be4 CG |
503 | cfg = irq_cfg(irq); |
504 | for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) { | |
505 | unsigned int reg; | |
506 | pin = entry->pin; | |
507 | reg = io_apic_read(entry->apic, 0x10 + pin * 2); | |
508 | reg &= mask_and; | |
509 | reg |= mask_or; | |
510 | io_apic_modify(entry->apic, 0x10 + pin * 2, reg); | |
511 | if (final) | |
512 | final(entry); | |
513 | } | |
514 | } | |
047c8fdb | 515 | |
87783be4 CG |
516 | static void __unmask_IO_APIC_irq(unsigned int irq) |
517 | { | |
518 | io_apic_modify_irq(irq, ~IO_APIC_REDIR_MASKED, 0, NULL); | |
519 | } | |
047c8fdb | 520 | |
4e738e2f | 521 | #ifdef CONFIG_X86_64 |
87783be4 | 522 | void io_apic_sync(struct irq_pin_list *entry) |
1da177e4 | 523 | { |
87783be4 CG |
524 | /* |
525 | * Synchronize the IO-APIC and the CPU by doing | |
526 | * a dummy read from the IO-APIC | |
527 | */ | |
528 | struct io_apic __iomem *io_apic; | |
529 | io_apic = io_apic_base(entry->apic); | |
4e738e2f | 530 | readl(&io_apic->data); |
1da177e4 LT |
531 | } |
532 | ||
87783be4 CG |
533 | static void __mask_IO_APIC_irq(unsigned int irq) |
534 | { | |
535 | io_apic_modify_irq(irq, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync); | |
536 | } | |
537 | #else /* CONFIG_X86_32 */ | |
538 | static void __mask_IO_APIC_irq(unsigned int irq) | |
539 | { | |
540 | io_apic_modify_irq(irq, ~0, IO_APIC_REDIR_MASKED, NULL); | |
541 | } | |
1da177e4 | 542 | |
87783be4 CG |
543 | static void __mask_and_edge_IO_APIC_irq(unsigned int irq) |
544 | { | |
545 | io_apic_modify_irq(irq, ~IO_APIC_REDIR_LEVEL_TRIGGER, | |
546 | IO_APIC_REDIR_MASKED, NULL); | |
547 | } | |
1da177e4 | 548 | |
87783be4 CG |
549 | static void __unmask_and_level_IO_APIC_irq(unsigned int irq) |
550 | { | |
551 | io_apic_modify_irq(irq, ~IO_APIC_REDIR_MASKED, | |
552 | IO_APIC_REDIR_LEVEL_TRIGGER, NULL); | |
553 | } | |
554 | #endif /* CONFIG_X86_32 */ | |
047c8fdb | 555 | |
54168ed7 | 556 | static void mask_IO_APIC_irq (unsigned int irq) |
1da177e4 LT |
557 | { |
558 | unsigned long flags; | |
559 | ||
560 | spin_lock_irqsave(&ioapic_lock, flags); | |
561 | __mask_IO_APIC_irq(irq); | |
562 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
563 | } | |
564 | ||
54168ed7 | 565 | static void unmask_IO_APIC_irq (unsigned int irq) |
1da177e4 LT |
566 | { |
567 | unsigned long flags; | |
568 | ||
569 | spin_lock_irqsave(&ioapic_lock, flags); | |
570 | __unmask_IO_APIC_irq(irq); | |
571 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
572 | } | |
573 | ||
574 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) | |
575 | { | |
576 | struct IO_APIC_route_entry entry; | |
36062448 | 577 | |
1da177e4 | 578 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 579 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
580 | if (entry.delivery_mode == dest_SMI) |
581 | return; | |
1da177e4 LT |
582 | /* |
583 | * Disable it in the IO-APIC irq-routing table: | |
584 | */ | |
f9dadfa7 | 585 | ioapic_mask_entry(apic, pin); |
1da177e4 LT |
586 | } |
587 | ||
54168ed7 | 588 | static void clear_IO_APIC (void) |
1da177e4 LT |
589 | { |
590 | int apic, pin; | |
591 | ||
592 | for (apic = 0; apic < nr_ioapics; apic++) | |
593 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) | |
594 | clear_IO_APIC_pin(apic, pin); | |
595 | } | |
596 | ||
54168ed7 | 597 | #if !defined(CONFIG_SMP) && defined(CONFIG_X86_32) |
75604d7f | 598 | void send_IPI_self(int vector) |
1da177e4 LT |
599 | { |
600 | unsigned int cfg; | |
601 | ||
602 | /* | |
603 | * Wait for idle. | |
604 | */ | |
605 | apic_wait_icr_idle(); | |
606 | cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL; | |
607 | /* | |
608 | * Send the IPI. The write to APIC_ICR fires this off. | |
609 | */ | |
593f4a78 | 610 | apic_write(APIC_ICR, cfg); |
1da177e4 | 611 | } |
54168ed7 | 612 | #endif /* !CONFIG_SMP && CONFIG_X86_32*/ |
1da177e4 | 613 | |
54168ed7 | 614 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
615 | /* |
616 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
617 | * specific CPU-side IRQs. | |
618 | */ | |
619 | ||
620 | #define MAX_PIRQS 8 | |
621 | static int pirq_entries [MAX_PIRQS]; | |
622 | static int pirqs_enabled; | |
1da177e4 | 623 | |
1da177e4 LT |
624 | static int __init ioapic_pirq_setup(char *str) |
625 | { | |
626 | int i, max; | |
627 | int ints[MAX_PIRQS+1]; | |
628 | ||
629 | get_options(str, ARRAY_SIZE(ints), ints); | |
630 | ||
631 | for (i = 0; i < MAX_PIRQS; i++) | |
632 | pirq_entries[i] = -1; | |
633 | ||
634 | pirqs_enabled = 1; | |
635 | apic_printk(APIC_VERBOSE, KERN_INFO | |
636 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
637 | max = MAX_PIRQS; | |
638 | if (ints[0] < MAX_PIRQS) | |
639 | max = ints[0]; | |
640 | ||
641 | for (i = 0; i < max; i++) { | |
642 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
643 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
644 | /* | |
645 | * PIRQs are mapped upside down, usually. | |
646 | */ | |
647 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
648 | } | |
649 | return 1; | |
650 | } | |
651 | ||
652 | __setup("pirq=", ioapic_pirq_setup); | |
54168ed7 IM |
653 | #endif /* CONFIG_X86_32 */ |
654 | ||
655 | #ifdef CONFIG_INTR_REMAP | |
656 | /* I/O APIC RTE contents at the OS boot up */ | |
657 | static struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS]; | |
658 | ||
659 | /* | |
660 | * Saves and masks all the unmasked IO-APIC RTE's | |
661 | */ | |
662 | int save_mask_IO_APIC_setup(void) | |
663 | { | |
664 | union IO_APIC_reg_01 reg_01; | |
665 | unsigned long flags; | |
666 | int apic, pin; | |
667 | ||
668 | /* | |
669 | * The number of IO-APIC IRQ registers (== #pins): | |
670 | */ | |
671 | for (apic = 0; apic < nr_ioapics; apic++) { | |
672 | spin_lock_irqsave(&ioapic_lock, flags); | |
673 | reg_01.raw = io_apic_read(apic, 1); | |
674 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
675 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; | |
676 | } | |
677 | ||
678 | for (apic = 0; apic < nr_ioapics; apic++) { | |
679 | early_ioapic_entries[apic] = | |
680 | kzalloc(sizeof(struct IO_APIC_route_entry) * | |
681 | nr_ioapic_registers[apic], GFP_KERNEL); | |
682 | if (!early_ioapic_entries[apic]) | |
5ffa4eb2 | 683 | goto nomem; |
54168ed7 IM |
684 | } |
685 | ||
686 | for (apic = 0; apic < nr_ioapics; apic++) | |
687 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
688 | struct IO_APIC_route_entry entry; | |
689 | ||
690 | entry = early_ioapic_entries[apic][pin] = | |
691 | ioapic_read_entry(apic, pin); | |
692 | if (!entry.mask) { | |
693 | entry.mask = 1; | |
694 | ioapic_write_entry(apic, pin, entry); | |
695 | } | |
696 | } | |
5ffa4eb2 | 697 | |
54168ed7 | 698 | return 0; |
5ffa4eb2 CG |
699 | |
700 | nomem: | |
c1370b49 CG |
701 | while (apic >= 0) |
702 | kfree(early_ioapic_entries[apic--]); | |
5ffa4eb2 CG |
703 | memset(early_ioapic_entries, 0, |
704 | ARRAY_SIZE(early_ioapic_entries)); | |
705 | ||
706 | return -ENOMEM; | |
54168ed7 IM |
707 | } |
708 | ||
709 | void restore_IO_APIC_setup(void) | |
710 | { | |
711 | int apic, pin; | |
712 | ||
5ffa4eb2 CG |
713 | for (apic = 0; apic < nr_ioapics; apic++) { |
714 | if (!early_ioapic_entries[apic]) | |
715 | break; | |
54168ed7 IM |
716 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
717 | ioapic_write_entry(apic, pin, | |
718 | early_ioapic_entries[apic][pin]); | |
5ffa4eb2 CG |
719 | kfree(early_ioapic_entries[apic]); |
720 | early_ioapic_entries[apic] = NULL; | |
721 | } | |
54168ed7 IM |
722 | } |
723 | ||
724 | void reinit_intr_remapped_IO_APIC(int intr_remapping) | |
725 | { | |
726 | /* | |
727 | * for now plain restore of previous settings. | |
728 | * TBD: In the case of OS enabling interrupt-remapping, | |
729 | * IO-APIC RTE's need to be setup to point to interrupt-remapping | |
730 | * table entries. for now, do a plain restore, and wait for | |
731 | * the setup_IO_APIC_irqs() to do proper initialization. | |
732 | */ | |
733 | restore_IO_APIC_setup(); | |
734 | } | |
735 | #endif | |
1da177e4 LT |
736 | |
737 | /* | |
738 | * Find the IRQ entry number of a certain pin. | |
739 | */ | |
740 | static int find_irq_entry(int apic, int pin, int type) | |
741 | { | |
742 | int i; | |
743 | ||
744 | for (i = 0; i < mp_irq_entries; i++) | |
2fddb6e2 AS |
745 | if (mp_irqs[i].mp_irqtype == type && |
746 | (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid || | |
747 | mp_irqs[i].mp_dstapic == MP_APIC_ALL) && | |
748 | mp_irqs[i].mp_dstirq == pin) | |
1da177e4 LT |
749 | return i; |
750 | ||
751 | return -1; | |
752 | } | |
753 | ||
754 | /* | |
755 | * Find the pin to which IRQ[irq] (ISA) is connected | |
756 | */ | |
fcfd636a | 757 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
758 | { |
759 | int i; | |
760 | ||
761 | for (i = 0; i < mp_irq_entries; i++) { | |
2fddb6e2 | 762 | int lbus = mp_irqs[i].mp_srcbus; |
1da177e4 | 763 | |
d27e2b8e | 764 | if (test_bit(lbus, mp_bus_not_pci) && |
2fddb6e2 AS |
765 | (mp_irqs[i].mp_irqtype == type) && |
766 | (mp_irqs[i].mp_srcbusirq == irq)) | |
1da177e4 | 767 | |
2fddb6e2 | 768 | return mp_irqs[i].mp_dstirq; |
1da177e4 LT |
769 | } |
770 | return -1; | |
771 | } | |
772 | ||
fcfd636a EB |
773 | static int __init find_isa_irq_apic(int irq, int type) |
774 | { | |
775 | int i; | |
776 | ||
777 | for (i = 0; i < mp_irq_entries; i++) { | |
2fddb6e2 | 778 | int lbus = mp_irqs[i].mp_srcbus; |
fcfd636a | 779 | |
73b2961b | 780 | if (test_bit(lbus, mp_bus_not_pci) && |
2fddb6e2 AS |
781 | (mp_irqs[i].mp_irqtype == type) && |
782 | (mp_irqs[i].mp_srcbusirq == irq)) | |
fcfd636a EB |
783 | break; |
784 | } | |
785 | if (i < mp_irq_entries) { | |
786 | int apic; | |
54168ed7 | 787 | for(apic = 0; apic < nr_ioapics; apic++) { |
2fddb6e2 | 788 | if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic) |
fcfd636a EB |
789 | return apic; |
790 | } | |
791 | } | |
792 | ||
793 | return -1; | |
794 | } | |
795 | ||
1da177e4 LT |
796 | /* |
797 | * Find a specific PCI IRQ entry. | |
798 | * Not an __init, possibly needed by modules | |
799 | */ | |
800 | static int pin_2_irq(int idx, int apic, int pin); | |
801 | ||
802 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin) | |
803 | { | |
804 | int apic, i, best_guess = -1; | |
805 | ||
54168ed7 IM |
806 | apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", |
807 | bus, slot, pin); | |
ce6444d3 | 808 | if (test_bit(bus, mp_bus_not_pci)) { |
54168ed7 | 809 | apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus); |
1da177e4 LT |
810 | return -1; |
811 | } | |
812 | for (i = 0; i < mp_irq_entries; i++) { | |
2fddb6e2 | 813 | int lbus = mp_irqs[i].mp_srcbus; |
1da177e4 LT |
814 | |
815 | for (apic = 0; apic < nr_ioapics; apic++) | |
2fddb6e2 AS |
816 | if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic || |
817 | mp_irqs[i].mp_dstapic == MP_APIC_ALL) | |
1da177e4 LT |
818 | break; |
819 | ||
47cab822 | 820 | if (!test_bit(lbus, mp_bus_not_pci) && |
2fddb6e2 | 821 | !mp_irqs[i].mp_irqtype && |
1da177e4 | 822 | (bus == lbus) && |
2fddb6e2 | 823 | (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) { |
54168ed7 | 824 | int irq = pin_2_irq(i,apic,mp_irqs[i].mp_dstirq); |
1da177e4 LT |
825 | |
826 | if (!(apic || IO_APIC_IRQ(irq))) | |
827 | continue; | |
828 | ||
2fddb6e2 | 829 | if (pin == (mp_irqs[i].mp_srcbusirq & 3)) |
1da177e4 LT |
830 | return irq; |
831 | /* | |
832 | * Use the first all-but-pin matching entry as a | |
833 | * best-guess fuzzy result for broken mptables. | |
834 | */ | |
835 | if (best_guess < 0) | |
836 | best_guess = irq; | |
837 | } | |
838 | } | |
839 | return best_guess; | |
840 | } | |
54168ed7 | 841 | |
129f6946 | 842 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); |
1da177e4 | 843 | |
c0a282c2 | 844 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
1da177e4 LT |
845 | /* |
846 | * EISA Edge/Level control register, ELCR | |
847 | */ | |
848 | static int EISA_ELCR(unsigned int irq) | |
849 | { | |
850 | if (irq < 16) { | |
851 | unsigned int port = 0x4d0 + (irq >> 3); | |
852 | return (inb(port) >> (irq & 7)) & 1; | |
853 | } | |
854 | apic_printk(APIC_VERBOSE, KERN_INFO | |
855 | "Broken MPtable reports ISA irq %d\n", irq); | |
856 | return 0; | |
857 | } | |
54168ed7 | 858 | |
c0a282c2 | 859 | #endif |
1da177e4 | 860 | |
6728801d AS |
861 | /* ISA interrupts are always polarity zero edge triggered, |
862 | * when listed as conforming in the MP table. */ | |
863 | ||
864 | #define default_ISA_trigger(idx) (0) | |
865 | #define default_ISA_polarity(idx) (0) | |
866 | ||
1da177e4 LT |
867 | /* EISA interrupts are always polarity zero and can be edge or level |
868 | * trigger depending on the ELCR value. If an interrupt is listed as | |
869 | * EISA conforming in the MP table, that means its trigger type must | |
870 | * be read in from the ELCR */ | |
871 | ||
2fddb6e2 | 872 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq)) |
6728801d | 873 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
874 | |
875 | /* PCI interrupts are always polarity one level triggered, | |
876 | * when listed as conforming in the MP table. */ | |
877 | ||
878 | #define default_PCI_trigger(idx) (1) | |
879 | #define default_PCI_polarity(idx) (1) | |
880 | ||
881 | /* MCA interrupts are always polarity zero level triggered, | |
882 | * when listed as conforming in the MP table. */ | |
883 | ||
884 | #define default_MCA_trigger(idx) (1) | |
6728801d | 885 | #define default_MCA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 | 886 | |
61fd47e0 | 887 | static int MPBIOS_polarity(int idx) |
1da177e4 | 888 | { |
2fddb6e2 | 889 | int bus = mp_irqs[idx].mp_srcbus; |
1da177e4 LT |
890 | int polarity; |
891 | ||
892 | /* | |
893 | * Determine IRQ line polarity (high active or low active): | |
894 | */ | |
54168ed7 | 895 | switch (mp_irqs[idx].mp_irqflag & 3) |
36062448 | 896 | { |
54168ed7 IM |
897 | case 0: /* conforms, ie. bus-type dependent polarity */ |
898 | if (test_bit(bus, mp_bus_not_pci)) | |
899 | polarity = default_ISA_polarity(idx); | |
900 | else | |
901 | polarity = default_PCI_polarity(idx); | |
902 | break; | |
903 | case 1: /* high active */ | |
904 | { | |
905 | polarity = 0; | |
906 | break; | |
907 | } | |
908 | case 2: /* reserved */ | |
909 | { | |
910 | printk(KERN_WARNING "broken BIOS!!\n"); | |
911 | polarity = 1; | |
912 | break; | |
913 | } | |
914 | case 3: /* low active */ | |
915 | { | |
916 | polarity = 1; | |
917 | break; | |
918 | } | |
919 | default: /* invalid */ | |
920 | { | |
921 | printk(KERN_WARNING "broken BIOS!!\n"); | |
922 | polarity = 1; | |
923 | break; | |
924 | } | |
1da177e4 LT |
925 | } |
926 | return polarity; | |
927 | } | |
928 | ||
929 | static int MPBIOS_trigger(int idx) | |
930 | { | |
2fddb6e2 | 931 | int bus = mp_irqs[idx].mp_srcbus; |
1da177e4 LT |
932 | int trigger; |
933 | ||
934 | /* | |
935 | * Determine IRQ trigger mode (edge or level sensitive): | |
936 | */ | |
54168ed7 | 937 | switch ((mp_irqs[idx].mp_irqflag>>2) & 3) |
1da177e4 | 938 | { |
54168ed7 IM |
939 | case 0: /* conforms, ie. bus-type dependent */ |
940 | if (test_bit(bus, mp_bus_not_pci)) | |
941 | trigger = default_ISA_trigger(idx); | |
942 | else | |
943 | trigger = default_PCI_trigger(idx); | |
c0a282c2 | 944 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
54168ed7 IM |
945 | switch (mp_bus_id_to_type[bus]) { |
946 | case MP_BUS_ISA: /* ISA pin */ | |
947 | { | |
948 | /* set before the switch */ | |
949 | break; | |
950 | } | |
951 | case MP_BUS_EISA: /* EISA pin */ | |
952 | { | |
953 | trigger = default_EISA_trigger(idx); | |
954 | break; | |
955 | } | |
956 | case MP_BUS_PCI: /* PCI pin */ | |
957 | { | |
958 | /* set before the switch */ | |
959 | break; | |
960 | } | |
961 | case MP_BUS_MCA: /* MCA pin */ | |
962 | { | |
963 | trigger = default_MCA_trigger(idx); | |
964 | break; | |
965 | } | |
966 | default: | |
967 | { | |
968 | printk(KERN_WARNING "broken BIOS!!\n"); | |
969 | trigger = 1; | |
970 | break; | |
971 | } | |
972 | } | |
973 | #endif | |
1da177e4 | 974 | break; |
54168ed7 | 975 | case 1: /* edge */ |
1da177e4 | 976 | { |
54168ed7 | 977 | trigger = 0; |
1da177e4 LT |
978 | break; |
979 | } | |
54168ed7 | 980 | case 2: /* reserved */ |
1da177e4 | 981 | { |
54168ed7 IM |
982 | printk(KERN_WARNING "broken BIOS!!\n"); |
983 | trigger = 1; | |
1da177e4 LT |
984 | break; |
985 | } | |
54168ed7 | 986 | case 3: /* level */ |
1da177e4 | 987 | { |
54168ed7 | 988 | trigger = 1; |
1da177e4 LT |
989 | break; |
990 | } | |
54168ed7 | 991 | default: /* invalid */ |
1da177e4 LT |
992 | { |
993 | printk(KERN_WARNING "broken BIOS!!\n"); | |
54168ed7 | 994 | trigger = 0; |
1da177e4 LT |
995 | break; |
996 | } | |
997 | } | |
998 | return trigger; | |
999 | } | |
1000 | ||
1001 | static inline int irq_polarity(int idx) | |
1002 | { | |
1003 | return MPBIOS_polarity(idx); | |
1004 | } | |
1005 | ||
1006 | static inline int irq_trigger(int idx) | |
1007 | { | |
1008 | return MPBIOS_trigger(idx); | |
1009 | } | |
1010 | ||
efa2559f | 1011 | int (*ioapic_renumber_irq)(int ioapic, int irq); |
1da177e4 LT |
1012 | static int pin_2_irq(int idx, int apic, int pin) |
1013 | { | |
1014 | int irq, i; | |
2fddb6e2 | 1015 | int bus = mp_irqs[idx].mp_srcbus; |
1da177e4 LT |
1016 | |
1017 | /* | |
1018 | * Debugging check, we are in big trouble if this message pops up! | |
1019 | */ | |
2fddb6e2 | 1020 | if (mp_irqs[idx].mp_dstirq != pin) |
1da177e4 LT |
1021 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); |
1022 | ||
54168ed7 | 1023 | if (test_bit(bus, mp_bus_not_pci)) { |
2fddb6e2 | 1024 | irq = mp_irqs[idx].mp_srcbusirq; |
54168ed7 | 1025 | } else { |
643befed AS |
1026 | /* |
1027 | * PCI IRQs are mapped in order | |
1028 | */ | |
1029 | i = irq = 0; | |
1030 | while (i < apic) | |
1031 | irq += nr_ioapic_registers[i++]; | |
1032 | irq += pin; | |
d6c88a50 | 1033 | /* |
54168ed7 IM |
1034 | * For MPS mode, so far only needed by ES7000 platform |
1035 | */ | |
d6c88a50 TG |
1036 | if (ioapic_renumber_irq) |
1037 | irq = ioapic_renumber_irq(apic, irq); | |
1da177e4 LT |
1038 | } |
1039 | ||
54168ed7 | 1040 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1041 | /* |
1042 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
1043 | */ | |
1044 | if ((pin >= 16) && (pin <= 23)) { | |
1045 | if (pirq_entries[pin-16] != -1) { | |
1046 | if (!pirq_entries[pin-16]) { | |
1047 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1048 | "disabling PIRQ%d\n", pin-16); | |
1049 | } else { | |
1050 | irq = pirq_entries[pin-16]; | |
1051 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1052 | "using PIRQ%d -> IRQ %d\n", | |
1053 | pin-16, irq); | |
1054 | } | |
1055 | } | |
1056 | } | |
54168ed7 IM |
1057 | #endif |
1058 | ||
1da177e4 LT |
1059 | return irq; |
1060 | } | |
1061 | ||
497c9a19 YL |
1062 | void lock_vector_lock(void) |
1063 | { | |
1064 | /* Used to the online set of cpus does not change | |
1065 | * during assign_irq_vector. | |
1066 | */ | |
1067 | spin_lock(&vector_lock); | |
1068 | } | |
1da177e4 | 1069 | |
497c9a19 | 1070 | void unlock_vector_lock(void) |
1da177e4 | 1071 | { |
497c9a19 YL |
1072 | spin_unlock(&vector_lock); |
1073 | } | |
1da177e4 | 1074 | |
497c9a19 YL |
1075 | static int __assign_irq_vector(int irq, cpumask_t mask) |
1076 | { | |
047c8fdb YL |
1077 | /* |
1078 | * NOTE! The local APIC isn't very good at handling | |
1079 | * multiple interrupts at the same interrupt level. | |
1080 | * As the interrupt level is determined by taking the | |
1081 | * vector number and shifting that right by 4, we | |
1082 | * want to spread these out a bit so that they don't | |
1083 | * all fall in the same interrupt level. | |
1084 | * | |
1085 | * Also, we've got to be careful not to trash gate | |
1086 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
1087 | */ | |
54168ed7 IM |
1088 | static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0; |
1089 | unsigned int old_vector; | |
1090 | int cpu; | |
1091 | struct irq_cfg *cfg; | |
ace80ab7 | 1092 | |
54168ed7 | 1093 | cfg = irq_cfg(irq); |
8339f000 | 1094 | |
54168ed7 IM |
1095 | /* Only try and allocate irqs on cpus that are present */ |
1096 | cpus_and(mask, mask, cpu_online_map); | |
ace80ab7 | 1097 | |
54168ed7 IM |
1098 | if ((cfg->move_in_progress) || cfg->move_cleanup_count) |
1099 | return -EBUSY; | |
0a1ad60d | 1100 | |
54168ed7 IM |
1101 | old_vector = cfg->vector; |
1102 | if (old_vector) { | |
1103 | cpumask_t tmp; | |
1104 | cpus_and(tmp, cfg->domain, mask); | |
1105 | if (!cpus_empty(tmp)) | |
1106 | return 0; | |
1107 | } | |
497c9a19 | 1108 | |
54168ed7 IM |
1109 | for_each_cpu_mask_nr(cpu, mask) { |
1110 | cpumask_t domain, new_mask; | |
1111 | int new_cpu; | |
1112 | int vector, offset; | |
497c9a19 | 1113 | |
54168ed7 IM |
1114 | domain = vector_allocation_domain(cpu); |
1115 | cpus_and(new_mask, domain, cpu_online_map); | |
497c9a19 | 1116 | |
54168ed7 IM |
1117 | vector = current_vector; |
1118 | offset = current_offset; | |
497c9a19 | 1119 | next: |
54168ed7 IM |
1120 | vector += 8; |
1121 | if (vector >= first_system_vector) { | |
1122 | /* If we run out of vectors on large boxen, must share them. */ | |
1123 | offset = (offset + 1) % 8; | |
1124 | vector = FIRST_DEVICE_VECTOR + offset; | |
1125 | } | |
1126 | if (unlikely(current_vector == vector)) | |
1127 | continue; | |
047c8fdb | 1128 | #ifdef CONFIG_X86_64 |
54168ed7 IM |
1129 | if (vector == IA32_SYSCALL_VECTOR) |
1130 | goto next; | |
047c8fdb | 1131 | #else |
54168ed7 IM |
1132 | if (vector == SYSCALL_VECTOR) |
1133 | goto next; | |
047c8fdb | 1134 | #endif |
54168ed7 IM |
1135 | for_each_cpu_mask_nr(new_cpu, new_mask) |
1136 | if (per_cpu(vector_irq, new_cpu)[vector] != -1) | |
1137 | goto next; | |
1138 | /* Found one! */ | |
1139 | current_vector = vector; | |
1140 | current_offset = offset; | |
1141 | if (old_vector) { | |
1142 | cfg->move_in_progress = 1; | |
1143 | cfg->old_domain = cfg->domain; | |
7a959cff | 1144 | } |
54168ed7 IM |
1145 | for_each_cpu_mask_nr(new_cpu, new_mask) |
1146 | per_cpu(vector_irq, new_cpu)[vector] = irq; | |
1147 | cfg->vector = vector; | |
1148 | cfg->domain = domain; | |
1149 | return 0; | |
1150 | } | |
1151 | return -ENOSPC; | |
497c9a19 YL |
1152 | } |
1153 | ||
1154 | static int assign_irq_vector(int irq, cpumask_t mask) | |
1155 | { | |
1156 | int err; | |
ace80ab7 | 1157 | unsigned long flags; |
ace80ab7 EB |
1158 | |
1159 | spin_lock_irqsave(&vector_lock, flags); | |
497c9a19 | 1160 | err = __assign_irq_vector(irq, mask); |
26a3c49c | 1161 | spin_unlock_irqrestore(&vector_lock, flags); |
497c9a19 YL |
1162 | return err; |
1163 | } | |
1164 | ||
1165 | static void __clear_irq_vector(int irq) | |
1166 | { | |
1167 | struct irq_cfg *cfg; | |
1168 | cpumask_t mask; | |
1169 | int cpu, vector; | |
1170 | ||
1171 | cfg = irq_cfg(irq); | |
1172 | BUG_ON(!cfg->vector); | |
1173 | ||
1174 | vector = cfg->vector; | |
1175 | cpus_and(mask, cfg->domain, cpu_online_map); | |
1176 | for_each_cpu_mask_nr(cpu, mask) | |
1177 | per_cpu(vector_irq, cpu)[vector] = -1; | |
1178 | ||
1179 | cfg->vector = 0; | |
1180 | cpus_clear(cfg->domain); | |
0ca4b6b0 MW |
1181 | |
1182 | if (likely(!cfg->move_in_progress)) | |
1183 | return; | |
1184 | cpus_and(mask, cfg->old_domain, cpu_online_map); | |
1185 | for_each_cpu_mask_nr(cpu, mask) { | |
1186 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; | |
1187 | vector++) { | |
1188 | if (per_cpu(vector_irq, cpu)[vector] != irq) | |
1189 | continue; | |
1190 | per_cpu(vector_irq, cpu)[vector] = -1; | |
1191 | break; | |
1192 | } | |
1193 | } | |
1194 | cfg->move_in_progress = 0; | |
497c9a19 YL |
1195 | } |
1196 | ||
1197 | void __setup_vector_irq(int cpu) | |
1198 | { | |
1199 | /* Initialize vector_irq on a new cpu */ | |
1200 | /* This function must be called with vector_lock held */ | |
1201 | int irq, vector; | |
1202 | struct irq_cfg *cfg; | |
0b8f1efa | 1203 | struct irq_desc *desc; |
497c9a19 YL |
1204 | |
1205 | /* Mark the inuse vectors */ | |
0b8f1efa YL |
1206 | for_each_irq_desc(irq, desc) { |
1207 | if (!desc) | |
1208 | continue; | |
1209 | cfg = desc->chip_data; | |
497c9a19 YL |
1210 | if (!cpu_isset(cpu, cfg->domain)) |
1211 | continue; | |
1212 | vector = cfg->vector; | |
497c9a19 YL |
1213 | per_cpu(vector_irq, cpu)[vector] = irq; |
1214 | } | |
1215 | /* Mark the free vectors */ | |
1216 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
1217 | irq = per_cpu(vector_irq, cpu)[vector]; | |
1218 | if (irq < 0) | |
1219 | continue; | |
1220 | ||
1221 | cfg = irq_cfg(irq); | |
1222 | if (!cpu_isset(cpu, cfg->domain)) | |
1223 | per_cpu(vector_irq, cpu)[vector] = -1; | |
54168ed7 | 1224 | } |
1da177e4 | 1225 | } |
3fde6900 | 1226 | |
f5b9ed7a | 1227 | static struct irq_chip ioapic_chip; |
54168ed7 IM |
1228 | #ifdef CONFIG_INTR_REMAP |
1229 | static struct irq_chip ir_ioapic_chip; | |
1230 | #endif | |
1da177e4 | 1231 | |
54168ed7 IM |
1232 | #define IOAPIC_AUTO -1 |
1233 | #define IOAPIC_EDGE 0 | |
1234 | #define IOAPIC_LEVEL 1 | |
1da177e4 | 1235 | |
047c8fdb | 1236 | #ifdef CONFIG_X86_32 |
1d025192 YL |
1237 | static inline int IO_APIC_irq_trigger(int irq) |
1238 | { | |
d6c88a50 | 1239 | int apic, idx, pin; |
1d025192 | 1240 | |
d6c88a50 TG |
1241 | for (apic = 0; apic < nr_ioapics; apic++) { |
1242 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1243 | idx = find_irq_entry(apic, pin, mp_INT); | |
1244 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin))) | |
1245 | return irq_trigger(idx); | |
1246 | } | |
1247 | } | |
1248 | /* | |
54168ed7 IM |
1249 | * nonexistent IRQs are edge default |
1250 | */ | |
d6c88a50 | 1251 | return 0; |
1d025192 | 1252 | } |
047c8fdb YL |
1253 | #else |
1254 | static inline int IO_APIC_irq_trigger(int irq) | |
1255 | { | |
54168ed7 | 1256 | return 1; |
047c8fdb YL |
1257 | } |
1258 | #endif | |
1d025192 | 1259 | |
497c9a19 | 1260 | static void ioapic_register_intr(int irq, unsigned long trigger) |
1da177e4 | 1261 | { |
08678b08 YL |
1262 | struct irq_desc *desc; |
1263 | ||
ee32c973 | 1264 | desc = irq_to_desc(irq); |
199751d7 | 1265 | |
6ebcc00e | 1266 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
047c8fdb | 1267 | trigger == IOAPIC_LEVEL) |
08678b08 | 1268 | desc->status |= IRQ_LEVEL; |
047c8fdb YL |
1269 | else |
1270 | desc->status &= ~IRQ_LEVEL; | |
1271 | ||
54168ed7 IM |
1272 | #ifdef CONFIG_INTR_REMAP |
1273 | if (irq_remapped(irq)) { | |
1274 | desc->status |= IRQ_MOVE_PCNTXT; | |
1275 | if (trigger) | |
1276 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1277 | handle_fasteoi_irq, | |
1278 | "fasteoi"); | |
1279 | else | |
1280 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1281 | handle_edge_irq, "edge"); | |
1282 | return; | |
1283 | } | |
1284 | #endif | |
047c8fdb YL |
1285 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
1286 | trigger == IOAPIC_LEVEL) | |
a460e745 | 1287 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 IM |
1288 | handle_fasteoi_irq, |
1289 | "fasteoi"); | |
047c8fdb | 1290 | else |
a460e745 | 1291 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 | 1292 | handle_edge_irq, "edge"); |
1da177e4 LT |
1293 | } |
1294 | ||
497c9a19 YL |
1295 | static int setup_ioapic_entry(int apic, int irq, |
1296 | struct IO_APIC_route_entry *entry, | |
1297 | unsigned int destination, int trigger, | |
1298 | int polarity, int vector) | |
1da177e4 | 1299 | { |
497c9a19 YL |
1300 | /* |
1301 | * add it to the IO-APIC irq-routing table: | |
1302 | */ | |
1303 | memset(entry,0,sizeof(*entry)); | |
1304 | ||
54168ed7 IM |
1305 | #ifdef CONFIG_INTR_REMAP |
1306 | if (intr_remapping_enabled) { | |
1307 | struct intel_iommu *iommu = map_ioapic_to_ir(apic); | |
1308 | struct irte irte; | |
1309 | struct IR_IO_APIC_route_entry *ir_entry = | |
1310 | (struct IR_IO_APIC_route_entry *) entry; | |
1311 | int index; | |
1312 | ||
1313 | if (!iommu) | |
1314 | panic("No mapping iommu for ioapic %d\n", apic); | |
1315 | ||
1316 | index = alloc_irte(iommu, irq, 1); | |
1317 | if (index < 0) | |
1318 | panic("Failed to allocate IRTE for ioapic %d\n", apic); | |
1319 | ||
1320 | memset(&irte, 0, sizeof(irte)); | |
1321 | ||
1322 | irte.present = 1; | |
1323 | irte.dst_mode = INT_DEST_MODE; | |
1324 | irte.trigger_mode = trigger; | |
1325 | irte.dlvry_mode = INT_DELIVERY_MODE; | |
1326 | irte.vector = vector; | |
1327 | irte.dest_id = IRTE_DEST(destination); | |
1328 | ||
1329 | modify_irte(irq, &irte); | |
1330 | ||
1331 | ir_entry->index2 = (index >> 15) & 0x1; | |
1332 | ir_entry->zero = 0; | |
1333 | ir_entry->format = 1; | |
1334 | ir_entry->index = (index & 0x7fff); | |
1335 | } else | |
1336 | #endif | |
1337 | { | |
1338 | entry->delivery_mode = INT_DELIVERY_MODE; | |
1339 | entry->dest_mode = INT_DEST_MODE; | |
1340 | entry->dest = destination; | |
1341 | } | |
497c9a19 | 1342 | |
54168ed7 | 1343 | entry->mask = 0; /* enable IRQ */ |
497c9a19 YL |
1344 | entry->trigger = trigger; |
1345 | entry->polarity = polarity; | |
1346 | entry->vector = vector; | |
1347 | ||
1348 | /* Mask level triggered irqs. | |
1349 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. | |
1350 | */ | |
1351 | if (trigger) | |
1352 | entry->mask = 1; | |
497c9a19 YL |
1353 | return 0; |
1354 | } | |
1355 | ||
1356 | static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq, | |
54168ed7 | 1357 | int trigger, int polarity) |
497c9a19 YL |
1358 | { |
1359 | struct irq_cfg *cfg; | |
1da177e4 | 1360 | struct IO_APIC_route_entry entry; |
497c9a19 YL |
1361 | cpumask_t mask; |
1362 | ||
1363 | if (!IO_APIC_IRQ(irq)) | |
1364 | return; | |
1365 | ||
1366 | cfg = irq_cfg(irq); | |
1367 | ||
1368 | mask = TARGET_CPUS; | |
1369 | if (assign_irq_vector(irq, mask)) | |
1370 | return; | |
1371 | ||
1372 | cpus_and(mask, cfg->domain, mask); | |
1373 | ||
1374 | apic_printk(APIC_VERBOSE,KERN_DEBUG | |
1375 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " | |
1376 | "IRQ %d Mode:%i Active:%i)\n", | |
1377 | apic, mp_ioapics[apic].mp_apicid, pin, cfg->vector, | |
1378 | irq, trigger, polarity); | |
1379 | ||
1380 | ||
1381 | if (setup_ioapic_entry(mp_ioapics[apic].mp_apicid, irq, &entry, | |
1382 | cpu_mask_to_apicid(mask), trigger, polarity, | |
1383 | cfg->vector)) { | |
1384 | printk("Failed to setup ioapic entry for ioapic %d, pin %d\n", | |
1385 | mp_ioapics[apic].mp_apicid, pin); | |
1386 | __clear_irq_vector(irq); | |
1387 | return; | |
1388 | } | |
1389 | ||
1390 | ioapic_register_intr(irq, trigger); | |
1391 | if (irq < 16) | |
1392 | disable_8259A_irq(irq); | |
1393 | ||
1394 | ioapic_write_entry(apic, pin, entry); | |
1395 | } | |
1396 | ||
1397 | static void __init setup_IO_APIC_irqs(void) | |
1398 | { | |
3c2cbd24 CG |
1399 | int apic, pin, idx, irq; |
1400 | int notcon = 0; | |
0b8f1efa YL |
1401 | struct irq_desc *desc; |
1402 | int cpu = boot_cpu_id; | |
1da177e4 LT |
1403 | |
1404 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1405 | ||
1406 | for (apic = 0; apic < nr_ioapics; apic++) { | |
3c2cbd24 | 1407 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
20d225b9 | 1408 | |
3c2cbd24 CG |
1409 | idx = find_irq_entry(apic, pin, mp_INT); |
1410 | if (idx == -1) { | |
2a554fb1 | 1411 | if (!notcon) { |
3c2cbd24 | 1412 | notcon = 1; |
2a554fb1 CG |
1413 | apic_printk(APIC_VERBOSE, |
1414 | KERN_DEBUG " %d-%d", | |
1415 | mp_ioapics[apic].mp_apicid, | |
1416 | pin); | |
1417 | } else | |
1418 | apic_printk(APIC_VERBOSE, " %d-%d", | |
1419 | mp_ioapics[apic].mp_apicid, | |
1420 | pin); | |
3c2cbd24 CG |
1421 | continue; |
1422 | } | |
56ffa1a0 CG |
1423 | if (notcon) { |
1424 | apic_printk(APIC_VERBOSE, | |
1425 | " (apicid-pin) not connected\n"); | |
1426 | notcon = 0; | |
1427 | } | |
3c2cbd24 CG |
1428 | |
1429 | irq = pin_2_irq(idx, apic, pin); | |
54168ed7 | 1430 | #ifdef CONFIG_X86_32 |
3c2cbd24 CG |
1431 | if (multi_timer_check(apic, irq)) |
1432 | continue; | |
54168ed7 | 1433 | #endif |
0b8f1efa YL |
1434 | desc = irq_to_desc_alloc_cpu(irq, cpu); |
1435 | if (!desc) { | |
1436 | printk(KERN_INFO "can not get irq_desc for %d\n", irq); | |
1437 | continue; | |
1438 | } | |
1439 | add_pin_to_irq_cpu(irq, cpu, apic, pin); | |
36062448 | 1440 | |
3c2cbd24 CG |
1441 | setup_IO_APIC_irq(apic, pin, irq, |
1442 | irq_trigger(idx), irq_polarity(idx)); | |
1443 | } | |
1da177e4 LT |
1444 | } |
1445 | ||
3c2cbd24 CG |
1446 | if (notcon) |
1447 | apic_printk(APIC_VERBOSE, | |
2a554fb1 | 1448 | " (apicid-pin) not connected\n"); |
1da177e4 LT |
1449 | } |
1450 | ||
1451 | /* | |
f7633ce5 | 1452 | * Set up the timer pin, possibly with the 8259A-master behind. |
1da177e4 | 1453 | */ |
f7633ce5 MR |
1454 | static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin, |
1455 | int vector) | |
1da177e4 LT |
1456 | { |
1457 | struct IO_APIC_route_entry entry; | |
1da177e4 | 1458 | |
54168ed7 IM |
1459 | #ifdef CONFIG_INTR_REMAP |
1460 | if (intr_remapping_enabled) | |
1461 | return; | |
1462 | #endif | |
1463 | ||
36062448 | 1464 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
1465 | |
1466 | /* | |
1467 | * We use logical delivery to get the timer IRQ | |
1468 | * to the first CPU. | |
1469 | */ | |
1470 | entry.dest_mode = INT_DEST_MODE; | |
03be7505 | 1471 | entry.mask = 1; /* mask IRQ now */ |
d83e94ac | 1472 | entry.dest = cpu_mask_to_apicid(TARGET_CPUS); |
1da177e4 LT |
1473 | entry.delivery_mode = INT_DELIVERY_MODE; |
1474 | entry.polarity = 0; | |
1475 | entry.trigger = 0; | |
1476 | entry.vector = vector; | |
1477 | ||
1478 | /* | |
1479 | * The timer IRQ doesn't have to know that behind the | |
f7633ce5 | 1480 | * scene we may have a 8259A-master in AEOI mode ... |
1da177e4 | 1481 | */ |
54168ed7 | 1482 | set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge"); |
1da177e4 LT |
1483 | |
1484 | /* | |
1485 | * Add it to the IO-APIC irq-routing table: | |
1486 | */ | |
cf4c6a2f | 1487 | ioapic_write_entry(apic, pin, entry); |
1da177e4 LT |
1488 | } |
1489 | ||
32f71aff MR |
1490 | |
1491 | __apicdebuginit(void) print_IO_APIC(void) | |
1da177e4 LT |
1492 | { |
1493 | int apic, i; | |
1494 | union IO_APIC_reg_00 reg_00; | |
1495 | union IO_APIC_reg_01 reg_01; | |
1496 | union IO_APIC_reg_02 reg_02; | |
1497 | union IO_APIC_reg_03 reg_03; | |
1498 | unsigned long flags; | |
0f978f45 | 1499 | struct irq_cfg *cfg; |
0b8f1efa | 1500 | struct irq_desc *desc; |
8f09cd20 | 1501 | unsigned int irq; |
1da177e4 LT |
1502 | |
1503 | if (apic_verbosity == APIC_QUIET) | |
1504 | return; | |
1505 | ||
36062448 | 1506 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); |
1da177e4 LT |
1507 | for (i = 0; i < nr_ioapics; i++) |
1508 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", | |
ec2cd0a2 | 1509 | mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]); |
1da177e4 LT |
1510 | |
1511 | /* | |
1512 | * We are a bit conservative about what we expect. We have to | |
1513 | * know about every hardware change ASAP. | |
1514 | */ | |
1515 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1516 | ||
1517 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1518 | ||
1519 | spin_lock_irqsave(&ioapic_lock, flags); | |
1520 | reg_00.raw = io_apic_read(apic, 0); | |
1521 | reg_01.raw = io_apic_read(apic, 1); | |
1522 | if (reg_01.bits.version >= 0x10) | |
1523 | reg_02.raw = io_apic_read(apic, 2); | |
d6c88a50 TG |
1524 | if (reg_01.bits.version >= 0x20) |
1525 | reg_03.raw = io_apic_read(apic, 3); | |
1da177e4 LT |
1526 | spin_unlock_irqrestore(&ioapic_lock, flags); |
1527 | ||
54168ed7 | 1528 | printk("\n"); |
ec2cd0a2 | 1529 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
1530 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1531 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1532 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1533 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 | 1534 | |
54168ed7 | 1535 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); |
1da177e4 | 1536 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); |
1da177e4 LT |
1537 | |
1538 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
1539 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); | |
1da177e4 LT |
1540 | |
1541 | /* | |
1542 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1543 | * but the value of reg_02 is read as the previous read register | |
1544 | * value, so ignore it if reg_02 == reg_01. | |
1545 | */ | |
1546 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1547 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1548 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1549 | } |
1550 | ||
1551 | /* | |
1552 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1553 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1554 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1555 | */ | |
1556 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1557 | reg_03.raw != reg_01.raw) { | |
1558 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1559 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1560 | } |
1561 | ||
1562 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1563 | ||
d83e94ac YL |
1564 | printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol" |
1565 | " Stat Dmod Deli Vect: \n"); | |
1da177e4 LT |
1566 | |
1567 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
1568 | struct IO_APIC_route_entry entry; | |
1569 | ||
cf4c6a2f | 1570 | entry = ioapic_read_entry(apic, i); |
1da177e4 | 1571 | |
54168ed7 IM |
1572 | printk(KERN_DEBUG " %02x %03X ", |
1573 | i, | |
1574 | entry.dest | |
1575 | ); | |
1da177e4 LT |
1576 | |
1577 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", | |
1578 | entry.mask, | |
1579 | entry.trigger, | |
1580 | entry.irr, | |
1581 | entry.polarity, | |
1582 | entry.delivery_status, | |
1583 | entry.dest_mode, | |
1584 | entry.delivery_mode, | |
1585 | entry.vector | |
1586 | ); | |
1587 | } | |
1588 | } | |
1da177e4 | 1589 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
0b8f1efa YL |
1590 | for_each_irq_desc(irq, desc) { |
1591 | struct irq_pin_list *entry; | |
1592 | ||
1593 | if (!desc) | |
1594 | continue; | |
1595 | cfg = desc->chip_data; | |
1596 | entry = cfg->irq_2_pin; | |
0f978f45 | 1597 | if (!entry) |
1da177e4 | 1598 | continue; |
8f09cd20 | 1599 | printk(KERN_DEBUG "IRQ%d ", irq); |
1da177e4 LT |
1600 | for (;;) { |
1601 | printk("-> %d:%d", entry->apic, entry->pin); | |
1602 | if (!entry->next) | |
1603 | break; | |
0f978f45 | 1604 | entry = entry->next; |
1da177e4 LT |
1605 | } |
1606 | printk("\n"); | |
1607 | } | |
1608 | ||
1609 | printk(KERN_INFO ".................................... done.\n"); | |
1610 | ||
1611 | return; | |
1612 | } | |
1613 | ||
32f71aff | 1614 | __apicdebuginit(void) print_APIC_bitfield(int base) |
1da177e4 LT |
1615 | { |
1616 | unsigned int v; | |
1617 | int i, j; | |
1618 | ||
1619 | if (apic_verbosity == APIC_QUIET) | |
1620 | return; | |
1621 | ||
1622 | printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG); | |
1623 | for (i = 0; i < 8; i++) { | |
1624 | v = apic_read(base + i*0x10); | |
1625 | for (j = 0; j < 32; j++) { | |
1626 | if (v & (1<<j)) | |
1627 | printk("1"); | |
1628 | else | |
1629 | printk("0"); | |
1630 | } | |
1631 | printk("\n"); | |
1632 | } | |
1633 | } | |
1634 | ||
32f71aff | 1635 | __apicdebuginit(void) print_local_APIC(void *dummy) |
1da177e4 LT |
1636 | { |
1637 | unsigned int v, ver, maxlvt; | |
7ab6af7a | 1638 | u64 icr; |
1da177e4 LT |
1639 | |
1640 | if (apic_verbosity == APIC_QUIET) | |
1641 | return; | |
1642 | ||
1643 | printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", | |
1644 | smp_processor_id(), hard_smp_processor_id()); | |
66823114 | 1645 | v = apic_read(APIC_ID); |
54168ed7 | 1646 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
1da177e4 LT |
1647 | v = apic_read(APIC_LVR); |
1648 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1649 | ver = GET_APIC_VERSION(v); | |
e05d723f | 1650 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1651 | |
1652 | v = apic_read(APIC_TASKPRI); | |
1653 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1654 | ||
54168ed7 | 1655 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
a11b5abe YL |
1656 | if (!APIC_XAPIC(ver)) { |
1657 | v = apic_read(APIC_ARBPRI); | |
1658 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1659 | v & APIC_ARBPRI_MASK); | |
1660 | } | |
1da177e4 LT |
1661 | v = apic_read(APIC_PROCPRI); |
1662 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1663 | } | |
1664 | ||
a11b5abe YL |
1665 | /* |
1666 | * Remote read supported only in the 82489DX and local APIC for | |
1667 | * Pentium processors. | |
1668 | */ | |
1669 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
1670 | v = apic_read(APIC_RRR); | |
1671 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1672 | } | |
1673 | ||
1da177e4 LT |
1674 | v = apic_read(APIC_LDR); |
1675 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
a11b5abe YL |
1676 | if (!x2apic_enabled()) { |
1677 | v = apic_read(APIC_DFR); | |
1678 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1679 | } | |
1da177e4 LT |
1680 | v = apic_read(APIC_SPIV); |
1681 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1682 | ||
1683 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
1684 | print_APIC_bitfield(APIC_ISR); | |
1685 | printk(KERN_DEBUG "... APIC TMR field:\n"); | |
1686 | print_APIC_bitfield(APIC_TMR); | |
1687 | printk(KERN_DEBUG "... APIC IRR field:\n"); | |
1688 | print_APIC_bitfield(APIC_IRR); | |
1689 | ||
54168ed7 IM |
1690 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
1691 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1da177e4 | 1692 | apic_write(APIC_ESR, 0); |
54168ed7 | 1693 | |
1da177e4 LT |
1694 | v = apic_read(APIC_ESR); |
1695 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1696 | } | |
1697 | ||
7ab6af7a | 1698 | icr = apic_icr_read(); |
0c425cec IM |
1699 | printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr); |
1700 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
1da177e4 LT |
1701 | |
1702 | v = apic_read(APIC_LVTT); | |
1703 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1704 | ||
1705 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1706 | v = apic_read(APIC_LVTPC); | |
1707 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1708 | } | |
1709 | v = apic_read(APIC_LVT0); | |
1710 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1711 | v = apic_read(APIC_LVT1); | |
1712 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1713 | ||
1714 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1715 | v = apic_read(APIC_LVTERR); | |
1716 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1717 | } | |
1718 | ||
1719 | v = apic_read(APIC_TMICT); | |
1720 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1721 | v = apic_read(APIC_TMCCT); | |
1722 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1723 | v = apic_read(APIC_TDCR); | |
1724 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
1725 | printk("\n"); | |
1726 | } | |
1727 | ||
32f71aff | 1728 | __apicdebuginit(void) print_all_local_APICs(void) |
1da177e4 | 1729 | { |
ffd5aae7 YL |
1730 | int cpu; |
1731 | ||
1732 | preempt_disable(); | |
1733 | for_each_online_cpu(cpu) | |
1734 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); | |
1735 | preempt_enable(); | |
1da177e4 LT |
1736 | } |
1737 | ||
32f71aff | 1738 | __apicdebuginit(void) print_PIC(void) |
1da177e4 | 1739 | { |
1da177e4 LT |
1740 | unsigned int v; |
1741 | unsigned long flags; | |
1742 | ||
1743 | if (apic_verbosity == APIC_QUIET) | |
1744 | return; | |
1745 | ||
1746 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1747 | ||
1748 | spin_lock_irqsave(&i8259A_lock, flags); | |
1749 | ||
1750 | v = inb(0xa1) << 8 | inb(0x21); | |
1751 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1752 | ||
1753 | v = inb(0xa0) << 8 | inb(0x20); | |
1754 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1755 | ||
54168ed7 IM |
1756 | outb(0x0b,0xa0); |
1757 | outb(0x0b,0x20); | |
1da177e4 | 1758 | v = inb(0xa0) << 8 | inb(0x20); |
54168ed7 IM |
1759 | outb(0x0a,0xa0); |
1760 | outb(0x0a,0x20); | |
1da177e4 LT |
1761 | |
1762 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
1763 | ||
1764 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1765 | ||
1766 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1767 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1768 | } | |
1769 | ||
32f71aff MR |
1770 | __apicdebuginit(int) print_all_ICs(void) |
1771 | { | |
1772 | print_PIC(); | |
1773 | print_all_local_APICs(); | |
1774 | print_IO_APIC(); | |
1775 | ||
1776 | return 0; | |
1777 | } | |
1778 | ||
1779 | fs_initcall(print_all_ICs); | |
1780 | ||
1da177e4 | 1781 | |
efa2559f YL |
1782 | /* Where if anywhere is the i8259 connect in external int mode */ |
1783 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
1784 | ||
54168ed7 | 1785 | void __init enable_IO_APIC(void) |
1da177e4 LT |
1786 | { |
1787 | union IO_APIC_reg_01 reg_01; | |
fcfd636a | 1788 | int i8259_apic, i8259_pin; |
54168ed7 | 1789 | int apic; |
1da177e4 LT |
1790 | unsigned long flags; |
1791 | ||
54168ed7 IM |
1792 | #ifdef CONFIG_X86_32 |
1793 | int i; | |
1da177e4 LT |
1794 | if (!pirqs_enabled) |
1795 | for (i = 0; i < MAX_PIRQS; i++) | |
1796 | pirq_entries[i] = -1; | |
54168ed7 | 1797 | #endif |
1da177e4 LT |
1798 | |
1799 | /* | |
1800 | * The number of IO-APIC IRQ registers (== #pins): | |
1801 | */ | |
fcfd636a | 1802 | for (apic = 0; apic < nr_ioapics; apic++) { |
1da177e4 | 1803 | spin_lock_irqsave(&ioapic_lock, flags); |
fcfd636a | 1804 | reg_01.raw = io_apic_read(apic, 1); |
1da177e4 | 1805 | spin_unlock_irqrestore(&ioapic_lock, flags); |
fcfd636a EB |
1806 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; |
1807 | } | |
54168ed7 | 1808 | for(apic = 0; apic < nr_ioapics; apic++) { |
fcfd636a EB |
1809 | int pin; |
1810 | /* See if any of the pins is in ExtINT mode */ | |
1008fddc | 1811 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
fcfd636a | 1812 | struct IO_APIC_route_entry entry; |
cf4c6a2f | 1813 | entry = ioapic_read_entry(apic, pin); |
fcfd636a | 1814 | |
fcfd636a EB |
1815 | /* If the interrupt line is enabled and in ExtInt mode |
1816 | * I have found the pin where the i8259 is connected. | |
1817 | */ | |
1818 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1819 | ioapic_i8259.apic = apic; | |
1820 | ioapic_i8259.pin = pin; | |
1821 | goto found_i8259; | |
1822 | } | |
1823 | } | |
1824 | } | |
1825 | found_i8259: | |
1826 | /* Look to see what if the MP table has reported the ExtINT */ | |
1827 | /* If we could not find the appropriate pin by looking at the ioapic | |
1828 | * the i8259 probably is not connected the ioapic but give the | |
1829 | * mptable a chance anyway. | |
1830 | */ | |
1831 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1832 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1833 | /* Trust the MP table if nothing is setup in the hardware */ | |
1834 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1835 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1836 | ioapic_i8259.pin = i8259_pin; | |
1837 | ioapic_i8259.apic = i8259_apic; | |
1838 | } | |
1839 | /* Complain if the MP table and the hardware disagree */ | |
1840 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1841 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1842 | { | |
1843 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1844 | } |
1845 | ||
1846 | /* | |
1847 | * Do not trust the IO-APIC being empty at bootup | |
1848 | */ | |
1849 | clear_IO_APIC(); | |
1850 | } | |
1851 | ||
1852 | /* | |
1853 | * Not an __init, needed by the reboot code | |
1854 | */ | |
1855 | void disable_IO_APIC(void) | |
1856 | { | |
1857 | /* | |
1858 | * Clear the IO-APIC before rebooting: | |
1859 | */ | |
1860 | clear_IO_APIC(); | |
1861 | ||
650927ef | 1862 | /* |
0b968d23 | 1863 | * If the i8259 is routed through an IOAPIC |
650927ef | 1864 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 1865 | * so legacy interrupts can be delivered. |
650927ef | 1866 | */ |
fcfd636a | 1867 | if (ioapic_i8259.pin != -1) { |
650927ef | 1868 | struct IO_APIC_route_entry entry; |
650927ef EB |
1869 | |
1870 | memset(&entry, 0, sizeof(entry)); | |
1871 | entry.mask = 0; /* Enabled */ | |
1872 | entry.trigger = 0; /* Edge */ | |
1873 | entry.irr = 0; | |
1874 | entry.polarity = 0; /* High */ | |
1875 | entry.delivery_status = 0; | |
1876 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 1877 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 1878 | entry.vector = 0; |
54168ed7 | 1879 | entry.dest = read_apic_id(); |
650927ef EB |
1880 | |
1881 | /* | |
1882 | * Add it to the IO-APIC irq-routing table: | |
1883 | */ | |
cf4c6a2f | 1884 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 1885 | } |
54168ed7 | 1886 | |
fcfd636a | 1887 | disconnect_bsp_APIC(ioapic_i8259.pin != -1); |
1da177e4 LT |
1888 | } |
1889 | ||
54168ed7 | 1890 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1891 | /* |
1892 | * function to set the IO-APIC physical IDs based on the | |
1893 | * values stored in the MPC table. | |
1894 | * | |
1895 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
1896 | */ | |
1897 | ||
1da177e4 LT |
1898 | static void __init setup_ioapic_ids_from_mpc(void) |
1899 | { | |
1900 | union IO_APIC_reg_00 reg_00; | |
1901 | physid_mask_t phys_id_present_map; | |
1902 | int apic; | |
1903 | int i; | |
1904 | unsigned char old_id; | |
1905 | unsigned long flags; | |
1906 | ||
a4dbc34d | 1907 | if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids()) |
d49c4288 | 1908 | return; |
d49c4288 | 1909 | |
ca05fea6 NP |
1910 | /* |
1911 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
1912 | * no meaning without the serial APIC bus. | |
1913 | */ | |
7c5c1e42 SL |
1914 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
1915 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
ca05fea6 | 1916 | return; |
1da177e4 LT |
1917 | /* |
1918 | * This is broken; anything with a real cpu count has to | |
1919 | * circumvent this idiocy regardless. | |
1920 | */ | |
1921 | phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map); | |
1922 | ||
1923 | /* | |
1924 | * Set the IOAPIC ID to the value stored in the MPC table. | |
1925 | */ | |
1926 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1927 | ||
1928 | /* Read the register 0 value */ | |
1929 | spin_lock_irqsave(&ioapic_lock, flags); | |
1930 | reg_00.raw = io_apic_read(apic, 0); | |
1931 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
36062448 | 1932 | |
ec2cd0a2 | 1933 | old_id = mp_ioapics[apic].mp_apicid; |
1da177e4 | 1934 | |
ec2cd0a2 | 1935 | if (mp_ioapics[apic].mp_apicid >= get_physical_broadcast()) { |
1da177e4 | 1936 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
ec2cd0a2 | 1937 | apic, mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
1938 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
1939 | reg_00.bits.ID); | |
ec2cd0a2 | 1940 | mp_ioapics[apic].mp_apicid = reg_00.bits.ID; |
1da177e4 LT |
1941 | } |
1942 | ||
1da177e4 LT |
1943 | /* |
1944 | * Sanity check, is the ID really free? Every APIC in a | |
1945 | * system must have a unique ID or we get lots of nice | |
1946 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
1947 | */ | |
1948 | if (check_apicid_used(phys_id_present_map, | |
ec2cd0a2 | 1949 | mp_ioapics[apic].mp_apicid)) { |
1da177e4 | 1950 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
ec2cd0a2 | 1951 | apic, mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
1952 | for (i = 0; i < get_physical_broadcast(); i++) |
1953 | if (!physid_isset(i, phys_id_present_map)) | |
1954 | break; | |
1955 | if (i >= get_physical_broadcast()) | |
1956 | panic("Max APIC ID exceeded!\n"); | |
1957 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
1958 | i); | |
1959 | physid_set(i, phys_id_present_map); | |
ec2cd0a2 | 1960 | mp_ioapics[apic].mp_apicid = i; |
1da177e4 LT |
1961 | } else { |
1962 | physid_mask_t tmp; | |
ec2cd0a2 | 1963 | tmp = apicid_to_cpu_present(mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
1964 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
1965 | "phys_id_present_map\n", | |
ec2cd0a2 | 1966 | mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
1967 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
1968 | } | |
1969 | ||
1970 | ||
1971 | /* | |
1972 | * We need to adjust the IRQ routing table | |
1973 | * if the ID changed. | |
1974 | */ | |
ec2cd0a2 | 1975 | if (old_id != mp_ioapics[apic].mp_apicid) |
1da177e4 | 1976 | for (i = 0; i < mp_irq_entries; i++) |
2fddb6e2 AS |
1977 | if (mp_irqs[i].mp_dstapic == old_id) |
1978 | mp_irqs[i].mp_dstapic | |
ec2cd0a2 | 1979 | = mp_ioapics[apic].mp_apicid; |
1da177e4 LT |
1980 | |
1981 | /* | |
1982 | * Read the right value from the MPC table and | |
1983 | * write it into the ID register. | |
36062448 | 1984 | */ |
1da177e4 LT |
1985 | apic_printk(APIC_VERBOSE, KERN_INFO |
1986 | "...changing IO-APIC physical APIC ID to %d ...", | |
ec2cd0a2 | 1987 | mp_ioapics[apic].mp_apicid); |
1da177e4 | 1988 | |
ec2cd0a2 | 1989 | reg_00.bits.ID = mp_ioapics[apic].mp_apicid; |
1da177e4 | 1990 | spin_lock_irqsave(&ioapic_lock, flags); |
a2d332fa YL |
1991 | io_apic_write(apic, 0, reg_00.raw); |
1992 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1da177e4 LT |
1993 | |
1994 | /* | |
1995 | * Sanity check | |
1996 | */ | |
1997 | spin_lock_irqsave(&ioapic_lock, flags); | |
1998 | reg_00.raw = io_apic_read(apic, 0); | |
1999 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
ec2cd0a2 | 2000 | if (reg_00.bits.ID != mp_ioapics[apic].mp_apicid) |
1da177e4 LT |
2001 | printk("could not set ID!\n"); |
2002 | else | |
2003 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
2004 | } | |
2005 | } | |
54168ed7 | 2006 | #endif |
1da177e4 | 2007 | |
7ce0bcfd | 2008 | int no_timer_check __initdata; |
8542b200 ZA |
2009 | |
2010 | static int __init notimercheck(char *s) | |
2011 | { | |
2012 | no_timer_check = 1; | |
2013 | return 1; | |
2014 | } | |
2015 | __setup("no_timer_check", notimercheck); | |
2016 | ||
1da177e4 LT |
2017 | /* |
2018 | * There is a nasty bug in some older SMP boards, their mptable lies | |
2019 | * about the timer IRQ. We do the following to work around the situation: | |
2020 | * | |
2021 | * - timer IRQ defaults to IO-APIC IRQ | |
2022 | * - if this function detects that timer IRQs are defunct, then we fall | |
2023 | * back to ISA timer IRQs | |
2024 | */ | |
f0a7a5c9 | 2025 | static int __init timer_irq_works(void) |
1da177e4 LT |
2026 | { |
2027 | unsigned long t1 = jiffies; | |
4aae0702 | 2028 | unsigned long flags; |
1da177e4 | 2029 | |
8542b200 ZA |
2030 | if (no_timer_check) |
2031 | return 1; | |
2032 | ||
4aae0702 | 2033 | local_save_flags(flags); |
1da177e4 LT |
2034 | local_irq_enable(); |
2035 | /* Let ten ticks pass... */ | |
2036 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 2037 | local_irq_restore(flags); |
1da177e4 LT |
2038 | |
2039 | /* | |
2040 | * Expect a few ticks at least, to be sure some possible | |
2041 | * glue logic does not lock up after one or two first | |
2042 | * ticks in a non-ExtINT mode. Also the local APIC | |
2043 | * might have cached one ExtINT interrupt. Finally, at | |
2044 | * least one tick may be lost due to delays. | |
2045 | */ | |
54168ed7 IM |
2046 | |
2047 | /* jiffies wrap? */ | |
1d16b53e | 2048 | if (time_after(jiffies, t1 + 4)) |
1da177e4 | 2049 | return 1; |
1da177e4 LT |
2050 | return 0; |
2051 | } | |
2052 | ||
2053 | /* | |
2054 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
2055 | * number of pending IRQ events unhandled. These cases are very rare, | |
2056 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
2057 | * better to do it this way as thus we do not have to be aware of | |
2058 | * 'pending' interrupts in the IRQ path, except at this point. | |
2059 | */ | |
2060 | /* | |
2061 | * Edge triggered needs to resend any interrupt | |
2062 | * that was delayed but this is now handled in the device | |
2063 | * independent code. | |
2064 | */ | |
2065 | ||
2066 | /* | |
2067 | * Starting up a edge-triggered IO-APIC interrupt is | |
2068 | * nasty - we need to make sure that we get the edge. | |
2069 | * If it is already asserted for some reason, we need | |
2070 | * return 1 to indicate that is was pending. | |
2071 | * | |
2072 | * This is not complete - we should be able to fake | |
2073 | * an edge even if it isn't on the 8259A... | |
2074 | */ | |
54168ed7 | 2075 | |
f5b9ed7a | 2076 | static unsigned int startup_ioapic_irq(unsigned int irq) |
1da177e4 LT |
2077 | { |
2078 | int was_pending = 0; | |
2079 | unsigned long flags; | |
0b8f1efa | 2080 | struct irq_cfg *cfg; |
1da177e4 LT |
2081 | |
2082 | spin_lock_irqsave(&ioapic_lock, flags); | |
2083 | if (irq < 16) { | |
2084 | disable_8259A_irq(irq); | |
2085 | if (i8259A_irq_pending(irq)) | |
2086 | was_pending = 1; | |
2087 | } | |
0b8f1efa | 2088 | cfg = irq_cfg(irq); |
1da177e4 LT |
2089 | __unmask_IO_APIC_irq(irq); |
2090 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2091 | ||
2092 | return was_pending; | |
2093 | } | |
2094 | ||
54168ed7 | 2095 | #ifdef CONFIG_X86_64 |
ace80ab7 | 2096 | static int ioapic_retrigger_irq(unsigned int irq) |
1da177e4 | 2097 | { |
54168ed7 IM |
2098 | |
2099 | struct irq_cfg *cfg = irq_cfg(irq); | |
2100 | unsigned long flags; | |
2101 | ||
2102 | spin_lock_irqsave(&vector_lock, flags); | |
2103 | send_IPI_mask(cpumask_of_cpu(first_cpu(cfg->domain)), cfg->vector); | |
2104 | spin_unlock_irqrestore(&vector_lock, flags); | |
c0ad90a3 IM |
2105 | |
2106 | return 1; | |
2107 | } | |
54168ed7 IM |
2108 | #else |
2109 | static int ioapic_retrigger_irq(unsigned int irq) | |
497c9a19 | 2110 | { |
d6c88a50 | 2111 | send_IPI_self(irq_cfg(irq)->vector); |
497c9a19 | 2112 | |
d6c88a50 | 2113 | return 1; |
54168ed7 IM |
2114 | } |
2115 | #endif | |
497c9a19 | 2116 | |
54168ed7 IM |
2117 | /* |
2118 | * Level and edge triggered IO-APIC interrupts need different handling, | |
2119 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be | |
2120 | * handled with the level-triggered descriptor, but that one has slightly | |
2121 | * more overhead. Level-triggered interrupts cannot be handled with the | |
2122 | * edge-triggered handler, without risking IRQ storms and other ugly | |
2123 | * races. | |
2124 | */ | |
497c9a19 | 2125 | |
54168ed7 | 2126 | #ifdef CONFIG_SMP |
497c9a19 | 2127 | |
54168ed7 IM |
2128 | #ifdef CONFIG_INTR_REMAP |
2129 | static void ir_irq_migration(struct work_struct *work); | |
497c9a19 | 2130 | |
54168ed7 | 2131 | static DECLARE_DELAYED_WORK(ir_migration_work, ir_irq_migration); |
497c9a19 | 2132 | |
54168ed7 IM |
2133 | /* |
2134 | * Migrate the IO-APIC irq in the presence of intr-remapping. | |
2135 | * | |
2136 | * For edge triggered, irq migration is a simple atomic update(of vector | |
2137 | * and cpu destination) of IRTE and flush the hardware cache. | |
2138 | * | |
2139 | * For level triggered, we need to modify the io-apic RTE aswell with the update | |
2140 | * vector information, along with modifying IRTE with vector and destination. | |
2141 | * So irq migration for level triggered is little bit more complex compared to | |
2142 | * edge triggered migration. But the good news is, we use the same algorithm | |
2143 | * for level triggered migration as we have today, only difference being, | |
2144 | * we now initiate the irq migration from process context instead of the | |
2145 | * interrupt context. | |
2146 | * | |
2147 | * In future, when we do a directed EOI (combined with cpu EOI broadcast | |
2148 | * suppression) to the IO-APIC, level triggered irq migration will also be | |
2149 | * as simple as edge triggered migration and we can do the irq migration | |
2150 | * with a simple atomic update to IO-APIC RTE. | |
2151 | */ | |
2152 | static void migrate_ioapic_irq(int irq, cpumask_t mask) | |
497c9a19 | 2153 | { |
54168ed7 IM |
2154 | struct irq_cfg *cfg; |
2155 | struct irq_desc *desc; | |
2156 | cpumask_t tmp, cleanup_mask; | |
2157 | struct irte irte; | |
2158 | int modify_ioapic_rte; | |
2159 | unsigned int dest; | |
2160 | unsigned long flags; | |
497c9a19 | 2161 | |
54168ed7 IM |
2162 | cpus_and(tmp, mask, cpu_online_map); |
2163 | if (cpus_empty(tmp)) | |
497c9a19 YL |
2164 | return; |
2165 | ||
54168ed7 IM |
2166 | if (get_irte(irq, &irte)) |
2167 | return; | |
497c9a19 | 2168 | |
54168ed7 IM |
2169 | if (assign_irq_vector(irq, mask)) |
2170 | return; | |
2171 | ||
2172 | cfg = irq_cfg(irq); | |
2173 | cpus_and(tmp, cfg->domain, mask); | |
2174 | dest = cpu_mask_to_apicid(tmp); | |
2175 | ||
2176 | desc = irq_to_desc(irq); | |
2177 | modify_ioapic_rte = desc->status & IRQ_LEVEL; | |
2178 | if (modify_ioapic_rte) { | |
2179 | spin_lock_irqsave(&ioapic_lock, flags); | |
2180 | __target_IO_APIC_irq(irq, dest, cfg->vector); | |
2181 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2182 | } | |
2183 | ||
2184 | irte.vector = cfg->vector; | |
2185 | irte.dest_id = IRTE_DEST(dest); | |
2186 | ||
2187 | /* | |
2188 | * Modified the IRTE and flushes the Interrupt entry cache. | |
2189 | */ | |
2190 | modify_irte(irq, &irte); | |
2191 | ||
2192 | if (cfg->move_in_progress) { | |
2193 | cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map); | |
2194 | cfg->move_cleanup_count = cpus_weight(cleanup_mask); | |
2195 | send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); | |
2196 | cfg->move_in_progress = 0; | |
2197 | } | |
2198 | ||
2199 | desc->affinity = mask; | |
2200 | } | |
2201 | ||
2202 | static int migrate_irq_remapped_level(int irq) | |
2203 | { | |
2204 | int ret = -1; | |
2205 | struct irq_desc *desc = irq_to_desc(irq); | |
2206 | ||
2207 | mask_IO_APIC_irq(irq); | |
2208 | ||
2209 | if (io_apic_level_ack_pending(irq)) { | |
2210 | /* | |
d6c88a50 | 2211 | * Interrupt in progress. Migrating irq now will change the |
54168ed7 IM |
2212 | * vector information in the IO-APIC RTE and that will confuse |
2213 | * the EOI broadcast performed by cpu. | |
2214 | * So, delay the irq migration to the next instance. | |
2215 | */ | |
2216 | schedule_delayed_work(&ir_migration_work, 1); | |
2217 | goto unmask; | |
2218 | } | |
2219 | ||
2220 | /* everthing is clear. we have right of way */ | |
2221 | migrate_ioapic_irq(irq, desc->pending_mask); | |
2222 | ||
2223 | ret = 0; | |
2224 | desc->status &= ~IRQ_MOVE_PENDING; | |
2225 | cpus_clear(desc->pending_mask); | |
2226 | ||
2227 | unmask: | |
2228 | unmask_IO_APIC_irq(irq); | |
2229 | return ret; | |
2230 | } | |
2231 | ||
2232 | static void ir_irq_migration(struct work_struct *work) | |
2233 | { | |
2234 | unsigned int irq; | |
2235 | struct irq_desc *desc; | |
2236 | ||
2237 | for_each_irq_desc(irq, desc) { | |
0b8f1efa YL |
2238 | if (!desc) |
2239 | continue; | |
2240 | ||
54168ed7 IM |
2241 | if (desc->status & IRQ_MOVE_PENDING) { |
2242 | unsigned long flags; | |
2243 | ||
2244 | spin_lock_irqsave(&desc->lock, flags); | |
2245 | if (!desc->chip->set_affinity || | |
2246 | !(desc->status & IRQ_MOVE_PENDING)) { | |
2247 | desc->status &= ~IRQ_MOVE_PENDING; | |
2248 | spin_unlock_irqrestore(&desc->lock, flags); | |
2249 | continue; | |
2250 | } | |
2251 | ||
2252 | desc->chip->set_affinity(irq, desc->pending_mask); | |
2253 | spin_unlock_irqrestore(&desc->lock, flags); | |
2254 | } | |
2255 | } | |
2256 | } | |
2257 | ||
2258 | /* | |
2259 | * Migrates the IRQ destination in the process context. | |
2260 | */ | |
2261 | static void set_ir_ioapic_affinity_irq(unsigned int irq, cpumask_t mask) | |
2262 | { | |
2263 | struct irq_desc *desc = irq_to_desc(irq); | |
2264 | ||
2265 | if (desc->status & IRQ_LEVEL) { | |
2266 | desc->status |= IRQ_MOVE_PENDING; | |
2267 | desc->pending_mask = mask; | |
2268 | migrate_irq_remapped_level(irq); | |
2269 | return; | |
2270 | } | |
2271 | ||
2272 | migrate_ioapic_irq(irq, mask); | |
2273 | } | |
2274 | #endif | |
2275 | ||
2276 | asmlinkage void smp_irq_move_cleanup_interrupt(void) | |
2277 | { | |
2278 | unsigned vector, me; | |
2279 | ack_APIC_irq(); | |
2280 | #ifdef CONFIG_X86_64 | |
2281 | exit_idle(); | |
2282 | #endif | |
2283 | irq_enter(); | |
2284 | ||
2285 | me = smp_processor_id(); | |
2286 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
2287 | unsigned int irq; | |
2288 | struct irq_desc *desc; | |
2289 | struct irq_cfg *cfg; | |
2290 | irq = __get_cpu_var(vector_irq)[vector]; | |
2291 | ||
0b8f1efa YL |
2292 | if (irq == -1) |
2293 | continue; | |
2294 | ||
54168ed7 IM |
2295 | desc = irq_to_desc(irq); |
2296 | if (!desc) | |
2297 | continue; | |
2298 | ||
2299 | cfg = irq_cfg(irq); | |
2300 | spin_lock(&desc->lock); | |
2301 | if (!cfg->move_cleanup_count) | |
2302 | goto unlock; | |
2303 | ||
2304 | if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) | |
2305 | goto unlock; | |
2306 | ||
2307 | __get_cpu_var(vector_irq)[vector] = -1; | |
2308 | cfg->move_cleanup_count--; | |
2309 | unlock: | |
2310 | spin_unlock(&desc->lock); | |
2311 | } | |
2312 | ||
2313 | irq_exit(); | |
2314 | } | |
2315 | ||
2316 | static void irq_complete_move(unsigned int irq) | |
2317 | { | |
2318 | struct irq_cfg *cfg = irq_cfg(irq); | |
2319 | unsigned vector, me; | |
2320 | ||
2321 | if (likely(!cfg->move_in_progress)) | |
2322 | return; | |
2323 | ||
2324 | vector = ~get_irq_regs()->orig_ax; | |
2325 | me = smp_processor_id(); | |
2326 | if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) { | |
2327 | cpumask_t cleanup_mask; | |
2328 | ||
2329 | cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map); | |
2330 | cfg->move_cleanup_count = cpus_weight(cleanup_mask); | |
2331 | send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); | |
497c9a19 YL |
2332 | cfg->move_in_progress = 0; |
2333 | } | |
2334 | } | |
2335 | #else | |
2336 | static inline void irq_complete_move(unsigned int irq) {} | |
2337 | #endif | |
54168ed7 IM |
2338 | #ifdef CONFIG_INTR_REMAP |
2339 | static void ack_x2apic_level(unsigned int irq) | |
2340 | { | |
2341 | ack_x2APIC_irq(); | |
2342 | } | |
2343 | ||
2344 | static void ack_x2apic_edge(unsigned int irq) | |
2345 | { | |
2346 | ack_x2APIC_irq(); | |
2347 | } | |
2348 | #endif | |
497c9a19 | 2349 | |
1d025192 YL |
2350 | static void ack_apic_edge(unsigned int irq) |
2351 | { | |
2352 | irq_complete_move(irq); | |
2353 | move_native_irq(irq); | |
2354 | ack_APIC_irq(); | |
2355 | } | |
2356 | ||
3eb2cce8 | 2357 | atomic_t irq_mis_count; |
3eb2cce8 | 2358 | |
047c8fdb YL |
2359 | static void ack_apic_level(unsigned int irq) |
2360 | { | |
3eb2cce8 YL |
2361 | #ifdef CONFIG_X86_32 |
2362 | unsigned long v; | |
2363 | int i; | |
2364 | #endif | |
54168ed7 | 2365 | int do_unmask_irq = 0; |
047c8fdb | 2366 | |
54168ed7 | 2367 | irq_complete_move(irq); |
047c8fdb | 2368 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
54168ed7 IM |
2369 | /* If we are moving the irq we need to mask it */ |
2370 | if (unlikely(irq_to_desc(irq)->status & IRQ_MOVE_PENDING)) { | |
2371 | do_unmask_irq = 1; | |
2372 | mask_IO_APIC_irq(irq); | |
2373 | } | |
047c8fdb YL |
2374 | #endif |
2375 | ||
3eb2cce8 YL |
2376 | #ifdef CONFIG_X86_32 |
2377 | /* | |
2378 | * It appears there is an erratum which affects at least version 0x11 | |
2379 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
2380 | * chipsets). Under certain conditions a level-triggered interrupt is | |
2381 | * erroneously delivered as edge-triggered one but the respective IRR | |
2382 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
2383 | * message but it will never arrive and further interrupts are blocked | |
2384 | * from the source. The exact reason is so far unknown, but the | |
2385 | * phenomenon was observed when two consecutive interrupt requests | |
2386 | * from a given source get delivered to the same CPU and the source is | |
2387 | * temporarily disabled in between. | |
2388 | * | |
2389 | * A workaround is to simulate an EOI message manually. We achieve it | |
2390 | * by setting the trigger mode to edge and then to level when the edge | |
2391 | * trigger mode gets detected in the TMR of a local APIC for a | |
2392 | * level-triggered interrupt. We mask the source for the time of the | |
2393 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
2394 | * The idea is from Manfred Spraul. --macro | |
2395 | */ | |
2396 | i = irq_cfg(irq)->vector; | |
2397 | ||
2398 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); | |
2399 | #endif | |
2400 | ||
54168ed7 IM |
2401 | /* |
2402 | * We must acknowledge the irq before we move it or the acknowledge will | |
2403 | * not propagate properly. | |
2404 | */ | |
2405 | ack_APIC_irq(); | |
2406 | ||
2407 | /* Now we can move and renable the irq */ | |
2408 | if (unlikely(do_unmask_irq)) { | |
2409 | /* Only migrate the irq if the ack has been received. | |
2410 | * | |
2411 | * On rare occasions the broadcast level triggered ack gets | |
2412 | * delayed going to ioapics, and if we reprogram the | |
2413 | * vector while Remote IRR is still set the irq will never | |
2414 | * fire again. | |
2415 | * | |
2416 | * To prevent this scenario we read the Remote IRR bit | |
2417 | * of the ioapic. This has two effects. | |
2418 | * - On any sane system the read of the ioapic will | |
2419 | * flush writes (and acks) going to the ioapic from | |
2420 | * this cpu. | |
2421 | * - We get to see if the ACK has actually been delivered. | |
2422 | * | |
2423 | * Based on failed experiments of reprogramming the | |
2424 | * ioapic entry from outside of irq context starting | |
2425 | * with masking the ioapic entry and then polling until | |
2426 | * Remote IRR was clear before reprogramming the | |
2427 | * ioapic I don't trust the Remote IRR bit to be | |
2428 | * completey accurate. | |
2429 | * | |
2430 | * However there appears to be no other way to plug | |
2431 | * this race, so if the Remote IRR bit is not | |
2432 | * accurate and is causing problems then it is a hardware bug | |
2433 | * and you can go talk to the chipset vendor about it. | |
2434 | */ | |
2435 | if (!io_apic_level_ack_pending(irq)) | |
2436 | move_masked_irq(irq); | |
2437 | unmask_IO_APIC_irq(irq); | |
2438 | } | |
1d025192 | 2439 | |
3eb2cce8 | 2440 | #ifdef CONFIG_X86_32 |
1d025192 YL |
2441 | if (!(v & (1 << (i & 0x1f)))) { |
2442 | atomic_inc(&irq_mis_count); | |
2443 | spin_lock(&ioapic_lock); | |
2444 | __mask_and_edge_IO_APIC_irq(irq); | |
2445 | __unmask_and_level_IO_APIC_irq(irq); | |
2446 | spin_unlock(&ioapic_lock); | |
2447 | } | |
047c8fdb | 2448 | #endif |
3eb2cce8 | 2449 | } |
1d025192 | 2450 | |
f5b9ed7a | 2451 | static struct irq_chip ioapic_chip __read_mostly = { |
d6c88a50 TG |
2452 | .name = "IO-APIC", |
2453 | .startup = startup_ioapic_irq, | |
2454 | .mask = mask_IO_APIC_irq, | |
2455 | .unmask = unmask_IO_APIC_irq, | |
2456 | .ack = ack_apic_edge, | |
2457 | .eoi = ack_apic_level, | |
54d5d424 | 2458 | #ifdef CONFIG_SMP |
d6c88a50 | 2459 | .set_affinity = set_ioapic_affinity_irq, |
54d5d424 | 2460 | #endif |
ace80ab7 | 2461 | .retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
2462 | }; |
2463 | ||
54168ed7 IM |
2464 | #ifdef CONFIG_INTR_REMAP |
2465 | static struct irq_chip ir_ioapic_chip __read_mostly = { | |
d6c88a50 TG |
2466 | .name = "IR-IO-APIC", |
2467 | .startup = startup_ioapic_irq, | |
2468 | .mask = mask_IO_APIC_irq, | |
2469 | .unmask = unmask_IO_APIC_irq, | |
2470 | .ack = ack_x2apic_edge, | |
2471 | .eoi = ack_x2apic_level, | |
54168ed7 | 2472 | #ifdef CONFIG_SMP |
d6c88a50 | 2473 | .set_affinity = set_ir_ioapic_affinity_irq, |
54168ed7 IM |
2474 | #endif |
2475 | .retrigger = ioapic_retrigger_irq, | |
2476 | }; | |
2477 | #endif | |
1da177e4 LT |
2478 | |
2479 | static inline void init_IO_APIC_traps(void) | |
2480 | { | |
2481 | int irq; | |
08678b08 | 2482 | struct irq_desc *desc; |
da51a821 | 2483 | struct irq_cfg *cfg; |
1da177e4 LT |
2484 | |
2485 | /* | |
2486 | * NOTE! The local APIC isn't very good at handling | |
2487 | * multiple interrupts at the same interrupt level. | |
2488 | * As the interrupt level is determined by taking the | |
2489 | * vector number and shifting that right by 4, we | |
2490 | * want to spread these out a bit so that they don't | |
2491 | * all fall in the same interrupt level. | |
2492 | * | |
2493 | * Also, we've got to be careful not to trash gate | |
2494 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
2495 | */ | |
0b8f1efa YL |
2496 | for_each_irq_desc(irq, desc) { |
2497 | if (!desc) | |
2498 | continue; | |
2499 | ||
2500 | cfg = desc->chip_data; | |
2501 | if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { | |
1da177e4 LT |
2502 | /* |
2503 | * Hmm.. We don't have an entry for this, | |
2504 | * so default to an old-fashioned 8259 | |
2505 | * interrupt if we can.. | |
2506 | */ | |
2507 | if (irq < 16) | |
2508 | make_8259A_irq(irq); | |
0b8f1efa | 2509 | else |
1da177e4 | 2510 | /* Strange. Oh, well.. */ |
08678b08 | 2511 | desc->chip = &no_irq_chip; |
1da177e4 LT |
2512 | } |
2513 | } | |
2514 | } | |
2515 | ||
f5b9ed7a IM |
2516 | /* |
2517 | * The local APIC irq-chip implementation: | |
2518 | */ | |
1da177e4 | 2519 | |
36062448 | 2520 | static void mask_lapic_irq(unsigned int irq) |
1da177e4 LT |
2521 | { |
2522 | unsigned long v; | |
2523 | ||
2524 | v = apic_read(APIC_LVT0); | |
593f4a78 | 2525 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
2526 | } |
2527 | ||
36062448 | 2528 | static void unmask_lapic_irq(unsigned int irq) |
1da177e4 | 2529 | { |
f5b9ed7a | 2530 | unsigned long v; |
1da177e4 | 2531 | |
f5b9ed7a | 2532 | v = apic_read(APIC_LVT0); |
593f4a78 | 2533 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
f5b9ed7a | 2534 | } |
1da177e4 | 2535 | |
54168ed7 | 2536 | static void ack_lapic_irq (unsigned int irq) |
1d025192 YL |
2537 | { |
2538 | ack_APIC_irq(); | |
2539 | } | |
2540 | ||
f5b9ed7a | 2541 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 2542 | .name = "local-APIC", |
f5b9ed7a IM |
2543 | .mask = mask_lapic_irq, |
2544 | .unmask = unmask_lapic_irq, | |
c88ac1df | 2545 | .ack = ack_lapic_irq, |
1da177e4 LT |
2546 | }; |
2547 | ||
497c9a19 | 2548 | static void lapic_register_intr(int irq) |
c88ac1df | 2549 | { |
08678b08 YL |
2550 | struct irq_desc *desc; |
2551 | ||
2552 | desc = irq_to_desc(irq); | |
2553 | desc->status &= ~IRQ_LEVEL; | |
c88ac1df MR |
2554 | set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
2555 | "edge"); | |
c88ac1df MR |
2556 | } |
2557 | ||
e9427101 | 2558 | static void __init setup_nmi(void) |
1da177e4 LT |
2559 | { |
2560 | /* | |
36062448 | 2561 | * Dirty trick to enable the NMI watchdog ... |
1da177e4 LT |
2562 | * We put the 8259A master into AEOI mode and |
2563 | * unmask on all local APICs LVT0 as NMI. | |
2564 | * | |
2565 | * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') | |
2566 | * is from Maciej W. Rozycki - so we do not have to EOI from | |
2567 | * the NMI handler or the timer interrupt. | |
36062448 | 2568 | */ |
1da177e4 LT |
2569 | apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ..."); |
2570 | ||
e9427101 | 2571 | enable_NMI_through_LVT0(); |
1da177e4 LT |
2572 | |
2573 | apic_printk(APIC_VERBOSE, " done.\n"); | |
2574 | } | |
2575 | ||
2576 | /* | |
2577 | * This looks a bit hackish but it's about the only one way of sending | |
2578 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2579 | * not support the ExtINT mode, unfortunately. We need to send these | |
2580 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2581 | * 8259A interrupt line asserted until INTA. --macro | |
2582 | */ | |
28acf285 | 2583 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2584 | { |
fcfd636a | 2585 | int apic, pin, i; |
1da177e4 LT |
2586 | struct IO_APIC_route_entry entry0, entry1; |
2587 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2588 | |
fcfd636a | 2589 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2590 | if (pin == -1) { |
2591 | WARN_ON_ONCE(1); | |
2592 | return; | |
2593 | } | |
fcfd636a | 2594 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2595 | if (apic == -1) { |
2596 | WARN_ON_ONCE(1); | |
1da177e4 | 2597 | return; |
956fb531 | 2598 | } |
1da177e4 | 2599 | |
cf4c6a2f | 2600 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2601 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2602 | |
2603 | memset(&entry1, 0, sizeof(entry1)); | |
2604 | ||
2605 | entry1.dest_mode = 0; /* physical delivery */ | |
2606 | entry1.mask = 0; /* unmask IRQ now */ | |
d83e94ac | 2607 | entry1.dest = hard_smp_processor_id(); |
1da177e4 LT |
2608 | entry1.delivery_mode = dest_ExtINT; |
2609 | entry1.polarity = entry0.polarity; | |
2610 | entry1.trigger = 0; | |
2611 | entry1.vector = 0; | |
2612 | ||
cf4c6a2f | 2613 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2614 | |
2615 | save_control = CMOS_READ(RTC_CONTROL); | |
2616 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2617 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2618 | RTC_FREQ_SELECT); | |
2619 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2620 | ||
2621 | i = 100; | |
2622 | while (i-- > 0) { | |
2623 | mdelay(10); | |
2624 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2625 | i -= 10; | |
2626 | } | |
2627 | ||
2628 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2629 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2630 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2631 | |
cf4c6a2f | 2632 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2633 | } |
2634 | ||
efa2559f | 2635 | static int disable_timer_pin_1 __initdata; |
047c8fdb | 2636 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
54168ed7 | 2637 | static int __init disable_timer_pin_setup(char *arg) |
efa2559f YL |
2638 | { |
2639 | disable_timer_pin_1 = 1; | |
2640 | return 0; | |
2641 | } | |
54168ed7 | 2642 | early_param("disable_timer_pin_1", disable_timer_pin_setup); |
efa2559f YL |
2643 | |
2644 | int timer_through_8259 __initdata; | |
2645 | ||
1da177e4 LT |
2646 | /* |
2647 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2648 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2649 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2650 | * fanatically on his truly buggy board. | |
54168ed7 IM |
2651 | * |
2652 | * FIXME: really need to revamp this for all platforms. | |
1da177e4 | 2653 | */ |
8542b200 | 2654 | static inline void __init check_timer(void) |
1da177e4 | 2655 | { |
497c9a19 | 2656 | struct irq_cfg *cfg = irq_cfg(0); |
fcfd636a | 2657 | int apic1, pin1, apic2, pin2; |
4aae0702 | 2658 | unsigned long flags; |
047c8fdb YL |
2659 | unsigned int ver; |
2660 | int no_pin1 = 0; | |
4aae0702 IM |
2661 | |
2662 | local_irq_save(flags); | |
d4d25dec | 2663 | |
d6c88a50 TG |
2664 | ver = apic_read(APIC_LVR); |
2665 | ver = GET_APIC_VERSION(ver); | |
6e908947 | 2666 | |
1da177e4 LT |
2667 | /* |
2668 | * get/set the timer IRQ vector: | |
2669 | */ | |
2670 | disable_8259A_irq(0); | |
497c9a19 | 2671 | assign_irq_vector(0, TARGET_CPUS); |
1da177e4 LT |
2672 | |
2673 | /* | |
d11d5794 MR |
2674 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2675 | * wire has to be disabled in the local APIC. Also | |
2676 | * timer interrupts need to be acknowledged manually in | |
2677 | * the 8259A for the i82489DX when using the NMI | |
2678 | * watchdog as that APIC treats NMIs as level-triggered. | |
2679 | * The AEOI mode will finish them in the 8259A | |
2680 | * automatically. | |
1da177e4 | 2681 | */ |
593f4a78 | 2682 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
1da177e4 | 2683 | init_8259A(1); |
54168ed7 | 2684 | #ifdef CONFIG_X86_32 |
d11d5794 | 2685 | timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver)); |
54168ed7 | 2686 | #endif |
1da177e4 | 2687 | |
fcfd636a EB |
2688 | pin1 = find_isa_irq_pin(0, mp_INT); |
2689 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2690 | pin2 = ioapic_i8259.pin; | |
2691 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2692 | |
49a66a0b MR |
2693 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
2694 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", | |
497c9a19 | 2695 | cfg->vector, apic1, pin1, apic2, pin2); |
1da177e4 | 2696 | |
691874fa MR |
2697 | /* |
2698 | * Some BIOS writers are clueless and report the ExtINTA | |
2699 | * I/O APIC input from the cascaded 8259A as the timer | |
2700 | * interrupt input. So just in case, if only one pin | |
2701 | * was found above, try it both directly and through the | |
2702 | * 8259A. | |
2703 | */ | |
2704 | if (pin1 == -1) { | |
54168ed7 IM |
2705 | #ifdef CONFIG_INTR_REMAP |
2706 | if (intr_remapping_enabled) | |
2707 | panic("BIOS bug: timer not connected to IO-APIC"); | |
2708 | #endif | |
691874fa MR |
2709 | pin1 = pin2; |
2710 | apic1 = apic2; | |
2711 | no_pin1 = 1; | |
2712 | } else if (pin2 == -1) { | |
2713 | pin2 = pin1; | |
2714 | apic2 = apic1; | |
2715 | } | |
2716 | ||
1da177e4 LT |
2717 | if (pin1 != -1) { |
2718 | /* | |
2719 | * Ok, does IRQ0 through the IOAPIC work? | |
2720 | */ | |
691874fa | 2721 | if (no_pin1) { |
0b8f1efa | 2722 | add_pin_to_irq_cpu(0, boot_cpu_id, apic1, pin1); |
497c9a19 | 2723 | setup_timer_IRQ0_pin(apic1, pin1, cfg->vector); |
691874fa | 2724 | } |
1da177e4 LT |
2725 | unmask_IO_APIC_irq(0); |
2726 | if (timer_irq_works()) { | |
2727 | if (nmi_watchdog == NMI_IO_APIC) { | |
1da177e4 LT |
2728 | setup_nmi(); |
2729 | enable_8259A_irq(0); | |
1da177e4 | 2730 | } |
66759a01 CE |
2731 | if (disable_timer_pin_1 > 0) |
2732 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 2733 | goto out; |
1da177e4 | 2734 | } |
54168ed7 IM |
2735 | #ifdef CONFIG_INTR_REMAP |
2736 | if (intr_remapping_enabled) | |
2737 | panic("timer doesn't work through Interrupt-remapped IO-APIC"); | |
2738 | #endif | |
fcfd636a | 2739 | clear_IO_APIC_pin(apic1, pin1); |
691874fa | 2740 | if (!no_pin1) |
49a66a0b MR |
2741 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
2742 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 2743 | |
49a66a0b MR |
2744 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
2745 | "(IRQ0) through the 8259A ...\n"); | |
2746 | apic_printk(APIC_QUIET, KERN_INFO | |
2747 | "..... (found apic %d pin %d) ...\n", apic2, pin2); | |
1da177e4 LT |
2748 | /* |
2749 | * legacy devices should be connected to IO APIC #0 | |
2750 | */ | |
0b8f1efa | 2751 | replace_pin_at_irq(0, boot_cpu_id, apic1, pin1, apic2, pin2); |
497c9a19 | 2752 | setup_timer_IRQ0_pin(apic2, pin2, cfg->vector); |
24742ece | 2753 | unmask_IO_APIC_irq(0); |
ecd29476 | 2754 | enable_8259A_irq(0); |
1da177e4 | 2755 | if (timer_irq_works()) { |
49a66a0b | 2756 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
35542c5e | 2757 | timer_through_8259 = 1; |
1da177e4 | 2758 | if (nmi_watchdog == NMI_IO_APIC) { |
60134ebe | 2759 | disable_8259A_irq(0); |
1da177e4 | 2760 | setup_nmi(); |
60134ebe | 2761 | enable_8259A_irq(0); |
1da177e4 | 2762 | } |
4aae0702 | 2763 | goto out; |
1da177e4 LT |
2764 | } |
2765 | /* | |
2766 | * Cleanup, just in case ... | |
2767 | */ | |
ecd29476 | 2768 | disable_8259A_irq(0); |
fcfd636a | 2769 | clear_IO_APIC_pin(apic2, pin2); |
49a66a0b | 2770 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
1da177e4 | 2771 | } |
1da177e4 LT |
2772 | |
2773 | if (nmi_watchdog == NMI_IO_APIC) { | |
49a66a0b MR |
2774 | apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work " |
2775 | "through the IO-APIC - disabling NMI Watchdog!\n"); | |
067fa0ff | 2776 | nmi_watchdog = NMI_NONE; |
1da177e4 | 2777 | } |
54168ed7 | 2778 | #ifdef CONFIG_X86_32 |
d11d5794 | 2779 | timer_ack = 0; |
54168ed7 | 2780 | #endif |
1da177e4 | 2781 | |
49a66a0b MR |
2782 | apic_printk(APIC_QUIET, KERN_INFO |
2783 | "...trying to set up timer as Virtual Wire IRQ...\n"); | |
1da177e4 | 2784 | |
497c9a19 YL |
2785 | lapic_register_intr(0); |
2786 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ | |
1da177e4 LT |
2787 | enable_8259A_irq(0); |
2788 | ||
2789 | if (timer_irq_works()) { | |
49a66a0b | 2790 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2791 | goto out; |
1da177e4 | 2792 | } |
e67465f1 | 2793 | disable_8259A_irq(0); |
497c9a19 | 2794 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
49a66a0b | 2795 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
1da177e4 | 2796 | |
49a66a0b MR |
2797 | apic_printk(APIC_QUIET, KERN_INFO |
2798 | "...trying to set up timer as ExtINT IRQ...\n"); | |
1da177e4 | 2799 | |
1da177e4 LT |
2800 | init_8259A(0); |
2801 | make_8259A_irq(0); | |
593f4a78 | 2802 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
2803 | |
2804 | unlock_ExtINT_logic(); | |
2805 | ||
2806 | if (timer_irq_works()) { | |
49a66a0b | 2807 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2808 | goto out; |
1da177e4 | 2809 | } |
49a66a0b | 2810 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
1da177e4 | 2811 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
49a66a0b | 2812 | "report. Then try booting with the 'noapic' option.\n"); |
4aae0702 IM |
2813 | out: |
2814 | local_irq_restore(flags); | |
1da177e4 LT |
2815 | } |
2816 | ||
2817 | /* | |
af174783 MR |
2818 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
2819 | * to devices. However there may be an I/O APIC pin available for | |
2820 | * this interrupt regardless. The pin may be left unconnected, but | |
2821 | * typically it will be reused as an ExtINT cascade interrupt for | |
2822 | * the master 8259A. In the MPS case such a pin will normally be | |
2823 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
2824 | * there is no provision for ExtINT interrupts, and in the absence | |
2825 | * of an override it would be treated as an ordinary ISA I/O APIC | |
2826 | * interrupt, that is edge-triggered and unmasked by default. We | |
2827 | * used to do this, but it caused problems on some systems because | |
2828 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
2829 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
2830 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
2831 | * the I/O APIC in all cases now. No actual device should request | |
2832 | * it anyway. --macro | |
1da177e4 LT |
2833 | */ |
2834 | #define PIC_IRQS (1 << PIC_CASCADE_IR) | |
2835 | ||
2836 | void __init setup_IO_APIC(void) | |
2837 | { | |
54168ed7 IM |
2838 | |
2839 | #ifdef CONFIG_X86_32 | |
1da177e4 | 2840 | enable_IO_APIC(); |
54168ed7 IM |
2841 | #else |
2842 | /* | |
2843 | * calling enable_IO_APIC() is moved to setup_local_APIC for BP | |
2844 | */ | |
2845 | #endif | |
1da177e4 | 2846 | |
af174783 | 2847 | io_apic_irqs = ~PIC_IRQS; |
1da177e4 | 2848 | |
54168ed7 | 2849 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); |
d6c88a50 | 2850 | /* |
54168ed7 IM |
2851 | * Set up IO-APIC IRQ routing. |
2852 | */ | |
2853 | #ifdef CONFIG_X86_32 | |
d6c88a50 TG |
2854 | if (!acpi_ioapic) |
2855 | setup_ioapic_ids_from_mpc(); | |
54168ed7 | 2856 | #endif |
1da177e4 LT |
2857 | sync_Arb_IDs(); |
2858 | setup_IO_APIC_irqs(); | |
2859 | init_IO_APIC_traps(); | |
1e4c85f9 | 2860 | check_timer(); |
1da177e4 LT |
2861 | } |
2862 | ||
2863 | /* | |
54168ed7 IM |
2864 | * Called after all the initialization is done. If we didnt find any |
2865 | * APIC bugs then we can allow the modify fast path | |
1da177e4 | 2866 | */ |
36062448 | 2867 | |
1da177e4 LT |
2868 | static int __init io_apic_bug_finalize(void) |
2869 | { | |
d6c88a50 TG |
2870 | if (sis_apic_bug == -1) |
2871 | sis_apic_bug = 0; | |
2872 | return 0; | |
1da177e4 LT |
2873 | } |
2874 | ||
2875 | late_initcall(io_apic_bug_finalize); | |
2876 | ||
2877 | struct sysfs_ioapic_data { | |
2878 | struct sys_device dev; | |
2879 | struct IO_APIC_route_entry entry[0]; | |
2880 | }; | |
54168ed7 | 2881 | static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS]; |
1da177e4 | 2882 | |
438510f6 | 2883 | static int ioapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
2884 | { |
2885 | struct IO_APIC_route_entry *entry; | |
2886 | struct sysfs_ioapic_data *data; | |
1da177e4 | 2887 | int i; |
36062448 | 2888 | |
1da177e4 LT |
2889 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
2890 | entry = data->entry; | |
54168ed7 IM |
2891 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) |
2892 | *entry = ioapic_read_entry(dev->id, i); | |
1da177e4 LT |
2893 | |
2894 | return 0; | |
2895 | } | |
2896 | ||
2897 | static int ioapic_resume(struct sys_device *dev) | |
2898 | { | |
2899 | struct IO_APIC_route_entry *entry; | |
2900 | struct sysfs_ioapic_data *data; | |
2901 | unsigned long flags; | |
2902 | union IO_APIC_reg_00 reg_00; | |
2903 | int i; | |
36062448 | 2904 | |
1da177e4 LT |
2905 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
2906 | entry = data->entry; | |
2907 | ||
2908 | spin_lock_irqsave(&ioapic_lock, flags); | |
2909 | reg_00.raw = io_apic_read(dev->id, 0); | |
ec2cd0a2 AS |
2910 | if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) { |
2911 | reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid; | |
1da177e4 LT |
2912 | io_apic_write(dev->id, 0, reg_00.raw); |
2913 | } | |
1da177e4 | 2914 | spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 2915 | for (i = 0; i < nr_ioapic_registers[dev->id]; i++) |
cf4c6a2f | 2916 | ioapic_write_entry(dev->id, i, entry[i]); |
1da177e4 LT |
2917 | |
2918 | return 0; | |
2919 | } | |
2920 | ||
2921 | static struct sysdev_class ioapic_sysdev_class = { | |
af5ca3f4 | 2922 | .name = "ioapic", |
1da177e4 LT |
2923 | .suspend = ioapic_suspend, |
2924 | .resume = ioapic_resume, | |
2925 | }; | |
2926 | ||
2927 | static int __init ioapic_init_sysfs(void) | |
2928 | { | |
54168ed7 IM |
2929 | struct sys_device * dev; |
2930 | int i, size, error; | |
1da177e4 LT |
2931 | |
2932 | error = sysdev_class_register(&ioapic_sysdev_class); | |
2933 | if (error) | |
2934 | return error; | |
2935 | ||
54168ed7 | 2936 | for (i = 0; i < nr_ioapics; i++ ) { |
36062448 | 2937 | size = sizeof(struct sys_device) + nr_ioapic_registers[i] |
1da177e4 | 2938 | * sizeof(struct IO_APIC_route_entry); |
25556c16 | 2939 | mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL); |
1da177e4 LT |
2940 | if (!mp_ioapic_data[i]) { |
2941 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
2942 | continue; | |
2943 | } | |
1da177e4 | 2944 | dev = &mp_ioapic_data[i]->dev; |
36062448 | 2945 | dev->id = i; |
1da177e4 LT |
2946 | dev->cls = &ioapic_sysdev_class; |
2947 | error = sysdev_register(dev); | |
2948 | if (error) { | |
2949 | kfree(mp_ioapic_data[i]); | |
2950 | mp_ioapic_data[i] = NULL; | |
2951 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
2952 | continue; | |
2953 | } | |
2954 | } | |
2955 | ||
2956 | return 0; | |
2957 | } | |
2958 | ||
2959 | device_initcall(ioapic_init_sysfs); | |
2960 | ||
3fc471ed | 2961 | /* |
95d77884 | 2962 | * Dynamic irq allocate and deallocation |
3fc471ed | 2963 | */ |
199751d7 | 2964 | unsigned int create_irq_nr(unsigned int irq_want) |
3fc471ed | 2965 | { |
ace80ab7 | 2966 | /* Allocate an unused irq */ |
54168ed7 IM |
2967 | unsigned int irq; |
2968 | unsigned int new; | |
3fc471ed | 2969 | unsigned long flags; |
0b8f1efa YL |
2970 | struct irq_cfg *cfg_new = NULL; |
2971 | int cpu = boot_cpu_id; | |
2972 | struct irq_desc *desc_new = NULL; | |
199751d7 YL |
2973 | |
2974 | irq = 0; | |
ace80ab7 | 2975 | spin_lock_irqsave(&vector_lock, flags); |
54168ed7 | 2976 | for (new = irq_want; new > 0; new--) { |
ace80ab7 EB |
2977 | if (platform_legacy_irq(new)) |
2978 | continue; | |
0b8f1efa YL |
2979 | |
2980 | desc_new = irq_to_desc_alloc_cpu(new, cpu); | |
2981 | if (!desc_new) { | |
2982 | printk(KERN_INFO "can not get irq_desc for %d\n", new); | |
2983 | continue; | |
2984 | } | |
2985 | cfg_new = desc_new->chip_data; | |
2986 | ||
2987 | if (cfg_new->vector != 0) | |
ace80ab7 | 2988 | continue; |
497c9a19 | 2989 | if (__assign_irq_vector(new, TARGET_CPUS) == 0) |
ace80ab7 EB |
2990 | irq = new; |
2991 | break; | |
2992 | } | |
2993 | spin_unlock_irqrestore(&vector_lock, flags); | |
3fc471ed | 2994 | |
199751d7 | 2995 | if (irq > 0) { |
3fc471ed | 2996 | dynamic_irq_init(irq); |
0b8f1efa YL |
2997 | /* restore it, in case dynamic_irq_init clear it */ |
2998 | if (desc_new) | |
2999 | desc_new->chip_data = cfg_new; | |
3fc471ed EB |
3000 | } |
3001 | return irq; | |
3002 | } | |
3003 | ||
199751d7 YL |
3004 | int create_irq(void) |
3005 | { | |
54168ed7 IM |
3006 | int irq; |
3007 | ||
3008 | irq = create_irq_nr(nr_irqs - 1); | |
3009 | ||
3010 | if (irq == 0) | |
3011 | irq = -1; | |
3012 | ||
3013 | return irq; | |
199751d7 YL |
3014 | } |
3015 | ||
3fc471ed EB |
3016 | void destroy_irq(unsigned int irq) |
3017 | { | |
3018 | unsigned long flags; | |
0b8f1efa YL |
3019 | struct irq_cfg *cfg; |
3020 | struct irq_desc *desc; | |
3fc471ed | 3021 | |
0b8f1efa YL |
3022 | /* store it, in case dynamic_irq_cleanup clear it */ |
3023 | desc = irq_to_desc(irq); | |
3024 | cfg = desc->chip_data; | |
3fc471ed | 3025 | dynamic_irq_cleanup(irq); |
0b8f1efa YL |
3026 | /* connect back irq_cfg */ |
3027 | if (desc) | |
3028 | desc->chip_data = cfg; | |
3fc471ed | 3029 | |
54168ed7 IM |
3030 | #ifdef CONFIG_INTR_REMAP |
3031 | free_irte(irq); | |
3032 | #endif | |
3fc471ed | 3033 | spin_lock_irqsave(&vector_lock, flags); |
497c9a19 | 3034 | __clear_irq_vector(irq); |
3fc471ed EB |
3035 | spin_unlock_irqrestore(&vector_lock, flags); |
3036 | } | |
3fc471ed | 3037 | |
2d3fcc1c | 3038 | /* |
27b46d76 | 3039 | * MSI message composition |
2d3fcc1c EB |
3040 | */ |
3041 | #ifdef CONFIG_PCI_MSI | |
3b7d1921 | 3042 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg) |
2d3fcc1c | 3043 | { |
497c9a19 YL |
3044 | struct irq_cfg *cfg; |
3045 | int err; | |
2d3fcc1c | 3046 | unsigned dest; |
497c9a19 | 3047 | cpumask_t tmp; |
2d3fcc1c | 3048 | |
497c9a19 YL |
3049 | tmp = TARGET_CPUS; |
3050 | err = assign_irq_vector(irq, tmp); | |
3051 | if (err) | |
3052 | return err; | |
2d3fcc1c | 3053 | |
497c9a19 YL |
3054 | cfg = irq_cfg(irq); |
3055 | cpus_and(tmp, cfg->domain, tmp); | |
3056 | dest = cpu_mask_to_apicid(tmp); | |
3057 | ||
54168ed7 IM |
3058 | #ifdef CONFIG_INTR_REMAP |
3059 | if (irq_remapped(irq)) { | |
3060 | struct irte irte; | |
3061 | int ir_index; | |
3062 | u16 sub_handle; | |
3063 | ||
3064 | ir_index = map_irq_to_irte_handle(irq, &sub_handle); | |
3065 | BUG_ON(ir_index == -1); | |
3066 | ||
3067 | memset (&irte, 0, sizeof(irte)); | |
3068 | ||
3069 | irte.present = 1; | |
3070 | irte.dst_mode = INT_DEST_MODE; | |
3071 | irte.trigger_mode = 0; /* edge */ | |
3072 | irte.dlvry_mode = INT_DELIVERY_MODE; | |
3073 | irte.vector = cfg->vector; | |
3074 | irte.dest_id = IRTE_DEST(dest); | |
3075 | ||
3076 | modify_irte(irq, &irte); | |
3077 | ||
3078 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3079 | msg->data = sub_handle; | |
3080 | msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT | | |
3081 | MSI_ADDR_IR_SHV | | |
3082 | MSI_ADDR_IR_INDEX1(ir_index) | | |
3083 | MSI_ADDR_IR_INDEX2(ir_index); | |
3084 | } else | |
3085 | #endif | |
3086 | { | |
3087 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3088 | msg->address_lo = | |
3089 | MSI_ADDR_BASE_LO | | |
3090 | ((INT_DEST_MODE == 0) ? | |
3091 | MSI_ADDR_DEST_MODE_PHYSICAL: | |
3092 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
3093 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
3094 | MSI_ADDR_REDIRECTION_CPU: | |
3095 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
3096 | MSI_ADDR_DEST_ID(dest); | |
497c9a19 | 3097 | |
54168ed7 IM |
3098 | msg->data = |
3099 | MSI_DATA_TRIGGER_EDGE | | |
3100 | MSI_DATA_LEVEL_ASSERT | | |
3101 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
3102 | MSI_DATA_DELIVERY_FIXED: | |
3103 | MSI_DATA_DELIVERY_LOWPRI) | | |
3104 | MSI_DATA_VECTOR(cfg->vector); | |
3105 | } | |
497c9a19 | 3106 | return err; |
2d3fcc1c EB |
3107 | } |
3108 | ||
3b7d1921 EB |
3109 | #ifdef CONFIG_SMP |
3110 | static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask) | |
2d3fcc1c | 3111 | { |
497c9a19 | 3112 | struct irq_cfg *cfg; |
3b7d1921 EB |
3113 | struct msi_msg msg; |
3114 | unsigned int dest; | |
3115 | cpumask_t tmp; | |
54168ed7 | 3116 | struct irq_desc *desc; |
3b7d1921 EB |
3117 | |
3118 | cpus_and(tmp, mask, cpu_online_map); | |
3119 | if (cpus_empty(tmp)) | |
497c9a19 | 3120 | return; |
2d3fcc1c | 3121 | |
497c9a19 | 3122 | if (assign_irq_vector(irq, mask)) |
3b7d1921 | 3123 | return; |
2d3fcc1c | 3124 | |
497c9a19 YL |
3125 | cfg = irq_cfg(irq); |
3126 | cpus_and(tmp, cfg->domain, mask); | |
3127 | dest = cpu_mask_to_apicid(tmp); | |
3b7d1921 EB |
3128 | |
3129 | read_msi_msg(irq, &msg); | |
3130 | ||
3131 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
497c9a19 | 3132 | msg.data |= MSI_DATA_VECTOR(cfg->vector); |
3b7d1921 EB |
3133 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; |
3134 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3135 | ||
3136 | write_msi_msg(irq, &msg); | |
54168ed7 IM |
3137 | desc = irq_to_desc(irq); |
3138 | desc->affinity = mask; | |
2d3fcc1c | 3139 | } |
54168ed7 IM |
3140 | |
3141 | #ifdef CONFIG_INTR_REMAP | |
3142 | /* | |
3143 | * Migrate the MSI irq to another cpumask. This migration is | |
3144 | * done in the process context using interrupt-remapping hardware. | |
3145 | */ | |
3146 | static void ir_set_msi_irq_affinity(unsigned int irq, cpumask_t mask) | |
3147 | { | |
3148 | struct irq_cfg *cfg; | |
3149 | unsigned int dest; | |
3150 | cpumask_t tmp, cleanup_mask; | |
3151 | struct irte irte; | |
3152 | struct irq_desc *desc; | |
3153 | ||
3154 | cpus_and(tmp, mask, cpu_online_map); | |
3155 | if (cpus_empty(tmp)) | |
3156 | return; | |
3157 | ||
3158 | if (get_irte(irq, &irte)) | |
3159 | return; | |
3160 | ||
3161 | if (assign_irq_vector(irq, mask)) | |
3162 | return; | |
3163 | ||
3164 | cfg = irq_cfg(irq); | |
3165 | cpus_and(tmp, cfg->domain, mask); | |
3166 | dest = cpu_mask_to_apicid(tmp); | |
3167 | ||
3168 | irte.vector = cfg->vector; | |
3169 | irte.dest_id = IRTE_DEST(dest); | |
3170 | ||
3171 | /* | |
3172 | * atomically update the IRTE with the new destination and vector. | |
3173 | */ | |
3174 | modify_irte(irq, &irte); | |
3175 | ||
3176 | /* | |
3177 | * After this point, all the interrupts will start arriving | |
3178 | * at the new destination. So, time to cleanup the previous | |
3179 | * vector allocation. | |
3180 | */ | |
3181 | if (cfg->move_in_progress) { | |
3182 | cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map); | |
3183 | cfg->move_cleanup_count = cpus_weight(cleanup_mask); | |
3184 | send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); | |
3185 | cfg->move_in_progress = 0; | |
3186 | } | |
3187 | ||
3188 | desc = irq_to_desc(irq); | |
3189 | desc->affinity = mask; | |
3190 | } | |
3191 | #endif | |
3b7d1921 | 3192 | #endif /* CONFIG_SMP */ |
2d3fcc1c | 3193 | |
3b7d1921 EB |
3194 | /* |
3195 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
3196 | * which implement the MSI or MSI-X Capability Structure. | |
3197 | */ | |
3198 | static struct irq_chip msi_chip = { | |
3199 | .name = "PCI-MSI", | |
3200 | .unmask = unmask_msi_irq, | |
3201 | .mask = mask_msi_irq, | |
1d025192 | 3202 | .ack = ack_apic_edge, |
3b7d1921 EB |
3203 | #ifdef CONFIG_SMP |
3204 | .set_affinity = set_msi_irq_affinity, | |
3205 | #endif | |
3206 | .retrigger = ioapic_retrigger_irq, | |
2d3fcc1c EB |
3207 | }; |
3208 | ||
54168ed7 IM |
3209 | #ifdef CONFIG_INTR_REMAP |
3210 | static struct irq_chip msi_ir_chip = { | |
3211 | .name = "IR-PCI-MSI", | |
3212 | .unmask = unmask_msi_irq, | |
3213 | .mask = mask_msi_irq, | |
3214 | .ack = ack_x2apic_edge, | |
3215 | #ifdef CONFIG_SMP | |
3216 | .set_affinity = ir_set_msi_irq_affinity, | |
3217 | #endif | |
3218 | .retrigger = ioapic_retrigger_irq, | |
3219 | }; | |
3220 | ||
3221 | /* | |
3222 | * Map the PCI dev to the corresponding remapping hardware unit | |
3223 | * and allocate 'nvec' consecutive interrupt-remapping table entries | |
3224 | * in it. | |
3225 | */ | |
3226 | static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec) | |
3227 | { | |
3228 | struct intel_iommu *iommu; | |
3229 | int index; | |
3230 | ||
3231 | iommu = map_dev_to_ir(dev); | |
3232 | if (!iommu) { | |
3233 | printk(KERN_ERR | |
3234 | "Unable to map PCI %s to iommu\n", pci_name(dev)); | |
3235 | return -ENOENT; | |
3236 | } | |
3237 | ||
3238 | index = alloc_irte(iommu, irq, nvec); | |
3239 | if (index < 0) { | |
3240 | printk(KERN_ERR | |
3241 | "Unable to allocate %d IRTE for PCI %s\n", nvec, | |
d6c88a50 | 3242 | pci_name(dev)); |
54168ed7 IM |
3243 | return -ENOSPC; |
3244 | } | |
3245 | return index; | |
3246 | } | |
3247 | #endif | |
1d025192 YL |
3248 | |
3249 | static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc, int irq) | |
3250 | { | |
3251 | int ret; | |
3252 | struct msi_msg msg; | |
3253 | ||
3254 | ret = msi_compose_msg(dev, irq, &msg); | |
3255 | if (ret < 0) | |
3256 | return ret; | |
3257 | ||
3258 | set_irq_msi(irq, desc); | |
3259 | write_msi_msg(irq, &msg); | |
3260 | ||
54168ed7 IM |
3261 | #ifdef CONFIG_INTR_REMAP |
3262 | if (irq_remapped(irq)) { | |
3263 | struct irq_desc *desc = irq_to_desc(irq); | |
3264 | /* | |
3265 | * irq migration in process context | |
3266 | */ | |
3267 | desc->status |= IRQ_MOVE_PCNTXT; | |
3268 | set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge"); | |
3269 | } else | |
3270 | #endif | |
3271 | set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge"); | |
1d025192 | 3272 | |
c81bba49 YL |
3273 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq); |
3274 | ||
1d025192 YL |
3275 | return 0; |
3276 | } | |
3277 | ||
0b8f1efa | 3278 | int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc) |
3b7d1921 | 3279 | { |
54168ed7 IM |
3280 | unsigned int irq; |
3281 | int ret; | |
199751d7 YL |
3282 | unsigned int irq_want; |
3283 | ||
0b8f1efa | 3284 | irq_want = nr_irqs - 1; |
199751d7 | 3285 | irq = create_irq_nr(irq_want); |
199751d7 YL |
3286 | if (irq == 0) |
3287 | return -1; | |
f7feaca7 | 3288 | |
54168ed7 IM |
3289 | #ifdef CONFIG_INTR_REMAP |
3290 | if (!intr_remapping_enabled) | |
3291 | goto no_ir; | |
3292 | ||
3293 | ret = msi_alloc_irte(dev, irq, 1); | |
3294 | if (ret < 0) | |
3295 | goto error; | |
3296 | no_ir: | |
3297 | #endif | |
0b8f1efa | 3298 | ret = setup_msi_irq(dev, msidesc, irq); |
f7feaca7 EB |
3299 | if (ret < 0) { |
3300 | destroy_irq(irq); | |
3b7d1921 | 3301 | return ret; |
54168ed7 | 3302 | } |
7fe3730d | 3303 | return 0; |
54168ed7 IM |
3304 | |
3305 | #ifdef CONFIG_INTR_REMAP | |
3306 | error: | |
3307 | destroy_irq(irq); | |
3308 | return ret; | |
3309 | #endif | |
3b7d1921 EB |
3310 | } |
3311 | ||
047c8fdb YL |
3312 | int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
3313 | { | |
54168ed7 IM |
3314 | unsigned int irq; |
3315 | int ret, sub_handle; | |
0b8f1efa | 3316 | struct msi_desc *msidesc; |
54168ed7 IM |
3317 | unsigned int irq_want; |
3318 | ||
3319 | #ifdef CONFIG_INTR_REMAP | |
3320 | struct intel_iommu *iommu = 0; | |
3321 | int index = 0; | |
3322 | #endif | |
3323 | ||
0b8f1efa | 3324 | irq_want = nr_irqs - 1; |
54168ed7 | 3325 | sub_handle = 0; |
0b8f1efa YL |
3326 | list_for_each_entry(msidesc, &dev->msi_list, list) { |
3327 | irq = create_irq_nr(irq_want); | |
3328 | irq_want--; | |
54168ed7 IM |
3329 | if (irq == 0) |
3330 | return -1; | |
3331 | #ifdef CONFIG_INTR_REMAP | |
3332 | if (!intr_remapping_enabled) | |
3333 | goto no_ir; | |
3334 | ||
3335 | if (!sub_handle) { | |
3336 | /* | |
3337 | * allocate the consecutive block of IRTE's | |
3338 | * for 'nvec' | |
3339 | */ | |
3340 | index = msi_alloc_irte(dev, irq, nvec); | |
3341 | if (index < 0) { | |
3342 | ret = index; | |
3343 | goto error; | |
3344 | } | |
3345 | } else { | |
3346 | iommu = map_dev_to_ir(dev); | |
3347 | if (!iommu) { | |
3348 | ret = -ENOENT; | |
3349 | goto error; | |
3350 | } | |
3351 | /* | |
3352 | * setup the mapping between the irq and the IRTE | |
3353 | * base index, the sub_handle pointing to the | |
3354 | * appropriate interrupt remap table entry. | |
3355 | */ | |
3356 | set_irte_irq(irq, iommu, index, sub_handle); | |
3357 | } | |
3358 | no_ir: | |
3359 | #endif | |
0b8f1efa | 3360 | ret = setup_msi_irq(dev, msidesc, irq); |
54168ed7 IM |
3361 | if (ret < 0) |
3362 | goto error; | |
3363 | sub_handle++; | |
3364 | } | |
3365 | return 0; | |
047c8fdb YL |
3366 | |
3367 | error: | |
54168ed7 IM |
3368 | destroy_irq(irq); |
3369 | return ret; | |
047c8fdb YL |
3370 | } |
3371 | ||
3b7d1921 EB |
3372 | void arch_teardown_msi_irq(unsigned int irq) |
3373 | { | |
f7feaca7 | 3374 | destroy_irq(irq); |
3b7d1921 EB |
3375 | } |
3376 | ||
54168ed7 IM |
3377 | #ifdef CONFIG_DMAR |
3378 | #ifdef CONFIG_SMP | |
3379 | static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask) | |
3380 | { | |
3381 | struct irq_cfg *cfg; | |
3382 | struct msi_msg msg; | |
3383 | unsigned int dest; | |
3384 | cpumask_t tmp; | |
3385 | struct irq_desc *desc; | |
3386 | ||
3387 | cpus_and(tmp, mask, cpu_online_map); | |
3388 | if (cpus_empty(tmp)) | |
3389 | return; | |
3390 | ||
3391 | if (assign_irq_vector(irq, mask)) | |
3392 | return; | |
3393 | ||
3394 | cfg = irq_cfg(irq); | |
3395 | cpus_and(tmp, cfg->domain, mask); | |
3396 | dest = cpu_mask_to_apicid(tmp); | |
3397 | ||
3398 | dmar_msi_read(irq, &msg); | |
3399 | ||
3400 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3401 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3402 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3403 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3404 | ||
3405 | dmar_msi_write(irq, &msg); | |
3406 | desc = irq_to_desc(irq); | |
3407 | desc->affinity = mask; | |
3408 | } | |
3409 | #endif /* CONFIG_SMP */ | |
3410 | ||
3411 | struct irq_chip dmar_msi_type = { | |
3412 | .name = "DMAR_MSI", | |
3413 | .unmask = dmar_msi_unmask, | |
3414 | .mask = dmar_msi_mask, | |
3415 | .ack = ack_apic_edge, | |
3416 | #ifdef CONFIG_SMP | |
3417 | .set_affinity = dmar_msi_set_affinity, | |
3418 | #endif | |
3419 | .retrigger = ioapic_retrigger_irq, | |
3420 | }; | |
3421 | ||
3422 | int arch_setup_dmar_msi(unsigned int irq) | |
3423 | { | |
3424 | int ret; | |
3425 | struct msi_msg msg; | |
2d3fcc1c | 3426 | |
54168ed7 IM |
3427 | ret = msi_compose_msg(NULL, irq, &msg); |
3428 | if (ret < 0) | |
3429 | return ret; | |
3430 | dmar_msi_write(irq, &msg); | |
3431 | set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, | |
3432 | "edge"); | |
3433 | return 0; | |
3434 | } | |
3435 | #endif | |
3436 | ||
58ac1e76 | 3437 | #ifdef CONFIG_HPET_TIMER |
3438 | ||
3439 | #ifdef CONFIG_SMP | |
3440 | static void hpet_msi_set_affinity(unsigned int irq, cpumask_t mask) | |
3441 | { | |
3442 | struct irq_cfg *cfg; | |
3443 | struct irq_desc *desc; | |
3444 | struct msi_msg msg; | |
3445 | unsigned int dest; | |
3446 | cpumask_t tmp; | |
3447 | ||
3448 | cpus_and(tmp, mask, cpu_online_map); | |
3449 | if (cpus_empty(tmp)) | |
3450 | return; | |
3451 | ||
3452 | if (assign_irq_vector(irq, mask)) | |
3453 | return; | |
3454 | ||
3455 | cfg = irq_cfg(irq); | |
3456 | cpus_and(tmp, cfg->domain, mask); | |
3457 | dest = cpu_mask_to_apicid(tmp); | |
3458 | ||
3459 | hpet_msi_read(irq, &msg); | |
3460 | ||
3461 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3462 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3463 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3464 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3465 | ||
3466 | hpet_msi_write(irq, &msg); | |
3467 | desc = irq_to_desc(irq); | |
3468 | desc->affinity = mask; | |
3469 | } | |
3470 | #endif /* CONFIG_SMP */ | |
3471 | ||
3472 | struct irq_chip hpet_msi_type = { | |
3473 | .name = "HPET_MSI", | |
3474 | .unmask = hpet_msi_unmask, | |
3475 | .mask = hpet_msi_mask, | |
3476 | .ack = ack_apic_edge, | |
3477 | #ifdef CONFIG_SMP | |
3478 | .set_affinity = hpet_msi_set_affinity, | |
3479 | #endif | |
3480 | .retrigger = ioapic_retrigger_irq, | |
3481 | }; | |
3482 | ||
3483 | int arch_setup_hpet_msi(unsigned int irq) | |
3484 | { | |
3485 | int ret; | |
3486 | struct msi_msg msg; | |
3487 | ||
3488 | ret = msi_compose_msg(NULL, irq, &msg); | |
3489 | if (ret < 0) | |
3490 | return ret; | |
3491 | ||
3492 | hpet_msi_write(irq, &msg); | |
3493 | set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq, | |
3494 | "edge"); | |
c81bba49 | 3495 | |
58ac1e76 | 3496 | return 0; |
3497 | } | |
3498 | #endif | |
3499 | ||
54168ed7 | 3500 | #endif /* CONFIG_PCI_MSI */ |
8b955b0d EB |
3501 | /* |
3502 | * Hypertransport interrupt support | |
3503 | */ | |
3504 | #ifdef CONFIG_HT_IRQ | |
3505 | ||
3506 | #ifdef CONFIG_SMP | |
3507 | ||
497c9a19 | 3508 | static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) |
8b955b0d | 3509 | { |
ec68307c EB |
3510 | struct ht_irq_msg msg; |
3511 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 3512 | |
497c9a19 | 3513 | msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); |
ec68307c | 3514 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); |
8b955b0d | 3515 | |
497c9a19 | 3516 | msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); |
ec68307c | 3517 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3518 | |
ec68307c | 3519 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
3520 | } |
3521 | ||
3522 | static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask) | |
3523 | { | |
497c9a19 | 3524 | struct irq_cfg *cfg; |
8b955b0d EB |
3525 | unsigned int dest; |
3526 | cpumask_t tmp; | |
54168ed7 | 3527 | struct irq_desc *desc; |
8b955b0d EB |
3528 | |
3529 | cpus_and(tmp, mask, cpu_online_map); | |
3530 | if (cpus_empty(tmp)) | |
497c9a19 | 3531 | return; |
8b955b0d | 3532 | |
497c9a19 YL |
3533 | if (assign_irq_vector(irq, mask)) |
3534 | return; | |
8b955b0d | 3535 | |
497c9a19 YL |
3536 | cfg = irq_cfg(irq); |
3537 | cpus_and(tmp, cfg->domain, mask); | |
3538 | dest = cpu_mask_to_apicid(tmp); | |
8b955b0d | 3539 | |
497c9a19 | 3540 | target_ht_irq(irq, dest, cfg->vector); |
54168ed7 IM |
3541 | desc = irq_to_desc(irq); |
3542 | desc->affinity = mask; | |
8b955b0d EB |
3543 | } |
3544 | #endif | |
3545 | ||
c37e108d | 3546 | static struct irq_chip ht_irq_chip = { |
8b955b0d EB |
3547 | .name = "PCI-HT", |
3548 | .mask = mask_ht_irq, | |
3549 | .unmask = unmask_ht_irq, | |
1d025192 | 3550 | .ack = ack_apic_edge, |
8b955b0d EB |
3551 | #ifdef CONFIG_SMP |
3552 | .set_affinity = set_ht_irq_affinity, | |
3553 | #endif | |
3554 | .retrigger = ioapic_retrigger_irq, | |
3555 | }; | |
3556 | ||
3557 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
3558 | { | |
497c9a19 YL |
3559 | struct irq_cfg *cfg; |
3560 | int err; | |
3561 | cpumask_t tmp; | |
8b955b0d | 3562 | |
497c9a19 YL |
3563 | tmp = TARGET_CPUS; |
3564 | err = assign_irq_vector(irq, tmp); | |
54168ed7 | 3565 | if (!err) { |
ec68307c | 3566 | struct ht_irq_msg msg; |
8b955b0d | 3567 | unsigned dest; |
8b955b0d | 3568 | |
497c9a19 YL |
3569 | cfg = irq_cfg(irq); |
3570 | cpus_and(tmp, cfg->domain, tmp); | |
8b955b0d EB |
3571 | dest = cpu_mask_to_apicid(tmp); |
3572 | ||
ec68307c | 3573 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3574 | |
ec68307c EB |
3575 | msg.address_lo = |
3576 | HT_IRQ_LOW_BASE | | |
8b955b0d | 3577 | HT_IRQ_LOW_DEST_ID(dest) | |
497c9a19 | 3578 | HT_IRQ_LOW_VECTOR(cfg->vector) | |
8b955b0d EB |
3579 | ((INT_DEST_MODE == 0) ? |
3580 | HT_IRQ_LOW_DM_PHYSICAL : | |
3581 | HT_IRQ_LOW_DM_LOGICAL) | | |
3582 | HT_IRQ_LOW_RQEOI_EDGE | | |
3583 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
3584 | HT_IRQ_LOW_MT_FIXED : | |
3585 | HT_IRQ_LOW_MT_ARBITRATED) | | |
3586 | HT_IRQ_LOW_IRQ_MASKED; | |
3587 | ||
ec68307c | 3588 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 3589 | |
a460e745 IM |
3590 | set_irq_chip_and_handler_name(irq, &ht_irq_chip, |
3591 | handle_edge_irq, "edge"); | |
c81bba49 YL |
3592 | |
3593 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq); | |
8b955b0d | 3594 | } |
497c9a19 | 3595 | return err; |
8b955b0d EB |
3596 | } |
3597 | #endif /* CONFIG_HT_IRQ */ | |
3598 | ||
4173a0e7 DN |
3599 | #ifdef CONFIG_X86_64 |
3600 | /* | |
3601 | * Re-target the irq to the specified CPU and enable the specified MMR located | |
3602 | * on the specified blade to allow the sending of MSIs to the specified CPU. | |
3603 | */ | |
3604 | int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade, | |
3605 | unsigned long mmr_offset) | |
3606 | { | |
3607 | const cpumask_t *eligible_cpu = get_cpu_mask(cpu); | |
3608 | struct irq_cfg *cfg; | |
3609 | int mmr_pnode; | |
3610 | unsigned long mmr_value; | |
3611 | struct uv_IO_APIC_route_entry *entry; | |
3612 | unsigned long flags; | |
3613 | int err; | |
3614 | ||
3615 | err = assign_irq_vector(irq, *eligible_cpu); | |
3616 | if (err != 0) | |
3617 | return err; | |
3618 | ||
3619 | spin_lock_irqsave(&vector_lock, flags); | |
3620 | set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq, | |
3621 | irq_name); | |
3622 | spin_unlock_irqrestore(&vector_lock, flags); | |
3623 | ||
3624 | cfg = irq_cfg(irq); | |
3625 | ||
3626 | mmr_value = 0; | |
3627 | entry = (struct uv_IO_APIC_route_entry *)&mmr_value; | |
3628 | BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long)); | |
3629 | ||
3630 | entry->vector = cfg->vector; | |
3631 | entry->delivery_mode = INT_DELIVERY_MODE; | |
3632 | entry->dest_mode = INT_DEST_MODE; | |
3633 | entry->polarity = 0; | |
3634 | entry->trigger = 0; | |
3635 | entry->mask = 0; | |
3636 | entry->dest = cpu_mask_to_apicid(*eligible_cpu); | |
3637 | ||
3638 | mmr_pnode = uv_blade_to_pnode(mmr_blade); | |
3639 | uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value); | |
3640 | ||
3641 | return irq; | |
3642 | } | |
3643 | ||
3644 | /* | |
3645 | * Disable the specified MMR located on the specified blade so that MSIs are | |
3646 | * longer allowed to be sent. | |
3647 | */ | |
3648 | void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset) | |
3649 | { | |
3650 | unsigned long mmr_value; | |
3651 | struct uv_IO_APIC_route_entry *entry; | |
3652 | int mmr_pnode; | |
3653 | ||
3654 | mmr_value = 0; | |
3655 | entry = (struct uv_IO_APIC_route_entry *)&mmr_value; | |
3656 | BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long)); | |
3657 | ||
3658 | entry->mask = 1; | |
3659 | ||
3660 | mmr_pnode = uv_blade_to_pnode(mmr_blade); | |
3661 | uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value); | |
3662 | } | |
3663 | #endif /* CONFIG_X86_64 */ | |
3664 | ||
9d6a4d08 YL |
3665 | int __init io_apic_get_redir_entries (int ioapic) |
3666 | { | |
3667 | union IO_APIC_reg_01 reg_01; | |
3668 | unsigned long flags; | |
3669 | ||
3670 | spin_lock_irqsave(&ioapic_lock, flags); | |
3671 | reg_01.raw = io_apic_read(ioapic, 1); | |
3672 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3673 | ||
3674 | return reg_01.bits.entries; | |
3675 | } | |
3676 | ||
3677 | int __init probe_nr_irqs(void) | |
3678 | { | |
a1967d64 | 3679 | return NR_IRQS; |
9d6a4d08 YL |
3680 | } |
3681 | ||
1da177e4 | 3682 | /* -------------------------------------------------------------------------- |
54168ed7 | 3683 | ACPI-based IOAPIC Configuration |
1da177e4 LT |
3684 | -------------------------------------------------------------------------- */ |
3685 | ||
888ba6c6 | 3686 | #ifdef CONFIG_ACPI |
1da177e4 | 3687 | |
54168ed7 | 3688 | #ifdef CONFIG_X86_32 |
36062448 | 3689 | int __init io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
3690 | { |
3691 | union IO_APIC_reg_00 reg_00; | |
3692 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
3693 | physid_mask_t tmp; | |
3694 | unsigned long flags; | |
3695 | int i = 0; | |
3696 | ||
3697 | /* | |
36062448 PC |
3698 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
3699 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 3700 | * supports up to 16 on one shared APIC bus. |
36062448 | 3701 | * |
1da177e4 LT |
3702 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
3703 | * advantage of new APIC bus architecture. | |
3704 | */ | |
3705 | ||
3706 | if (physids_empty(apic_id_map)) | |
3707 | apic_id_map = ioapic_phys_id_map(phys_cpu_present_map); | |
3708 | ||
3709 | spin_lock_irqsave(&ioapic_lock, flags); | |
3710 | reg_00.raw = io_apic_read(ioapic, 0); | |
3711 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3712 | ||
3713 | if (apic_id >= get_physical_broadcast()) { | |
3714 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
3715 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
3716 | apic_id = reg_00.bits.ID; | |
3717 | } | |
3718 | ||
3719 | /* | |
36062448 | 3720 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
3721 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
3722 | */ | |
3723 | if (check_apicid_used(apic_id_map, apic_id)) { | |
3724 | ||
3725 | for (i = 0; i < get_physical_broadcast(); i++) { | |
3726 | if (!check_apicid_used(apic_id_map, i)) | |
3727 | break; | |
3728 | } | |
3729 | ||
3730 | if (i == get_physical_broadcast()) | |
3731 | panic("Max apic_id exceeded!\n"); | |
3732 | ||
3733 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
3734 | "trying %d\n", ioapic, apic_id, i); | |
3735 | ||
3736 | apic_id = i; | |
36062448 | 3737 | } |
1da177e4 LT |
3738 | |
3739 | tmp = apicid_to_cpu_present(apic_id); | |
3740 | physids_or(apic_id_map, apic_id_map, tmp); | |
3741 | ||
3742 | if (reg_00.bits.ID != apic_id) { | |
3743 | reg_00.bits.ID = apic_id; | |
3744 | ||
3745 | spin_lock_irqsave(&ioapic_lock, flags); | |
3746 | io_apic_write(ioapic, 0, reg_00.raw); | |
3747 | reg_00.raw = io_apic_read(ioapic, 0); | |
3748 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3749 | ||
3750 | /* Sanity check */ | |
6070f9ec AD |
3751 | if (reg_00.bits.ID != apic_id) { |
3752 | printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); | |
3753 | return -1; | |
3754 | } | |
1da177e4 LT |
3755 | } |
3756 | ||
3757 | apic_printk(APIC_VERBOSE, KERN_INFO | |
3758 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
3759 | ||
3760 | return apic_id; | |
3761 | } | |
3762 | ||
36062448 | 3763 | int __init io_apic_get_version(int ioapic) |
1da177e4 LT |
3764 | { |
3765 | union IO_APIC_reg_01 reg_01; | |
3766 | unsigned long flags; | |
3767 | ||
3768 | spin_lock_irqsave(&ioapic_lock, flags); | |
3769 | reg_01.raw = io_apic_read(ioapic, 1); | |
3770 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3771 | ||
3772 | return reg_01.bits.version; | |
3773 | } | |
54168ed7 | 3774 | #endif |
1da177e4 | 3775 | |
54168ed7 | 3776 | int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity) |
1da177e4 | 3777 | { |
0b8f1efa YL |
3778 | struct irq_desc *desc; |
3779 | struct irq_cfg *cfg; | |
3780 | int cpu = boot_cpu_id; | |
3781 | ||
1da177e4 | 3782 | if (!IO_APIC_IRQ(irq)) { |
54168ed7 | 3783 | apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", |
1da177e4 LT |
3784 | ioapic); |
3785 | return -EINVAL; | |
3786 | } | |
3787 | ||
0b8f1efa YL |
3788 | desc = irq_to_desc_alloc_cpu(irq, cpu); |
3789 | if (!desc) { | |
3790 | printk(KERN_INFO "can not get irq_desc %d\n", irq); | |
3791 | return 0; | |
3792 | } | |
3793 | ||
1da177e4 LT |
3794 | /* |
3795 | * IRQs < 16 are already in the irq_2_pin[] map | |
3796 | */ | |
0b8f1efa YL |
3797 | if (irq >= 16) { |
3798 | cfg = desc->chip_data; | |
3799 | add_pin_to_irq_cpu(irq, cpu, ioapic, pin); | |
3800 | } | |
1da177e4 | 3801 | |
497c9a19 | 3802 | setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity); |
1da177e4 LT |
3803 | |
3804 | return 0; | |
3805 | } | |
3806 | ||
54168ed7 | 3807 | |
61fd47e0 SL |
3808 | int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity) |
3809 | { | |
3810 | int i; | |
3811 | ||
3812 | if (skip_ioapic_setup) | |
3813 | return -1; | |
3814 | ||
3815 | for (i = 0; i < mp_irq_entries; i++) | |
2fddb6e2 AS |
3816 | if (mp_irqs[i].mp_irqtype == mp_INT && |
3817 | mp_irqs[i].mp_srcbusirq == bus_irq) | |
61fd47e0 SL |
3818 | break; |
3819 | if (i >= mp_irq_entries) | |
3820 | return -1; | |
3821 | ||
3822 | *trigger = irq_trigger(i); | |
3823 | *polarity = irq_polarity(i); | |
3824 | return 0; | |
3825 | } | |
3826 | ||
888ba6c6 | 3827 | #endif /* CONFIG_ACPI */ |
1a3f239d | 3828 | |
497c9a19 YL |
3829 | /* |
3830 | * This function currently is only a helper for the i386 smp boot process where | |
3831 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
3832 | * so mask in all cases should simply be TARGET_CPUS | |
3833 | */ | |
3834 | #ifdef CONFIG_SMP | |
3835 | void __init setup_ioapic_dest(void) | |
3836 | { | |
3837 | int pin, ioapic, irq, irq_entry; | |
6c2e9403 | 3838 | struct irq_desc *desc; |
497c9a19 | 3839 | struct irq_cfg *cfg; |
6c2e9403 | 3840 | cpumask_t mask; |
497c9a19 YL |
3841 | |
3842 | if (skip_ioapic_setup == 1) | |
3843 | return; | |
3844 | ||
3845 | for (ioapic = 0; ioapic < nr_ioapics; ioapic++) { | |
3846 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { | |
3847 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); | |
3848 | if (irq_entry == -1) | |
3849 | continue; | |
3850 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
3851 | ||
3852 | /* setup_IO_APIC_irqs could fail to get vector for some device | |
3853 | * when you have too many devices, because at that time only boot | |
3854 | * cpu is online. | |
3855 | */ | |
0b8f1efa YL |
3856 | desc = irq_to_desc(irq); |
3857 | cfg = desc->chip_data; | |
6c2e9403 | 3858 | if (!cfg->vector) { |
497c9a19 YL |
3859 | setup_IO_APIC_irq(ioapic, pin, irq, |
3860 | irq_trigger(irq_entry), | |
3861 | irq_polarity(irq_entry)); | |
6c2e9403 TG |
3862 | continue; |
3863 | ||
3864 | } | |
3865 | ||
3866 | /* | |
3867 | * Honour affinities which have been set in early boot | |
3868 | */ | |
6c2e9403 TG |
3869 | if (desc->status & |
3870 | (IRQ_NO_BALANCING | IRQ_AFFINITY_SET)) | |
3871 | mask = desc->affinity; | |
3872 | else | |
3873 | mask = TARGET_CPUS; | |
3874 | ||
54168ed7 | 3875 | #ifdef CONFIG_INTR_REMAP |
6c2e9403 TG |
3876 | if (intr_remapping_enabled) |
3877 | set_ir_ioapic_affinity_irq(irq, mask); | |
54168ed7 | 3878 | else |
6c2e9403 TG |
3879 | #endif |
3880 | set_ioapic_affinity_irq(irq, mask); | |
497c9a19 YL |
3881 | } |
3882 | ||
3883 | } | |
3884 | } | |
3885 | #endif | |
3886 | ||
54168ed7 IM |
3887 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
3888 | ||
3889 | static struct resource *ioapic_resources; | |
3890 | ||
3891 | static struct resource * __init ioapic_setup_resources(void) | |
3892 | { | |
3893 | unsigned long n; | |
3894 | struct resource *res; | |
3895 | char *mem; | |
3896 | int i; | |
3897 | ||
3898 | if (nr_ioapics <= 0) | |
3899 | return NULL; | |
3900 | ||
3901 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); | |
3902 | n *= nr_ioapics; | |
3903 | ||
3904 | mem = alloc_bootmem(n); | |
3905 | res = (void *)mem; | |
3906 | ||
3907 | if (mem != NULL) { | |
3908 | mem += sizeof(struct resource) * nr_ioapics; | |
3909 | ||
3910 | for (i = 0; i < nr_ioapics; i++) { | |
3911 | res[i].name = mem; | |
3912 | res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
3913 | sprintf(mem, "IOAPIC %u", i); | |
3914 | mem += IOAPIC_RESOURCE_NAME_SIZE; | |
3915 | } | |
3916 | } | |
3917 | ||
3918 | ioapic_resources = res; | |
3919 | ||
3920 | return res; | |
3921 | } | |
54168ed7 | 3922 | |
f3294a33 YL |
3923 | void __init ioapic_init_mappings(void) |
3924 | { | |
3925 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
54168ed7 | 3926 | struct resource *ioapic_res; |
d6c88a50 | 3927 | int i; |
f3294a33 | 3928 | |
54168ed7 | 3929 | ioapic_res = ioapic_setup_resources(); |
f3294a33 YL |
3930 | for (i = 0; i < nr_ioapics; i++) { |
3931 | if (smp_found_config) { | |
3932 | ioapic_phys = mp_ioapics[i].mp_apicaddr; | |
54168ed7 | 3933 | #ifdef CONFIG_X86_32 |
d6c88a50 TG |
3934 | if (!ioapic_phys) { |
3935 | printk(KERN_ERR | |
3936 | "WARNING: bogus zero IO-APIC " | |
3937 | "address found in MPTABLE, " | |
3938 | "disabling IO/APIC support!\n"); | |
3939 | smp_found_config = 0; | |
3940 | skip_ioapic_setup = 1; | |
3941 | goto fake_ioapic_page; | |
3942 | } | |
54168ed7 | 3943 | #endif |
f3294a33 | 3944 | } else { |
54168ed7 | 3945 | #ifdef CONFIG_X86_32 |
f3294a33 | 3946 | fake_ioapic_page: |
54168ed7 | 3947 | #endif |
f3294a33 | 3948 | ioapic_phys = (unsigned long) |
54168ed7 | 3949 | alloc_bootmem_pages(PAGE_SIZE); |
f3294a33 YL |
3950 | ioapic_phys = __pa(ioapic_phys); |
3951 | } | |
3952 | set_fixmap_nocache(idx, ioapic_phys); | |
54168ed7 IM |
3953 | apic_printk(APIC_VERBOSE, |
3954 | "mapped IOAPIC to %08lx (%08lx)\n", | |
3955 | __fix_to_virt(idx), ioapic_phys); | |
f3294a33 | 3956 | idx++; |
54168ed7 | 3957 | |
54168ed7 IM |
3958 | if (ioapic_res != NULL) { |
3959 | ioapic_res->start = ioapic_phys; | |
3960 | ioapic_res->end = ioapic_phys + (4 * 1024) - 1; | |
3961 | ioapic_res++; | |
3962 | } | |
f3294a33 YL |
3963 | } |
3964 | } | |
3965 | ||
54168ed7 IM |
3966 | static int __init ioapic_insert_resources(void) |
3967 | { | |
3968 | int i; | |
3969 | struct resource *r = ioapic_resources; | |
3970 | ||
3971 | if (!r) { | |
3972 | printk(KERN_ERR | |
3973 | "IO APIC resources could be not be allocated.\n"); | |
3974 | return -1; | |
3975 | } | |
3976 | ||
3977 | for (i = 0; i < nr_ioapics; i++) { | |
3978 | insert_resource(&iomem_resource, r); | |
3979 | r++; | |
3980 | } | |
3981 | ||
3982 | return 0; | |
3983 | } | |
3984 | ||
3985 | /* Insert the IO APIC resources after PCI initialization has occured to handle | |
3986 | * IO APICS that are mapped in on a BAR in PCI space. */ | |
3987 | late_initcall(ioapic_insert_resources); |