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x86: unify ack_apic_edge
[deliverable/linux.git] / arch / x86 / kernel / io_apic.c
CommitLineData
1da177e4
LT		 1/*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23#include <linux/mm.h>
1da177e4
LT		 24#include <linux/interrupt.h>
25#include <linux/init.h>
26#include <linux/delay.h>
27#include <linux/sched.h>
d4057bdb 28#include <linux/pci.h>
1da177e4
LT		 29#include <linux/mc146818rtc.h>
30#include <linux/compiler.h>
31#include <linux/acpi.h>
129f6946 32#include <linux/module.h>
1da177e4 33#include <linux/sysdev.h>
3b7d1921 34#include <linux/msi.h>
95d77884 35#include <linux/htirq.h>
7dfb7103 36#include <linux/freezer.h>
f26d6a2b 37#include <linux/kthread.h>
54168ed7 38#include <linux/jiffies.h> /* time_after() */
d4057bdb
YL		 39#ifdef CONFIG_ACPI
40#include <acpi/acpi_bus.h>
41#endif
42#include <linux/bootmem.h>
43#include <linux/dmar.h>
54d5d424 44
d4057bdb 45#include <asm/idle.h>
1da177e4
LT		 46#include <asm/io.h>
47#include <asm/smp.h>
48#include <asm/desc.h>
d4057bdb
YL		 49#include <asm/proto.h>
50#include <asm/acpi.h>
51#include <asm/dma.h>
1da177e4 52#include <asm/timer.h>
306e440d 53#include <asm/i8259.h>
3e4ff115 54#include <asm/nmi.h>
2d3fcc1c 55#include <asm/msidef.h>
8b955b0d 56#include <asm/hypertransport.h>
a4dbc34d 57#include <asm/setup.h>
d4057bdb 58#include <asm/irq_remapping.h>
1da177e4 59
497c9a19 60#include <mach_ipi.h>
1da177e4 61#include <mach_apic.h>
874c4fe3 62#include <mach_apicdef.h>
1da177e4 63
32f71aff
MR		 64#define __apicdebuginit(type) static type __init
65
1da177e4 66/*
54168ed7
IM		 67 * Is the SiS APIC rmw bug present ?
68 * -1 = don't know, 0 = no, 1 = yes
1da177e4
LT		 69 */
70int sis_apic_bug = -1;
71
efa2559f
YL		 72static DEFINE_SPINLOCK(ioapic_lock);
73static DEFINE_SPINLOCK(vector_lock);
74
301e6190 75int first_free_entry;
efa2559f
YL		 76/*
77 * Rough estimation of how many shared IRQs there are, can
78 * be changed anytime.
79 */
80int pin_map_size;
81
1da177e4
LT		 82/*
83 * # of IRQ routing registers
84 */
85int nr_ioapic_registers[MAX_IO_APICS];
86
9f640ccb 87/* I/O APIC entries */
ec2cd0a2 88struct mp_config_ioapic mp_ioapics[MAX_IO_APICS];
9f640ccb
AS		 89int nr_ioapics;
90
584f734d 91/* MP IRQ source entries */
2fddb6e2 92struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
584f734d
AS		 93
94/* # of MP IRQ source entries */
95int mp_irq_entries;
96
8732fc4b
AS		 97#if defined (CONFIG_MCA) || defined (CONFIG_EISA)
98int mp_bus_id_to_type[MAX_MP_BUSSES];
99#endif
100
101DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
102
efa2559f
YL		 103int skip_ioapic_setup;
104
54168ed7 105static int __init parse_noapic(char *str)
efa2559f
YL		 106{
107 /* disable IO-APIC */
108 disable_ioapic_setup();
109 return 0;
110}
111early_param("noapic", parse_noapic);
66759a01 112
da51a821 113struct irq_cfg;
0f978f45 114struct irq_pin_list;
a1420f39 115struct irq_cfg {
da51a821
YL		 116 unsigned int irq;
117 struct irq_cfg *next;
0f978f45 118 struct irq_pin_list *irq_2_pin;
497c9a19
YL		 119 cpumask_t domain;
120 cpumask_t old_domain;
121 unsigned move_cleanup_count;
a1420f39 122 u8 vector;
497c9a19 123 u8 move_in_progress : 1;
a1420f39
YL		 124};
125
a1420f39
YL		 126/* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
127static struct irq_cfg irq_cfg_legacy[] __initdata = {
497c9a19
YL		 128 [0] = { .irq = 0, .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
129 [1] = { .irq = 1, .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
130 [2] = { .irq = 2, .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
131 [3] = { .irq = 3, .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
132 [4] = { .irq = 4, .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
133 [5] = { .irq = 5, .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
134 [6] = { .irq = 6, .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
135 [7] = { .irq = 7, .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
136 [8] = { .irq = 8, .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
137 [9] = { .irq = 9, .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
138 [10] = { .irq = 10, .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
139 [11] = { .irq = 11, .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
140 [12] = { .irq = 12, .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
141 [13] = { .irq = 13, .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
142 [14] = { .irq = 14, .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
143 [15] = { .irq = 15, .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
a1420f39
YL		 144};
145
da51a821
YL		 146static struct irq_cfg irq_cfg_init = { .irq = -1U, };
147/* need to be biger than size of irq_cfg_legacy */
148static int nr_irq_cfg = 32;
149
150static int __init parse_nr_irq_cfg(char *arg)
151{
152 if (arg) {
153 nr_irq_cfg = simple_strtoul(arg, NULL, 0);
154 if (nr_irq_cfg < 32)
155 nr_irq_cfg = 32;
156 }
157 return 0;
158}
159
160early_param("nr_irq_cfg", parse_nr_irq_cfg);
161
162static void init_one_irq_cfg(struct irq_cfg *cfg)
163{
164 memcpy(cfg, &irq_cfg_init, sizeof(struct irq_cfg));
165}
166
167static struct irq_cfg *irq_cfgx;
168static struct irq_cfg *irq_cfgx_free;
a1420f39
YL		 169static void __init init_work(void *data)
170{
da51a821
YL		 171 struct dyn_array *da = data;
172 struct irq_cfg *cfg;
173 int legacy_count;
174 int i;
175
176 cfg = *da->name;
a1420f39 177
da51a821 178 memcpy(cfg, irq_cfg_legacy, sizeof(irq_cfg_legacy));
a1420f39 179
da51a821
YL		 180 legacy_count = sizeof(irq_cfg_legacy)/sizeof(irq_cfg_legacy[0]);
181 for (i = legacy_count; i < *da->nr; i++)
182 init_one_irq_cfg(&cfg[i]);
a1420f39 183
da51a821
YL		 184 for (i = 1; i < *da->nr; i++)
185 cfg[i-1].next = &cfg[i];
a1420f39 186
da51a821
YL		 187 irq_cfgx_free = &irq_cfgx[legacy_count];
188 irq_cfgx[legacy_count - 1].next = NULL;
a1420f39
YL		 189}
190
54168ed7 191#define for_each_irq_cfg(cfg) \
da51a821
YL		 192 for (cfg = irq_cfgx; cfg; cfg = cfg->next)
193
194DEFINE_DYN_ARRAY(irq_cfgx, sizeof(struct irq_cfg), nr_irq_cfg, PAGE_SIZE, init_work);
a1420f39
YL		 195
196static struct irq_cfg *irq_cfg(unsigned int irq)
197{
da51a821
YL		 198 struct irq_cfg *cfg;
199
200 cfg = irq_cfgx;
201 while (cfg) {
202 if (cfg->irq == irq)
203 return cfg;
204
205 cfg = cfg->next;
206 }
207
208 return NULL;
209}
210
211static struct irq_cfg *irq_cfg_alloc(unsigned int irq)
212{
213 struct irq_cfg *cfg, *cfg_pri;
214 int i;
215 int count = 0;
216
217 cfg_pri = cfg = irq_cfgx;
218 while (cfg) {
219 if (cfg->irq == irq)
220 return cfg;
221
222 cfg_pri = cfg;
223 cfg = cfg->next;
224 count++;
225 }
226
227 if (!irq_cfgx_free) {
228 unsigned long phys;
229 unsigned long total_bytes;
230 /*
231 * we run out of pre-allocate ones, allocate more
232 */
233 printk(KERN_DEBUG "try to get more irq_cfg %d\n", nr_irq_cfg);
234
235 total_bytes = sizeof(struct irq_cfg) * nr_irq_cfg;
236 if (after_bootmem)
237 cfg = kzalloc(total_bytes, GFP_ATOMIC);
238 else
239 cfg = __alloc_bootmem_nopanic(total_bytes, PAGE_SIZE, 0);
a1420f39 240
da51a821
YL		 241 if (!cfg)
242 panic("please boot with nr_irq_cfg= %d\n", count * 2);
243
244 phys = __pa(cfg);
245 printk(KERN_DEBUG "irq_irq ==> [%#lx - %#lx]\n", phys, phys + total_bytes);
246
247 for (i = 0; i < nr_irq_cfg; i++)
248 init_one_irq_cfg(&cfg[i]);
249
250 for (i = 1; i < nr_irq_cfg; i++)
251 cfg[i-1].next = &cfg[i];
252
253 irq_cfgx_free = cfg;
254 }
255
256 cfg = irq_cfgx_free;
257 irq_cfgx_free = irq_cfgx_free->next;
258 cfg->next = NULL;
259 if (cfg_pri)
260 cfg_pri->next = cfg;
261 else
262 irq_cfgx = cfg;
263 cfg->irq = irq;
264 printk(KERN_DEBUG "found new irq_cfg for irq %d\n", cfg->irq);
da51a821
YL		 265#ifdef CONFIG_HAVE_SPARSE_IRQ_DEBUG
266 {
267 /* dump the results */
268 struct irq_cfg *cfg;
269 unsigned long phys;
270 unsigned long bytes = sizeof(struct irq_cfg);
271
272 printk(KERN_DEBUG "=========================== %d\n", irq);
273 printk(KERN_DEBUG "irq_cfg dump after get that for %d\n", irq);
274 for_each_irq_cfg(cfg) {
275 phys = __pa(cfg);
276 printk(KERN_DEBUG "irq_cfg %d ==> [%#lx - %#lx]\n", cfg->irq, phys, phys + bytes);
277 }
278 printk(KERN_DEBUG "===========================\n");
279 }
280#endif
281 return cfg;
a1420f39
YL		 282}
283
1da177e4
LT		 284/*
285 * This is performance-critical, we want to do it O(1)
286 *
287 * the indexing order of this array favors 1:1 mappings
288 * between pins and IRQs.
289 */
290
0f978f45
YL		 291struct irq_pin_list {
292 int apic, pin;
293 struct irq_pin_list *next;
294};
295
296static struct irq_pin_list *irq_2_pin_head;
297/* fill one page ? */
298static int nr_irq_2_pin = 0x100;
299static struct irq_pin_list *irq_2_pin_ptr;
300static void __init irq_2_pin_init_work(void *data)
301{
302 struct dyn_array *da = data;
303 struct irq_pin_list *pin;
304 int i;
305
306 pin = *da->name;
307
308 for (i = 1; i < *da->nr; i++)
309 pin[i-1].next = &pin[i];
310
311 irq_2_pin_ptr = &pin[0];
312}
313DEFINE_DYN_ARRAY(irq_2_pin_head, sizeof(struct irq_pin_list), nr_irq_2_pin, PAGE_SIZE, irq_2_pin_init_work);
314
315static struct irq_pin_list *get_one_free_irq_2_pin(void)
316{
317 struct irq_pin_list *pin;
318 int i;
319
320 pin = irq_2_pin_ptr;
321
322 if (pin) {
323 irq_2_pin_ptr = pin->next;
324 pin->next = NULL;
325 return pin;
326 }
327
328 /*
329 * we run out of pre-allocate ones, allocate more
330 */
331 printk(KERN_DEBUG "try to get more irq_2_pin %d\n", nr_irq_2_pin);
332
333 if (after_bootmem)
334 pin = kzalloc(sizeof(struct irq_pin_list)*nr_irq_2_pin,
335 GFP_ATOMIC);
336 else
337 pin = __alloc_bootmem_nopanic(sizeof(struct irq_pin_list) *
338 nr_irq_2_pin, PAGE_SIZE, 0);
339
340 if (!pin)
341 panic("can not get more irq_2_pin\n");
301e6190 342
0f978f45
YL		 343 for (i = 1; i < nr_irq_2_pin; i++)
344 pin[i-1].next = &pin[i];
345
346 irq_2_pin_ptr = pin->next;
347 pin->next = NULL;
348
349 return pin;
350}
1da177e4 351
130fe05d
LT		 352struct io_apic {
353 unsigned int index;
354 unsigned int unused[3];
355 unsigned int data;
356};
357
358static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
359{
360 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
ec2cd0a2 361 + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK);
130fe05d
LT		 362}
363
364static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
365{
366 struct io_apic __iomem *io_apic = io_apic_base(apic);
367 writel(reg, &io_apic->index);
368 return readl(&io_apic->data);
369}
370
371static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
372{
373 struct io_apic __iomem *io_apic = io_apic_base(apic);
374 writel(reg, &io_apic->index);
375 writel(value, &io_apic->data);
376}
377
378/*
379 * Re-write a value: to be used for read-modify-write
380 * cycles where the read already set up the index register.
381 *
382 * Older SiS APIC requires we rewrite the index register
383 */
384static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
385{
54168ed7
IM		 386 struct io_apic __iomem *io_apic = io_apic_base(apic);
387 if (sis_apic_bug)
388 writel(reg, &io_apic->index);
130fe05d
LT		 389 writel(value, &io_apic->data);
390}
391
047c8fdb
YL		 392static bool io_apic_level_ack_pending(unsigned int irq)
393{
394 struct irq_pin_list *entry;
395 unsigned long flags;
396 struct irq_cfg *cfg = irq_cfg(irq);
397
398 spin_lock_irqsave(&ioapic_lock, flags);
399 entry = cfg->irq_2_pin;
400 for (;;) {
401 unsigned int reg;
402 int pin;
403
404 if (!entry)
405 break;
406 pin = entry->pin;
407 reg = io_apic_read(entry->apic, 0x10 + pin*2);
408 /* Is the remote IRR bit set? */
409 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
410 spin_unlock_irqrestore(&ioapic_lock, flags);
411 return true;
412 }
413 if (!entry->next)
414 break;
415 entry = entry->next;
416 }
417 spin_unlock_irqrestore(&ioapic_lock, flags);
418
419 return false;
420}
047c8fdb 421
cf4c6a2f
AK		 422union entry_union {
423 struct { u32 w1, w2; };
424 struct IO_APIC_route_entry entry;
425};
426
427static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
428{
429 union entry_union eu;
430 unsigned long flags;
431 spin_lock_irqsave(&ioapic_lock, flags);
432 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
433 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
434 spin_unlock_irqrestore(&ioapic_lock, flags);
435 return eu.entry;
436}
437
f9dadfa7
LT		 438/*
439 * When we write a new IO APIC routing entry, we need to write the high
440 * word first! If the mask bit in the low word is clear, we will enable
441 * the interrupt, and we need to make sure the entry is fully populated
442 * before that happens.
443 */
d15512f4
AK		 444static void
445__ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
cf4c6a2f 446{
cf4c6a2f
AK		 447 union entry_union eu;
448 eu.entry = e;
f9dadfa7
LT		 449 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
450 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
d15512f4
AK		 451}
452
453static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
454{
455 unsigned long flags;
456 spin_lock_irqsave(&ioapic_lock, flags);
457 __ioapic_write_entry(apic, pin, e);
f9dadfa7
LT		 458 spin_unlock_irqrestore(&ioapic_lock, flags);
459}
460
461/*
462 * When we mask an IO APIC routing entry, we need to write the low
463 * word first, in order to set the mask bit before we change the
464 * high bits!
465 */
466static void ioapic_mask_entry(int apic, int pin)
467{
468 unsigned long flags;
469 union entry_union eu = { .entry.mask = 1 };
470
cf4c6a2f
AK		 471 spin_lock_irqsave(&ioapic_lock, flags);
472 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
473 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
474 spin_unlock_irqrestore(&ioapic_lock, flags);
475}
476
497c9a19
YL		 477#ifdef CONFIG_SMP
478static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
479{
480 int apic, pin;
481 struct irq_cfg *cfg;
482 struct irq_pin_list *entry;
483
484 cfg = irq_cfg(irq);
485 entry = cfg->irq_2_pin;
486 for (;;) {
487 unsigned int reg;
488
489 if (!entry)
490 break;
491
492 apic = entry->apic;
493 pin = entry->pin;
54168ed7
IM		 494#ifdef CONFIG_INTR_REMAP
495 /*
496 * With interrupt-remapping, destination information comes
497 * from interrupt-remapping table entry.
498 */
499 if (!irq_remapped(irq))
500 io_apic_write(apic, 0x11 + pin*2, dest);
501#else
497c9a19 502 io_apic_write(apic, 0x11 + pin*2, dest);
54168ed7 503#endif
497c9a19
YL		 504 reg = io_apic_read(apic, 0x10 + pin*2);
505 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
506 reg |= vector;
54168ed7 507 io_apic_modify(apic, 0x10 + pin*2, reg);
497c9a19
YL		 508 if (!entry->next)
509 break;
510 entry = entry->next;
511 }
512}
efa2559f
YL		 513
514static int assign_irq_vector(int irq, cpumask_t mask);
515
497c9a19
YL		 516static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
517{
518 struct irq_cfg *cfg;
519 unsigned long flags;
520 unsigned int dest;
521 cpumask_t tmp;
54168ed7 522 struct irq_desc *desc;
497c9a19 523
497c9a19
YL		 524 cpus_and(tmp, mask, cpu_online_map);
525 if (cpus_empty(tmp))
526 return;
527
047c8fdb 528 cfg = irq_cfg(irq);
497c9a19
YL		 529 if (assign_irq_vector(irq, mask))
530 return;
531
532 cpus_and(tmp, cfg->domain, mask);
497c9a19
YL		 533 dest = cpu_mask_to_apicid(tmp);
534 /*
535 * Only the high 8 bits are valid.
536 */
537 dest = SET_APIC_LOGICAL_ID(dest);
538
54168ed7 539 desc = irq_to_desc(irq);
497c9a19
YL		 540 spin_lock_irqsave(&ioapic_lock, flags);
541 __target_IO_APIC_irq(irq, dest, cfg->vector);
54168ed7 542 desc->affinity = mask;
497c9a19
YL		 543 spin_unlock_irqrestore(&ioapic_lock, flags);
544}
497c9a19
YL		 545#endif /* CONFIG_SMP */
546
1da177e4
LT		 547/*
548 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
549 * shared ISA-space IRQs, so we have to support them. We are super
550 * fast in the common case, and fast for shared ISA-space IRQs.
551 */
552static void add_pin_to_irq(unsigned int irq, int apic, int pin)
553{
0f978f45
YL		 554 struct irq_cfg *cfg;
555 struct irq_pin_list *entry;
556
557 /* first time to refer irq_cfg, so with new */
558 cfg = irq_cfg_alloc(irq);
559 entry = cfg->irq_2_pin;
560 if (!entry) {
561 entry = get_one_free_irq_2_pin();
562 cfg->irq_2_pin = entry;
563 entry->apic = apic;
564 entry->pin = pin;
565 printk(KERN_DEBUG " 0 add_pin_to_irq: irq %d --> apic %d pin %d\n", irq, apic, pin);
566 return;
567 }
1da177e4 568
0f978f45
YL		 569 while (entry->next) {
570 /* not again, please */
571 if (entry->apic == apic && entry->pin == pin)
572 return;
1da177e4 573
0f978f45 574 entry = entry->next;
1da177e4 575 }
0f978f45
YL		 576
577 entry->next = get_one_free_irq_2_pin();
578 entry = entry->next;
1da177e4
LT		 579 entry->apic = apic;
580 entry->pin = pin;
0f978f45 581 printk(KERN_DEBUG " x add_pin_to_irq: irq %d --> apic %d pin %d\n", irq, apic, pin);
1da177e4
LT		 582}
583
584/*
585 * Reroute an IRQ to a different pin.
586 */
587static void __init replace_pin_at_irq(unsigned int irq,
588 int oldapic, int oldpin,
589 int newapic, int newpin)
590{
0f978f45
YL		 591 struct irq_cfg *cfg = irq_cfg(irq);
592 struct irq_pin_list *entry = cfg->irq_2_pin;
593 int replaced = 0;
1da177e4 594
0f978f45 595 while (entry) {
1da177e4
LT		 596 if (entry->apic == oldapic && entry->pin == oldpin) {
597 entry->apic = newapic;
598 entry->pin = newpin;
0f978f45
YL		 599 replaced = 1;
600 /* every one is different, right? */
1da177e4 601 break;
0f978f45
YL		 602 }
603 entry = entry->next;
1da177e4 604 }
0f978f45
YL		 605
606 /* why? call replace before add? */
607 if (!replaced)
608 add_pin_to_irq(irq, newapic, newpin);
1da177e4
LT		 609}
610
4e738e2f 611#define __DO_ACTION(R, ACTION_ENABLE, ACTION_DISABLE, FINAL) \
047c8fdb
YL		 612 \
613{ \
614 int pin; \
615 struct irq_cfg *cfg; \
616 struct irq_pin_list *entry; \
617 \
618 cfg = irq_cfg(irq); \
619 entry = cfg->irq_2_pin; \
620 for (;;) { \
621 unsigned int reg; \
622 if (!entry) \
623 break; \
624 pin = entry->pin; \
625 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
4e738e2f
YL		 626 reg ACTION_DISABLE; \
627 reg ACTION_ENABLE; \
047c8fdb
YL		 628 io_apic_modify(entry->apic, 0x10 + R + pin*2, reg); \
629 FINAL; \
630 if (!entry->next) \
631 break; \
632 entry = entry->next; \
633 } \
634}
635
4e738e2f 636#define DO_ACTION(name,R, ACTION_ENABLE, ACTION_DISABLE, FINAL) \
047c8fdb
YL		 637 \
638 static void name##_IO_APIC_irq (unsigned int irq) \
4e738e2f 639 __DO_ACTION(R, ACTION_ENABLE, ACTION_DISABLE, FINAL)
047c8fdb
YL		 640
641/* mask = 0 */
4e738e2f 642DO_ACTION(__unmask, 0, |= 0, &= ~IO_APIC_REDIR_MASKED, )
047c8fdb 643
4e738e2f
YL		 644#ifdef CONFIG_X86_64
645/*
646 * Synchronize the IO-APIC and the CPU by doing
647 * a dummy read from the IO-APIC
648 */
649static inline void io_apic_sync(unsigned int apic)
1da177e4 650{
4e738e2f
YL		 651 struct io_apic __iomem *io_apic = io_apic_base(apic);
652 readl(&io_apic->data);
1da177e4
LT		 653}
654
655/* mask = 1 */
4e738e2f 656DO_ACTION(__mask, 0, |= IO_APIC_REDIR_MASKED, &= ~0, io_apic_sync(entry->apic))
1da177e4 657
4e738e2f
YL		 658#else
659
660/* mask = 1 */
661DO_ACTION(__mask, 0, |= IO_APIC_REDIR_MASKED, &= ~0, )
1da177e4
LT		 662
663/* mask = 1, trigger = 0 */
4e738e2f 664DO_ACTION(__mask_and_edge, 0, |= IO_APIC_REDIR_MASKED, &= ~IO_APIC_REDIR_LEVEL_TRIGGER, )
1da177e4
LT		 665
666/* mask = 0, trigger = 1 */
4e738e2f 667DO_ACTION(__unmask_and_level, 0, |= IO_APIC_REDIR_LEVEL_TRIGGER, &= ~IO_APIC_REDIR_MASKED, )
1da177e4 668
047c8fdb
YL		 669#endif
670
54168ed7 671static void mask_IO_APIC_irq (unsigned int irq)
1da177e4
LT		 672{
673 unsigned long flags;
674
675 spin_lock_irqsave(&ioapic_lock, flags);
676 __mask_IO_APIC_irq(irq);
677 spin_unlock_irqrestore(&ioapic_lock, flags);
678}
679
54168ed7 680static void unmask_IO_APIC_irq (unsigned int irq)
1da177e4
LT		 681{
682 unsigned long flags;
683
684 spin_lock_irqsave(&ioapic_lock, flags);
685 __unmask_IO_APIC_irq(irq);
686 spin_unlock_irqrestore(&ioapic_lock, flags);
687}
688
689static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
690{
691 struct IO_APIC_route_entry entry;
36062448 692
1da177e4 693 /* Check delivery_mode to be sure we're not clearing an SMI pin */
cf4c6a2f 694 entry = ioapic_read_entry(apic, pin);
1da177e4
LT		 695 if (entry.delivery_mode == dest_SMI)
696 return;
1da177e4
LT		 697 /*
698 * Disable it in the IO-APIC irq-routing table:
699 */
f9dadfa7 700 ioapic_mask_entry(apic, pin);
1da177e4
LT		 701}
702
54168ed7 703static void clear_IO_APIC (void)
1da177e4
LT		 704{
705 int apic, pin;
706
707 for (apic = 0; apic < nr_ioapics; apic++)
708 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
709 clear_IO_APIC_pin(apic, pin);
710}
711
54168ed7 712#if !defined(CONFIG_SMP) && defined(CONFIG_X86_32)
75604d7f 713void send_IPI_self(int vector)
1da177e4
LT		 714{
715 unsigned int cfg;
716
717 /*
718 * Wait for idle.
719 */
720 apic_wait_icr_idle();
721 cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
722 /*
723 * Send the IPI. The write to APIC_ICR fires this off.
724 */
593f4a78 725 apic_write(APIC_ICR, cfg);
1da177e4 726}
54168ed7 727#endif /* !CONFIG_SMP && CONFIG_X86_32*/
1da177e4 728
54168ed7 729#ifdef CONFIG_X86_32
1da177e4
LT		 730/*
731 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
732 * specific CPU-side IRQs.
733 */
734
735#define MAX_PIRQS 8
736static int pirq_entries [MAX_PIRQS];
737static int pirqs_enabled;
1da177e4 738
1da177e4
LT		 739static int __init ioapic_pirq_setup(char *str)
740{
741 int i, max;
742 int ints[MAX_PIRQS+1];
743
744 get_options(str, ARRAY_SIZE(ints), ints);
745
746 for (i = 0; i < MAX_PIRQS; i++)
747 pirq_entries[i] = -1;
748
749 pirqs_enabled = 1;
750 apic_printk(APIC_VERBOSE, KERN_INFO
751 "PIRQ redirection, working around broken MP-BIOS.\n");
752 max = MAX_PIRQS;
753 if (ints[0] < MAX_PIRQS)
754 max = ints[0];
755
756 for (i = 0; i < max; i++) {
757 apic_printk(APIC_VERBOSE, KERN_DEBUG
758 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
759 /*
760 * PIRQs are mapped upside down, usually.
761 */
762 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
763 }
764 return 1;
765}
766
767__setup("pirq=", ioapic_pirq_setup);
54168ed7
IM		 768#endif /* CONFIG_X86_32 */
769
770#ifdef CONFIG_INTR_REMAP
771/* I/O APIC RTE contents at the OS boot up */
772static struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS];
773
774/*
775 * Saves and masks all the unmasked IO-APIC RTE's
776 */
777int save_mask_IO_APIC_setup(void)
778{
779 union IO_APIC_reg_01 reg_01;
780 unsigned long flags;
781 int apic, pin;
782
783 /*
784 * The number of IO-APIC IRQ registers (== #pins):
785 */
786 for (apic = 0; apic < nr_ioapics; apic++) {
787 spin_lock_irqsave(&ioapic_lock, flags);
788 reg_01.raw = io_apic_read(apic, 1);
789 spin_unlock_irqrestore(&ioapic_lock, flags);
790 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
791 }
792
793 for (apic = 0; apic < nr_ioapics; apic++) {
794 early_ioapic_entries[apic] =
795 kzalloc(sizeof(struct IO_APIC_route_entry) *
796 nr_ioapic_registers[apic], GFP_KERNEL);
797 if (!early_ioapic_entries[apic])
798 return -ENOMEM;
799 }
800
801 for (apic = 0; apic < nr_ioapics; apic++)
802 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
803 struct IO_APIC_route_entry entry;
804
805 entry = early_ioapic_entries[apic][pin] =
806 ioapic_read_entry(apic, pin);
807 if (!entry.mask) {
808 entry.mask = 1;
809 ioapic_write_entry(apic, pin, entry);
810 }
811 }
812 return 0;
813}
814
815void restore_IO_APIC_setup(void)
816{
817 int apic, pin;
818
819 for (apic = 0; apic < nr_ioapics; apic++)
820 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
821 ioapic_write_entry(apic, pin,
822 early_ioapic_entries[apic][pin]);
823}
824
825void reinit_intr_remapped_IO_APIC(int intr_remapping)
826{
827 /*
828 * for now plain restore of previous settings.
829 * TBD: In the case of OS enabling interrupt-remapping,
830 * IO-APIC RTE's need to be setup to point to interrupt-remapping
831 * table entries. for now, do a plain restore, and wait for
832 * the setup_IO_APIC_irqs() to do proper initialization.
833 */
834 restore_IO_APIC_setup();
835}
836#endif
1da177e4
LT		 837
838/*
839 * Find the IRQ entry number of a certain pin.
840 */
841static int find_irq_entry(int apic, int pin, int type)
842{
843 int i;
844
845 for (i = 0; i < mp_irq_entries; i++)
2fddb6e2
AS		 846 if (mp_irqs[i].mp_irqtype == type &&
847 (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid ||
848 mp_irqs[i].mp_dstapic == MP_APIC_ALL) &&
849 mp_irqs[i].mp_dstirq == pin)
1da177e4
LT		 850 return i;
851
852 return -1;
853}
854
855/*
856 * Find the pin to which IRQ[irq] (ISA) is connected
857 */
fcfd636a 858static int __init find_isa_irq_pin(int irq, int type)
1da177e4
LT		 859{
860 int i;
861
862 for (i = 0; i < mp_irq_entries; i++) {
2fddb6e2 863 int lbus = mp_irqs[i].mp_srcbus;
1da177e4 864
d27e2b8e 865 if (test_bit(lbus, mp_bus_not_pci) &&
2fddb6e2
AS		 866 (mp_irqs[i].mp_irqtype == type) &&
867 (mp_irqs[i].mp_srcbusirq == irq))
1da177e4 868
2fddb6e2 869 return mp_irqs[i].mp_dstirq;
1da177e4
LT		 870 }
871 return -1;
872}
873
fcfd636a
EB		 874static int __init find_isa_irq_apic(int irq, int type)
875{
876 int i;
877
878 for (i = 0; i < mp_irq_entries; i++) {
2fddb6e2 879 int lbus = mp_irqs[i].mp_srcbus;
fcfd636a 880
73b2961b 881 if (test_bit(lbus, mp_bus_not_pci) &&
2fddb6e2
AS		 882 (mp_irqs[i].mp_irqtype == type) &&
883 (mp_irqs[i].mp_srcbusirq == irq))
fcfd636a
EB		 884 break;
885 }
886 if (i < mp_irq_entries) {
887 int apic;
54168ed7 888 for(apic = 0; apic < nr_ioapics; apic++) {
2fddb6e2 889 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic)
fcfd636a
EB		 890 return apic;
891 }
892 }
893
894 return -1;
895}
896
1da177e4
LT		 897/*
898 * Find a specific PCI IRQ entry.
899 * Not an __init, possibly needed by modules
900 */
901static int pin_2_irq(int idx, int apic, int pin);
902
903int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
904{
905 int apic, i, best_guess = -1;
906
54168ed7
IM		 907 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
908 bus, slot, pin);
ce6444d3 909 if (test_bit(bus, mp_bus_not_pci)) {
54168ed7 910 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1da177e4
LT		 911 return -1;
912 }
913 for (i = 0; i < mp_irq_entries; i++) {
2fddb6e2 914 int lbus = mp_irqs[i].mp_srcbus;
1da177e4
LT		 915
916 for (apic = 0; apic < nr_ioapics; apic++)
2fddb6e2
AS		 917 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic ||
918 mp_irqs[i].mp_dstapic == MP_APIC_ALL)
1da177e4
LT		 919 break;
920
47cab822 921 if (!test_bit(lbus, mp_bus_not_pci) &&
2fddb6e2 922 !mp_irqs[i].mp_irqtype &&
1da177e4 923 (bus == lbus) &&
2fddb6e2 924 (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) {
54168ed7 925 int irq = pin_2_irq(i,apic,mp_irqs[i].mp_dstirq);
1da177e4
LT		 926
927 if (!(apic || IO_APIC_IRQ(irq)))
928 continue;
929
2fddb6e2 930 if (pin == (mp_irqs[i].mp_srcbusirq & 3))
1da177e4
LT		 931 return irq;
932 /*
933 * Use the first all-but-pin matching entry as a
934 * best-guess fuzzy result for broken mptables.
935 */
936 if (best_guess < 0)
937 best_guess = irq;
938 }
939 }
940 return best_guess;
941}
54168ed7 942
129f6946 943EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1da177e4 944
c0a282c2 945#if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1da177e4
LT		 946/*
947 * EISA Edge/Level control register, ELCR
948 */
949static int EISA_ELCR(unsigned int irq)
950{
951 if (irq < 16) {
952 unsigned int port = 0x4d0 + (irq >> 3);
953 return (inb(port) >> (irq & 7)) & 1;
954 }
955 apic_printk(APIC_VERBOSE, KERN_INFO
956 "Broken MPtable reports ISA irq %d\n", irq);
957 return 0;
958}
54168ed7 959
c0a282c2 960#endif
1da177e4 961
6728801d
AS		 962/* ISA interrupts are always polarity zero edge triggered,
963 * when listed as conforming in the MP table. */
964
965#define default_ISA_trigger(idx) (0)
966#define default_ISA_polarity(idx) (0)
967
1da177e4
LT		 968/* EISA interrupts are always polarity zero and can be edge or level
969 * trigger depending on the ELCR value. If an interrupt is listed as
970 * EISA conforming in the MP table, that means its trigger type must
971 * be read in from the ELCR */
972
2fddb6e2 973#define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq))
6728801d 974#define default_EISA_polarity(idx) default_ISA_polarity(idx)
1da177e4
LT		 975
976/* PCI interrupts are always polarity one level triggered,
977 * when listed as conforming in the MP table. */
978
979#define default_PCI_trigger(idx) (1)
980#define default_PCI_polarity(idx) (1)
981
982/* MCA interrupts are always polarity zero level triggered,
983 * when listed as conforming in the MP table. */
984
985#define default_MCA_trigger(idx) (1)
6728801d 986#define default_MCA_polarity(idx) default_ISA_polarity(idx)
1da177e4 987
61fd47e0 988static int MPBIOS_polarity(int idx)
1da177e4 989{
2fddb6e2 990 int bus = mp_irqs[idx].mp_srcbus;
1da177e4
LT		 991 int polarity;
992
993 /*
994 * Determine IRQ line polarity (high active or low active):
995 */
54168ed7 996 switch (mp_irqs[idx].mp_irqflag & 3)
36062448 997 {
54168ed7
IM		 998 case 0: /* conforms, ie. bus-type dependent polarity */
999 if (test_bit(bus, mp_bus_not_pci))
1000 polarity = default_ISA_polarity(idx);
1001 else
1002 polarity = default_PCI_polarity(idx);
1003 break;
1004 case 1: /* high active */
1005 {
1006 polarity = 0;
1007 break;
1008 }
1009 case 2: /* reserved */
1010 {
1011 printk(KERN_WARNING "broken BIOS!!\n");
1012 polarity = 1;
1013 break;
1014 }
1015 case 3: /* low active */
1016 {
1017 polarity = 1;
1018 break;
1019 }
1020 default: /* invalid */
1021 {
1022 printk(KERN_WARNING "broken BIOS!!\n");
1023 polarity = 1;
1024 break;
1025 }
1da177e4
LT		 1026 }
1027 return polarity;
1028}
1029
1030static int MPBIOS_trigger(int idx)
1031{
2fddb6e2 1032 int bus = mp_irqs[idx].mp_srcbus;
1da177e4
LT		 1033 int trigger;
1034
1035 /*
1036 * Determine IRQ trigger mode (edge or level sensitive):
1037 */
54168ed7 1038 switch ((mp_irqs[idx].mp_irqflag>>2) & 3)
1da177e4 1039 {
54168ed7
IM		 1040 case 0: /* conforms, ie. bus-type dependent */
1041 if (test_bit(bus, mp_bus_not_pci))
1042 trigger = default_ISA_trigger(idx);
1043 else
1044 trigger = default_PCI_trigger(idx);
c0a282c2 1045#if defined(CONFIG_EISA) || defined(CONFIG_MCA)
54168ed7
IM		 1046 switch (mp_bus_id_to_type[bus]) {
1047 case MP_BUS_ISA: /* ISA pin */
1048 {
1049 /* set before the switch */
1050 break;
1051 }
1052 case MP_BUS_EISA: /* EISA pin */
1053 {
1054 trigger = default_EISA_trigger(idx);
1055 break;
1056 }
1057 case MP_BUS_PCI: /* PCI pin */
1058 {
1059 /* set before the switch */
1060 break;
1061 }
1062 case MP_BUS_MCA: /* MCA pin */
1063 {
1064 trigger = default_MCA_trigger(idx);
1065 break;
1066 }
1067 default:
1068 {
1069 printk(KERN_WARNING "broken BIOS!!\n");
1070 trigger = 1;
1071 break;
1072 }
1073 }
1074#endif
1da177e4 1075 break;
54168ed7 1076 case 1: /* edge */
1da177e4 1077 {
54168ed7 1078 trigger = 0;
1da177e4
LT		 1079 break;
1080 }
54168ed7 1081 case 2: /* reserved */
1da177e4 1082 {
54168ed7
IM		 1083 printk(KERN_WARNING "broken BIOS!!\n");
1084 trigger = 1;
1da177e4
LT		 1085 break;
1086 }
54168ed7 1087 case 3: /* level */
1da177e4 1088 {
54168ed7 1089 trigger = 1;
1da177e4
LT		 1090 break;
1091 }
54168ed7 1092 default: /* invalid */
1da177e4
LT		 1093 {
1094 printk(KERN_WARNING "broken BIOS!!\n");
54168ed7 1095 trigger = 0;
1da177e4
LT		 1096 break;
1097 }
1098 }
1099 return trigger;
1100}
1101
1102static inline int irq_polarity(int idx)
1103{
1104 return MPBIOS_polarity(idx);
1105}
1106
1107static inline int irq_trigger(int idx)
1108{
1109 return MPBIOS_trigger(idx);
1110}
1111
efa2559f 1112int (*ioapic_renumber_irq)(int ioapic, int irq);
1da177e4
LT		 1113static int pin_2_irq(int idx, int apic, int pin)
1114{
1115 int irq, i;
2fddb6e2 1116 int bus = mp_irqs[idx].mp_srcbus;
1da177e4
LT		 1117
1118 /*
1119 * Debugging check, we are in big trouble if this message pops up!
1120 */
2fddb6e2 1121 if (mp_irqs[idx].mp_dstirq != pin)
1da177e4
LT		 1122 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1123
54168ed7 1124 if (test_bit(bus, mp_bus_not_pci)) {
2fddb6e2 1125 irq = mp_irqs[idx].mp_srcbusirq;
54168ed7 1126 } else {
643befed
AS		 1127 /*
1128 * PCI IRQs are mapped in order
1129 */
1130 i = irq = 0;
1131 while (i < apic)
1132 irq += nr_ioapic_registers[i++];
1133 irq += pin;
54168ed7
IM		 1134 /*
1135 * For MPS mode, so far only needed by ES7000 platform
1136 */
1137 if (ioapic_renumber_irq)
1138 irq = ioapic_renumber_irq(apic, irq);
1da177e4
LT		 1139 }
1140
54168ed7 1141#ifdef CONFIG_X86_32
1da177e4
LT		 1142 /*
1143 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1144 */
1145 if ((pin >= 16) && (pin <= 23)) {
1146 if (pirq_entries[pin-16] != -1) {
1147 if (!pirq_entries[pin-16]) {
1148 apic_printk(APIC_VERBOSE, KERN_DEBUG
1149 "disabling PIRQ%d\n", pin-16);
1150 } else {
1151 irq = pirq_entries[pin-16];
1152 apic_printk(APIC_VERBOSE, KERN_DEBUG
1153 "using PIRQ%d -> IRQ %d\n",
1154 pin-16, irq);
1155 }
1156 }
1157 }
54168ed7
IM		 1158#endif
1159
1da177e4
LT		 1160 return irq;
1161}
1162
497c9a19
YL		 1163void lock_vector_lock(void)
1164{
1165 /* Used to the online set of cpus does not change
1166 * during assign_irq_vector.
1167 */
1168 spin_lock(&vector_lock);
1169}
1da177e4 1170
497c9a19 1171void unlock_vector_lock(void)
1da177e4 1172{
497c9a19
YL		 1173 spin_unlock(&vector_lock);
1174}
1da177e4 1175
497c9a19
YL		 1176static int __assign_irq_vector(int irq, cpumask_t mask)
1177{
047c8fdb
YL		 1178 /*
1179 * NOTE! The local APIC isn't very good at handling
1180 * multiple interrupts at the same interrupt level.
1181 * As the interrupt level is determined by taking the
1182 * vector number and shifting that right by 4, we
1183 * want to spread these out a bit so that they don't
1184 * all fall in the same interrupt level.
1185 *
1186 * Also, we've got to be careful not to trash gate
1187 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1188 */
54168ed7
IM		 1189 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1190 unsigned int old_vector;
1191 int cpu;
1192 struct irq_cfg *cfg;
ace80ab7 1193
54168ed7 1194 cfg = irq_cfg(irq);
8339f000 1195
54168ed7
IM		 1196 /* Only try and allocate irqs on cpus that are present */
1197 cpus_and(mask, mask, cpu_online_map);
ace80ab7 1198
54168ed7
IM		 1199 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1200 return -EBUSY;
0a1ad60d 1201
54168ed7
IM		 1202 old_vector = cfg->vector;
1203 if (old_vector) {
1204 cpumask_t tmp;
1205 cpus_and(tmp, cfg->domain, mask);
1206 if (!cpus_empty(tmp))
1207 return 0;
1208 }
497c9a19 1209
54168ed7
IM		 1210 for_each_cpu_mask_nr(cpu, mask) {
1211 cpumask_t domain, new_mask;
1212 int new_cpu;
1213 int vector, offset;
497c9a19 1214
54168ed7
IM		 1215 domain = vector_allocation_domain(cpu);
1216 cpus_and(new_mask, domain, cpu_online_map);
497c9a19 1217
54168ed7
IM		 1218 vector = current_vector;
1219 offset = current_offset;
497c9a19 1220next:
54168ed7
IM		 1221 vector += 8;
1222 if (vector >= first_system_vector) {
1223 /* If we run out of vectors on large boxen, must share them. */
1224 offset = (offset + 1) % 8;
1225 vector = FIRST_DEVICE_VECTOR + offset;
1226 }
1227 if (unlikely(current_vector == vector))
1228 continue;
047c8fdb 1229#ifdef CONFIG_X86_64
54168ed7
IM		 1230 if (vector == IA32_SYSCALL_VECTOR)
1231 goto next;
047c8fdb 1232#else
54168ed7
IM		 1233 if (vector == SYSCALL_VECTOR)
1234 goto next;
047c8fdb 1235#endif
54168ed7
IM		 1236 for_each_cpu_mask_nr(new_cpu, new_mask)
1237 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1238 goto next;
1239 /* Found one! */
1240 current_vector = vector;
1241 current_offset = offset;
1242 if (old_vector) {
1243 cfg->move_in_progress = 1;
1244 cfg->old_domain = cfg->domain;
7a959cff 1245 }
54168ed7
IM		 1246 for_each_cpu_mask_nr(new_cpu, new_mask)
1247 per_cpu(vector_irq, new_cpu)[vector] = irq;
1248 cfg->vector = vector;
1249 cfg->domain = domain;
1250 return 0;
1251 }
1252 return -ENOSPC;
497c9a19
YL		 1253}
1254
1255static int assign_irq_vector(int irq, cpumask_t mask)
1256{
1257 int err;
ace80ab7 1258 unsigned long flags;
ace80ab7
EB		 1259
1260 spin_lock_irqsave(&vector_lock, flags);
497c9a19 1261 err = __assign_irq_vector(irq, mask);
26a3c49c 1262 spin_unlock_irqrestore(&vector_lock, flags);
497c9a19
YL		 1263 return err;
1264}
1265
1266static void __clear_irq_vector(int irq)
1267{
1268 struct irq_cfg *cfg;
1269 cpumask_t mask;
1270 int cpu, vector;
1271
1272 cfg = irq_cfg(irq);
1273 BUG_ON(!cfg->vector);
1274
1275 vector = cfg->vector;
1276 cpus_and(mask, cfg->domain, cpu_online_map);
1277 for_each_cpu_mask_nr(cpu, mask)
1278 per_cpu(vector_irq, cpu)[vector] = -1;
1279
1280 cfg->vector = 0;
1281 cpus_clear(cfg->domain);
1282}
1283
1284void __setup_vector_irq(int cpu)
1285{
1286 /* Initialize vector_irq on a new cpu */
1287 /* This function must be called with vector_lock held */
1288 int irq, vector;
1289 struct irq_cfg *cfg;
1290
1291 /* Mark the inuse vectors */
1292 for_each_irq_cfg(cfg) {
1293 if (!cpu_isset(cpu, cfg->domain))
1294 continue;
1295 vector = cfg->vector;
1296 irq = cfg->irq;
1297 per_cpu(vector_irq, cpu)[vector] = irq;
1298 }
1299 /* Mark the free vectors */
1300 for (vector = 0; vector < NR_VECTORS; ++vector) {
1301 irq = per_cpu(vector_irq, cpu)[vector];
1302 if (irq < 0)
1303 continue;
1304
1305 cfg = irq_cfg(irq);
1306 if (!cpu_isset(cpu, cfg->domain))
1307 per_cpu(vector_irq, cpu)[vector] = -1;
54168ed7 1308 }
1da177e4 1309}
3fde6900 1310
f5b9ed7a 1311static struct irq_chip ioapic_chip;
54168ed7
IM		 1312#ifdef CONFIG_INTR_REMAP
1313static struct irq_chip ir_ioapic_chip;
1314#endif
1da177e4 1315
54168ed7
IM		 1316#define IOAPIC_AUTO -1
1317#define IOAPIC_EDGE 0
1318#define IOAPIC_LEVEL 1
1da177e4 1319
047c8fdb 1320#ifdef CONFIG_X86_32
1d025192
YL		 1321static inline int IO_APIC_irq_trigger(int irq)
1322{
54168ed7 1323 int apic, idx, pin;
1d025192 1324
54168ed7
IM		 1325 for (apic = 0; apic < nr_ioapics; apic++) {
1326 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1327 idx = find_irq_entry(apic, pin, mp_INT);
1328 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1329 return irq_trigger(idx);
1330 }
1331 }
1332 /*
1333 * nonexistent IRQs are edge default
1334 */
1335 return 0;
1d025192 1336}
047c8fdb
YL		 1337#else
1338static inline int IO_APIC_irq_trigger(int irq)
1339{
54168ed7 1340 return 1;
047c8fdb
YL		 1341}
1342#endif
1d025192 1343
497c9a19 1344static void ioapic_register_intr(int irq, unsigned long trigger)
1da177e4 1345{
08678b08
YL		 1346 struct irq_desc *desc;
1347
199751d7
YL		 1348 /* first time to use this irq_desc */
1349 if (irq < 16)
1350 desc = irq_to_desc(irq);
1351 else
1352 desc = irq_to_desc_alloc(irq);
1353
6ebcc00e 1354 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
047c8fdb 1355 trigger == IOAPIC_LEVEL)
08678b08 1356 desc->status |= IRQ_LEVEL;
047c8fdb
YL		 1357 else
1358 desc->status &= ~IRQ_LEVEL;
1359
54168ed7
IM		 1360#ifdef CONFIG_INTR_REMAP
1361 if (irq_remapped(irq)) {
1362 desc->status |= IRQ_MOVE_PCNTXT;
1363 if (trigger)
1364 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1365 handle_fasteoi_irq,
1366 "fasteoi");
1367 else
1368 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1369 handle_edge_irq, "edge");
1370 return;
1371 }
1372#endif
047c8fdb
YL		 1373 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1374 trigger == IOAPIC_LEVEL)
a460e745 1375 set_irq_chip_and_handler_name(irq, &ioapic_chip,
54168ed7
IM		 1376 handle_fasteoi_irq,
1377 "fasteoi");
047c8fdb 1378 else
a460e745 1379 set_irq_chip_and_handler_name(irq, &ioapic_chip,
54168ed7 1380 handle_edge_irq, "edge");
1da177e4
LT		 1381}
1382
497c9a19
YL		 1383static int setup_ioapic_entry(int apic, int irq,
1384 struct IO_APIC_route_entry *entry,
1385 unsigned int destination, int trigger,
1386 int polarity, int vector)
1da177e4 1387{
497c9a19
YL		 1388 /*
1389 * add it to the IO-APIC irq-routing table:
1390 */
1391 memset(entry,0,sizeof(*entry));
1392
54168ed7
IM		 1393#ifdef CONFIG_INTR_REMAP
1394 if (intr_remapping_enabled) {
1395 struct intel_iommu *iommu = map_ioapic_to_ir(apic);
1396 struct irte irte;
1397 struct IR_IO_APIC_route_entry *ir_entry =
1398 (struct IR_IO_APIC_route_entry *) entry;
1399 int index;
1400
1401 if (!iommu)
1402 panic("No mapping iommu for ioapic %d\n", apic);
1403
1404 index = alloc_irte(iommu, irq, 1);
1405 if (index < 0)
1406 panic("Failed to allocate IRTE for ioapic %d\n", apic);
1407
1408 memset(&irte, 0, sizeof(irte));
1409
1410 irte.present = 1;
1411 irte.dst_mode = INT_DEST_MODE;
1412 irte.trigger_mode = trigger;
1413 irte.dlvry_mode = INT_DELIVERY_MODE;
1414 irte.vector = vector;
1415 irte.dest_id = IRTE_DEST(destination);
1416
1417 modify_irte(irq, &irte);
1418
1419 ir_entry->index2 = (index >> 15) & 0x1;
1420 ir_entry->zero = 0;
1421 ir_entry->format = 1;
1422 ir_entry->index = (index & 0x7fff);
1423 } else
1424#endif
1425 {
1426 entry->delivery_mode = INT_DELIVERY_MODE;
1427 entry->dest_mode = INT_DEST_MODE;
1428 entry->dest = destination;
1429 }
497c9a19 1430
54168ed7 1431 entry->mask = 0; /* enable IRQ */
497c9a19
YL		 1432 entry->trigger = trigger;
1433 entry->polarity = polarity;
1434 entry->vector = vector;
1435
1436 /* Mask level triggered irqs.
1437 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1438 */
1439 if (trigger)
1440 entry->mask = 1;
497c9a19
YL		 1441 return 0;
1442}
1443
1444static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
54168ed7 1445 int trigger, int polarity)
497c9a19
YL		 1446{
1447 struct irq_cfg *cfg;
1da177e4 1448 struct IO_APIC_route_entry entry;
497c9a19
YL		 1449 cpumask_t mask;
1450
1451 if (!IO_APIC_IRQ(irq))
1452 return;
1453
1454 cfg = irq_cfg(irq);
1455
1456 mask = TARGET_CPUS;
1457 if (assign_irq_vector(irq, mask))
1458 return;
1459
1460 cpus_and(mask, cfg->domain, mask);
1461
1462 apic_printk(APIC_VERBOSE,KERN_DEBUG
1463 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1464 "IRQ %d Mode:%i Active:%i)\n",
1465 apic, mp_ioapics[apic].mp_apicid, pin, cfg->vector,
1466 irq, trigger, polarity);
1467
1468
1469 if (setup_ioapic_entry(mp_ioapics[apic].mp_apicid, irq, &entry,
1470 cpu_mask_to_apicid(mask), trigger, polarity,
1471 cfg->vector)) {
1472 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1473 mp_ioapics[apic].mp_apicid, pin);
1474 __clear_irq_vector(irq);
1475 return;
1476 }
1477
1478 ioapic_register_intr(irq, trigger);
1479 if (irq < 16)
1480 disable_8259A_irq(irq);
1481
1482 ioapic_write_entry(apic, pin, entry);
1483}
1484
1485static void __init setup_IO_APIC_irqs(void)
1486{
1487 int apic, pin, idx, irq, first_notcon = 1;
1da177e4
LT		 1488
1489 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1490
1491 for (apic = 0; apic < nr_ioapics; apic++) {
1492 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1493
497c9a19 1494 idx = find_irq_entry(apic,pin,mp_INT);
1da177e4
LT		 1495 if (idx == -1) {
1496 if (first_notcon) {
497c9a19 1497 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mp_apicid, pin);
1da177e4
LT		 1498 first_notcon = 0;
1499 } else
497c9a19 1500 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mp_apicid, pin);
1da177e4
LT		 1501 continue;
1502 }
20d225b9
YL		 1503 if (!first_notcon) {
1504 apic_printk(APIC_VERBOSE, " not connected.\n");
1505 first_notcon = 1;
1506 }
1507
1da177e4 1508 irq = pin_2_irq(idx, apic, pin);
54168ed7 1509#ifdef CONFIG_X86_32
497c9a19
YL		 1510 if (multi_timer_check(apic, irq))
1511 continue;
54168ed7 1512#endif
497c9a19 1513 add_pin_to_irq(irq, apic, pin);
36062448 1514
497c9a19
YL		 1515 setup_IO_APIC_irq(apic, pin, irq,
1516 irq_trigger(idx), irq_polarity(idx));
1da177e4
LT		 1517 }
1518 }
1519
1520 if (!first_notcon)
1521 apic_printk(APIC_VERBOSE, " not connected.\n");
1522}
1523
1524/*
f7633ce5 1525 * Set up the timer pin, possibly with the 8259A-master behind.
1da177e4 1526 */
f7633ce5
MR		 1527static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
1528 int vector)
1da177e4
LT		 1529{
1530 struct IO_APIC_route_entry entry;
1da177e4 1531
54168ed7
IM		 1532#ifdef CONFIG_INTR_REMAP
1533 if (intr_remapping_enabled)
1534 return;
1535#endif
1536
36062448 1537 memset(&entry, 0, sizeof(entry));
1da177e4
LT		 1538
1539 /*
1540 * We use logical delivery to get the timer IRQ
1541 * to the first CPU.
1542 */
1543 entry.dest_mode = INT_DEST_MODE;
03be7505 1544 entry.mask = 1; /* mask IRQ now */
d83e94ac 1545 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
1da177e4
LT		 1546 entry.delivery_mode = INT_DELIVERY_MODE;
1547 entry.polarity = 0;
1548 entry.trigger = 0;
1549 entry.vector = vector;
1550
1551 /*
1552 * The timer IRQ doesn't have to know that behind the
f7633ce5 1553 * scene we may have a 8259A-master in AEOI mode ...
1da177e4 1554 */
54168ed7 1555 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1da177e4
LT		 1556
1557 /*
1558 * Add it to the IO-APIC irq-routing table:
1559 */
cf4c6a2f 1560 ioapic_write_entry(apic, pin, entry);
1da177e4
LT		 1561}
1562
32f71aff
MR		 1563
1564__apicdebuginit(void) print_IO_APIC(void)
1da177e4
LT		 1565{
1566 int apic, i;
1567 union IO_APIC_reg_00 reg_00;
1568 union IO_APIC_reg_01 reg_01;
1569 union IO_APIC_reg_02 reg_02;
1570 union IO_APIC_reg_03 reg_03;
1571 unsigned long flags;
0f978f45 1572 struct irq_cfg *cfg;
1da177e4
LT		 1573
1574 if (apic_verbosity == APIC_QUIET)
1575 return;
1576
36062448 1577 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1da177e4
LT		 1578 for (i = 0; i < nr_ioapics; i++)
1579 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
ec2cd0a2 1580 mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]);
1da177e4
LT		 1581
1582 /*
1583 * We are a bit conservative about what we expect. We have to
1584 * know about every hardware change ASAP.
1585 */
1586 printk(KERN_INFO "testing the IO APIC.......................\n");
1587
1588 for (apic = 0; apic < nr_ioapics; apic++) {
1589
1590 spin_lock_irqsave(&ioapic_lock, flags);
1591 reg_00.raw = io_apic_read(apic, 0);
1592 reg_01.raw = io_apic_read(apic, 1);
1593 if (reg_01.bits.version >= 0x10)
1594 reg_02.raw = io_apic_read(apic, 2);
54168ed7
IM		 1595 if (reg_01.bits.version >= 0x20)
1596 reg_03.raw = io_apic_read(apic, 3);
1da177e4
LT		 1597 spin_unlock_irqrestore(&ioapic_lock, flags);
1598
54168ed7 1599 printk("\n");
ec2cd0a2 1600 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid);
1da177e4
LT		 1601 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1602 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1603 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1604 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1da177e4 1605
54168ed7 1606 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1da177e4 1607 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1da177e4
LT		 1608
1609 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1610 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1da177e4
LT		 1611
1612 /*
1613 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1614 * but the value of reg_02 is read as the previous read register
1615 * value, so ignore it if reg_02 == reg_01.
1616 */
1617 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1618 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1619 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1da177e4
LT		 1620 }
1621
1622 /*
1623 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1624 * or reg_03, but the value of reg_0[23] is read as the previous read
1625 * register value, so ignore it if reg_03 == reg_0[12].
1626 */
1627 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1628 reg_03.raw != reg_01.raw) {
1629 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1630 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1da177e4
LT		 1631 }
1632
1633 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1634
d83e94ac
YL		 1635 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1636 " Stat Dmod Deli Vect: \n");
1da177e4
LT		 1637
1638 for (i = 0; i <= reg_01.bits.entries; i++) {
1639 struct IO_APIC_route_entry entry;
1640
cf4c6a2f 1641 entry = ioapic_read_entry(apic, i);
1da177e4 1642
54168ed7
IM		 1643 printk(KERN_DEBUG " %02x %03X ",
1644 i,
1645 entry.dest
1646 );
1da177e4
LT		 1647
1648 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1649 entry.mask,
1650 entry.trigger,
1651 entry.irr,
1652 entry.polarity,
1653 entry.delivery_status,
1654 entry.dest_mode,
1655 entry.delivery_mode,
1656 entry.vector
1657 );
1658 }
1659 }
1da177e4 1660 printk(KERN_DEBUG "IRQ to pin mappings:\n");
0f978f45
YL		 1661 for_each_irq_cfg(cfg) {
1662 struct irq_pin_list *entry = cfg->irq_2_pin;
1663 if (!entry)
1da177e4 1664 continue;
54168ed7 1665 printk(KERN_DEBUG "IRQ%d ", cfg->irq);
1da177e4
LT		 1666 for (;;) {
1667 printk("-> %d:%d", entry->apic, entry->pin);
1668 if (!entry->next)
1669 break;
0f978f45 1670 entry = entry->next;
1da177e4
LT		 1671 }
1672 printk("\n");
1673 }
1674
1675 printk(KERN_INFO ".................................... done.\n");
1676
1677 return;
1678}
1679
32f71aff 1680__apicdebuginit(void) print_APIC_bitfield(int base)
1da177e4
LT		 1681{
1682 unsigned int v;
1683 int i, j;
1684
1685 if (apic_verbosity == APIC_QUIET)
1686 return;
1687
1688 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1689 for (i = 0; i < 8; i++) {
1690 v = apic_read(base + i*0x10);
1691 for (j = 0; j < 32; j++) {
1692 if (v & (1<<j))
1693 printk("1");
1694 else
1695 printk("0");
1696 }
1697 printk("\n");
1698 }
1699}
1700
32f71aff 1701__apicdebuginit(void) print_local_APIC(void *dummy)
1da177e4
LT		 1702{
1703 unsigned int v, ver, maxlvt;
7ab6af7a 1704 u64 icr;
1da177e4
LT		 1705
1706 if (apic_verbosity == APIC_QUIET)
1707 return;
1708
1709 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1710 smp_processor_id(), hard_smp_processor_id());
66823114 1711 v = apic_read(APIC_ID);
54168ed7 1712 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1da177e4
LT		 1713 v = apic_read(APIC_LVR);
1714 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1715 ver = GET_APIC_VERSION(v);
e05d723f 1716 maxlvt = lapic_get_maxlvt();
1da177e4
LT		 1717
1718 v = apic_read(APIC_TASKPRI);
1719 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1720
54168ed7 1721 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1da177e4
LT		 1722 v = apic_read(APIC_ARBPRI);
1723 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1724 v & APIC_ARBPRI_MASK);
1725 v = apic_read(APIC_PROCPRI);
1726 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1727 }
1728
1729 v = apic_read(APIC_EOI);
1730 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1731 v = apic_read(APIC_RRR);
1732 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1733 v = apic_read(APIC_LDR);
1734 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1735 v = apic_read(APIC_DFR);
1736 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1737 v = apic_read(APIC_SPIV);
1738 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1739
1740 printk(KERN_DEBUG "... APIC ISR field:\n");
1741 print_APIC_bitfield(APIC_ISR);
1742 printk(KERN_DEBUG "... APIC TMR field:\n");
1743 print_APIC_bitfield(APIC_TMR);
1744 printk(KERN_DEBUG "... APIC IRR field:\n");
1745 print_APIC_bitfield(APIC_IRR);
1746
54168ed7
IM		 1747 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1748 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1da177e4 1749 apic_write(APIC_ESR, 0);
54168ed7 1750
1da177e4
LT		 1751 v = apic_read(APIC_ESR);
1752 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1753 }
1754
7ab6af7a
HS		 1755 icr = apic_icr_read();
1756 printk(KERN_DEBUG "... APIC ICR: %08x\n", icr);
1757 printk(KERN_DEBUG "... APIC ICR2: %08x\n", icr >> 32);
1da177e4
LT		 1758
1759 v = apic_read(APIC_LVTT);
1760 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1761
1762 if (maxlvt > 3) { /* PC is LVT#4. */
1763 v = apic_read(APIC_LVTPC);
1764 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1765 }
1766 v = apic_read(APIC_LVT0);
1767 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1768 v = apic_read(APIC_LVT1);
1769 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1770
1771 if (maxlvt > 2) { /* ERR is LVT#3. */
1772 v = apic_read(APIC_LVTERR);
1773 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1774 }
1775
1776 v = apic_read(APIC_TMICT);
1777 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1778 v = apic_read(APIC_TMCCT);
1779 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1780 v = apic_read(APIC_TDCR);
1781 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1782 printk("\n");
1783}
1784
32f71aff 1785__apicdebuginit(void) print_all_local_APICs(void)
1da177e4 1786{
15c8b6c1 1787 on_each_cpu(print_local_APIC, NULL, 1);
1da177e4
LT		 1788}
1789
32f71aff 1790__apicdebuginit(void) print_PIC(void)
1da177e4 1791{
1da177e4
LT		 1792 unsigned int v;
1793 unsigned long flags;
1794
1795 if (apic_verbosity == APIC_QUIET)
1796 return;
1797
1798 printk(KERN_DEBUG "\nprinting PIC contents\n");
1799
1800 spin_lock_irqsave(&i8259A_lock, flags);
1801
1802 v = inb(0xa1) << 8 | inb(0x21);
1803 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1804
1805 v = inb(0xa0) << 8 | inb(0x20);
1806 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1807
54168ed7
IM		 1808 outb(0x0b,0xa0);
1809 outb(0x0b,0x20);
1da177e4 1810 v = inb(0xa0) << 8 | inb(0x20);
54168ed7
IM		 1811 outb(0x0a,0xa0);
1812 outb(0x0a,0x20);
1da177e4
LT		 1813
1814 spin_unlock_irqrestore(&i8259A_lock, flags);
1815
1816 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1817
1818 v = inb(0x4d1) << 8 | inb(0x4d0);
1819 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1820}
1821
32f71aff
MR		 1822__apicdebuginit(int) print_all_ICs(void)
1823{
1824 print_PIC();
1825 print_all_local_APICs();
1826 print_IO_APIC();
1827
1828 return 0;
1829}
1830
1831fs_initcall(print_all_ICs);
1832
1da177e4 1833
efa2559f
YL		 1834/* Where if anywhere is the i8259 connect in external int mode */
1835static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1836
54168ed7 1837void __init enable_IO_APIC(void)
1da177e4
LT		 1838{
1839 union IO_APIC_reg_01 reg_01;
fcfd636a 1840 int i8259_apic, i8259_pin;
54168ed7 1841 int apic;
1da177e4
LT		 1842 unsigned long flags;
1843
54168ed7
IM		 1844#ifdef CONFIG_X86_32
1845 int i;
1da177e4
LT		 1846 if (!pirqs_enabled)
1847 for (i = 0; i < MAX_PIRQS; i++)
1848 pirq_entries[i] = -1;
54168ed7 1849#endif
1da177e4
LT		 1850
1851 /*
1852 * The number of IO-APIC IRQ registers (== #pins):
1853 */
fcfd636a 1854 for (apic = 0; apic < nr_ioapics; apic++) {
1da177e4 1855 spin_lock_irqsave(&ioapic_lock, flags);
fcfd636a 1856 reg_01.raw = io_apic_read(apic, 1);
1da177e4 1857 spin_unlock_irqrestore(&ioapic_lock, flags);
fcfd636a
EB		 1858 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1859 }
54168ed7 1860 for(apic = 0; apic < nr_ioapics; apic++) {
fcfd636a
EB		 1861 int pin;
1862 /* See if any of the pins is in ExtINT mode */
1008fddc 1863 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
fcfd636a 1864 struct IO_APIC_route_entry entry;
cf4c6a2f 1865 entry = ioapic_read_entry(apic, pin);
fcfd636a 1866
fcfd636a
EB		 1867 /* If the interrupt line is enabled and in ExtInt mode
1868 * I have found the pin where the i8259 is connected.
1869 */
1870 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1871 ioapic_i8259.apic = apic;
1872 ioapic_i8259.pin = pin;
1873 goto found_i8259;
1874 }
1875 }
1876 }
1877 found_i8259:
1878 /* Look to see what if the MP table has reported the ExtINT */
1879 /* If we could not find the appropriate pin by looking at the ioapic
1880 * the i8259 probably is not connected the ioapic but give the
1881 * mptable a chance anyway.
1882 */
1883 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1884 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1885 /* Trust the MP table if nothing is setup in the hardware */
1886 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1887 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1888 ioapic_i8259.pin = i8259_pin;
1889 ioapic_i8259.apic = i8259_apic;
1890 }
1891 /* Complain if the MP table and the hardware disagree */
1892 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1893 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1894 {
1895 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1da177e4
LT		 1896 }
1897
1898 /*
1899 * Do not trust the IO-APIC being empty at bootup
1900 */
1901 clear_IO_APIC();
1902}
1903
1904/*
1905 * Not an __init, needed by the reboot code
1906 */
1907void disable_IO_APIC(void)
1908{
1909 /*
1910 * Clear the IO-APIC before rebooting:
1911 */
1912 clear_IO_APIC();
1913
650927ef 1914 /*
0b968d23 1915 * If the i8259 is routed through an IOAPIC
650927ef 1916 * Put that IOAPIC in virtual wire mode
0b968d23 1917 * so legacy interrupts can be delivered.
650927ef 1918 */
fcfd636a 1919 if (ioapic_i8259.pin != -1) {
650927ef 1920 struct IO_APIC_route_entry entry;
650927ef
EB		 1921
1922 memset(&entry, 0, sizeof(entry));
1923 entry.mask = 0; /* Enabled */
1924 entry.trigger = 0; /* Edge */
1925 entry.irr = 0;
1926 entry.polarity = 0; /* High */
1927 entry.delivery_status = 0;
1928 entry.dest_mode = 0; /* Physical */
fcfd636a 1929 entry.delivery_mode = dest_ExtINT; /* ExtInt */
650927ef 1930 entry.vector = 0;
54168ed7 1931 entry.dest = read_apic_id();
650927ef
EB		 1932
1933 /*
1934 * Add it to the IO-APIC irq-routing table:
1935 */
cf4c6a2f 1936 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
650927ef 1937 }
54168ed7 1938
fcfd636a 1939 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1da177e4
LT		 1940}
1941
54168ed7 1942#ifdef CONFIG_X86_32
1da177e4
LT		 1943/*
1944 * function to set the IO-APIC physical IDs based on the
1945 * values stored in the MPC table.
1946 *
1947 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1948 */
1949
1da177e4
LT		 1950static void __init setup_ioapic_ids_from_mpc(void)
1951{
1952 union IO_APIC_reg_00 reg_00;
1953 physid_mask_t phys_id_present_map;
1954 int apic;
1955 int i;
1956 unsigned char old_id;
1957 unsigned long flags;
1958
a4dbc34d 1959 if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
d49c4288 1960 return;
d49c4288 1961
ca05fea6
NP		 1962 /*
1963 * Don't check I/O APIC IDs for xAPIC systems. They have
1964 * no meaning without the serial APIC bus.
1965 */
7c5c1e42
SL		 1966 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1967 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
ca05fea6 1968 return;
1da177e4
LT		 1969 /*
1970 * This is broken; anything with a real cpu count has to
1971 * circumvent this idiocy regardless.
1972 */
1973 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1974
1975 /*
1976 * Set the IOAPIC ID to the value stored in the MPC table.
1977 */
1978 for (apic = 0; apic < nr_ioapics; apic++) {
1979
1980 /* Read the register 0 value */
1981 spin_lock_irqsave(&ioapic_lock, flags);
1982 reg_00.raw = io_apic_read(apic, 0);
1983 spin_unlock_irqrestore(&ioapic_lock, flags);
36062448 1984
ec2cd0a2 1985 old_id = mp_ioapics[apic].mp_apicid;
1da177e4 1986
ec2cd0a2 1987 if (mp_ioapics[apic].mp_apicid >= get_physical_broadcast()) {
1da177e4 1988 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
ec2cd0a2 1989 apic, mp_ioapics[apic].mp_apicid);
1da177e4
LT		 1990 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1991 reg_00.bits.ID);
ec2cd0a2 1992 mp_ioapics[apic].mp_apicid = reg_00.bits.ID;
1da177e4
LT		 1993 }
1994
1da177e4
LT		 1995 /*
1996 * Sanity check, is the ID really free? Every APIC in a
1997 * system must have a unique ID or we get lots of nice
1998 * 'stuck on smp_invalidate_needed IPI wait' messages.
1999 */
2000 if (check_apicid_used(phys_id_present_map,
ec2cd0a2 2001 mp_ioapics[apic].mp_apicid)) {
1da177e4 2002 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
ec2cd0a2 2003 apic, mp_ioapics[apic].mp_apicid);
1da177e4
LT		 2004 for (i = 0; i < get_physical_broadcast(); i++)
2005 if (!physid_isset(i, phys_id_present_map))
2006 break;
2007 if (i >= get_physical_broadcast())
2008 panic("Max APIC ID exceeded!\n");
2009 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2010 i);
2011 physid_set(i, phys_id_present_map);
ec2cd0a2 2012 mp_ioapics[apic].mp_apicid = i;
1da177e4
LT		 2013 } else {
2014 physid_mask_t tmp;
ec2cd0a2 2015 tmp = apicid_to_cpu_present(mp_ioapics[apic].mp_apicid);
1da177e4
LT		 2016 apic_printk(APIC_VERBOSE, "Setting %d in the "
2017 "phys_id_present_map\n",
ec2cd0a2 2018 mp_ioapics[apic].mp_apicid);
1da177e4
LT		 2019 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2020 }
2021
2022
2023 /*
2024 * We need to adjust the IRQ routing table
2025 * if the ID changed.
2026 */
ec2cd0a2 2027 if (old_id != mp_ioapics[apic].mp_apicid)
1da177e4 2028 for (i = 0; i < mp_irq_entries; i++)
2fddb6e2
AS		 2029 if (mp_irqs[i].mp_dstapic == old_id)
2030 mp_irqs[i].mp_dstapic
ec2cd0a2 2031 = mp_ioapics[apic].mp_apicid;
1da177e4
LT		 2032
2033 /*
2034 * Read the right value from the MPC table and
2035 * write it into the ID register.
36062448 2036 */
1da177e4
LT		 2037 apic_printk(APIC_VERBOSE, KERN_INFO
2038 "...changing IO-APIC physical APIC ID to %d ...",
ec2cd0a2 2039 mp_ioapics[apic].mp_apicid);
1da177e4 2040
ec2cd0a2 2041 reg_00.bits.ID = mp_ioapics[apic].mp_apicid;
1da177e4 2042 spin_lock_irqsave(&ioapic_lock, flags);
1da177e4
LT		 2043
2044 /*
2045 * Sanity check
2046 */
2047 spin_lock_irqsave(&ioapic_lock, flags);
2048 reg_00.raw = io_apic_read(apic, 0);
2049 spin_unlock_irqrestore(&ioapic_lock, flags);
ec2cd0a2 2050 if (reg_00.bits.ID != mp_ioapics[apic].mp_apicid)
1da177e4
LT		 2051 printk("could not set ID!\n");
2052 else
2053 apic_printk(APIC_VERBOSE, " ok.\n");
2054 }
2055}
54168ed7 2056#endif
1da177e4 2057
7ce0bcfd 2058int no_timer_check __initdata;
8542b200
ZA		 2059
2060static int __init notimercheck(char *s)
2061{
2062 no_timer_check = 1;
2063 return 1;
2064}
2065__setup("no_timer_check", notimercheck);
2066
1da177e4
LT		 2067/*
2068 * There is a nasty bug in some older SMP boards, their mptable lies
2069 * about the timer IRQ. We do the following to work around the situation:
2070 *
2071 * - timer IRQ defaults to IO-APIC IRQ
2072 * - if this function detects that timer IRQs are defunct, then we fall
2073 * back to ISA timer IRQs
2074 */
f0a7a5c9 2075static int __init timer_irq_works(void)
1da177e4
LT		 2076{
2077 unsigned long t1 = jiffies;
4aae0702 2078 unsigned long flags;
1da177e4 2079
8542b200
ZA		 2080 if (no_timer_check)
2081 return 1;
2082
4aae0702 2083 local_save_flags(flags);
1da177e4
LT		 2084 local_irq_enable();
2085 /* Let ten ticks pass... */
2086 mdelay((10 * 1000) / HZ);
4aae0702 2087 local_irq_restore(flags);
1da177e4
LT		 2088
2089 /*
2090 * Expect a few ticks at least, to be sure some possible
2091 * glue logic does not lock up after one or two first
2092 * ticks in a non-ExtINT mode. Also the local APIC
2093 * might have cached one ExtINT interrupt. Finally, at
2094 * least one tick may be lost due to delays.
2095 */
54168ed7
IM		 2096
2097 /* jiffies wrap? */
1d16b53e 2098 if (time_after(jiffies, t1 + 4))
1da177e4 2099 return 1;
1da177e4
LT		 2100 return 0;
2101}
2102
2103/*
2104 * In the SMP+IOAPIC case it might happen that there are an unspecified
2105 * number of pending IRQ events unhandled. These cases are very rare,
2106 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2107 * better to do it this way as thus we do not have to be aware of
2108 * 'pending' interrupts in the IRQ path, except at this point.
2109 */
2110/*
2111 * Edge triggered needs to resend any interrupt
2112 * that was delayed but this is now handled in the device
2113 * independent code.
2114 */
2115
2116/*
2117 * Starting up a edge-triggered IO-APIC interrupt is
2118 * nasty - we need to make sure that we get the edge.
2119 * If it is already asserted for some reason, we need
2120 * return 1 to indicate that is was pending.
2121 *
2122 * This is not complete - we should be able to fake
2123 * an edge even if it isn't on the 8259A...
2124 */
54168ed7 2125
f5b9ed7a 2126static unsigned int startup_ioapic_irq(unsigned int irq)
1da177e4
LT		 2127{
2128 int was_pending = 0;
2129 unsigned long flags;
2130
2131 spin_lock_irqsave(&ioapic_lock, flags);
2132 if (irq < 16) {
2133 disable_8259A_irq(irq);
2134 if (i8259A_irq_pending(irq))
2135 was_pending = 1;
2136 }
2137 __unmask_IO_APIC_irq(irq);
2138 spin_unlock_irqrestore(&ioapic_lock, flags);
2139
2140 return was_pending;
2141}
2142
54168ed7 2143#ifdef CONFIG_X86_64
ace80ab7 2144static int ioapic_retrigger_irq(unsigned int irq)
1da177e4 2145{
54168ed7
IM		 2146
2147 struct irq_cfg *cfg = irq_cfg(irq);
2148 unsigned long flags;
2149
2150 spin_lock_irqsave(&vector_lock, flags);
2151 send_IPI_mask(cpumask_of_cpu(first_cpu(cfg->domain)), cfg->vector);
2152 spin_unlock_irqrestore(&vector_lock, flags);
c0ad90a3
IM		 2153
2154 return 1;
2155}
54168ed7
IM		 2156#else
2157static int ioapic_retrigger_irq(unsigned int irq)
497c9a19 2158{
54168ed7 2159 send_IPI_self(irq_cfg(irq)->vector);
497c9a19 2160
54168ed7
IM		 2161 return 1;
2162}
2163#endif
497c9a19 2164
54168ed7
IM		 2165/*
2166 * Level and edge triggered IO-APIC interrupts need different handling,
2167 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2168 * handled with the level-triggered descriptor, but that one has slightly
2169 * more overhead. Level-triggered interrupts cannot be handled with the
2170 * edge-triggered handler, without risking IRQ storms and other ugly
2171 * races.
2172 */
497c9a19 2173
54168ed7 2174#ifdef CONFIG_SMP
497c9a19 2175
54168ed7
IM		 2176#ifdef CONFIG_INTR_REMAP
2177static void ir_irq_migration(struct work_struct *work);
497c9a19 2178
54168ed7 2179static DECLARE_DELAYED_WORK(ir_migration_work, ir_irq_migration);
497c9a19 2180
54168ed7
IM		 2181/*
2182 * Migrate the IO-APIC irq in the presence of intr-remapping.
2183 *
2184 * For edge triggered, irq migration is a simple atomic update(of vector
2185 * and cpu destination) of IRTE and flush the hardware cache.
2186 *
2187 * For level triggered, we need to modify the io-apic RTE aswell with the update
2188 * vector information, along with modifying IRTE with vector and destination.
2189 * So irq migration for level triggered is little bit more complex compared to
2190 * edge triggered migration. But the good news is, we use the same algorithm
2191 * for level triggered migration as we have today, only difference being,
2192 * we now initiate the irq migration from process context instead of the
2193 * interrupt context.
2194 *
2195 * In future, when we do a directed EOI (combined with cpu EOI broadcast
2196 * suppression) to the IO-APIC, level triggered irq migration will also be
2197 * as simple as edge triggered migration and we can do the irq migration
2198 * with a simple atomic update to IO-APIC RTE.
2199 */
2200static void migrate_ioapic_irq(int irq, cpumask_t mask)
497c9a19 2201{
54168ed7
IM		 2202 struct irq_cfg *cfg;
2203 struct irq_desc *desc;
2204 cpumask_t tmp, cleanup_mask;
2205 struct irte irte;
2206 int modify_ioapic_rte;
2207 unsigned int dest;
2208 unsigned long flags;
497c9a19 2209
54168ed7
IM		 2210 cpus_and(tmp, mask, cpu_online_map);
2211 if (cpus_empty(tmp))
497c9a19
YL		 2212 return;
2213
54168ed7
IM		 2214 if (get_irte(irq, &irte))
2215 return;
497c9a19 2216
54168ed7
IM		 2217 if (assign_irq_vector(irq, mask))
2218 return;
2219
2220 cfg = irq_cfg(irq);
2221 cpus_and(tmp, cfg->domain, mask);
2222 dest = cpu_mask_to_apicid(tmp);
2223
2224 desc = irq_to_desc(irq);
2225 modify_ioapic_rte = desc->status & IRQ_LEVEL;
2226 if (modify_ioapic_rte) {
2227 spin_lock_irqsave(&ioapic_lock, flags);
2228 __target_IO_APIC_irq(irq, dest, cfg->vector);
2229 spin_unlock_irqrestore(&ioapic_lock, flags);
2230 }
2231
2232 irte.vector = cfg->vector;
2233 irte.dest_id = IRTE_DEST(dest);
2234
2235 /*
2236 * Modified the IRTE and flushes the Interrupt entry cache.
2237 */
2238 modify_irte(irq, &irte);
2239
2240 if (cfg->move_in_progress) {
2241 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
2242 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
2243 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2244 cfg->move_in_progress = 0;
2245 }
2246
2247 desc->affinity = mask;
2248}
2249
2250static int migrate_irq_remapped_level(int irq)
2251{
2252 int ret = -1;
2253 struct irq_desc *desc = irq_to_desc(irq);
2254
2255 mask_IO_APIC_irq(irq);
2256
2257 if (io_apic_level_ack_pending(irq)) {
2258 /*
2259 * Interrupt in progress. Migrating irq now will change the
2260 * vector information in the IO-APIC RTE and that will confuse
2261 * the EOI broadcast performed by cpu.
2262 * So, delay the irq migration to the next instance.
2263 */
2264 schedule_delayed_work(&ir_migration_work, 1);
2265 goto unmask;
2266 }
2267
2268 /* everthing is clear. we have right of way */
2269 migrate_ioapic_irq(irq, desc->pending_mask);
2270
2271 ret = 0;
2272 desc->status &= ~IRQ_MOVE_PENDING;
2273 cpus_clear(desc->pending_mask);
2274
2275unmask:
2276 unmask_IO_APIC_irq(irq);
2277 return ret;
2278}
2279
2280static void ir_irq_migration(struct work_struct *work)
2281{
2282 unsigned int irq;
2283 struct irq_desc *desc;
2284
2285 for_each_irq_desc(irq, desc) {
2286 if (desc->status & IRQ_MOVE_PENDING) {
2287 unsigned long flags;
2288
2289 spin_lock_irqsave(&desc->lock, flags);
2290 if (!desc->chip->set_affinity ||
2291 !(desc->status & IRQ_MOVE_PENDING)) {
2292 desc->status &= ~IRQ_MOVE_PENDING;
2293 spin_unlock_irqrestore(&desc->lock, flags);
2294 continue;
2295 }
2296
2297 desc->chip->set_affinity(irq, desc->pending_mask);
2298 spin_unlock_irqrestore(&desc->lock, flags);
2299 }
2300 }
2301}
2302
2303/*
2304 * Migrates the IRQ destination in the process context.
2305 */
2306static void set_ir_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
2307{
2308 struct irq_desc *desc = irq_to_desc(irq);
2309
2310 if (desc->status & IRQ_LEVEL) {
2311 desc->status |= IRQ_MOVE_PENDING;
2312 desc->pending_mask = mask;
2313 migrate_irq_remapped_level(irq);
2314 return;
2315 }
2316
2317 migrate_ioapic_irq(irq, mask);
2318}
2319#endif
2320
2321asmlinkage void smp_irq_move_cleanup_interrupt(void)
2322{
2323 unsigned vector, me;
2324 ack_APIC_irq();
2325#ifdef CONFIG_X86_64
2326 exit_idle();
2327#endif
2328 irq_enter();
2329
2330 me = smp_processor_id();
2331 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2332 unsigned int irq;
2333 struct irq_desc *desc;
2334 struct irq_cfg *cfg;
2335 irq = __get_cpu_var(vector_irq)[vector];
2336
2337 desc = irq_to_desc(irq);
2338 if (!desc)
2339 continue;
2340
2341 cfg = irq_cfg(irq);
2342 spin_lock(&desc->lock);
2343 if (!cfg->move_cleanup_count)
2344 goto unlock;
2345
2346 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
2347 goto unlock;
2348
2349 __get_cpu_var(vector_irq)[vector] = -1;
2350 cfg->move_cleanup_count--;
2351unlock:
2352 spin_unlock(&desc->lock);
2353 }
2354
2355 irq_exit();
2356}
2357
2358static void irq_complete_move(unsigned int irq)
2359{
2360 struct irq_cfg *cfg = irq_cfg(irq);
2361 unsigned vector, me;
2362
2363 if (likely(!cfg->move_in_progress))
2364 return;
2365
2366 vector = ~get_irq_regs()->orig_ax;
2367 me = smp_processor_id();
2368 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
2369 cpumask_t cleanup_mask;
2370
2371 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
2372 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
2373 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
497c9a19
YL		 2374 cfg->move_in_progress = 0;
2375 }
2376}
2377#else
2378static inline void irq_complete_move(unsigned int irq) {}
2379#endif
54168ed7
IM		 2380#ifdef CONFIG_INTR_REMAP
2381static void ack_x2apic_level(unsigned int irq)
2382{
2383 ack_x2APIC_irq();
2384}
2385
2386static void ack_x2apic_edge(unsigned int irq)
2387{
2388 ack_x2APIC_irq();
2389}
2390#endif
497c9a19 2391
1d025192
YL		 2392static void ack_apic_edge(unsigned int irq)
2393{
2394 irq_complete_move(irq);
2395 move_native_irq(irq);
2396 ack_APIC_irq();
2397}
2398
3eb2cce8
YL		 2399#ifdef CONFIG_X86_32
2400atomic_t irq_mis_count;
2401#endif
2402
047c8fdb
YL		 2403static void ack_apic_level(unsigned int irq)
2404{
3eb2cce8
YL		 2405#ifdef CONFIG_X86_32
2406 unsigned long v;
2407 int i;
2408#endif
54168ed7 2409 int do_unmask_irq = 0;
047c8fdb 2410
54168ed7 2411 irq_complete_move(irq);
047c8fdb 2412#ifdef CONFIG_GENERIC_PENDING_IRQ
54168ed7
IM		 2413 /* If we are moving the irq we need to mask it */
2414 if (unlikely(irq_to_desc(irq)->status & IRQ_MOVE_PENDING)) {
2415 do_unmask_irq = 1;
2416 mask_IO_APIC_irq(irq);
2417 }
047c8fdb
YL		 2418#endif
2419
3eb2cce8
YL		 2420#ifdef CONFIG_X86_32
2421 /*
2422 * It appears there is an erratum which affects at least version 0x11
2423 * of I/O APIC (that's the 82093AA and cores integrated into various
2424 * chipsets). Under certain conditions a level-triggered interrupt is
2425 * erroneously delivered as edge-triggered one but the respective IRR
2426 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2427 * message but it will never arrive and further interrupts are blocked
2428 * from the source. The exact reason is so far unknown, but the
2429 * phenomenon was observed when two consecutive interrupt requests
2430 * from a given source get delivered to the same CPU and the source is
2431 * temporarily disabled in between.
2432 *
2433 * A workaround is to simulate an EOI message manually. We achieve it
2434 * by setting the trigger mode to edge and then to level when the edge
2435 * trigger mode gets detected in the TMR of a local APIC for a
2436 * level-triggered interrupt. We mask the source for the time of the
2437 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2438 * The idea is from Manfred Spraul. --macro
2439 */
2440 i = irq_cfg(irq)->vector;
2441
2442 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2443#endif
2444
54168ed7
IM		 2445 /*
2446 * We must acknowledge the irq before we move it or the acknowledge will
2447 * not propagate properly.
2448 */
2449 ack_APIC_irq();
2450
2451 /* Now we can move and renable the irq */
2452 if (unlikely(do_unmask_irq)) {
2453 /* Only migrate the irq if the ack has been received.
2454 *
2455 * On rare occasions the broadcast level triggered ack gets
2456 * delayed going to ioapics, and if we reprogram the
2457 * vector while Remote IRR is still set the irq will never
2458 * fire again.
2459 *
2460 * To prevent this scenario we read the Remote IRR bit
2461 * of the ioapic. This has two effects.
2462 * - On any sane system the read of the ioapic will
2463 * flush writes (and acks) going to the ioapic from
2464 * this cpu.
2465 * - We get to see if the ACK has actually been delivered.
2466 *
2467 * Based on failed experiments of reprogramming the
2468 * ioapic entry from outside of irq context starting
2469 * with masking the ioapic entry and then polling until
2470 * Remote IRR was clear before reprogramming the
2471 * ioapic I don't trust the Remote IRR bit to be
2472 * completey accurate.
2473 *
2474 * However there appears to be no other way to plug
2475 * this race, so if the Remote IRR bit is not
2476 * accurate and is causing problems then it is a hardware bug
2477 * and you can go talk to the chipset vendor about it.
2478 */
2479 if (!io_apic_level_ack_pending(irq))
2480 move_masked_irq(irq);
2481 unmask_IO_APIC_irq(irq);
2482 }
1d025192 2483
3eb2cce8 2484#ifdef CONFIG_X86_32
1d025192
YL		 2485 if (!(v & (1 << (i & 0x1f)))) {
2486 atomic_inc(&irq_mis_count);
2487 spin_lock(&ioapic_lock);
2488 __mask_and_edge_IO_APIC_irq(irq);
2489 __unmask_and_level_IO_APIC_irq(irq);
2490 spin_unlock(&ioapic_lock);
2491 }
047c8fdb 2492#endif
3eb2cce8 2493}
1d025192 2494
f5b9ed7a
IM		 2495static struct irq_chip ioapic_chip __read_mostly = {
2496 .name = "IO-APIC",
ace80ab7
EB		 2497 .startup = startup_ioapic_irq,
2498 .mask = mask_IO_APIC_irq,
2499 .unmask = unmask_IO_APIC_irq,
1d025192
YL		 2500 .ack = ack_apic_edge,
2501 .eoi = ack_apic_level,
54d5d424 2502#ifdef CONFIG_SMP
ace80ab7 2503 .set_affinity = set_ioapic_affinity_irq,
54d5d424 2504#endif
ace80ab7 2505 .retrigger = ioapic_retrigger_irq,
1da177e4
LT		 2506};
2507
54168ed7
IM		 2508#ifdef CONFIG_INTR_REMAP
2509static struct irq_chip ir_ioapic_chip __read_mostly = {
2510 .name = "IR-IO-APIC",
2511 .startup = startup_ioapic_irq,
2512 .mask = mask_IO_APIC_irq,
2513 .unmask = unmask_IO_APIC_irq,
2514 .ack = ack_x2apic_edge,
2515 .eoi = ack_x2apic_level,
2516#ifdef CONFIG_SMP
2517 .set_affinity = set_ir_ioapic_affinity_irq,
2518#endif
2519 .retrigger = ioapic_retrigger_irq,
2520};
2521#endif
1da177e4
LT		 2522
2523static inline void init_IO_APIC_traps(void)
2524{
2525 int irq;
08678b08 2526 struct irq_desc *desc;
da51a821 2527 struct irq_cfg *cfg;
1da177e4
LT		 2528
2529 /*
2530 * NOTE! The local APIC isn't very good at handling
2531 * multiple interrupts at the same interrupt level.
2532 * As the interrupt level is determined by taking the
2533 * vector number and shifting that right by 4, we
2534 * want to spread these out a bit so that they don't
2535 * all fall in the same interrupt level.
2536 *
2537 * Also, we've got to be careful not to trash gate
2538 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2539 */
da51a821
YL		 2540 for_each_irq_cfg(cfg) {
2541 irq = cfg->irq;
2542 if (IO_APIC_IRQ(irq) && !cfg->vector) {
1da177e4
LT		 2543 /*
2544 * Hmm.. We don't have an entry for this,
2545 * so default to an old-fashioned 8259
2546 * interrupt if we can..
2547 */
2548 if (irq < 16)
2549 make_8259A_irq(irq);
08678b08
YL		 2550 else {
2551 desc = irq_to_desc(irq);
1da177e4 2552 /* Strange. Oh, well.. */
08678b08
YL		 2553 desc->chip = &no_irq_chip;
2554 }
1da177e4
LT		 2555 }
2556 }
2557}
2558
f5b9ed7a
IM		 2559/*
2560 * The local APIC irq-chip implementation:
2561 */
1da177e4 2562
36062448 2563static void mask_lapic_irq(unsigned int irq)
1da177e4
LT		 2564{
2565 unsigned long v;
2566
2567 v = apic_read(APIC_LVT0);
593f4a78 2568 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1da177e4
LT		 2569}
2570
36062448 2571static void unmask_lapic_irq(unsigned int irq)
1da177e4 2572{
f5b9ed7a 2573 unsigned long v;
1da177e4 2574
f5b9ed7a 2575 v = apic_read(APIC_LVT0);
593f4a78 2576 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
f5b9ed7a 2577}
1da177e4 2578
54168ed7 2579static void ack_lapic_irq (unsigned int irq)
1d025192
YL		 2580{
2581 ack_APIC_irq();
2582}
2583
f5b9ed7a 2584static struct irq_chip lapic_chip __read_mostly = {
9a1c6192 2585 .name = "local-APIC",
f5b9ed7a
IM		 2586 .mask = mask_lapic_irq,
2587 .unmask = unmask_lapic_irq,
c88ac1df 2588 .ack = ack_lapic_irq,
1da177e4
LT		 2589};
2590
497c9a19 2591static void lapic_register_intr(int irq)
c88ac1df 2592{
08678b08
YL		 2593 struct irq_desc *desc;
2594
2595 desc = irq_to_desc(irq);
2596 desc->status &= ~IRQ_LEVEL;
c88ac1df
MR		 2597 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2598 "edge");
c88ac1df
MR		 2599}
2600
e9427101 2601static void __init setup_nmi(void)
1da177e4
LT		 2602{
2603 /*
36062448 2604 * Dirty trick to enable the NMI watchdog ...
1da177e4
LT		 2605 * We put the 8259A master into AEOI mode and
2606 * unmask on all local APICs LVT0 as NMI.
2607 *
2608 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2609 * is from Maciej W. Rozycki - so we do not have to EOI from
2610 * the NMI handler or the timer interrupt.
36062448 2611 */
1da177e4
LT		 2612 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2613
e9427101 2614 enable_NMI_through_LVT0();
1da177e4
LT		 2615
2616 apic_printk(APIC_VERBOSE, " done.\n");
2617}
2618
2619/*
2620 * This looks a bit hackish but it's about the only one way of sending
2621 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2622 * not support the ExtINT mode, unfortunately. We need to send these
2623 * cycles as some i82489DX-based boards have glue logic that keeps the
2624 * 8259A interrupt line asserted until INTA. --macro
2625 */
28acf285 2626static inline void __init unlock_ExtINT_logic(void)
1da177e4 2627{
fcfd636a 2628 int apic, pin, i;
1da177e4
LT		 2629 struct IO_APIC_route_entry entry0, entry1;
2630 unsigned char save_control, save_freq_select;
1da177e4 2631
fcfd636a 2632 pin = find_isa_irq_pin(8, mp_INT);
956fb531
AB		 2633 if (pin == -1) {
2634 WARN_ON_ONCE(1);
2635 return;
2636 }
fcfd636a 2637 apic = find_isa_irq_apic(8, mp_INT);
956fb531
AB		 2638 if (apic == -1) {
2639 WARN_ON_ONCE(1);
1da177e4 2640 return;
956fb531 2641 }
1da177e4 2642
cf4c6a2f 2643 entry0 = ioapic_read_entry(apic, pin);
fcfd636a 2644 clear_IO_APIC_pin(apic, pin);
1da177e4
LT		 2645
2646 memset(&entry1, 0, sizeof(entry1));
2647
2648 entry1.dest_mode = 0; /* physical delivery */
2649 entry1.mask = 0; /* unmask IRQ now */
d83e94ac 2650 entry1.dest = hard_smp_processor_id();
1da177e4
LT		 2651 entry1.delivery_mode = dest_ExtINT;
2652 entry1.polarity = entry0.polarity;
2653 entry1.trigger = 0;
2654 entry1.vector = 0;
2655
cf4c6a2f 2656 ioapic_write_entry(apic, pin, entry1);
1da177e4
LT		 2657
2658 save_control = CMOS_READ(RTC_CONTROL);
2659 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2660 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2661 RTC_FREQ_SELECT);
2662 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2663
2664 i = 100;
2665 while (i-- > 0) {
2666 mdelay(10);
2667 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2668 i -= 10;
2669 }
2670
2671 CMOS_WRITE(save_control, RTC_CONTROL);
2672 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
fcfd636a 2673 clear_IO_APIC_pin(apic, pin);
1da177e4 2674
cf4c6a2f 2675 ioapic_write_entry(apic, pin, entry0);
1da177e4
LT		 2676}
2677
efa2559f 2678static int disable_timer_pin_1 __initdata;
047c8fdb 2679/* Actually the next is obsolete, but keep it for paranoid reasons -AK */
54168ed7 2680static int __init disable_timer_pin_setup(char *arg)
efa2559f
YL		 2681{
2682 disable_timer_pin_1 = 1;
2683 return 0;
2684}
54168ed7 2685early_param("disable_timer_pin_1", disable_timer_pin_setup);
efa2559f
YL		 2686
2687int timer_through_8259 __initdata;
2688
1da177e4
LT		 2689/*
2690 * This code may look a bit paranoid, but it's supposed to cooperate with
2691 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2692 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2693 * fanatically on his truly buggy board.
54168ed7
IM		 2694 *
2695 * FIXME: really need to revamp this for all platforms.
1da177e4 2696 */
8542b200 2697static inline void __init check_timer(void)
1da177e4 2698{
497c9a19 2699 struct irq_cfg *cfg = irq_cfg(0);
fcfd636a 2700 int apic1, pin1, apic2, pin2;
4aae0702 2701 unsigned long flags;
047c8fdb
YL		 2702 unsigned int ver;
2703 int no_pin1 = 0;
4aae0702
IM		 2704
2705 local_irq_save(flags);
d4d25dec 2706
54168ed7
IM		 2707 ver = apic_read(APIC_LVR);
2708 ver = GET_APIC_VERSION(ver);
6e908947 2709
1da177e4
LT		 2710 /*
2711 * get/set the timer IRQ vector:
2712 */
2713 disable_8259A_irq(0);
497c9a19 2714 assign_irq_vector(0, TARGET_CPUS);
1da177e4
LT		 2715
2716 /*
d11d5794
MR		 2717 * As IRQ0 is to be enabled in the 8259A, the virtual
2718 * wire has to be disabled in the local APIC. Also
2719 * timer interrupts need to be acknowledged manually in
2720 * the 8259A for the i82489DX when using the NMI
2721 * watchdog as that APIC treats NMIs as level-triggered.
2722 * The AEOI mode will finish them in the 8259A
2723 * automatically.
1da177e4 2724 */
593f4a78 2725 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1da177e4 2726 init_8259A(1);
54168ed7 2727#ifdef CONFIG_X86_32
d11d5794 2728 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
54168ed7 2729#endif
1da177e4 2730
fcfd636a
EB		 2731 pin1 = find_isa_irq_pin(0, mp_INT);
2732 apic1 = find_isa_irq_apic(0, mp_INT);
2733 pin2 = ioapic_i8259.pin;
2734 apic2 = ioapic_i8259.apic;
1da177e4 2735
49a66a0b
MR		 2736 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2737 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
497c9a19 2738 cfg->vector, apic1, pin1, apic2, pin2);
1da177e4 2739
691874fa
MR		 2740 /*
2741 * Some BIOS writers are clueless and report the ExtINTA
2742 * I/O APIC input from the cascaded 8259A as the timer
2743 * interrupt input. So just in case, if only one pin
2744 * was found above, try it both directly and through the
2745 * 8259A.
2746 */
2747 if (pin1 == -1) {
54168ed7
IM		 2748#ifdef CONFIG_INTR_REMAP
2749 if (intr_remapping_enabled)
2750 panic("BIOS bug: timer not connected to IO-APIC");
2751#endif
691874fa
MR		 2752 pin1 = pin2;
2753 apic1 = apic2;
2754 no_pin1 = 1;
2755 } else if (pin2 == -1) {
2756 pin2 = pin1;
2757 apic2 = apic1;
2758 }
2759
1da177e4
LT		 2760 if (pin1 != -1) {
2761 /*
2762 * Ok, does IRQ0 through the IOAPIC work?
2763 */
691874fa
MR		 2764 if (no_pin1) {
2765 add_pin_to_irq(0, apic1, pin1);
497c9a19 2766 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
691874fa 2767 }
1da177e4
LT		 2768 unmask_IO_APIC_irq(0);
2769 if (timer_irq_works()) {
2770 if (nmi_watchdog == NMI_IO_APIC) {
1da177e4
LT		 2771 setup_nmi();
2772 enable_8259A_irq(0);
1da177e4 2773 }
66759a01
CE		 2774 if (disable_timer_pin_1 > 0)
2775 clear_IO_APIC_pin(0, pin1);
4aae0702 2776 goto out;
1da177e4 2777 }
54168ed7
IM		 2778#ifdef CONFIG_INTR_REMAP
2779 if (intr_remapping_enabled)
2780 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2781#endif
fcfd636a 2782 clear_IO_APIC_pin(apic1, pin1);
691874fa 2783 if (!no_pin1)
49a66a0b
MR		 2784 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2785 "8254 timer not connected to IO-APIC\n");
1da177e4 2786
49a66a0b
MR		 2787 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2788 "(IRQ0) through the 8259A ...\n");
2789 apic_printk(APIC_QUIET, KERN_INFO
2790 "..... (found apic %d pin %d) ...\n", apic2, pin2);
1da177e4
LT		 2791 /*
2792 * legacy devices should be connected to IO APIC #0
2793 */
691874fa 2794 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
497c9a19 2795 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
24742ece 2796 unmask_IO_APIC_irq(0);
ecd29476 2797 enable_8259A_irq(0);
1da177e4 2798 if (timer_irq_works()) {
49a66a0b 2799 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
35542c5e 2800 timer_through_8259 = 1;
1da177e4 2801 if (nmi_watchdog == NMI_IO_APIC) {
60134ebe 2802 disable_8259A_irq(0);
1da177e4 2803 setup_nmi();
60134ebe 2804 enable_8259A_irq(0);
1da177e4 2805 }
4aae0702 2806 goto out;
1da177e4
LT		 2807 }
2808 /*
2809 * Cleanup, just in case ...
2810 */
ecd29476 2811 disable_8259A_irq(0);
fcfd636a 2812 clear_IO_APIC_pin(apic2, pin2);
49a66a0b 2813 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
1da177e4 2814 }
1da177e4
LT		 2815
2816 if (nmi_watchdog == NMI_IO_APIC) {
49a66a0b
MR		 2817 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2818 "through the IO-APIC - disabling NMI Watchdog!\n");
067fa0ff 2819 nmi_watchdog = NMI_NONE;
1da177e4 2820 }
54168ed7 2821#ifdef CONFIG_X86_32
d11d5794 2822 timer_ack = 0;
54168ed7 2823#endif
1da177e4 2824
49a66a0b
MR		 2825 apic_printk(APIC_QUIET, KERN_INFO
2826 "...trying to set up timer as Virtual Wire IRQ...\n");
1da177e4 2827
497c9a19
YL		 2828 lapic_register_intr(0);
2829 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
1da177e4
LT		 2830 enable_8259A_irq(0);
2831
2832 if (timer_irq_works()) {
49a66a0b 2833 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
4aae0702 2834 goto out;
1da177e4 2835 }
e67465f1 2836 disable_8259A_irq(0);
497c9a19 2837 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
49a66a0b 2838 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
1da177e4 2839
49a66a0b
MR		 2840 apic_printk(APIC_QUIET, KERN_INFO
2841 "...trying to set up timer as ExtINT IRQ...\n");
1da177e4 2842
1da177e4
LT		 2843 init_8259A(0);
2844 make_8259A_irq(0);
593f4a78 2845 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1da177e4
LT		 2846
2847 unlock_ExtINT_logic();
2848
2849 if (timer_irq_works()) {
49a66a0b 2850 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
4aae0702 2851 goto out;
1da177e4 2852 }
49a66a0b 2853 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
1da177e4 2854 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
49a66a0b 2855 "report. Then try booting with the 'noapic' option.\n");
4aae0702
IM		 2856out:
2857 local_irq_restore(flags);
1da177e4
LT		 2858}
2859
2860/*
af174783
MR		 2861 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2862 * to devices. However there may be an I/O APIC pin available for
2863 * this interrupt regardless. The pin may be left unconnected, but
2864 * typically it will be reused as an ExtINT cascade interrupt for
2865 * the master 8259A. In the MPS case such a pin will normally be
2866 * reported as an ExtINT interrupt in the MP table. With ACPI
2867 * there is no provision for ExtINT interrupts, and in the absence
2868 * of an override it would be treated as an ordinary ISA I/O APIC
2869 * interrupt, that is edge-triggered and unmasked by default. We
2870 * used to do this, but it caused problems on some systems because
2871 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2872 * the same ExtINT cascade interrupt to drive the local APIC of the
2873 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2874 * the I/O APIC in all cases now. No actual device should request
2875 * it anyway. --macro
1da177e4
LT		 2876 */
2877#define PIC_IRQS (1 << PIC_CASCADE_IR)
2878
2879void __init setup_IO_APIC(void)
2880{
54168ed7
IM		 2881
2882#ifdef CONFIG_X86_32
1da177e4 2883 enable_IO_APIC();
54168ed7
IM		 2884#else
2885 /*
2886 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2887 */
2888#endif
1da177e4 2889
af174783 2890 io_apic_irqs = ~PIC_IRQS;
1da177e4 2891
54168ed7
IM		 2892 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2893 /*
2894 * Set up IO-APIC IRQ routing.
2895 */
2896#ifdef CONFIG_X86_32
2897 if (!acpi_ioapic)
2898 setup_ioapic_ids_from_mpc();
2899#endif
1da177e4
LT		 2900 sync_Arb_IDs();
2901 setup_IO_APIC_irqs();
2902 init_IO_APIC_traps();
1e4c85f9 2903 check_timer();
1da177e4
LT		 2904}
2905
2906/*
54168ed7
IM		 2907 * Called after all the initialization is done. If we didnt find any
2908 * APIC bugs then we can allow the modify fast path
1da177e4 2909 */
36062448 2910
1da177e4
LT		 2911static int __init io_apic_bug_finalize(void)
2912{
54168ed7
IM		 2913 if (sis_apic_bug == -1)
2914 sis_apic_bug = 0;
2915 return 0;
1da177e4
LT		 2916}
2917
2918late_initcall(io_apic_bug_finalize);
2919
2920struct sysfs_ioapic_data {
2921 struct sys_device dev;
2922 struct IO_APIC_route_entry entry[0];
2923};
54168ed7 2924static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1da177e4 2925
438510f6 2926static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1da177e4
LT		 2927{
2928 struct IO_APIC_route_entry *entry;
2929 struct sysfs_ioapic_data *data;
1da177e4 2930 int i;
36062448 2931
1da177e4
LT		 2932 data = container_of(dev, struct sysfs_ioapic_data, dev);
2933 entry = data->entry;
54168ed7
IM		 2934 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
2935 *entry = ioapic_read_entry(dev->id, i);
1da177e4
LT		 2936
2937 return 0;
2938}
2939
2940static int ioapic_resume(struct sys_device *dev)
2941{
2942 struct IO_APIC_route_entry *entry;
2943 struct sysfs_ioapic_data *data;
2944 unsigned long flags;
2945 union IO_APIC_reg_00 reg_00;
2946 int i;
36062448 2947
1da177e4
LT		 2948 data = container_of(dev, struct sysfs_ioapic_data, dev);
2949 entry = data->entry;
2950
2951 spin_lock_irqsave(&ioapic_lock, flags);
2952 reg_00.raw = io_apic_read(dev->id, 0);
ec2cd0a2
AS		 2953 if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) {
2954 reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid;
1da177e4
LT		 2955 io_apic_write(dev->id, 0, reg_00.raw);
2956 }
1da177e4 2957 spin_unlock_irqrestore(&ioapic_lock, flags);
36062448 2958 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
cf4c6a2f 2959 ioapic_write_entry(dev->id, i, entry[i]);
1da177e4
LT		 2960
2961 return 0;
2962}
2963
2964static struct sysdev_class ioapic_sysdev_class = {
af5ca3f4 2965 .name = "ioapic",
1da177e4
LT		 2966 .suspend = ioapic_suspend,
2967 .resume = ioapic_resume,
2968};
2969
2970static int __init ioapic_init_sysfs(void)
2971{
54168ed7
IM		 2972 struct sys_device * dev;
2973 int i, size, error;
1da177e4
LT		 2974
2975 error = sysdev_class_register(&ioapic_sysdev_class);
2976 if (error)
2977 return error;
2978
54168ed7 2979 for (i = 0; i < nr_ioapics; i++ ) {
36062448 2980 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1da177e4 2981 * sizeof(struct IO_APIC_route_entry);
25556c16 2982 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
1da177e4
LT		 2983 if (!mp_ioapic_data[i]) {
2984 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2985 continue;
2986 }
1da177e4 2987 dev = &mp_ioapic_data[i]->dev;
36062448 2988 dev->id = i;
1da177e4
LT		 2989 dev->cls = &ioapic_sysdev_class;
2990 error = sysdev_register(dev);
2991 if (error) {
2992 kfree(mp_ioapic_data[i]);
2993 mp_ioapic_data[i] = NULL;
2994 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2995 continue;
2996 }
2997 }
2998
2999 return 0;
3000}
3001
3002device_initcall(ioapic_init_sysfs);
3003
3fc471ed 3004/*
95d77884 3005 * Dynamic irq allocate and deallocation
3fc471ed 3006 */
199751d7 3007unsigned int create_irq_nr(unsigned int irq_want)
3fc471ed 3008{
ace80ab7 3009 /* Allocate an unused irq */
54168ed7
IM		 3010 unsigned int irq;
3011 unsigned int new;
3fc471ed 3012 unsigned long flags;
da51a821 3013 struct irq_cfg *cfg_new;
3fc471ed 3014
497c9a19 3015#ifndef CONFIG_HAVE_SPARSE_IRQ
199751d7 3016 irq_want = nr_irqs - 1;
497c9a19 3017#endif
199751d7
YL		 3018
3019 irq = 0;
ace80ab7 3020 spin_lock_irqsave(&vector_lock, flags);
54168ed7 3021 for (new = irq_want; new > 0; new--) {
ace80ab7
EB		 3022 if (platform_legacy_irq(new))
3023 continue;
da51a821
YL		 3024 cfg_new = irq_cfg(new);
3025 if (cfg_new && cfg_new->vector != 0)
ace80ab7 3026 continue;
047c8fdb 3027 /* check if need to create one */
da51a821
YL		 3028 if (!cfg_new)
3029 cfg_new = irq_cfg_alloc(new);
497c9a19 3030 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
ace80ab7
EB		 3031 irq = new;
3032 break;
3033 }
3034 spin_unlock_irqrestore(&vector_lock, flags);
3fc471ed 3035
199751d7 3036 if (irq > 0) {
3fc471ed
EB		 3037 dynamic_irq_init(irq);
3038 }
3039 return irq;
3040}
3041
199751d7
YL		 3042int create_irq(void)
3043{
54168ed7
IM		 3044 int irq;
3045
3046 irq = create_irq_nr(nr_irqs - 1);
3047
3048 if (irq == 0)
3049 irq = -1;
3050
3051 return irq;
199751d7
YL		 3052}
3053
3fc471ed
EB		 3054void destroy_irq(unsigned int irq)
3055{
3056 unsigned long flags;
3fc471ed
EB		 3057
3058 dynamic_irq_cleanup(irq);
3059
54168ed7
IM		 3060#ifdef CONFIG_INTR_REMAP
3061 free_irte(irq);
3062#endif
3fc471ed 3063 spin_lock_irqsave(&vector_lock, flags);
497c9a19 3064 __clear_irq_vector(irq);
3fc471ed
EB		 3065 spin_unlock_irqrestore(&vector_lock, flags);
3066}
3fc471ed 3067
2d3fcc1c 3068/*
27b46d76 3069 * MSI message composition
2d3fcc1c
EB		 3070 */
3071#ifdef CONFIG_PCI_MSI
3b7d1921 3072static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2d3fcc1c 3073{
497c9a19
YL		 3074 struct irq_cfg *cfg;
3075 int err;
2d3fcc1c 3076 unsigned dest;
497c9a19 3077 cpumask_t tmp;
2d3fcc1c 3078
497c9a19
YL		 3079 tmp = TARGET_CPUS;
3080 err = assign_irq_vector(irq, tmp);
3081 if (err)
3082 return err;
2d3fcc1c 3083
497c9a19
YL		 3084 cfg = irq_cfg(irq);
3085 cpus_and(tmp, cfg->domain, tmp);
3086 dest = cpu_mask_to_apicid(tmp);
3087
54168ed7
IM		 3088#ifdef CONFIG_INTR_REMAP
3089 if (irq_remapped(irq)) {
3090 struct irte irte;
3091 int ir_index;
3092 u16 sub_handle;
3093
3094 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3095 BUG_ON(ir_index == -1);
3096
3097 memset (&irte, 0, sizeof(irte));
3098
3099 irte.present = 1;
3100 irte.dst_mode = INT_DEST_MODE;
3101 irte.trigger_mode = 0; /* edge */
3102 irte.dlvry_mode = INT_DELIVERY_MODE;
3103 irte.vector = cfg->vector;
3104 irte.dest_id = IRTE_DEST(dest);
3105
3106 modify_irte(irq, &irte);
3107
3108 msg->address_hi = MSI_ADDR_BASE_HI;
3109 msg->data = sub_handle;
3110 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3111 MSI_ADDR_IR_SHV |
3112 MSI_ADDR_IR_INDEX1(ir_index) |
3113 MSI_ADDR_IR_INDEX2(ir_index);
3114 } else
3115#endif
3116 {
3117 msg->address_hi = MSI_ADDR_BASE_HI;
3118 msg->address_lo =
3119 MSI_ADDR_BASE_LO |
3120 ((INT_DEST_MODE == 0) ?
3121 MSI_ADDR_DEST_MODE_PHYSICAL:
3122 MSI_ADDR_DEST_MODE_LOGICAL) |
3123 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3124 MSI_ADDR_REDIRECTION_CPU:
3125 MSI_ADDR_REDIRECTION_LOWPRI) |
3126 MSI_ADDR_DEST_ID(dest);
497c9a19 3127
54168ed7
IM		 3128 msg->data =
3129 MSI_DATA_TRIGGER_EDGE |
3130 MSI_DATA_LEVEL_ASSERT |
3131 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3132 MSI_DATA_DELIVERY_FIXED:
3133 MSI_DATA_DELIVERY_LOWPRI) |
3134 MSI_DATA_VECTOR(cfg->vector);
3135 }
497c9a19 3136 return err;
2d3fcc1c
EB		 3137}
3138
3b7d1921
EB		 3139#ifdef CONFIG_SMP
3140static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2d3fcc1c 3141{
497c9a19 3142 struct irq_cfg *cfg;
3b7d1921
EB		 3143 struct msi_msg msg;
3144 unsigned int dest;
3145 cpumask_t tmp;
54168ed7 3146 struct irq_desc *desc;
3b7d1921
EB		 3147
3148 cpus_and(tmp, mask, cpu_online_map);
3149 if (cpus_empty(tmp))
497c9a19 3150 return;
2d3fcc1c 3151
497c9a19 3152 if (assign_irq_vector(irq, mask))
3b7d1921 3153 return;
2d3fcc1c 3154
497c9a19
YL		 3155 cfg = irq_cfg(irq);
3156 cpus_and(tmp, cfg->domain, mask);
3157 dest = cpu_mask_to_apicid(tmp);
3b7d1921
EB		 3158
3159 read_msi_msg(irq, &msg);
3160
3161 msg.data &= ~MSI_DATA_VECTOR_MASK;
497c9a19 3162 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3b7d1921
EB		 3163 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3164 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3165
3166 write_msi_msg(irq, &msg);
54168ed7
IM		 3167 desc = irq_to_desc(irq);
3168 desc->affinity = mask;
2d3fcc1c 3169}
54168ed7
IM		 3170
3171#ifdef CONFIG_INTR_REMAP
3172/*
3173 * Migrate the MSI irq to another cpumask. This migration is
3174 * done in the process context using interrupt-remapping hardware.
3175 */
3176static void ir_set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
3177{
3178 struct irq_cfg *cfg;
3179 unsigned int dest;
3180 cpumask_t tmp, cleanup_mask;
3181 struct irte irte;
3182 struct irq_desc *desc;
3183
3184 cpus_and(tmp, mask, cpu_online_map);
3185 if (cpus_empty(tmp))
3186 return;
3187
3188 if (get_irte(irq, &irte))
3189 return;
3190
3191 if (assign_irq_vector(irq, mask))
3192 return;
3193
3194 cfg = irq_cfg(irq);
3195 cpus_and(tmp, cfg->domain, mask);
3196 dest = cpu_mask_to_apicid(tmp);
3197
3198 irte.vector = cfg->vector;
3199 irte.dest_id = IRTE_DEST(dest);
3200
3201 /*
3202 * atomically update the IRTE with the new destination and vector.
3203 */
3204 modify_irte(irq, &irte);
3205
3206 /*
3207 * After this point, all the interrupts will start arriving
3208 * at the new destination. So, time to cleanup the previous
3209 * vector allocation.
3210 */
3211 if (cfg->move_in_progress) {
3212 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
3213 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
3214 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
3215 cfg->move_in_progress = 0;
3216 }
3217
3218 desc = irq_to_desc(irq);
3219 desc->affinity = mask;
3220}
3221#endif
3b7d1921 3222#endif /* CONFIG_SMP */
2d3fcc1c 3223
3b7d1921
EB		 3224/*
3225 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3226 * which implement the MSI or MSI-X Capability Structure.
3227 */
3228static struct irq_chip msi_chip = {
3229 .name = "PCI-MSI",
3230 .unmask = unmask_msi_irq,
3231 .mask = mask_msi_irq,
1d025192 3232 .ack = ack_apic_edge,
3b7d1921
EB		 3233#ifdef CONFIG_SMP
3234 .set_affinity = set_msi_irq_affinity,
3235#endif
3236 .retrigger = ioapic_retrigger_irq,
2d3fcc1c
EB		 3237};
3238
54168ed7
IM		 3239#ifdef CONFIG_INTR_REMAP
3240static struct irq_chip msi_ir_chip = {
3241 .name = "IR-PCI-MSI",
3242 .unmask = unmask_msi_irq,
3243 .mask = mask_msi_irq,
3244 .ack = ack_x2apic_edge,
3245#ifdef CONFIG_SMP
3246 .set_affinity = ir_set_msi_irq_affinity,
3247#endif
3248 .retrigger = ioapic_retrigger_irq,
3249};
3250
3251/*
3252 * Map the PCI dev to the corresponding remapping hardware unit
3253 * and allocate 'nvec' consecutive interrupt-remapping table entries
3254 * in it.
3255 */
3256static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3257{
3258 struct intel_iommu *iommu;
3259 int index;
3260
3261 iommu = map_dev_to_ir(dev);
3262 if (!iommu) {
3263 printk(KERN_ERR
3264 "Unable to map PCI %s to iommu\n", pci_name(dev));
3265 return -ENOENT;
3266 }
3267
3268 index = alloc_irte(iommu, irq, nvec);
3269 if (index < 0) {
3270 printk(KERN_ERR
3271 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3272 pci_name(dev));
3273 return -ENOSPC;
3274 }
3275 return index;
3276}
3277#endif
1d025192
YL		 3278
3279static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc, int irq)
3280{
3281 int ret;
3282 struct msi_msg msg;
3283
3284 ret = msi_compose_msg(dev, irq, &msg);
3285 if (ret < 0)
3286 return ret;
3287
3288 set_irq_msi(irq, desc);
3289 write_msi_msg(irq, &msg);
3290
54168ed7
IM		 3291#ifdef CONFIG_INTR_REMAP
3292 if (irq_remapped(irq)) {
3293 struct irq_desc *desc = irq_to_desc(irq);
3294 /*
3295 * irq migration in process context
3296 */
3297 desc->status |= IRQ_MOVE_PCNTXT;
3298 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3299 } else
3300#endif
3301 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
1d025192
YL		 3302
3303 return 0;
3304}
3305
199751d7
YL		 3306static unsigned int build_irq_for_pci_dev(struct pci_dev *dev)
3307{
3308 unsigned int irq;
3309
3310 irq = dev->bus->number;
3311 irq <<= 8;
3312 irq |= dev->devfn;
3313 irq <<= 12;
3314
3315 return irq;
3316}
3317
f7feaca7 3318int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
3b7d1921 3319{
54168ed7
IM		 3320 unsigned int irq;
3321 int ret;
199751d7
YL		 3322 unsigned int irq_want;
3323
3324 irq_want = build_irq_for_pci_dev(dev) + 0x100;
3325
3326 irq = create_irq_nr(irq_want);
199751d7
YL		 3327 if (irq == 0)
3328 return -1;
f7feaca7 3329
54168ed7
IM		 3330#ifdef CONFIG_INTR_REMAP
3331 if (!intr_remapping_enabled)
3332 goto no_ir;
3333
3334 ret = msi_alloc_irte(dev, irq, 1);
3335 if (ret < 0)
3336 goto error;
3337no_ir:
3338#endif
1d025192 3339 ret = setup_msi_irq(dev, desc, irq);
f7feaca7
EB		 3340 if (ret < 0) {
3341 destroy_irq(irq);
3b7d1921 3342 return ret;
54168ed7 3343 }
7fe3730d 3344 return 0;
54168ed7
IM		 3345
3346#ifdef CONFIG_INTR_REMAP
3347error:
3348 destroy_irq(irq);
3349 return ret;
3350#endif
3b7d1921
EB		 3351}
3352
047c8fdb
YL		 3353int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3354{
54168ed7
IM		 3355 unsigned int irq;
3356 int ret, sub_handle;
3357 struct msi_desc *desc;
3358 unsigned int irq_want;
3359
3360#ifdef CONFIG_INTR_REMAP
3361 struct intel_iommu *iommu = 0;
3362 int index = 0;
3363#endif
3364
3365 irq_want = build_irq_for_pci_dev(dev) + 0x100;
3366 sub_handle = 0;
3367 list_for_each_entry(desc, &dev->msi_list, list) {
3368 irq = create_irq_nr(irq_want--);
3369 if (irq == 0)
3370 return -1;
3371#ifdef CONFIG_INTR_REMAP
3372 if (!intr_remapping_enabled)
3373 goto no_ir;
3374
3375 if (!sub_handle) {
3376 /*
3377 * allocate the consecutive block of IRTE's
3378 * for 'nvec'
3379 */
3380 index = msi_alloc_irte(dev, irq, nvec);
3381 if (index < 0) {
3382 ret = index;
3383 goto error;
3384 }
3385 } else {
3386 iommu = map_dev_to_ir(dev);
3387 if (!iommu) {
3388 ret = -ENOENT;
3389 goto error;
3390 }
3391 /*
3392 * setup the mapping between the irq and the IRTE
3393 * base index, the sub_handle pointing to the
3394 * appropriate interrupt remap table entry.
3395 */
3396 set_irte_irq(irq, iommu, index, sub_handle);
3397 }
3398no_ir:
3399#endif
3400 ret = setup_msi_irq(dev, desc, irq);
3401 if (ret < 0)
3402 goto error;
3403 sub_handle++;
3404 }
3405 return 0;
047c8fdb
YL		 3406
3407error:
54168ed7
IM		 3408 destroy_irq(irq);
3409 return ret;
047c8fdb
YL		 3410}
3411
3b7d1921
EB		 3412void arch_teardown_msi_irq(unsigned int irq)
3413{
f7feaca7 3414 destroy_irq(irq);
3b7d1921
EB		 3415}
3416
54168ed7
IM		 3417#ifdef CONFIG_DMAR
3418#ifdef CONFIG_SMP
3419static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask)
3420{
3421 struct irq_cfg *cfg;
3422 struct msi_msg msg;
3423 unsigned int dest;
3424 cpumask_t tmp;
3425 struct irq_desc *desc;
3426
3427 cpus_and(tmp, mask, cpu_online_map);
3428 if (cpus_empty(tmp))
3429 return;
3430
3431 if (assign_irq_vector(irq, mask))
3432 return;
3433
3434 cfg = irq_cfg(irq);
3435 cpus_and(tmp, cfg->domain, mask);
3436 dest = cpu_mask_to_apicid(tmp);
3437
3438 dmar_msi_read(irq, &msg);
3439
3440 msg.data &= ~MSI_DATA_VECTOR_MASK;
3441 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3442 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3443 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3444
3445 dmar_msi_write(irq, &msg);
3446 desc = irq_to_desc(irq);
3447 desc->affinity = mask;
3448}
3449#endif /* CONFIG_SMP */
3450
3451struct irq_chip dmar_msi_type = {
3452 .name = "DMAR_MSI",
3453 .unmask = dmar_msi_unmask,
3454 .mask = dmar_msi_mask,
3455 .ack = ack_apic_edge,
3456#ifdef CONFIG_SMP
3457 .set_affinity = dmar_msi_set_affinity,
3458#endif
3459 .retrigger = ioapic_retrigger_irq,
3460};
3461
3462int arch_setup_dmar_msi(unsigned int irq)
3463{
3464 int ret;
3465 struct msi_msg msg;
2d3fcc1c 3466
54168ed7
IM		 3467 ret = msi_compose_msg(NULL, irq, &msg);
3468 if (ret < 0)
3469 return ret;
3470 dmar_msi_write(irq, &msg);
3471 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3472 "edge");
3473 return 0;
3474}
3475#endif
3476
3477#endif /* CONFIG_PCI_MSI */
8b955b0d
EB		 3478/*
3479 * Hypertransport interrupt support
3480 */
3481#ifdef CONFIG_HT_IRQ
3482
3483#ifdef CONFIG_SMP
3484
497c9a19 3485static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
8b955b0d 3486{
ec68307c
EB		 3487 struct ht_irq_msg msg;
3488 fetch_ht_irq_msg(irq, &msg);
8b955b0d 3489
497c9a19 3490 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
ec68307c 3491 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
8b955b0d 3492
497c9a19 3493 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
ec68307c 3494 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
8b955b0d 3495
ec68307c 3496 write_ht_irq_msg(irq, &msg);
8b955b0d
EB		 3497}
3498
3499static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
3500{
497c9a19 3501 struct irq_cfg *cfg;
8b955b0d
EB		 3502 unsigned int dest;
3503 cpumask_t tmp;
54168ed7 3504 struct irq_desc *desc;
8b955b0d
EB		 3505
3506 cpus_and(tmp, mask, cpu_online_map);
3507 if (cpus_empty(tmp))
497c9a19 3508 return;
8b955b0d 3509
497c9a19
YL		 3510 if (assign_irq_vector(irq, mask))
3511 return;
8b955b0d 3512
497c9a19
YL		 3513 cfg = irq_cfg(irq);
3514 cpus_and(tmp, cfg->domain, mask);
3515 dest = cpu_mask_to_apicid(tmp);
8b955b0d 3516
497c9a19 3517 target_ht_irq(irq, dest, cfg->vector);
54168ed7
IM		 3518 desc = irq_to_desc(irq);
3519 desc->affinity = mask;
8b955b0d
EB		 3520}
3521#endif
3522
c37e108d 3523static struct irq_chip ht_irq_chip = {
8b955b0d
EB		 3524 .name = "PCI-HT",
3525 .mask = mask_ht_irq,
3526 .unmask = unmask_ht_irq,
1d025192 3527 .ack = ack_apic_edge,
8b955b0d
EB		 3528#ifdef CONFIG_SMP
3529 .set_affinity = set_ht_irq_affinity,
3530#endif
3531 .retrigger = ioapic_retrigger_irq,
3532};
3533
3534int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3535{
497c9a19
YL		 3536 struct irq_cfg *cfg;
3537 int err;
3538 cpumask_t tmp;
8b955b0d 3539
497c9a19
YL		 3540 tmp = TARGET_CPUS;
3541 err = assign_irq_vector(irq, tmp);
54168ed7 3542 if (!err) {
ec68307c 3543 struct ht_irq_msg msg;
8b955b0d 3544 unsigned dest;
8b955b0d 3545
497c9a19
YL		 3546 cfg = irq_cfg(irq);
3547 cpus_and(tmp, cfg->domain, tmp);
8b955b0d
EB		 3548 dest = cpu_mask_to_apicid(tmp);
3549
ec68307c 3550 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
8b955b0d 3551
ec68307c
EB		 3552 msg.address_lo =
3553 HT_IRQ_LOW_BASE |
8b955b0d 3554 HT_IRQ_LOW_DEST_ID(dest) |
497c9a19 3555 HT_IRQ_LOW_VECTOR(cfg->vector) |
8b955b0d
EB		 3556 ((INT_DEST_MODE == 0) ?
3557 HT_IRQ_LOW_DM_PHYSICAL :
3558 HT_IRQ_LOW_DM_LOGICAL) |
3559 HT_IRQ_LOW_RQEOI_EDGE |
3560 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3561 HT_IRQ_LOW_MT_FIXED :
3562 HT_IRQ_LOW_MT_ARBITRATED) |
3563 HT_IRQ_LOW_IRQ_MASKED;
3564
ec68307c 3565 write_ht_irq_msg(irq, &msg);
8b955b0d 3566
a460e745
IM		 3567 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3568 handle_edge_irq, "edge");
8b955b0d 3569 }
497c9a19 3570 return err;
8b955b0d
EB		 3571}
3572#endif /* CONFIG_HT_IRQ */
3573
1da177e4 3574/* --------------------------------------------------------------------------
54168ed7 3575 ACPI-based IOAPIC Configuration
1da177e4
LT		 3576 -------------------------------------------------------------------------- */
3577
888ba6c6 3578#ifdef CONFIG_ACPI
1da177e4 3579
54168ed7 3580#ifdef CONFIG_X86_32
36062448 3581int __init io_apic_get_unique_id(int ioapic, int apic_id)
1da177e4
LT		 3582{
3583 union IO_APIC_reg_00 reg_00;
3584 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3585 physid_mask_t tmp;
3586 unsigned long flags;
3587 int i = 0;
3588
3589 /*
36062448
PC		 3590 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3591 * buses (one for LAPICs, one for IOAPICs), where predecessors only
1da177e4 3592 * supports up to 16 on one shared APIC bus.
36062448 3593 *
1da177e4
LT		 3594 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3595 * advantage of new APIC bus architecture.
3596 */
3597
3598 if (physids_empty(apic_id_map))
3599 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
3600
3601 spin_lock_irqsave(&ioapic_lock, flags);
3602 reg_00.raw = io_apic_read(ioapic, 0);
3603 spin_unlock_irqrestore(&ioapic_lock, flags);
3604
3605 if (apic_id >= get_physical_broadcast()) {
3606 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3607 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3608 apic_id = reg_00.bits.ID;
3609 }
3610
3611 /*
36062448 3612 * Every APIC in a system must have a unique ID or we get lots of nice
1da177e4
LT		 3613 * 'stuck on smp_invalidate_needed IPI wait' messages.
3614 */
3615 if (check_apicid_used(apic_id_map, apic_id)) {
3616
3617 for (i = 0; i < get_physical_broadcast(); i++) {
3618 if (!check_apicid_used(apic_id_map, i))
3619 break;
3620 }
3621
3622 if (i == get_physical_broadcast())
3623 panic("Max apic_id exceeded!\n");
3624
3625 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3626 "trying %d\n", ioapic, apic_id, i);
3627
3628 apic_id = i;
36062448 3629 }
1da177e4
LT		 3630
3631 tmp = apicid_to_cpu_present(apic_id);
3632 physids_or(apic_id_map, apic_id_map, tmp);
3633
3634 if (reg_00.bits.ID != apic_id) {
3635 reg_00.bits.ID = apic_id;
3636
3637 spin_lock_irqsave(&ioapic_lock, flags);
3638 io_apic_write(ioapic, 0, reg_00.raw);
3639 reg_00.raw = io_apic_read(ioapic, 0);
3640 spin_unlock_irqrestore(&ioapic_lock, flags);
3641
3642 /* Sanity check */
6070f9ec
AD		 3643 if (reg_00.bits.ID != apic_id) {
3644 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3645 return -1;
3646 }
1da177e4
LT		 3647 }
3648
3649 apic_printk(APIC_VERBOSE, KERN_INFO
3650 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3651
3652 return apic_id;
3653}
3654
36062448 3655int __init io_apic_get_version(int ioapic)
1da177e4
LT		 3656{
3657 union IO_APIC_reg_01 reg_01;
3658 unsigned long flags;
3659
3660 spin_lock_irqsave(&ioapic_lock, flags);
3661 reg_01.raw = io_apic_read(ioapic, 1);
3662 spin_unlock_irqrestore(&ioapic_lock, flags);
3663
3664 return reg_01.bits.version;
3665}
54168ed7 3666#endif
1da177e4 3667
54168ed7 3668int __init io_apic_get_redir_entries (int ioapic)
1da177e4
LT		 3669{
3670 union IO_APIC_reg_01 reg_01;
3671 unsigned long flags;
3672
3673 spin_lock_irqsave(&ioapic_lock, flags);
3674 reg_01.raw = io_apic_read(ioapic, 1);
3675 spin_unlock_irqrestore(&ioapic_lock, flags);
3676
3677 return reg_01.bits.entries;
3678}
3679
3680
54168ed7 3681int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
1da177e4 3682{
1da177e4 3683 if (!IO_APIC_IRQ(irq)) {
54168ed7 3684 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
1da177e4
LT		 3685 ioapic);
3686 return -EINVAL;
3687 }
3688
1da177e4
LT		 3689 /*
3690 * IRQs < 16 are already in the irq_2_pin[] map
3691 */
3692 if (irq >= 16)
3693 add_pin_to_irq(irq, ioapic, pin);
3694
497c9a19 3695 setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
1da177e4
LT		 3696
3697 return 0;
3698}
3699
54168ed7 3700
61fd47e0
SL		 3701int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
3702{
3703 int i;
3704
3705 if (skip_ioapic_setup)
3706 return -1;
3707
3708 for (i = 0; i < mp_irq_entries; i++)
2fddb6e2
AS		 3709 if (mp_irqs[i].mp_irqtype == mp_INT &&
3710 mp_irqs[i].mp_srcbusirq == bus_irq)
61fd47e0
SL		 3711 break;
3712 if (i >= mp_irq_entries)
3713 return -1;
3714
3715 *trigger = irq_trigger(i);
3716 *polarity = irq_polarity(i);
3717 return 0;
3718}
3719
888ba6c6 3720#endif /* CONFIG_ACPI */
1a3f239d 3721
497c9a19
YL		 3722/*
3723 * This function currently is only a helper for the i386 smp boot process where
3724 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3725 * so mask in all cases should simply be TARGET_CPUS
3726 */
3727#ifdef CONFIG_SMP
3728void __init setup_ioapic_dest(void)
3729{
3730 int pin, ioapic, irq, irq_entry;
3731 struct irq_cfg *cfg;
497c9a19
YL		 3732
3733 if (skip_ioapic_setup == 1)
3734 return;
3735
3736 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
3737 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
3738 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
3739 if (irq_entry == -1)
3740 continue;
3741 irq = pin_2_irq(irq_entry, ioapic, pin);
3742
3743 /* setup_IO_APIC_irqs could fail to get vector for some device
3744 * when you have too many devices, because at that time only boot
3745 * cpu is online.
3746 */
3747 cfg = irq_cfg(irq);
3748 if (!cfg->vector)
3749 setup_IO_APIC_irq(ioapic, pin, irq,
3750 irq_trigger(irq_entry),
3751 irq_polarity(irq_entry));
54168ed7
IM		 3752#ifdef CONFIG_INTR_REMAP
3753 else if (intr_remapping_enabled)
3754 set_ir_ioapic_affinity_irq(irq, TARGET_CPUS);
3755#endif
3756 else
497c9a19 3757 set_ioapic_affinity_irq(irq, TARGET_CPUS);
497c9a19
YL		 3758 }
3759
3760 }
3761}
3762#endif
3763
54168ed7
IM		 3764#define IOAPIC_RESOURCE_NAME_SIZE 11
3765
3766static struct resource *ioapic_resources;
3767
3768static struct resource * __init ioapic_setup_resources(void)
3769{
3770 unsigned long n;
3771 struct resource *res;
3772 char *mem;
3773 int i;
3774
3775 if (nr_ioapics <= 0)
3776 return NULL;
3777
3778 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
3779 n *= nr_ioapics;
3780
3781 mem = alloc_bootmem(n);
3782 res = (void *)mem;
3783
3784 if (mem != NULL) {
3785 mem += sizeof(struct resource) * nr_ioapics;
3786
3787 for (i = 0; i < nr_ioapics; i++) {
3788 res[i].name = mem;
3789 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
3790 sprintf(mem, "IOAPIC %u", i);
3791 mem += IOAPIC_RESOURCE_NAME_SIZE;
3792 }
3793 }
3794
3795 ioapic_resources = res;
3796
3797 return res;
3798}
54168ed7 3799
f3294a33
YL		 3800void __init ioapic_init_mappings(void)
3801{
3802 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
3803 int i;
54168ed7 3804 struct resource *ioapic_res;
f3294a33 3805
54168ed7 3806 ioapic_res = ioapic_setup_resources();
f3294a33
YL		 3807 for (i = 0; i < nr_ioapics; i++) {
3808 if (smp_found_config) {
3809 ioapic_phys = mp_ioapics[i].mp_apicaddr;
54168ed7
IM		 3810#ifdef CONFIG_X86_32
3811 if (!ioapic_phys) {
3812 printk(KERN_ERR
3813 "WARNING: bogus zero IO-APIC "
3814 "address found in MPTABLE, "
3815 "disabling IO/APIC support!\n");
3816 smp_found_config = 0;
3817 skip_ioapic_setup = 1;
3818 goto fake_ioapic_page;
3819 }
3820#endif
f3294a33 3821 } else {
54168ed7 3822#ifdef CONFIG_X86_32
f3294a33 3823fake_ioapic_page:
54168ed7 3824#endif
f3294a33 3825 ioapic_phys = (unsigned long)
54168ed7 3826 alloc_bootmem_pages(PAGE_SIZE);
f3294a33
YL		 3827 ioapic_phys = __pa(ioapic_phys);
3828 }
3829 set_fixmap_nocache(idx, ioapic_phys);
54168ed7
IM		 3830 apic_printk(APIC_VERBOSE,
3831 "mapped IOAPIC to %08lx (%08lx)\n",
3832 __fix_to_virt(idx), ioapic_phys);
f3294a33 3833 idx++;
54168ed7 3834
54168ed7
IM		 3835 if (ioapic_res != NULL) {
3836 ioapic_res->start = ioapic_phys;
3837 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
3838 ioapic_res++;
3839 }
f3294a33
YL		 3840 }
3841}
3842
54168ed7
IM		 3843static int __init ioapic_insert_resources(void)
3844{
3845 int i;
3846 struct resource *r = ioapic_resources;
3847
3848 if (!r) {
3849 printk(KERN_ERR
3850 "IO APIC resources could be not be allocated.\n");
3851 return -1;
3852 }
3853
3854 for (i = 0; i < nr_ioapics; i++) {
3855 insert_resource(&iomem_resource, r);
3856 r++;
3857 }
3858
3859 return 0;
3860}
3861
3862/* Insert the IO APIC resources after PCI initialization has occured to handle
3863 * IO APICS that are mapped in on a BAR in PCI space. */
3864late_initcall(ioapic_insert_resources);
Linux kernel - Deliverables
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