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x86: kill #ifdef for exit_idle()
[deliverable/linux.git] / arch / x86 / kernel / io_apic.c
CommitLineData
1da177e4
LT		 1/*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23#include <linux/mm.h>
1da177e4
LT		 24#include <linux/interrupt.h>
25#include <linux/init.h>
26#include <linux/delay.h>
27#include <linux/sched.h>
d4057bdb 28#include <linux/pci.h>
1da177e4
LT		 29#include <linux/mc146818rtc.h>
30#include <linux/compiler.h>
31#include <linux/acpi.h>
129f6946 32#include <linux/module.h>
1da177e4 33#include <linux/sysdev.h>
3b7d1921 34#include <linux/msi.h>
95d77884 35#include <linux/htirq.h>
7dfb7103 36#include <linux/freezer.h>
f26d6a2b 37#include <linux/kthread.h>
54168ed7 38#include <linux/jiffies.h> /* time_after() */
d4057bdb
YL		 39#ifdef CONFIG_ACPI
40#include <acpi/acpi_bus.h>
41#endif
42#include <linux/bootmem.h>
43#include <linux/dmar.h>
58ac1e76 44#include <linux/hpet.h>
54d5d424 45
d4057bdb 46#include <asm/idle.h>
1da177e4
LT		 47#include <asm/io.h>
48#include <asm/smp.h>
49#include <asm/desc.h>
d4057bdb
YL		 50#include <asm/proto.h>
51#include <asm/acpi.h>
52#include <asm/dma.h>
1da177e4 53#include <asm/timer.h>
306e440d 54#include <asm/i8259.h>
3e4ff115 55#include <asm/nmi.h>
2d3fcc1c 56#include <asm/msidef.h>
8b955b0d 57#include <asm/hypertransport.h>
a4dbc34d 58#include <asm/setup.h>
d4057bdb 59#include <asm/irq_remapping.h>
58ac1e76 60#include <asm/hpet.h>
4173a0e7
DN		 61#include <asm/uv/uv_hub.h>
62#include <asm/uv/uv_irq.h>
1da177e4 63
497c9a19 64#include <mach_ipi.h>
1da177e4 65#include <mach_apic.h>
874c4fe3 66#include <mach_apicdef.h>
1da177e4 67
32f71aff
MR		 68#define __apicdebuginit(type) static type __init
69
1da177e4 70/*
54168ed7
IM		 71 * Is the SiS APIC rmw bug present ?
72 * -1 = don't know, 0 = no, 1 = yes
1da177e4
LT		 73 */
74int sis_apic_bug = -1;
75
efa2559f
YL		 76static DEFINE_SPINLOCK(ioapic_lock);
77static DEFINE_SPINLOCK(vector_lock);
78
1da177e4
LT		 79/*
80 * # of IRQ routing registers
81 */
82int nr_ioapic_registers[MAX_IO_APICS];
83
9f640ccb 84/* I/O APIC entries */
ec2cd0a2 85struct mp_config_ioapic mp_ioapics[MAX_IO_APICS];
9f640ccb
AS		 86int nr_ioapics;
87
584f734d 88/* MP IRQ source entries */
2fddb6e2 89struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
584f734d
AS		 90
91/* # of MP IRQ source entries */
92int mp_irq_entries;
93
8732fc4b
AS		 94#if defined (CONFIG_MCA) || defined (CONFIG_EISA)
95int mp_bus_id_to_type[MAX_MP_BUSSES];
96#endif
97
98DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
99
efa2559f
YL		 100int skip_ioapic_setup;
101
54168ed7 102static int __init parse_noapic(char *str)
efa2559f
YL		 103{
104 /* disable IO-APIC */
105 disable_ioapic_setup();
106 return 0;
107}
108early_param("noapic", parse_noapic);
66759a01 109
0f978f45 110struct irq_pin_list;
a1420f39 111struct irq_cfg {
da51a821 112 unsigned int irq;
0f978f45 113 struct irq_pin_list *irq_2_pin;
497c9a19
YL		 114 cpumask_t domain;
115 cpumask_t old_domain;
116 unsigned move_cleanup_count;
a1420f39 117 u8 vector;
497c9a19 118 u8 move_in_progress : 1;
a1420f39
YL		 119};
120
a1420f39 121/* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
d6c88a50 122static struct irq_cfg irq_cfgx[NR_IRQS] = {
497c9a19
YL		 123 [0] = { .irq = 0, .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
124 [1] = { .irq = 1, .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
125 [2] = { .irq = 2, .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
126 [3] = { .irq = 3, .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
127 [4] = { .irq = 4, .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
128 [5] = { .irq = 5, .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
129 [6] = { .irq = 6, .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
130 [7] = { .irq = 7, .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
131 [8] = { .irq = 8, .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
132 [9] = { .irq = 9, .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
133 [10] = { .irq = 10, .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
134 [11] = { .irq = 11, .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
135 [12] = { .irq = 12, .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
136 [13] = { .irq = 13, .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
137 [14] = { .irq = 14, .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
138 [15] = { .irq = 15, .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
a1420f39
YL		 139};
140
8f09cd20 141#define for_each_irq_cfg(irq, cfg) \
d6c88a50 142 for (irq = 0, cfg = irq_cfgx; irq < nr_irqs; irq++, cfg++)
8f09cd20 143
d6c88a50 144static struct irq_cfg *irq_cfg(unsigned int irq)
8f09cd20 145{
d6c88a50 146 return irq < nr_irqs ? irq_cfgx + irq : NULL;
8f09cd20 147}
d6c88a50
TG		 148
149static struct irq_cfg *irq_cfg_alloc(unsigned int irq)
8f09cd20 150{
2cc21ef8 151 return irq_cfg(irq);
8f09cd20
YL		 152}
153
d6c88a50
TG		 154/*
155 * Rough estimation of how many shared IRQs there are, can be changed
156 * anytime.
157 */
158#define MAX_PLUS_SHARED_IRQS NR_IRQS
159#define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
160
1da177e4
LT		 161/*
162 * This is performance-critical, we want to do it O(1)
163 *
164 * the indexing order of this array favors 1:1 mappings
165 * between pins and IRQs.
166 */
167
0f978f45
YL		 168struct irq_pin_list {
169 int apic, pin;
170 struct irq_pin_list *next;
171};
172
d6c88a50 173static struct irq_pin_list irq_2_pin_head[PIN_MAP_SIZE];
0f978f45 174static struct irq_pin_list *irq_2_pin_ptr;
d6c88a50
TG		 175
176static void __init irq_2_pin_init(void)
0f978f45 177{
d6c88a50 178 struct irq_pin_list *pin = irq_2_pin_head;
0f978f45
YL		 179 int i;
180
d6c88a50 181 for (i = 1; i < PIN_MAP_SIZE; i++)
0f978f45
YL		 182 pin[i-1].next = &pin[i];
183
184 irq_2_pin_ptr = &pin[0];
185}
0f978f45
YL		 186
187static struct irq_pin_list *get_one_free_irq_2_pin(void)
188{
d6c88a50 189 struct irq_pin_list *pin = irq_2_pin_ptr;
0f978f45
YL		 190
191 if (!pin)
192 panic("can not get more irq_2_pin\n");
301e6190 193
0f978f45
YL		 194 irq_2_pin_ptr = pin->next;
195 pin->next = NULL;
0f978f45
YL		 196 return pin;
197}
1da177e4 198
130fe05d
LT		 199struct io_apic {
200 unsigned int index;
201 unsigned int unused[3];
202 unsigned int data;
203};
204
205static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
206{
207 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
ec2cd0a2 208 + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK);
130fe05d
LT		 209}
210
211static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
212{
213 struct io_apic __iomem *io_apic = io_apic_base(apic);
214 writel(reg, &io_apic->index);
215 return readl(&io_apic->data);
216}
217
218static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
219{
220 struct io_apic __iomem *io_apic = io_apic_base(apic);
221 writel(reg, &io_apic->index);
222 writel(value, &io_apic->data);
223}
224
225/*
226 * Re-write a value: to be used for read-modify-write
227 * cycles where the read already set up the index register.
228 *
229 * Older SiS APIC requires we rewrite the index register
230 */
231static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
232{
54168ed7 233 struct io_apic __iomem *io_apic = io_apic_base(apic);
d6c88a50
TG		 234
235 if (sis_apic_bug)
236 writel(reg, &io_apic->index);
130fe05d
LT		 237 writel(value, &io_apic->data);
238}
239
047c8fdb
YL		 240static bool io_apic_level_ack_pending(unsigned int irq)
241{
242 struct irq_pin_list *entry;
243 unsigned long flags;
244 struct irq_cfg *cfg = irq_cfg(irq);
245
246 spin_lock_irqsave(&ioapic_lock, flags);
247 entry = cfg->irq_2_pin;
248 for (;;) {
249 unsigned int reg;
250 int pin;
251
252 if (!entry)
253 break;
254 pin = entry->pin;
255 reg = io_apic_read(entry->apic, 0x10 + pin*2);
256 /* Is the remote IRR bit set? */
257 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
258 spin_unlock_irqrestore(&ioapic_lock, flags);
259 return true;
260 }
261 if (!entry->next)
262 break;
263 entry = entry->next;
264 }
265 spin_unlock_irqrestore(&ioapic_lock, flags);
266
267 return false;
268}
047c8fdb 269
cf4c6a2f
AK		 270union entry_union {
271 struct { u32 w1, w2; };
272 struct IO_APIC_route_entry entry;
273};
274
275static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
276{
277 union entry_union eu;
278 unsigned long flags;
279 spin_lock_irqsave(&ioapic_lock, flags);
280 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
281 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
282 spin_unlock_irqrestore(&ioapic_lock, flags);
283 return eu.entry;
284}
285
f9dadfa7
LT		 286/*
287 * When we write a new IO APIC routing entry, we need to write the high
288 * word first! If the mask bit in the low word is clear, we will enable
289 * the interrupt, and we need to make sure the entry is fully populated
290 * before that happens.
291 */
d15512f4
AK		 292static void
293__ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
cf4c6a2f 294{
cf4c6a2f
AK		 295 union entry_union eu;
296 eu.entry = e;
f9dadfa7
LT		 297 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
298 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
d15512f4
AK		 299}
300
301static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
302{
303 unsigned long flags;
304 spin_lock_irqsave(&ioapic_lock, flags);
305 __ioapic_write_entry(apic, pin, e);
f9dadfa7
LT		 306 spin_unlock_irqrestore(&ioapic_lock, flags);
307}
308
309/*
310 * When we mask an IO APIC routing entry, we need to write the low
311 * word first, in order to set the mask bit before we change the
312 * high bits!
313 */
314static void ioapic_mask_entry(int apic, int pin)
315{
316 unsigned long flags;
317 union entry_union eu = { .entry.mask = 1 };
318
cf4c6a2f
AK		 319 spin_lock_irqsave(&ioapic_lock, flags);
320 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
321 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
322 spin_unlock_irqrestore(&ioapic_lock, flags);
323}
324
497c9a19
YL		 325#ifdef CONFIG_SMP
326static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
327{
328 int apic, pin;
329 struct irq_cfg *cfg;
330 struct irq_pin_list *entry;
331
332 cfg = irq_cfg(irq);
333 entry = cfg->irq_2_pin;
334 for (;;) {
335 unsigned int reg;
336
337 if (!entry)
338 break;
339
340 apic = entry->apic;
341 pin = entry->pin;
54168ed7
IM		 342#ifdef CONFIG_INTR_REMAP
343 /*
344 * With interrupt-remapping, destination information comes
345 * from interrupt-remapping table entry.
346 */
347 if (!irq_remapped(irq))
348 io_apic_write(apic, 0x11 + pin*2, dest);
349#else
497c9a19 350 io_apic_write(apic, 0x11 + pin*2, dest);
54168ed7 351#endif
497c9a19
YL		 352 reg = io_apic_read(apic, 0x10 + pin*2);
353 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
354 reg |= vector;
54168ed7 355 io_apic_modify(apic, 0x10 + pin*2, reg);
497c9a19
YL		 356 if (!entry->next)
357 break;
358 entry = entry->next;
359 }
360}
efa2559f
YL		 361
362static int assign_irq_vector(int irq, cpumask_t mask);
363
497c9a19
YL		 364static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
365{
366 struct irq_cfg *cfg;
367 unsigned long flags;
368 unsigned int dest;
369 cpumask_t tmp;
54168ed7 370 struct irq_desc *desc;
497c9a19 371
497c9a19
YL		 372 cpus_and(tmp, mask, cpu_online_map);
373 if (cpus_empty(tmp))
374 return;
375
047c8fdb 376 cfg = irq_cfg(irq);
497c9a19
YL		 377 if (assign_irq_vector(irq, mask))
378 return;
379
380 cpus_and(tmp, cfg->domain, mask);
497c9a19
YL		 381 dest = cpu_mask_to_apicid(tmp);
382 /*
383 * Only the high 8 bits are valid.
384 */
385 dest = SET_APIC_LOGICAL_ID(dest);
386
54168ed7 387 desc = irq_to_desc(irq);
497c9a19
YL		 388 spin_lock_irqsave(&ioapic_lock, flags);
389 __target_IO_APIC_irq(irq, dest, cfg->vector);
54168ed7 390 desc->affinity = mask;
497c9a19
YL		 391 spin_unlock_irqrestore(&ioapic_lock, flags);
392}
497c9a19
YL		 393#endif /* CONFIG_SMP */
394
1da177e4
LT		 395/*
396 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
397 * shared ISA-space IRQs, so we have to support them. We are super
398 * fast in the common case, and fast for shared ISA-space IRQs.
399 */
400static void add_pin_to_irq(unsigned int irq, int apic, int pin)
401{
0f978f45
YL		 402 struct irq_cfg *cfg;
403 struct irq_pin_list *entry;
404
405 /* first time to refer irq_cfg, so with new */
406 cfg = irq_cfg_alloc(irq);
407 entry = cfg->irq_2_pin;
408 if (!entry) {
409 entry = get_one_free_irq_2_pin();
410 cfg->irq_2_pin = entry;
411 entry->apic = apic;
412 entry->pin = pin;
0f978f45
YL		 413 return;
414 }
1da177e4 415
0f978f45
YL		 416 while (entry->next) {
417 /* not again, please */
418 if (entry->apic == apic && entry->pin == pin)
419 return;
1da177e4 420
0f978f45 421 entry = entry->next;
1da177e4 422 }
0f978f45
YL		 423
424 entry->next = get_one_free_irq_2_pin();
425 entry = entry->next;
1da177e4
LT		 426 entry->apic = apic;
427 entry->pin = pin;
428}
429
430/*
431 * Reroute an IRQ to a different pin.
432 */
433static void __init replace_pin_at_irq(unsigned int irq,
434 int oldapic, int oldpin,
435 int newapic, int newpin)
436{
0f978f45
YL		 437 struct irq_cfg *cfg = irq_cfg(irq);
438 struct irq_pin_list *entry = cfg->irq_2_pin;
439 int replaced = 0;
1da177e4 440
0f978f45 441 while (entry) {
1da177e4
LT		 442 if (entry->apic == oldapic && entry->pin == oldpin) {
443 entry->apic = newapic;
444 entry->pin = newpin;
0f978f45
YL		 445 replaced = 1;
446 /* every one is different, right? */
1da177e4 447 break;
0f978f45
YL		 448 }
449 entry = entry->next;
1da177e4 450 }
0f978f45
YL		 451
452 /* why? call replace before add? */
453 if (!replaced)
454 add_pin_to_irq(irq, newapic, newpin);
1da177e4
LT		 455}
456
87783be4
CG		 457static inline void io_apic_modify_irq(unsigned int irq,
458 int mask_and, int mask_or,
459 void (*final)(struct irq_pin_list *entry))
460{
461 int pin;
462 struct irq_cfg *cfg;
463 struct irq_pin_list *entry;
047c8fdb 464
87783be4
CG		 465 cfg = irq_cfg(irq);
466 for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) {
467 unsigned int reg;
468 pin = entry->pin;
469 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
470 reg &= mask_and;
471 reg |= mask_or;
472 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
473 if (final)
474 final(entry);
475 }
476}
047c8fdb 477
87783be4
CG		 478static void __unmask_IO_APIC_irq(unsigned int irq)
479{
480 io_apic_modify_irq(irq, ~IO_APIC_REDIR_MASKED, 0, NULL);
481}
047c8fdb 482
4e738e2f 483#ifdef CONFIG_X86_64
87783be4 484void io_apic_sync(struct irq_pin_list *entry)
1da177e4 485{
87783be4
CG		 486 /*
487 * Synchronize the IO-APIC and the CPU by doing
488 * a dummy read from the IO-APIC
489 */
490 struct io_apic __iomem *io_apic;
491 io_apic = io_apic_base(entry->apic);
4e738e2f 492 readl(&io_apic->data);
1da177e4
LT		 493}
494
87783be4
CG		 495static void __mask_IO_APIC_irq(unsigned int irq)
496{
497 io_apic_modify_irq(irq, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
498}
499#else /* CONFIG_X86_32 */
500static void __mask_IO_APIC_irq(unsigned int irq)
501{
502 io_apic_modify_irq(irq, ~0, IO_APIC_REDIR_MASKED, NULL);
503}
1da177e4 504
87783be4
CG		 505static void __mask_and_edge_IO_APIC_irq(unsigned int irq)
506{
507 io_apic_modify_irq(irq, ~IO_APIC_REDIR_LEVEL_TRIGGER,
508 IO_APIC_REDIR_MASKED, NULL);
509}
1da177e4 510
87783be4
CG		 511static void __unmask_and_level_IO_APIC_irq(unsigned int irq)
512{
513 io_apic_modify_irq(irq, ~IO_APIC_REDIR_MASKED,
514 IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
515}
516#endif /* CONFIG_X86_32 */
047c8fdb 517
54168ed7 518static void mask_IO_APIC_irq (unsigned int irq)
1da177e4
LT		 519{
520 unsigned long flags;
521
522 spin_lock_irqsave(&ioapic_lock, flags);
523 __mask_IO_APIC_irq(irq);
524 spin_unlock_irqrestore(&ioapic_lock, flags);
525}
526
54168ed7 527static void unmask_IO_APIC_irq (unsigned int irq)
1da177e4
LT		 528{
529 unsigned long flags;
530
531 spin_lock_irqsave(&ioapic_lock, flags);
532 __unmask_IO_APIC_irq(irq);
533 spin_unlock_irqrestore(&ioapic_lock, flags);
534}
535
536static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
537{
538 struct IO_APIC_route_entry entry;
36062448 539
1da177e4 540 /* Check delivery_mode to be sure we're not clearing an SMI pin */
cf4c6a2f 541 entry = ioapic_read_entry(apic, pin);
1da177e4
LT		 542 if (entry.delivery_mode == dest_SMI)
543 return;
1da177e4
LT		 544 /*
545 * Disable it in the IO-APIC irq-routing table:
546 */
f9dadfa7 547 ioapic_mask_entry(apic, pin);
1da177e4
LT		 548}
549
54168ed7 550static void clear_IO_APIC (void)
1da177e4
LT		 551{
552 int apic, pin;
553
554 for (apic = 0; apic < nr_ioapics; apic++)
555 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
556 clear_IO_APIC_pin(apic, pin);
557}
558
54168ed7 559#if !defined(CONFIG_SMP) && defined(CONFIG_X86_32)
75604d7f 560void send_IPI_self(int vector)
1da177e4
LT		 561{
562 unsigned int cfg;
563
564 /*
565 * Wait for idle.
566 */
567 apic_wait_icr_idle();
568 cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
569 /*
570 * Send the IPI. The write to APIC_ICR fires this off.
571 */
593f4a78 572 apic_write(APIC_ICR, cfg);
1da177e4 573}
54168ed7 574#endif /* !CONFIG_SMP && CONFIG_X86_32*/
1da177e4 575
54168ed7 576#ifdef CONFIG_X86_32
1da177e4
LT		 577/*
578 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
579 * specific CPU-side IRQs.
580 */
581
582#define MAX_PIRQS 8
583static int pirq_entries [MAX_PIRQS];
584static int pirqs_enabled;
1da177e4 585
1da177e4
LT		 586static int __init ioapic_pirq_setup(char *str)
587{
588 int i, max;
589 int ints[MAX_PIRQS+1];
590
591 get_options(str, ARRAY_SIZE(ints), ints);
592
593 for (i = 0; i < MAX_PIRQS; i++)
594 pirq_entries[i] = -1;
595
596 pirqs_enabled = 1;
597 apic_printk(APIC_VERBOSE, KERN_INFO
598 "PIRQ redirection, working around broken MP-BIOS.\n");
599 max = MAX_PIRQS;
600 if (ints[0] < MAX_PIRQS)
601 max = ints[0];
602
603 for (i = 0; i < max; i++) {
604 apic_printk(APIC_VERBOSE, KERN_DEBUG
605 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
606 /*
607 * PIRQs are mapped upside down, usually.
608 */
609 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
610 }
611 return 1;
612}
613
614__setup("pirq=", ioapic_pirq_setup);
54168ed7
IM		 615#endif /* CONFIG_X86_32 */
616
617#ifdef CONFIG_INTR_REMAP
618/* I/O APIC RTE contents at the OS boot up */
619static struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS];
620
621/*
622 * Saves and masks all the unmasked IO-APIC RTE's
623 */
624int save_mask_IO_APIC_setup(void)
625{
626 union IO_APIC_reg_01 reg_01;
627 unsigned long flags;
628 int apic, pin;
629
630 /*
631 * The number of IO-APIC IRQ registers (== #pins):
632 */
633 for (apic = 0; apic < nr_ioapics; apic++) {
634 spin_lock_irqsave(&ioapic_lock, flags);
635 reg_01.raw = io_apic_read(apic, 1);
636 spin_unlock_irqrestore(&ioapic_lock, flags);
637 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
638 }
639
640 for (apic = 0; apic < nr_ioapics; apic++) {
641 early_ioapic_entries[apic] =
642 kzalloc(sizeof(struct IO_APIC_route_entry) *
643 nr_ioapic_registers[apic], GFP_KERNEL);
644 if (!early_ioapic_entries[apic])
5ffa4eb2 645 goto nomem;
54168ed7
IM		 646 }
647
648 for (apic = 0; apic < nr_ioapics; apic++)
649 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
650 struct IO_APIC_route_entry entry;
651
652 entry = early_ioapic_entries[apic][pin] =
653 ioapic_read_entry(apic, pin);
654 if (!entry.mask) {
655 entry.mask = 1;
656 ioapic_write_entry(apic, pin, entry);
657 }
658 }
5ffa4eb2 659
54168ed7 660 return 0;
5ffa4eb2
CG		 661
662nomem:
c1370b49
CG		 663 while (apic >= 0)
664 kfree(early_ioapic_entries[apic--]);
5ffa4eb2
CG		 665 memset(early_ioapic_entries, 0,
666 ARRAY_SIZE(early_ioapic_entries));
667
668 return -ENOMEM;
54168ed7
IM		 669}
670
671void restore_IO_APIC_setup(void)
672{
673 int apic, pin;
674
5ffa4eb2
CG		 675 for (apic = 0; apic < nr_ioapics; apic++) {
676 if (!early_ioapic_entries[apic])
677 break;
54168ed7
IM		 678 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
679 ioapic_write_entry(apic, pin,
680 early_ioapic_entries[apic][pin]);
5ffa4eb2
CG		 681 kfree(early_ioapic_entries[apic]);
682 early_ioapic_entries[apic] = NULL;
683 }
54168ed7
IM		 684}
685
686void reinit_intr_remapped_IO_APIC(int intr_remapping)
687{
688 /*
689 * for now plain restore of previous settings.
690 * TBD: In the case of OS enabling interrupt-remapping,
691 * IO-APIC RTE's need to be setup to point to interrupt-remapping
692 * table entries. for now, do a plain restore, and wait for
693 * the setup_IO_APIC_irqs() to do proper initialization.
694 */
695 restore_IO_APIC_setup();
696}
697#endif
1da177e4
LT		 698
699/*
700 * Find the IRQ entry number of a certain pin.
701 */
702static int find_irq_entry(int apic, int pin, int type)
703{
704 int i;
705
706 for (i = 0; i < mp_irq_entries; i++)
2fddb6e2
AS		 707 if (mp_irqs[i].mp_irqtype == type &&
708 (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid ||
709 mp_irqs[i].mp_dstapic == MP_APIC_ALL) &&
710 mp_irqs[i].mp_dstirq == pin)
1da177e4
LT		 711 return i;
712
713 return -1;
714}
715
716/*
717 * Find the pin to which IRQ[irq] (ISA) is connected
718 */
fcfd636a 719static int __init find_isa_irq_pin(int irq, int type)
1da177e4
LT		 720{
721 int i;
722
723 for (i = 0; i < mp_irq_entries; i++) {
2fddb6e2 724 int lbus = mp_irqs[i].mp_srcbus;
1da177e4 725
d27e2b8e 726 if (test_bit(lbus, mp_bus_not_pci) &&
2fddb6e2
AS		 727 (mp_irqs[i].mp_irqtype == type) &&
728 (mp_irqs[i].mp_srcbusirq == irq))
1da177e4 729
2fddb6e2 730 return mp_irqs[i].mp_dstirq;
1da177e4
LT		 731 }
732 return -1;
733}
734
fcfd636a
EB		 735static int __init find_isa_irq_apic(int irq, int type)
736{
737 int i;
738
739 for (i = 0; i < mp_irq_entries; i++) {
2fddb6e2 740 int lbus = mp_irqs[i].mp_srcbus;
fcfd636a 741
73b2961b 742 if (test_bit(lbus, mp_bus_not_pci) &&
2fddb6e2
AS		 743 (mp_irqs[i].mp_irqtype == type) &&
744 (mp_irqs[i].mp_srcbusirq == irq))
fcfd636a
EB		 745 break;
746 }
747 if (i < mp_irq_entries) {
748 int apic;
54168ed7 749 for(apic = 0; apic < nr_ioapics; apic++) {
2fddb6e2 750 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic)
fcfd636a
EB		 751 return apic;
752 }
753 }
754
755 return -1;
756}
757
1da177e4
LT		 758/*
759 * Find a specific PCI IRQ entry.
760 * Not an __init, possibly needed by modules
761 */
762static int pin_2_irq(int idx, int apic, int pin);
763
764int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
765{
766 int apic, i, best_guess = -1;
767
54168ed7
IM		 768 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
769 bus, slot, pin);
ce6444d3 770 if (test_bit(bus, mp_bus_not_pci)) {
54168ed7 771 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1da177e4
LT		 772 return -1;
773 }
774 for (i = 0; i < mp_irq_entries; i++) {
2fddb6e2 775 int lbus = mp_irqs[i].mp_srcbus;
1da177e4
LT		 776
777 for (apic = 0; apic < nr_ioapics; apic++)
2fddb6e2
AS		 778 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic ||
779 mp_irqs[i].mp_dstapic == MP_APIC_ALL)
1da177e4
LT		 780 break;
781
47cab822 782 if (!test_bit(lbus, mp_bus_not_pci) &&
2fddb6e2 783 !mp_irqs[i].mp_irqtype &&
1da177e4 784 (bus == lbus) &&
2fddb6e2 785 (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) {
54168ed7 786 int irq = pin_2_irq(i,apic,mp_irqs[i].mp_dstirq);
1da177e4
LT		 787
788 if (!(apic || IO_APIC_IRQ(irq)))
789 continue;
790
2fddb6e2 791 if (pin == (mp_irqs[i].mp_srcbusirq & 3))
1da177e4
LT		 792 return irq;
793 /*
794 * Use the first all-but-pin matching entry as a
795 * best-guess fuzzy result for broken mptables.
796 */
797 if (best_guess < 0)
798 best_guess = irq;
799 }
800 }
801 return best_guess;
802}
54168ed7 803
129f6946 804EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1da177e4 805
c0a282c2 806#if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1da177e4
LT		 807/*
808 * EISA Edge/Level control register, ELCR
809 */
810static int EISA_ELCR(unsigned int irq)
811{
812 if (irq < 16) {
813 unsigned int port = 0x4d0 + (irq >> 3);
814 return (inb(port) >> (irq & 7)) & 1;
815 }
816 apic_printk(APIC_VERBOSE, KERN_INFO
817 "Broken MPtable reports ISA irq %d\n", irq);
818 return 0;
819}
54168ed7 820
c0a282c2 821#endif
1da177e4 822
6728801d
AS		 823/* ISA interrupts are always polarity zero edge triggered,
824 * when listed as conforming in the MP table. */
825
826#define default_ISA_trigger(idx) (0)
827#define default_ISA_polarity(idx) (0)
828
1da177e4
LT		 829/* EISA interrupts are always polarity zero and can be edge or level
830 * trigger depending on the ELCR value. If an interrupt is listed as
831 * EISA conforming in the MP table, that means its trigger type must
832 * be read in from the ELCR */
833
2fddb6e2 834#define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq))
6728801d 835#define default_EISA_polarity(idx) default_ISA_polarity(idx)
1da177e4
LT		 836
837/* PCI interrupts are always polarity one level triggered,
838 * when listed as conforming in the MP table. */
839
840#define default_PCI_trigger(idx) (1)
841#define default_PCI_polarity(idx) (1)
842
843/* MCA interrupts are always polarity zero level triggered,
844 * when listed as conforming in the MP table. */
845
846#define default_MCA_trigger(idx) (1)
6728801d 847#define default_MCA_polarity(idx) default_ISA_polarity(idx)
1da177e4 848
61fd47e0 849static int MPBIOS_polarity(int idx)
1da177e4 850{
2fddb6e2 851 int bus = mp_irqs[idx].mp_srcbus;
1da177e4
LT		 852 int polarity;
853
854 /*
855 * Determine IRQ line polarity (high active or low active):
856 */
54168ed7 857 switch (mp_irqs[idx].mp_irqflag & 3)
36062448 858 {
54168ed7
IM		 859 case 0: /* conforms, ie. bus-type dependent polarity */
860 if (test_bit(bus, mp_bus_not_pci))
861 polarity = default_ISA_polarity(idx);
862 else
863 polarity = default_PCI_polarity(idx);
864 break;
865 case 1: /* high active */
866 {
867 polarity = 0;
868 break;
869 }
870 case 2: /* reserved */
871 {
872 printk(KERN_WARNING "broken BIOS!!\n");
873 polarity = 1;
874 break;
875 }
876 case 3: /* low active */
877 {
878 polarity = 1;
879 break;
880 }
881 default: /* invalid */
882 {
883 printk(KERN_WARNING "broken BIOS!!\n");
884 polarity = 1;
885 break;
886 }
1da177e4
LT		 887 }
888 return polarity;
889}
890
891static int MPBIOS_trigger(int idx)
892{
2fddb6e2 893 int bus = mp_irqs[idx].mp_srcbus;
1da177e4
LT		 894 int trigger;
895
896 /*
897 * Determine IRQ trigger mode (edge or level sensitive):
898 */
54168ed7 899 switch ((mp_irqs[idx].mp_irqflag>>2) & 3)
1da177e4 900 {
54168ed7
IM		 901 case 0: /* conforms, ie. bus-type dependent */
902 if (test_bit(bus, mp_bus_not_pci))
903 trigger = default_ISA_trigger(idx);
904 else
905 trigger = default_PCI_trigger(idx);
c0a282c2 906#if defined(CONFIG_EISA) || defined(CONFIG_MCA)
54168ed7
IM		 907 switch (mp_bus_id_to_type[bus]) {
908 case MP_BUS_ISA: /* ISA pin */
909 {
910 /* set before the switch */
911 break;
912 }
913 case MP_BUS_EISA: /* EISA pin */
914 {
915 trigger = default_EISA_trigger(idx);
916 break;
917 }
918 case MP_BUS_PCI: /* PCI pin */
919 {
920 /* set before the switch */
921 break;
922 }
923 case MP_BUS_MCA: /* MCA pin */
924 {
925 trigger = default_MCA_trigger(idx);
926 break;
927 }
928 default:
929 {
930 printk(KERN_WARNING "broken BIOS!!\n");
931 trigger = 1;
932 break;
933 }
934 }
935#endif
1da177e4 936 break;
54168ed7 937 case 1: /* edge */
1da177e4 938 {
54168ed7 939 trigger = 0;
1da177e4
LT		 940 break;
941 }
54168ed7 942 case 2: /* reserved */
1da177e4 943 {
54168ed7
IM		 944 printk(KERN_WARNING "broken BIOS!!\n");
945 trigger = 1;
1da177e4
LT		 946 break;
947 }
54168ed7 948 case 3: /* level */
1da177e4 949 {
54168ed7 950 trigger = 1;
1da177e4
LT		 951 break;
952 }
54168ed7 953 default: /* invalid */
1da177e4
LT		 954 {
955 printk(KERN_WARNING "broken BIOS!!\n");
54168ed7 956 trigger = 0;
1da177e4
LT		 957 break;
958 }
959 }
960 return trigger;
961}
962
963static inline int irq_polarity(int idx)
964{
965 return MPBIOS_polarity(idx);
966}
967
968static inline int irq_trigger(int idx)
969{
970 return MPBIOS_trigger(idx);
971}
972
efa2559f 973int (*ioapic_renumber_irq)(int ioapic, int irq);
1da177e4
LT		 974static int pin_2_irq(int idx, int apic, int pin)
975{
976 int irq, i;
2fddb6e2 977 int bus = mp_irqs[idx].mp_srcbus;
1da177e4
LT		 978
979 /*
980 * Debugging check, we are in big trouble if this message pops up!
981 */
2fddb6e2 982 if (mp_irqs[idx].mp_dstirq != pin)
1da177e4
LT		 983 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
984
54168ed7 985 if (test_bit(bus, mp_bus_not_pci)) {
2fddb6e2 986 irq = mp_irqs[idx].mp_srcbusirq;
54168ed7 987 } else {
643befed
AS		 988 /*
989 * PCI IRQs are mapped in order
990 */
991 i = irq = 0;
992 while (i < apic)
993 irq += nr_ioapic_registers[i++];
994 irq += pin;
d6c88a50 995 /*
54168ed7
IM		 996 * For MPS mode, so far only needed by ES7000 platform
997 */
d6c88a50
TG		 998 if (ioapic_renumber_irq)
999 irq = ioapic_renumber_irq(apic, irq);
1da177e4
LT		 1000 }
1001
54168ed7 1002#ifdef CONFIG_X86_32
1da177e4
LT		 1003 /*
1004 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1005 */
1006 if ((pin >= 16) && (pin <= 23)) {
1007 if (pirq_entries[pin-16] != -1) {
1008 if (!pirq_entries[pin-16]) {
1009 apic_printk(APIC_VERBOSE, KERN_DEBUG
1010 "disabling PIRQ%d\n", pin-16);
1011 } else {
1012 irq = pirq_entries[pin-16];
1013 apic_printk(APIC_VERBOSE, KERN_DEBUG
1014 "using PIRQ%d -> IRQ %d\n",
1015 pin-16, irq);
1016 }
1017 }
1018 }
54168ed7
IM		 1019#endif
1020
1da177e4
LT		 1021 return irq;
1022}
1023
497c9a19
YL		 1024void lock_vector_lock(void)
1025{
1026 /* Used to the online set of cpus does not change
1027 * during assign_irq_vector.
1028 */
1029 spin_lock(&vector_lock);
1030}
1da177e4 1031
497c9a19 1032void unlock_vector_lock(void)
1da177e4 1033{
497c9a19
YL		 1034 spin_unlock(&vector_lock);
1035}
1da177e4 1036
497c9a19
YL		 1037static int __assign_irq_vector(int irq, cpumask_t mask)
1038{
047c8fdb
YL		 1039 /*
1040 * NOTE! The local APIC isn't very good at handling
1041 * multiple interrupts at the same interrupt level.
1042 * As the interrupt level is determined by taking the
1043 * vector number and shifting that right by 4, we
1044 * want to spread these out a bit so that they don't
1045 * all fall in the same interrupt level.
1046 *
1047 * Also, we've got to be careful not to trash gate
1048 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1049 */
54168ed7
IM		 1050 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1051 unsigned int old_vector;
1052 int cpu;
1053 struct irq_cfg *cfg;
ace80ab7 1054
54168ed7 1055 cfg = irq_cfg(irq);
8339f000 1056
54168ed7
IM		 1057 /* Only try and allocate irqs on cpus that are present */
1058 cpus_and(mask, mask, cpu_online_map);
ace80ab7 1059
54168ed7
IM		 1060 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1061 return -EBUSY;
0a1ad60d 1062
54168ed7
IM		 1063 old_vector = cfg->vector;
1064 if (old_vector) {
1065 cpumask_t tmp;
1066 cpus_and(tmp, cfg->domain, mask);
1067 if (!cpus_empty(tmp))
1068 return 0;
1069 }
497c9a19 1070
54168ed7
IM		 1071 for_each_cpu_mask_nr(cpu, mask) {
1072 cpumask_t domain, new_mask;
1073 int new_cpu;
1074 int vector, offset;
497c9a19 1075
54168ed7
IM		 1076 domain = vector_allocation_domain(cpu);
1077 cpus_and(new_mask, domain, cpu_online_map);
497c9a19 1078
54168ed7
IM		 1079 vector = current_vector;
1080 offset = current_offset;
497c9a19 1081next:
54168ed7
IM		 1082 vector += 8;
1083 if (vector >= first_system_vector) {
1084 /* If we run out of vectors on large boxen, must share them. */
1085 offset = (offset + 1) % 8;
1086 vector = FIRST_DEVICE_VECTOR + offset;
1087 }
1088 if (unlikely(current_vector == vector))
1089 continue;
047c8fdb 1090#ifdef CONFIG_X86_64
54168ed7
IM		 1091 if (vector == IA32_SYSCALL_VECTOR)
1092 goto next;
047c8fdb 1093#else
54168ed7
IM		 1094 if (vector == SYSCALL_VECTOR)
1095 goto next;
047c8fdb 1096#endif
54168ed7
IM		 1097 for_each_cpu_mask_nr(new_cpu, new_mask)
1098 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1099 goto next;
1100 /* Found one! */
1101 current_vector = vector;
1102 current_offset = offset;
1103 if (old_vector) {
1104 cfg->move_in_progress = 1;
1105 cfg->old_domain = cfg->domain;
7a959cff 1106 }
54168ed7
IM		 1107 for_each_cpu_mask_nr(new_cpu, new_mask)
1108 per_cpu(vector_irq, new_cpu)[vector] = irq;
1109 cfg->vector = vector;
1110 cfg->domain = domain;
1111 return 0;
1112 }
1113 return -ENOSPC;
497c9a19
YL		 1114}
1115
1116static int assign_irq_vector(int irq, cpumask_t mask)
1117{
1118 int err;
ace80ab7 1119 unsigned long flags;
ace80ab7
EB		 1120
1121 spin_lock_irqsave(&vector_lock, flags);
497c9a19 1122 err = __assign_irq_vector(irq, mask);
26a3c49c 1123 spin_unlock_irqrestore(&vector_lock, flags);
497c9a19
YL		 1124 return err;
1125}
1126
1127static void __clear_irq_vector(int irq)
1128{
1129 struct irq_cfg *cfg;
1130 cpumask_t mask;
1131 int cpu, vector;
1132
1133 cfg = irq_cfg(irq);
1134 BUG_ON(!cfg->vector);
1135
1136 vector = cfg->vector;
1137 cpus_and(mask, cfg->domain, cpu_online_map);
1138 for_each_cpu_mask_nr(cpu, mask)
1139 per_cpu(vector_irq, cpu)[vector] = -1;
1140
1141 cfg->vector = 0;
1142 cpus_clear(cfg->domain);
0ca4b6b0
MW		 1143
1144 if (likely(!cfg->move_in_progress))
1145 return;
1146 cpus_and(mask, cfg->old_domain, cpu_online_map);
1147 for_each_cpu_mask_nr(cpu, mask) {
1148 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1149 vector++) {
1150 if (per_cpu(vector_irq, cpu)[vector] != irq)
1151 continue;
1152 per_cpu(vector_irq, cpu)[vector] = -1;
1153 break;
1154 }
1155 }
1156 cfg->move_in_progress = 0;
497c9a19
YL		 1157}
1158
1159void __setup_vector_irq(int cpu)
1160{
1161 /* Initialize vector_irq on a new cpu */
1162 /* This function must be called with vector_lock held */
1163 int irq, vector;
1164 struct irq_cfg *cfg;
1165
1166 /* Mark the inuse vectors */
8f09cd20 1167 for_each_irq_cfg(irq, cfg) {
497c9a19
YL		 1168 if (!cpu_isset(cpu, cfg->domain))
1169 continue;
1170 vector = cfg->vector;
497c9a19
YL		 1171 per_cpu(vector_irq, cpu)[vector] = irq;
1172 }
1173 /* Mark the free vectors */
1174 for (vector = 0; vector < NR_VECTORS; ++vector) {
1175 irq = per_cpu(vector_irq, cpu)[vector];
1176 if (irq < 0)
1177 continue;
1178
1179 cfg = irq_cfg(irq);
1180 if (!cpu_isset(cpu, cfg->domain))
1181 per_cpu(vector_irq, cpu)[vector] = -1;
54168ed7 1182 }
1da177e4 1183}
3fde6900 1184
f5b9ed7a 1185static struct irq_chip ioapic_chip;
54168ed7
IM		 1186#ifdef CONFIG_INTR_REMAP
1187static struct irq_chip ir_ioapic_chip;
1188#endif
1da177e4 1189
54168ed7
IM		 1190#define IOAPIC_AUTO -1
1191#define IOAPIC_EDGE 0
1192#define IOAPIC_LEVEL 1
1da177e4 1193
047c8fdb 1194#ifdef CONFIG_X86_32
1d025192
YL		 1195static inline int IO_APIC_irq_trigger(int irq)
1196{
d6c88a50 1197 int apic, idx, pin;
1d025192 1198
d6c88a50
TG		 1199 for (apic = 0; apic < nr_ioapics; apic++) {
1200 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1201 idx = find_irq_entry(apic, pin, mp_INT);
1202 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1203 return irq_trigger(idx);
1204 }
1205 }
1206 /*
54168ed7
IM		 1207 * nonexistent IRQs are edge default
1208 */
d6c88a50 1209 return 0;
1d025192 1210}
047c8fdb
YL		 1211#else
1212static inline int IO_APIC_irq_trigger(int irq)
1213{
54168ed7 1214 return 1;
047c8fdb
YL		 1215}
1216#endif
1d025192 1217
497c9a19 1218static void ioapic_register_intr(int irq, unsigned long trigger)
1da177e4 1219{
08678b08
YL		 1220 struct irq_desc *desc;
1221
ee32c973 1222 desc = irq_to_desc(irq);
199751d7 1223
6ebcc00e 1224 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
047c8fdb 1225 trigger == IOAPIC_LEVEL)
08678b08 1226 desc->status |= IRQ_LEVEL;
047c8fdb
YL		 1227 else
1228 desc->status &= ~IRQ_LEVEL;
1229
54168ed7
IM		 1230#ifdef CONFIG_INTR_REMAP
1231 if (irq_remapped(irq)) {
1232 desc->status |= IRQ_MOVE_PCNTXT;
1233 if (trigger)
1234 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1235 handle_fasteoi_irq,
1236 "fasteoi");
1237 else
1238 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1239 handle_edge_irq, "edge");
1240 return;
1241 }
1242#endif
047c8fdb
YL		 1243 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1244 trigger == IOAPIC_LEVEL)
a460e745 1245 set_irq_chip_and_handler_name(irq, &ioapic_chip,
54168ed7
IM		 1246 handle_fasteoi_irq,
1247 "fasteoi");
047c8fdb 1248 else
a460e745 1249 set_irq_chip_and_handler_name(irq, &ioapic_chip,
54168ed7 1250 handle_edge_irq, "edge");
1da177e4
LT		 1251}
1252
497c9a19
YL		 1253static int setup_ioapic_entry(int apic, int irq,
1254 struct IO_APIC_route_entry *entry,
1255 unsigned int destination, int trigger,
1256 int polarity, int vector)
1da177e4 1257{
497c9a19
YL		 1258 /*
1259 * add it to the IO-APIC irq-routing table:
1260 */
1261 memset(entry,0,sizeof(*entry));
1262
54168ed7
IM		 1263#ifdef CONFIG_INTR_REMAP
1264 if (intr_remapping_enabled) {
1265 struct intel_iommu *iommu = map_ioapic_to_ir(apic);
1266 struct irte irte;
1267 struct IR_IO_APIC_route_entry *ir_entry =
1268 (struct IR_IO_APIC_route_entry *) entry;
1269 int index;
1270
1271 if (!iommu)
1272 panic("No mapping iommu for ioapic %d\n", apic);
1273
1274 index = alloc_irte(iommu, irq, 1);
1275 if (index < 0)
1276 panic("Failed to allocate IRTE for ioapic %d\n", apic);
1277
1278 memset(&irte, 0, sizeof(irte));
1279
1280 irte.present = 1;
1281 irte.dst_mode = INT_DEST_MODE;
1282 irte.trigger_mode = trigger;
1283 irte.dlvry_mode = INT_DELIVERY_MODE;
1284 irte.vector = vector;
1285 irte.dest_id = IRTE_DEST(destination);
1286
1287 modify_irte(irq, &irte);
1288
1289 ir_entry->index2 = (index >> 15) & 0x1;
1290 ir_entry->zero = 0;
1291 ir_entry->format = 1;
1292 ir_entry->index = (index & 0x7fff);
1293 } else
1294#endif
1295 {
1296 entry->delivery_mode = INT_DELIVERY_MODE;
1297 entry->dest_mode = INT_DEST_MODE;
1298 entry->dest = destination;
1299 }
497c9a19 1300
54168ed7 1301 entry->mask = 0; /* enable IRQ */
497c9a19
YL		 1302 entry->trigger = trigger;
1303 entry->polarity = polarity;
1304 entry->vector = vector;
1305
1306 /* Mask level triggered irqs.
1307 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1308 */
1309 if (trigger)
1310 entry->mask = 1;
497c9a19
YL		 1311 return 0;
1312}
1313
1314static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
54168ed7 1315 int trigger, int polarity)
497c9a19
YL		 1316{
1317 struct irq_cfg *cfg;
1da177e4 1318 struct IO_APIC_route_entry entry;
497c9a19
YL		 1319 cpumask_t mask;
1320
1321 if (!IO_APIC_IRQ(irq))
1322 return;
1323
1324 cfg = irq_cfg(irq);
1325
1326 mask = TARGET_CPUS;
1327 if (assign_irq_vector(irq, mask))
1328 return;
1329
1330 cpus_and(mask, cfg->domain, mask);
1331
1332 apic_printk(APIC_VERBOSE,KERN_DEBUG
1333 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1334 "IRQ %d Mode:%i Active:%i)\n",
1335 apic, mp_ioapics[apic].mp_apicid, pin, cfg->vector,
1336 irq, trigger, polarity);
1337
1338
1339 if (setup_ioapic_entry(mp_ioapics[apic].mp_apicid, irq, &entry,
1340 cpu_mask_to_apicid(mask), trigger, polarity,
1341 cfg->vector)) {
1342 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1343 mp_ioapics[apic].mp_apicid, pin);
1344 __clear_irq_vector(irq);
1345 return;
1346 }
1347
1348 ioapic_register_intr(irq, trigger);
1349 if (irq < 16)
1350 disable_8259A_irq(irq);
1351
1352 ioapic_write_entry(apic, pin, entry);
1353}
1354
1355static void __init setup_IO_APIC_irqs(void)
1356{
3c2cbd24
CG		 1357 int apic, pin, idx, irq;
1358 int notcon = 0;
1da177e4
LT		 1359
1360 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1361
1362 for (apic = 0; apic < nr_ioapics; apic++) {
3c2cbd24 1363 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
20d225b9 1364
3c2cbd24
CG		 1365 idx = find_irq_entry(apic, pin, mp_INT);
1366 if (idx == -1) {
2a554fb1 1367 if (!notcon) {
3c2cbd24 1368 notcon = 1;
2a554fb1
CG		 1369 apic_printk(APIC_VERBOSE,
1370 KERN_DEBUG " %d-%d",
1371 mp_ioapics[apic].mp_apicid,
1372 pin);
1373 } else
1374 apic_printk(APIC_VERBOSE, " %d-%d",
1375 mp_ioapics[apic].mp_apicid,
1376 pin);
3c2cbd24
CG		 1377 continue;
1378 }
56ffa1a0
CG		 1379 if (notcon) {
1380 apic_printk(APIC_VERBOSE,
1381 " (apicid-pin) not connected\n");
1382 notcon = 0;
1383 }
3c2cbd24
CG		 1384
1385 irq = pin_2_irq(idx, apic, pin);
54168ed7 1386#ifdef CONFIG_X86_32
3c2cbd24
CG		 1387 if (multi_timer_check(apic, irq))
1388 continue;
54168ed7 1389#endif
3c2cbd24 1390 add_pin_to_irq(irq, apic, pin);
36062448 1391
3c2cbd24
CG		 1392 setup_IO_APIC_irq(apic, pin, irq,
1393 irq_trigger(idx), irq_polarity(idx));
1394 }
1da177e4
LT		 1395 }
1396
3c2cbd24
CG		 1397 if (notcon)
1398 apic_printk(APIC_VERBOSE,
2a554fb1 1399 " (apicid-pin) not connected\n");
1da177e4
LT		 1400}
1401
1402/*
f7633ce5 1403 * Set up the timer pin, possibly with the 8259A-master behind.
1da177e4 1404 */
f7633ce5
MR		 1405static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
1406 int vector)
1da177e4
LT		 1407{
1408 struct IO_APIC_route_entry entry;
1da177e4 1409
54168ed7
IM		 1410#ifdef CONFIG_INTR_REMAP
1411 if (intr_remapping_enabled)
1412 return;
1413#endif
1414
36062448 1415 memset(&entry, 0, sizeof(entry));
1da177e4
LT		 1416
1417 /*
1418 * We use logical delivery to get the timer IRQ
1419 * to the first CPU.
1420 */
1421 entry.dest_mode = INT_DEST_MODE;
03be7505 1422 entry.mask = 1; /* mask IRQ now */
d83e94ac 1423 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
1da177e4
LT		 1424 entry.delivery_mode = INT_DELIVERY_MODE;
1425 entry.polarity = 0;
1426 entry.trigger = 0;
1427 entry.vector = vector;
1428
1429 /*
1430 * The timer IRQ doesn't have to know that behind the
f7633ce5 1431 * scene we may have a 8259A-master in AEOI mode ...
1da177e4 1432 */
54168ed7 1433 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1da177e4
LT		 1434
1435 /*
1436 * Add it to the IO-APIC irq-routing table:
1437 */
cf4c6a2f 1438 ioapic_write_entry(apic, pin, entry);
1da177e4
LT		 1439}
1440
32f71aff
MR		 1441
1442__apicdebuginit(void) print_IO_APIC(void)
1da177e4
LT		 1443{
1444 int apic, i;
1445 union IO_APIC_reg_00 reg_00;
1446 union IO_APIC_reg_01 reg_01;
1447 union IO_APIC_reg_02 reg_02;
1448 union IO_APIC_reg_03 reg_03;
1449 unsigned long flags;
0f978f45 1450 struct irq_cfg *cfg;
8f09cd20 1451 unsigned int irq;
1da177e4
LT		 1452
1453 if (apic_verbosity == APIC_QUIET)
1454 return;
1455
36062448 1456 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1da177e4
LT		 1457 for (i = 0; i < nr_ioapics; i++)
1458 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
ec2cd0a2 1459 mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]);
1da177e4
LT		 1460
1461 /*
1462 * We are a bit conservative about what we expect. We have to
1463 * know about every hardware change ASAP.
1464 */
1465 printk(KERN_INFO "testing the IO APIC.......................\n");
1466
1467 for (apic = 0; apic < nr_ioapics; apic++) {
1468
1469 spin_lock_irqsave(&ioapic_lock, flags);
1470 reg_00.raw = io_apic_read(apic, 0);
1471 reg_01.raw = io_apic_read(apic, 1);
1472 if (reg_01.bits.version >= 0x10)
1473 reg_02.raw = io_apic_read(apic, 2);
d6c88a50
TG		 1474 if (reg_01.bits.version >= 0x20)
1475 reg_03.raw = io_apic_read(apic, 3);
1da177e4
LT		 1476 spin_unlock_irqrestore(&ioapic_lock, flags);
1477
54168ed7 1478 printk("\n");
ec2cd0a2 1479 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid);
1da177e4
LT		 1480 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1481 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1482 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1483 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1da177e4 1484
54168ed7 1485 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1da177e4 1486 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1da177e4
LT		 1487
1488 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1489 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1da177e4
LT		 1490
1491 /*
1492 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1493 * but the value of reg_02 is read as the previous read register
1494 * value, so ignore it if reg_02 == reg_01.
1495 */
1496 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1497 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1498 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1da177e4
LT		 1499 }
1500
1501 /*
1502 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1503 * or reg_03, but the value of reg_0[23] is read as the previous read
1504 * register value, so ignore it if reg_03 == reg_0[12].
1505 */
1506 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1507 reg_03.raw != reg_01.raw) {
1508 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1509 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1da177e4
LT		 1510 }
1511
1512 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1513
d83e94ac
YL		 1514 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1515 " Stat Dmod Deli Vect: \n");
1da177e4
LT		 1516
1517 for (i = 0; i <= reg_01.bits.entries; i++) {
1518 struct IO_APIC_route_entry entry;
1519
cf4c6a2f 1520 entry = ioapic_read_entry(apic, i);
1da177e4 1521
54168ed7
IM		 1522 printk(KERN_DEBUG " %02x %03X ",
1523 i,
1524 entry.dest
1525 );
1da177e4
LT		 1526
1527 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1528 entry.mask,
1529 entry.trigger,
1530 entry.irr,
1531 entry.polarity,
1532 entry.delivery_status,
1533 entry.dest_mode,
1534 entry.delivery_mode,
1535 entry.vector
1536 );
1537 }
1538 }
1da177e4 1539 printk(KERN_DEBUG "IRQ to pin mappings:\n");
8f09cd20 1540 for_each_irq_cfg(irq, cfg) {
0f978f45
YL		 1541 struct irq_pin_list *entry = cfg->irq_2_pin;
1542 if (!entry)
1da177e4 1543 continue;
8f09cd20 1544 printk(KERN_DEBUG "IRQ%d ", irq);
1da177e4
LT		 1545 for (;;) {
1546 printk("-> %d:%d", entry->apic, entry->pin);
1547 if (!entry->next)
1548 break;
0f978f45 1549 entry = entry->next;
1da177e4
LT		 1550 }
1551 printk("\n");
1552 }
1553
1554 printk(KERN_INFO ".................................... done.\n");
1555
1556 return;
1557}
1558
32f71aff 1559__apicdebuginit(void) print_APIC_bitfield(int base)
1da177e4
LT		 1560{
1561 unsigned int v;
1562 int i, j;
1563
1564 if (apic_verbosity == APIC_QUIET)
1565 return;
1566
1567 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1568 for (i = 0; i < 8; i++) {
1569 v = apic_read(base + i*0x10);
1570 for (j = 0; j < 32; j++) {
1571 if (v & (1<<j))
1572 printk("1");
1573 else
1574 printk("0");
1575 }
1576 printk("\n");
1577 }
1578}
1579
32f71aff 1580__apicdebuginit(void) print_local_APIC(void *dummy)
1da177e4
LT		 1581{
1582 unsigned int v, ver, maxlvt;
7ab6af7a 1583 u64 icr;
1da177e4
LT		 1584
1585 if (apic_verbosity == APIC_QUIET)
1586 return;
1587
1588 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1589 smp_processor_id(), hard_smp_processor_id());
66823114 1590 v = apic_read(APIC_ID);
54168ed7 1591 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1da177e4
LT		 1592 v = apic_read(APIC_LVR);
1593 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1594 ver = GET_APIC_VERSION(v);
e05d723f 1595 maxlvt = lapic_get_maxlvt();
1da177e4
LT		 1596
1597 v = apic_read(APIC_TASKPRI);
1598 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1599
54168ed7 1600 if (APIC_INTEGRATED(ver)) { /* !82489DX */
a11b5abe
YL		 1601 if (!APIC_XAPIC(ver)) {
1602 v = apic_read(APIC_ARBPRI);
1603 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1604 v & APIC_ARBPRI_MASK);
1605 }
1da177e4
LT		 1606 v = apic_read(APIC_PROCPRI);
1607 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1608 }
1609
a11b5abe
YL		 1610 /*
1611 * Remote read supported only in the 82489DX and local APIC for
1612 * Pentium processors.
1613 */
1614 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1615 v = apic_read(APIC_RRR);
1616 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1617 }
1618
1da177e4
LT		 1619 v = apic_read(APIC_LDR);
1620 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
a11b5abe
YL		 1621 if (!x2apic_enabled()) {
1622 v = apic_read(APIC_DFR);
1623 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1624 }
1da177e4
LT		 1625 v = apic_read(APIC_SPIV);
1626 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1627
1628 printk(KERN_DEBUG "... APIC ISR field:\n");
1629 print_APIC_bitfield(APIC_ISR);
1630 printk(KERN_DEBUG "... APIC TMR field:\n");
1631 print_APIC_bitfield(APIC_TMR);
1632 printk(KERN_DEBUG "... APIC IRR field:\n");
1633 print_APIC_bitfield(APIC_IRR);
1634
54168ed7
IM		 1635 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1636 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1da177e4 1637 apic_write(APIC_ESR, 0);
54168ed7 1638
1da177e4
LT		 1639 v = apic_read(APIC_ESR);
1640 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1641 }
1642
7ab6af7a 1643 icr = apic_icr_read();
0c425cec
IM		 1644 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1645 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1da177e4
LT		 1646
1647 v = apic_read(APIC_LVTT);
1648 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1649
1650 if (maxlvt > 3) { /* PC is LVT#4. */
1651 v = apic_read(APIC_LVTPC);
1652 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1653 }
1654 v = apic_read(APIC_LVT0);
1655 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1656 v = apic_read(APIC_LVT1);
1657 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1658
1659 if (maxlvt > 2) { /* ERR is LVT#3. */
1660 v = apic_read(APIC_LVTERR);
1661 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1662 }
1663
1664 v = apic_read(APIC_TMICT);
1665 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1666 v = apic_read(APIC_TMCCT);
1667 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1668 v = apic_read(APIC_TDCR);
1669 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1670 printk("\n");
1671}
1672
32f71aff 1673__apicdebuginit(void) print_all_local_APICs(void)
1da177e4 1674{
ffd5aae7
YL		 1675 int cpu;
1676
1677 preempt_disable();
1678 for_each_online_cpu(cpu)
1679 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1680 preempt_enable();
1da177e4
LT		 1681}
1682
32f71aff 1683__apicdebuginit(void) print_PIC(void)
1da177e4 1684{
1da177e4
LT		 1685 unsigned int v;
1686 unsigned long flags;
1687
1688 if (apic_verbosity == APIC_QUIET)
1689 return;
1690
1691 printk(KERN_DEBUG "\nprinting PIC contents\n");
1692
1693 spin_lock_irqsave(&i8259A_lock, flags);
1694
1695 v = inb(0xa1) << 8 | inb(0x21);
1696 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1697
1698 v = inb(0xa0) << 8 | inb(0x20);
1699 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1700
54168ed7
IM		 1701 outb(0x0b,0xa0);
1702 outb(0x0b,0x20);
1da177e4 1703 v = inb(0xa0) << 8 | inb(0x20);
54168ed7
IM		 1704 outb(0x0a,0xa0);
1705 outb(0x0a,0x20);
1da177e4
LT		 1706
1707 spin_unlock_irqrestore(&i8259A_lock, flags);
1708
1709 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1710
1711 v = inb(0x4d1) << 8 | inb(0x4d0);
1712 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1713}
1714
32f71aff
MR		 1715__apicdebuginit(int) print_all_ICs(void)
1716{
1717 print_PIC();
1718 print_all_local_APICs();
1719 print_IO_APIC();
1720
1721 return 0;
1722}
1723
1724fs_initcall(print_all_ICs);
1725
1da177e4 1726
efa2559f
YL		 1727/* Where if anywhere is the i8259 connect in external int mode */
1728static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1729
54168ed7 1730void __init enable_IO_APIC(void)
1da177e4
LT		 1731{
1732 union IO_APIC_reg_01 reg_01;
fcfd636a 1733 int i8259_apic, i8259_pin;
54168ed7 1734 int apic;
1da177e4
LT		 1735 unsigned long flags;
1736
54168ed7
IM		 1737#ifdef CONFIG_X86_32
1738 int i;
1da177e4
LT		 1739 if (!pirqs_enabled)
1740 for (i = 0; i < MAX_PIRQS; i++)
1741 pirq_entries[i] = -1;
54168ed7 1742#endif
1da177e4
LT		 1743
1744 /*
1745 * The number of IO-APIC IRQ registers (== #pins):
1746 */
fcfd636a 1747 for (apic = 0; apic < nr_ioapics; apic++) {
1da177e4 1748 spin_lock_irqsave(&ioapic_lock, flags);
fcfd636a 1749 reg_01.raw = io_apic_read(apic, 1);
1da177e4 1750 spin_unlock_irqrestore(&ioapic_lock, flags);
fcfd636a
EB		 1751 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1752 }
54168ed7 1753 for(apic = 0; apic < nr_ioapics; apic++) {
fcfd636a
EB		 1754 int pin;
1755 /* See if any of the pins is in ExtINT mode */
1008fddc 1756 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
fcfd636a 1757 struct IO_APIC_route_entry entry;
cf4c6a2f 1758 entry = ioapic_read_entry(apic, pin);
fcfd636a 1759
fcfd636a
EB		 1760 /* If the interrupt line is enabled and in ExtInt mode
1761 * I have found the pin where the i8259 is connected.
1762 */
1763 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1764 ioapic_i8259.apic = apic;
1765 ioapic_i8259.pin = pin;
1766 goto found_i8259;
1767 }
1768 }
1769 }
1770 found_i8259:
1771 /* Look to see what if the MP table has reported the ExtINT */
1772 /* If we could not find the appropriate pin by looking at the ioapic
1773 * the i8259 probably is not connected the ioapic but give the
1774 * mptable a chance anyway.
1775 */
1776 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1777 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1778 /* Trust the MP table if nothing is setup in the hardware */
1779 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1780 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1781 ioapic_i8259.pin = i8259_pin;
1782 ioapic_i8259.apic = i8259_apic;
1783 }
1784 /* Complain if the MP table and the hardware disagree */
1785 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1786 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1787 {
1788 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1da177e4
LT		 1789 }
1790
1791 /*
1792 * Do not trust the IO-APIC being empty at bootup
1793 */
1794 clear_IO_APIC();
1795}
1796
1797/*
1798 * Not an __init, needed by the reboot code
1799 */
1800void disable_IO_APIC(void)
1801{
1802 /*
1803 * Clear the IO-APIC before rebooting:
1804 */
1805 clear_IO_APIC();
1806
650927ef 1807 /*
0b968d23 1808 * If the i8259 is routed through an IOAPIC
650927ef 1809 * Put that IOAPIC in virtual wire mode
0b968d23 1810 * so legacy interrupts can be delivered.
650927ef 1811 */
fcfd636a 1812 if (ioapic_i8259.pin != -1) {
650927ef 1813 struct IO_APIC_route_entry entry;
650927ef
EB		 1814
1815 memset(&entry, 0, sizeof(entry));
1816 entry.mask = 0; /* Enabled */
1817 entry.trigger = 0; /* Edge */
1818 entry.irr = 0;
1819 entry.polarity = 0; /* High */
1820 entry.delivery_status = 0;
1821 entry.dest_mode = 0; /* Physical */
fcfd636a 1822 entry.delivery_mode = dest_ExtINT; /* ExtInt */
650927ef 1823 entry.vector = 0;
54168ed7 1824 entry.dest = read_apic_id();
650927ef
EB		 1825
1826 /*
1827 * Add it to the IO-APIC irq-routing table:
1828 */
cf4c6a2f 1829 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
650927ef 1830 }
54168ed7 1831
fcfd636a 1832 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1da177e4
LT		 1833}
1834
54168ed7 1835#ifdef CONFIG_X86_32
1da177e4
LT		 1836/*
1837 * function to set the IO-APIC physical IDs based on the
1838 * values stored in the MPC table.
1839 *
1840 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1841 */
1842
1da177e4
LT		 1843static void __init setup_ioapic_ids_from_mpc(void)
1844{
1845 union IO_APIC_reg_00 reg_00;
1846 physid_mask_t phys_id_present_map;
1847 int apic;
1848 int i;
1849 unsigned char old_id;
1850 unsigned long flags;
1851
a4dbc34d 1852 if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
d49c4288 1853 return;
d49c4288 1854
ca05fea6
NP		 1855 /*
1856 * Don't check I/O APIC IDs for xAPIC systems. They have
1857 * no meaning without the serial APIC bus.
1858 */
7c5c1e42
SL		 1859 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1860 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
ca05fea6 1861 return;
1da177e4
LT		 1862 /*
1863 * This is broken; anything with a real cpu count has to
1864 * circumvent this idiocy regardless.
1865 */
1866 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1867
1868 /*
1869 * Set the IOAPIC ID to the value stored in the MPC table.
1870 */
1871 for (apic = 0; apic < nr_ioapics; apic++) {
1872
1873 /* Read the register 0 value */
1874 spin_lock_irqsave(&ioapic_lock, flags);
1875 reg_00.raw = io_apic_read(apic, 0);
1876 spin_unlock_irqrestore(&ioapic_lock, flags);
36062448 1877
ec2cd0a2 1878 old_id = mp_ioapics[apic].mp_apicid;
1da177e4 1879
ec2cd0a2 1880 if (mp_ioapics[apic].mp_apicid >= get_physical_broadcast()) {
1da177e4 1881 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
ec2cd0a2 1882 apic, mp_ioapics[apic].mp_apicid);
1da177e4
LT		 1883 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1884 reg_00.bits.ID);
ec2cd0a2 1885 mp_ioapics[apic].mp_apicid = reg_00.bits.ID;
1da177e4
LT		 1886 }
1887
1da177e4
LT		 1888 /*
1889 * Sanity check, is the ID really free? Every APIC in a
1890 * system must have a unique ID or we get lots of nice
1891 * 'stuck on smp_invalidate_needed IPI wait' messages.
1892 */
1893 if (check_apicid_used(phys_id_present_map,
ec2cd0a2 1894 mp_ioapics[apic].mp_apicid)) {
1da177e4 1895 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
ec2cd0a2 1896 apic, mp_ioapics[apic].mp_apicid);
1da177e4
LT		 1897 for (i = 0; i < get_physical_broadcast(); i++)
1898 if (!physid_isset(i, phys_id_present_map))
1899 break;
1900 if (i >= get_physical_broadcast())
1901 panic("Max APIC ID exceeded!\n");
1902 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1903 i);
1904 physid_set(i, phys_id_present_map);
ec2cd0a2 1905 mp_ioapics[apic].mp_apicid = i;
1da177e4
LT		 1906 } else {
1907 physid_mask_t tmp;
ec2cd0a2 1908 tmp = apicid_to_cpu_present(mp_ioapics[apic].mp_apicid);
1da177e4
LT		 1909 apic_printk(APIC_VERBOSE, "Setting %d in the "
1910 "phys_id_present_map\n",
ec2cd0a2 1911 mp_ioapics[apic].mp_apicid);
1da177e4
LT		 1912 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1913 }
1914
1915
1916 /*
1917 * We need to adjust the IRQ routing table
1918 * if the ID changed.
1919 */
ec2cd0a2 1920 if (old_id != mp_ioapics[apic].mp_apicid)
1da177e4 1921 for (i = 0; i < mp_irq_entries; i++)
2fddb6e2
AS		 1922 if (mp_irqs[i].mp_dstapic == old_id)
1923 mp_irqs[i].mp_dstapic
ec2cd0a2 1924 = mp_ioapics[apic].mp_apicid;
1da177e4
LT		 1925
1926 /*
1927 * Read the right value from the MPC table and
1928 * write it into the ID register.
36062448 1929 */
1da177e4
LT		 1930 apic_printk(APIC_VERBOSE, KERN_INFO
1931 "...changing IO-APIC physical APIC ID to %d ...",
ec2cd0a2 1932 mp_ioapics[apic].mp_apicid);
1da177e4 1933
ec2cd0a2 1934 reg_00.bits.ID = mp_ioapics[apic].mp_apicid;
1da177e4 1935 spin_lock_irqsave(&ioapic_lock, flags);
a2d332fa
YL		 1936 io_apic_write(apic, 0, reg_00.raw);
1937 spin_unlock_irqrestore(&ioapic_lock, flags);
1da177e4
LT		 1938
1939 /*
1940 * Sanity check
1941 */
1942 spin_lock_irqsave(&ioapic_lock, flags);
1943 reg_00.raw = io_apic_read(apic, 0);
1944 spin_unlock_irqrestore(&ioapic_lock, flags);
ec2cd0a2 1945 if (reg_00.bits.ID != mp_ioapics[apic].mp_apicid)
1da177e4
LT		 1946 printk("could not set ID!\n");
1947 else
1948 apic_printk(APIC_VERBOSE, " ok.\n");
1949 }
1950}
54168ed7 1951#endif
1da177e4 1952
7ce0bcfd 1953int no_timer_check __initdata;
8542b200
ZA		 1954
1955static int __init notimercheck(char *s)
1956{
1957 no_timer_check = 1;
1958 return 1;
1959}
1960__setup("no_timer_check", notimercheck);
1961
1da177e4
LT		 1962/*
1963 * There is a nasty bug in some older SMP boards, their mptable lies
1964 * about the timer IRQ. We do the following to work around the situation:
1965 *
1966 * - timer IRQ defaults to IO-APIC IRQ
1967 * - if this function detects that timer IRQs are defunct, then we fall
1968 * back to ISA timer IRQs
1969 */
f0a7a5c9 1970static int __init timer_irq_works(void)
1da177e4
LT		 1971{
1972 unsigned long t1 = jiffies;
4aae0702 1973 unsigned long flags;
1da177e4 1974
8542b200
ZA		 1975 if (no_timer_check)
1976 return 1;
1977
4aae0702 1978 local_save_flags(flags);
1da177e4
LT		 1979 local_irq_enable();
1980 /* Let ten ticks pass... */
1981 mdelay((10 * 1000) / HZ);
4aae0702 1982 local_irq_restore(flags);
1da177e4
LT		 1983
1984 /*
1985 * Expect a few ticks at least, to be sure some possible
1986 * glue logic does not lock up after one or two first
1987 * ticks in a non-ExtINT mode. Also the local APIC
1988 * might have cached one ExtINT interrupt. Finally, at
1989 * least one tick may be lost due to delays.
1990 */
54168ed7
IM		 1991
1992 /* jiffies wrap? */
1d16b53e 1993 if (time_after(jiffies, t1 + 4))
1da177e4 1994 return 1;
1da177e4
LT		 1995 return 0;
1996}
1997
1998/*
1999 * In the SMP+IOAPIC case it might happen that there are an unspecified
2000 * number of pending IRQ events unhandled. These cases are very rare,
2001 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2002 * better to do it this way as thus we do not have to be aware of
2003 * 'pending' interrupts in the IRQ path, except at this point.
2004 */
2005/*
2006 * Edge triggered needs to resend any interrupt
2007 * that was delayed but this is now handled in the device
2008 * independent code.
2009 */
2010
2011/*
2012 * Starting up a edge-triggered IO-APIC interrupt is
2013 * nasty - we need to make sure that we get the edge.
2014 * If it is already asserted for some reason, we need
2015 * return 1 to indicate that is was pending.
2016 *
2017 * This is not complete - we should be able to fake
2018 * an edge even if it isn't on the 8259A...
2019 */
54168ed7 2020
f5b9ed7a 2021static unsigned int startup_ioapic_irq(unsigned int irq)
1da177e4
LT		 2022{
2023 int was_pending = 0;
2024 unsigned long flags;
2025
2026 spin_lock_irqsave(&ioapic_lock, flags);
2027 if (irq < 16) {
2028 disable_8259A_irq(irq);
2029 if (i8259A_irq_pending(irq))
2030 was_pending = 1;
2031 }
2032 __unmask_IO_APIC_irq(irq);
2033 spin_unlock_irqrestore(&ioapic_lock, flags);
2034
2035 return was_pending;
2036}
2037
54168ed7 2038#ifdef CONFIG_X86_64
ace80ab7 2039static int ioapic_retrigger_irq(unsigned int irq)
1da177e4 2040{
54168ed7
IM		 2041
2042 struct irq_cfg *cfg = irq_cfg(irq);
2043 unsigned long flags;
2044
2045 spin_lock_irqsave(&vector_lock, flags);
2046 send_IPI_mask(cpumask_of_cpu(first_cpu(cfg->domain)), cfg->vector);
2047 spin_unlock_irqrestore(&vector_lock, flags);
c0ad90a3
IM		 2048
2049 return 1;
2050}
54168ed7
IM		 2051#else
2052static int ioapic_retrigger_irq(unsigned int irq)
497c9a19 2053{
d6c88a50 2054 send_IPI_self(irq_cfg(irq)->vector);
497c9a19 2055
d6c88a50 2056 return 1;
54168ed7
IM		 2057}
2058#endif
497c9a19 2059
54168ed7
IM		 2060/*
2061 * Level and edge triggered IO-APIC interrupts need different handling,
2062 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2063 * handled with the level-triggered descriptor, but that one has slightly
2064 * more overhead. Level-triggered interrupts cannot be handled with the
2065 * edge-triggered handler, without risking IRQ storms and other ugly
2066 * races.
2067 */
497c9a19 2068
54168ed7 2069#ifdef CONFIG_SMP
497c9a19 2070
54168ed7
IM		 2071#ifdef CONFIG_INTR_REMAP
2072static void ir_irq_migration(struct work_struct *work);
497c9a19 2073
54168ed7 2074static DECLARE_DELAYED_WORK(ir_migration_work, ir_irq_migration);
497c9a19 2075
54168ed7
IM		 2076/*
2077 * Migrate the IO-APIC irq in the presence of intr-remapping.
2078 *
2079 * For edge triggered, irq migration is a simple atomic update(of vector
2080 * and cpu destination) of IRTE and flush the hardware cache.
2081 *
2082 * For level triggered, we need to modify the io-apic RTE aswell with the update
2083 * vector information, along with modifying IRTE with vector and destination.
2084 * So irq migration for level triggered is little bit more complex compared to
2085 * edge triggered migration. But the good news is, we use the same algorithm
2086 * for level triggered migration as we have today, only difference being,
2087 * we now initiate the irq migration from process context instead of the
2088 * interrupt context.
2089 *
2090 * In future, when we do a directed EOI (combined with cpu EOI broadcast
2091 * suppression) to the IO-APIC, level triggered irq migration will also be
2092 * as simple as edge triggered migration and we can do the irq migration
2093 * with a simple atomic update to IO-APIC RTE.
2094 */
2095static void migrate_ioapic_irq(int irq, cpumask_t mask)
497c9a19 2096{
54168ed7
IM		 2097 struct irq_cfg *cfg;
2098 struct irq_desc *desc;
2099 cpumask_t tmp, cleanup_mask;
2100 struct irte irte;
2101 int modify_ioapic_rte;
2102 unsigned int dest;
2103 unsigned long flags;
497c9a19 2104
54168ed7
IM		 2105 cpus_and(tmp, mask, cpu_online_map);
2106 if (cpus_empty(tmp))
497c9a19
YL		 2107 return;
2108
54168ed7
IM		 2109 if (get_irte(irq, &irte))
2110 return;
497c9a19 2111
54168ed7
IM		 2112 if (assign_irq_vector(irq, mask))
2113 return;
2114
2115 cfg = irq_cfg(irq);
2116 cpus_and(tmp, cfg->domain, mask);
2117 dest = cpu_mask_to_apicid(tmp);
2118
2119 desc = irq_to_desc(irq);
2120 modify_ioapic_rte = desc->status & IRQ_LEVEL;
2121 if (modify_ioapic_rte) {
2122 spin_lock_irqsave(&ioapic_lock, flags);
2123 __target_IO_APIC_irq(irq, dest, cfg->vector);
2124 spin_unlock_irqrestore(&ioapic_lock, flags);
2125 }
2126
2127 irte.vector = cfg->vector;
2128 irte.dest_id = IRTE_DEST(dest);
2129
2130 /*
2131 * Modified the IRTE and flushes the Interrupt entry cache.
2132 */
2133 modify_irte(irq, &irte);
2134
2135 if (cfg->move_in_progress) {
2136 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
2137 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
2138 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2139 cfg->move_in_progress = 0;
2140 }
2141
2142 desc->affinity = mask;
2143}
2144
2145static int migrate_irq_remapped_level(int irq)
2146{
2147 int ret = -1;
2148 struct irq_desc *desc = irq_to_desc(irq);
2149
2150 mask_IO_APIC_irq(irq);
2151
2152 if (io_apic_level_ack_pending(irq)) {
2153 /*
d6c88a50 2154 * Interrupt in progress. Migrating irq now will change the
54168ed7
IM		 2155 * vector information in the IO-APIC RTE and that will confuse
2156 * the EOI broadcast performed by cpu.
2157 * So, delay the irq migration to the next instance.
2158 */
2159 schedule_delayed_work(&ir_migration_work, 1);
2160 goto unmask;
2161 }
2162
2163 /* everthing is clear. we have right of way */
2164 migrate_ioapic_irq(irq, desc->pending_mask);
2165
2166 ret = 0;
2167 desc->status &= ~IRQ_MOVE_PENDING;
2168 cpus_clear(desc->pending_mask);
2169
2170unmask:
2171 unmask_IO_APIC_irq(irq);
2172 return ret;
2173}
2174
2175static void ir_irq_migration(struct work_struct *work)
2176{
2177 unsigned int irq;
2178 struct irq_desc *desc;
2179
2180 for_each_irq_desc(irq, desc) {
2181 if (desc->status & IRQ_MOVE_PENDING) {
2182 unsigned long flags;
2183
2184 spin_lock_irqsave(&desc->lock, flags);
2185 if (!desc->chip->set_affinity ||
2186 !(desc->status & IRQ_MOVE_PENDING)) {
2187 desc->status &= ~IRQ_MOVE_PENDING;
2188 spin_unlock_irqrestore(&desc->lock, flags);
2189 continue;
2190 }
2191
2192 desc->chip->set_affinity(irq, desc->pending_mask);
2193 spin_unlock_irqrestore(&desc->lock, flags);
2194 }
2195 }
2196}
2197
2198/*
2199 * Migrates the IRQ destination in the process context.
2200 */
2201static void set_ir_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
2202{
2203 struct irq_desc *desc = irq_to_desc(irq);
2204
2205 if (desc->status & IRQ_LEVEL) {
2206 desc->status |= IRQ_MOVE_PENDING;
2207 desc->pending_mask = mask;
2208 migrate_irq_remapped_level(irq);
2209 return;
2210 }
2211
2212 migrate_ioapic_irq(irq, mask);
2213}
2214#endif
2215
2216asmlinkage void smp_irq_move_cleanup_interrupt(void)
2217{
2218 unsigned vector, me;
8f2466f4 2219
54168ed7 2220 ack_APIC_irq();
54168ed7 2221 exit_idle();
54168ed7
IM		 2222 irq_enter();
2223
2224 me = smp_processor_id();
2225 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2226 unsigned int irq;
2227 struct irq_desc *desc;
2228 struct irq_cfg *cfg;
2229 irq = __get_cpu_var(vector_irq)[vector];
2230
2231 desc = irq_to_desc(irq);
2232 if (!desc)
2233 continue;
2234
2235 cfg = irq_cfg(irq);
2236 spin_lock(&desc->lock);
2237 if (!cfg->move_cleanup_count)
2238 goto unlock;
2239
2240 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
2241 goto unlock;
2242
2243 __get_cpu_var(vector_irq)[vector] = -1;
2244 cfg->move_cleanup_count--;
2245unlock:
2246 spin_unlock(&desc->lock);
2247 }
2248
2249 irq_exit();
2250}
2251
2252static void irq_complete_move(unsigned int irq)
2253{
2254 struct irq_cfg *cfg = irq_cfg(irq);
2255 unsigned vector, me;
2256
2257 if (likely(!cfg->move_in_progress))
2258 return;
2259
2260 vector = ~get_irq_regs()->orig_ax;
2261 me = smp_processor_id();
2262 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
2263 cpumask_t cleanup_mask;
2264
2265 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
2266 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
2267 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
497c9a19
YL		 2268 cfg->move_in_progress = 0;
2269 }
2270}
2271#else
2272static inline void irq_complete_move(unsigned int irq) {}
2273#endif
54168ed7
IM		 2274#ifdef CONFIG_INTR_REMAP
2275static void ack_x2apic_level(unsigned int irq)
2276{
2277 ack_x2APIC_irq();
2278}
2279
2280static void ack_x2apic_edge(unsigned int irq)
2281{
2282 ack_x2APIC_irq();
2283}
2284#endif
497c9a19 2285
1d025192
YL		 2286static void ack_apic_edge(unsigned int irq)
2287{
2288 irq_complete_move(irq);
2289 move_native_irq(irq);
2290 ack_APIC_irq();
2291}
2292
3eb2cce8 2293atomic_t irq_mis_count;
3eb2cce8 2294
047c8fdb
YL		 2295static void ack_apic_level(unsigned int irq)
2296{
3eb2cce8
YL		 2297#ifdef CONFIG_X86_32
2298 unsigned long v;
2299 int i;
2300#endif
54168ed7 2301 int do_unmask_irq = 0;
047c8fdb 2302
54168ed7 2303 irq_complete_move(irq);
047c8fdb 2304#ifdef CONFIG_GENERIC_PENDING_IRQ
54168ed7
IM		 2305 /* If we are moving the irq we need to mask it */
2306 if (unlikely(irq_to_desc(irq)->status & IRQ_MOVE_PENDING)) {
2307 do_unmask_irq = 1;
2308 mask_IO_APIC_irq(irq);
2309 }
047c8fdb
YL		 2310#endif
2311
3eb2cce8
YL		 2312#ifdef CONFIG_X86_32
2313 /*
2314 * It appears there is an erratum which affects at least version 0x11
2315 * of I/O APIC (that's the 82093AA and cores integrated into various
2316 * chipsets). Under certain conditions a level-triggered interrupt is
2317 * erroneously delivered as edge-triggered one but the respective IRR
2318 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2319 * message but it will never arrive and further interrupts are blocked
2320 * from the source. The exact reason is so far unknown, but the
2321 * phenomenon was observed when two consecutive interrupt requests
2322 * from a given source get delivered to the same CPU and the source is
2323 * temporarily disabled in between.
2324 *
2325 * A workaround is to simulate an EOI message manually. We achieve it
2326 * by setting the trigger mode to edge and then to level when the edge
2327 * trigger mode gets detected in the TMR of a local APIC for a
2328 * level-triggered interrupt. We mask the source for the time of the
2329 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2330 * The idea is from Manfred Spraul. --macro
2331 */
2332 i = irq_cfg(irq)->vector;
2333
2334 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2335#endif
2336
54168ed7
IM		 2337 /*
2338 * We must acknowledge the irq before we move it or the acknowledge will
2339 * not propagate properly.
2340 */
2341 ack_APIC_irq();
2342
2343 /* Now we can move and renable the irq */
2344 if (unlikely(do_unmask_irq)) {
2345 /* Only migrate the irq if the ack has been received.
2346 *
2347 * On rare occasions the broadcast level triggered ack gets
2348 * delayed going to ioapics, and if we reprogram the
2349 * vector while Remote IRR is still set the irq will never
2350 * fire again.
2351 *
2352 * To prevent this scenario we read the Remote IRR bit
2353 * of the ioapic. This has two effects.
2354 * - On any sane system the read of the ioapic will
2355 * flush writes (and acks) going to the ioapic from
2356 * this cpu.
2357 * - We get to see if the ACK has actually been delivered.
2358 *
2359 * Based on failed experiments of reprogramming the
2360 * ioapic entry from outside of irq context starting
2361 * with masking the ioapic entry and then polling until
2362 * Remote IRR was clear before reprogramming the
2363 * ioapic I don't trust the Remote IRR bit to be
2364 * completey accurate.
2365 *
2366 * However there appears to be no other way to plug
2367 * this race, so if the Remote IRR bit is not
2368 * accurate and is causing problems then it is a hardware bug
2369 * and you can go talk to the chipset vendor about it.
2370 */
2371 if (!io_apic_level_ack_pending(irq))
2372 move_masked_irq(irq);
2373 unmask_IO_APIC_irq(irq);
2374 }
1d025192 2375
3eb2cce8 2376#ifdef CONFIG_X86_32
1d025192
YL		 2377 if (!(v & (1 << (i & 0x1f)))) {
2378 atomic_inc(&irq_mis_count);
2379 spin_lock(&ioapic_lock);
2380 __mask_and_edge_IO_APIC_irq(irq);
2381 __unmask_and_level_IO_APIC_irq(irq);
2382 spin_unlock(&ioapic_lock);
2383 }
047c8fdb 2384#endif
3eb2cce8 2385}
1d025192 2386
f5b9ed7a 2387static struct irq_chip ioapic_chip __read_mostly = {
d6c88a50
TG		 2388 .name = "IO-APIC",
2389 .startup = startup_ioapic_irq,
2390 .mask = mask_IO_APIC_irq,
2391 .unmask = unmask_IO_APIC_irq,
2392 .ack = ack_apic_edge,
2393 .eoi = ack_apic_level,
54d5d424 2394#ifdef CONFIG_SMP
d6c88a50 2395 .set_affinity = set_ioapic_affinity_irq,
54d5d424 2396#endif
ace80ab7 2397 .retrigger = ioapic_retrigger_irq,
1da177e4
LT		 2398};
2399
54168ed7
IM		 2400#ifdef CONFIG_INTR_REMAP
2401static struct irq_chip ir_ioapic_chip __read_mostly = {
d6c88a50
TG		 2402 .name = "IR-IO-APIC",
2403 .startup = startup_ioapic_irq,
2404 .mask = mask_IO_APIC_irq,
2405 .unmask = unmask_IO_APIC_irq,
2406 .ack = ack_x2apic_edge,
2407 .eoi = ack_x2apic_level,
54168ed7 2408#ifdef CONFIG_SMP
d6c88a50 2409 .set_affinity = set_ir_ioapic_affinity_irq,
54168ed7
IM		 2410#endif
2411 .retrigger = ioapic_retrigger_irq,
2412};
2413#endif
1da177e4
LT		 2414
2415static inline void init_IO_APIC_traps(void)
2416{
2417 int irq;
08678b08 2418 struct irq_desc *desc;
da51a821 2419 struct irq_cfg *cfg;
1da177e4
LT		 2420
2421 /*
2422 * NOTE! The local APIC isn't very good at handling
2423 * multiple interrupts at the same interrupt level.
2424 * As the interrupt level is determined by taking the
2425 * vector number and shifting that right by 4, we
2426 * want to spread these out a bit so that they don't
2427 * all fall in the same interrupt level.
2428 *
2429 * Also, we've got to be careful not to trash gate
2430 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2431 */
8f09cd20 2432 for_each_irq_cfg(irq, cfg) {
da51a821 2433 if (IO_APIC_IRQ(irq) && !cfg->vector) {
1da177e4
LT		 2434 /*
2435 * Hmm.. We don't have an entry for this,
2436 * so default to an old-fashioned 8259
2437 * interrupt if we can..
2438 */
2439 if (irq < 16)
2440 make_8259A_irq(irq);
08678b08
YL		 2441 else {
2442 desc = irq_to_desc(irq);
1da177e4 2443 /* Strange. Oh, well.. */
08678b08
YL		 2444 desc->chip = &no_irq_chip;
2445 }
1da177e4
LT		 2446 }
2447 }
2448}
2449
f5b9ed7a
IM		 2450/*
2451 * The local APIC irq-chip implementation:
2452 */
1da177e4 2453
36062448 2454static void mask_lapic_irq(unsigned int irq)
1da177e4
LT		 2455{
2456 unsigned long v;
2457
2458 v = apic_read(APIC_LVT0);
593f4a78 2459 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1da177e4
LT		 2460}
2461
36062448 2462static void unmask_lapic_irq(unsigned int irq)
1da177e4 2463{
f5b9ed7a 2464 unsigned long v;
1da177e4 2465
f5b9ed7a 2466 v = apic_read(APIC_LVT0);
593f4a78 2467 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
f5b9ed7a 2468}
1da177e4 2469
54168ed7 2470static void ack_lapic_irq (unsigned int irq)
1d025192
YL		 2471{
2472 ack_APIC_irq();
2473}
2474
f5b9ed7a 2475static struct irq_chip lapic_chip __read_mostly = {
9a1c6192 2476 .name = "local-APIC",
f5b9ed7a
IM		 2477 .mask = mask_lapic_irq,
2478 .unmask = unmask_lapic_irq,
c88ac1df 2479 .ack = ack_lapic_irq,
1da177e4
LT		 2480};
2481
497c9a19 2482static void lapic_register_intr(int irq)
c88ac1df 2483{
08678b08
YL		 2484 struct irq_desc *desc;
2485
2486 desc = irq_to_desc(irq);
2487 desc->status &= ~IRQ_LEVEL;
c88ac1df
MR		 2488 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2489 "edge");
c88ac1df
MR		 2490}
2491
e9427101 2492static void __init setup_nmi(void)
1da177e4
LT		 2493{
2494 /*
36062448 2495 * Dirty trick to enable the NMI watchdog ...
1da177e4
LT		 2496 * We put the 8259A master into AEOI mode and
2497 * unmask on all local APICs LVT0 as NMI.
2498 *
2499 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2500 * is from Maciej W. Rozycki - so we do not have to EOI from
2501 * the NMI handler or the timer interrupt.
36062448 2502 */
1da177e4
LT		 2503 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2504
e9427101 2505 enable_NMI_through_LVT0();
1da177e4
LT		 2506
2507 apic_printk(APIC_VERBOSE, " done.\n");
2508}
2509
2510/*
2511 * This looks a bit hackish but it's about the only one way of sending
2512 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2513 * not support the ExtINT mode, unfortunately. We need to send these
2514 * cycles as some i82489DX-based boards have glue logic that keeps the
2515 * 8259A interrupt line asserted until INTA. --macro
2516 */
28acf285 2517static inline void __init unlock_ExtINT_logic(void)
1da177e4 2518{
fcfd636a 2519 int apic, pin, i;
1da177e4
LT		 2520 struct IO_APIC_route_entry entry0, entry1;
2521 unsigned char save_control, save_freq_select;
1da177e4 2522
fcfd636a 2523 pin = find_isa_irq_pin(8, mp_INT);
956fb531
AB		 2524 if (pin == -1) {
2525 WARN_ON_ONCE(1);
2526 return;
2527 }
fcfd636a 2528 apic = find_isa_irq_apic(8, mp_INT);
956fb531
AB		 2529 if (apic == -1) {
2530 WARN_ON_ONCE(1);
1da177e4 2531 return;
956fb531 2532 }
1da177e4 2533
cf4c6a2f 2534 entry0 = ioapic_read_entry(apic, pin);
fcfd636a 2535 clear_IO_APIC_pin(apic, pin);
1da177e4
LT		 2536
2537 memset(&entry1, 0, sizeof(entry1));
2538
2539 entry1.dest_mode = 0; /* physical delivery */
2540 entry1.mask = 0; /* unmask IRQ now */
d83e94ac 2541 entry1.dest = hard_smp_processor_id();
1da177e4
LT		 2542 entry1.delivery_mode = dest_ExtINT;
2543 entry1.polarity = entry0.polarity;
2544 entry1.trigger = 0;
2545 entry1.vector = 0;
2546
cf4c6a2f 2547 ioapic_write_entry(apic, pin, entry1);
1da177e4
LT		 2548
2549 save_control = CMOS_READ(RTC_CONTROL);
2550 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2551 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2552 RTC_FREQ_SELECT);
2553 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2554
2555 i = 100;
2556 while (i-- > 0) {
2557 mdelay(10);
2558 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2559 i -= 10;
2560 }
2561
2562 CMOS_WRITE(save_control, RTC_CONTROL);
2563 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
fcfd636a 2564 clear_IO_APIC_pin(apic, pin);
1da177e4 2565
cf4c6a2f 2566 ioapic_write_entry(apic, pin, entry0);
1da177e4
LT		 2567}
2568
efa2559f 2569static int disable_timer_pin_1 __initdata;
047c8fdb 2570/* Actually the next is obsolete, but keep it for paranoid reasons -AK */
54168ed7 2571static int __init disable_timer_pin_setup(char *arg)
efa2559f
YL		 2572{
2573 disable_timer_pin_1 = 1;
2574 return 0;
2575}
54168ed7 2576early_param("disable_timer_pin_1", disable_timer_pin_setup);
efa2559f
YL		 2577
2578int timer_through_8259 __initdata;
2579
1da177e4
LT		 2580/*
2581 * This code may look a bit paranoid, but it's supposed to cooperate with
2582 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2583 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2584 * fanatically on his truly buggy board.
54168ed7
IM		 2585 *
2586 * FIXME: really need to revamp this for all platforms.
1da177e4 2587 */
8542b200 2588static inline void __init check_timer(void)
1da177e4 2589{
497c9a19 2590 struct irq_cfg *cfg = irq_cfg(0);
fcfd636a 2591 int apic1, pin1, apic2, pin2;
4aae0702 2592 unsigned long flags;
047c8fdb
YL		 2593 unsigned int ver;
2594 int no_pin1 = 0;
4aae0702
IM		 2595
2596 local_irq_save(flags);
d4d25dec 2597
d6c88a50
TG		 2598 ver = apic_read(APIC_LVR);
2599 ver = GET_APIC_VERSION(ver);
6e908947 2600
1da177e4
LT		 2601 /*
2602 * get/set the timer IRQ vector:
2603 */
2604 disable_8259A_irq(0);
497c9a19 2605 assign_irq_vector(0, TARGET_CPUS);
1da177e4
LT		 2606
2607 /*
d11d5794
MR		 2608 * As IRQ0 is to be enabled in the 8259A, the virtual
2609 * wire has to be disabled in the local APIC. Also
2610 * timer interrupts need to be acknowledged manually in
2611 * the 8259A for the i82489DX when using the NMI
2612 * watchdog as that APIC treats NMIs as level-triggered.
2613 * The AEOI mode will finish them in the 8259A
2614 * automatically.
1da177e4 2615 */
593f4a78 2616 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1da177e4 2617 init_8259A(1);
54168ed7 2618#ifdef CONFIG_X86_32
d11d5794 2619 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
54168ed7 2620#endif
1da177e4 2621
fcfd636a
EB		 2622 pin1 = find_isa_irq_pin(0, mp_INT);
2623 apic1 = find_isa_irq_apic(0, mp_INT);
2624 pin2 = ioapic_i8259.pin;
2625 apic2 = ioapic_i8259.apic;
1da177e4 2626
49a66a0b
MR		 2627 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2628 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
497c9a19 2629 cfg->vector, apic1, pin1, apic2, pin2);
1da177e4 2630
691874fa
MR		 2631 /*
2632 * Some BIOS writers are clueless and report the ExtINTA
2633 * I/O APIC input from the cascaded 8259A as the timer
2634 * interrupt input. So just in case, if only one pin
2635 * was found above, try it both directly and through the
2636 * 8259A.
2637 */
2638 if (pin1 == -1) {
54168ed7
IM		 2639#ifdef CONFIG_INTR_REMAP
2640 if (intr_remapping_enabled)
2641 panic("BIOS bug: timer not connected to IO-APIC");
2642#endif
691874fa
MR		 2643 pin1 = pin2;
2644 apic1 = apic2;
2645 no_pin1 = 1;
2646 } else if (pin2 == -1) {
2647 pin2 = pin1;
2648 apic2 = apic1;
2649 }
2650
1da177e4
LT		 2651 if (pin1 != -1) {
2652 /*
2653 * Ok, does IRQ0 through the IOAPIC work?
2654 */
691874fa
MR		 2655 if (no_pin1) {
2656 add_pin_to_irq(0, apic1, pin1);
497c9a19 2657 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
691874fa 2658 }
1da177e4
LT		 2659 unmask_IO_APIC_irq(0);
2660 if (timer_irq_works()) {
2661 if (nmi_watchdog == NMI_IO_APIC) {
1da177e4
LT		 2662 setup_nmi();
2663 enable_8259A_irq(0);
1da177e4 2664 }
66759a01
CE		 2665 if (disable_timer_pin_1 > 0)
2666 clear_IO_APIC_pin(0, pin1);
4aae0702 2667 goto out;
1da177e4 2668 }
54168ed7
IM		 2669#ifdef CONFIG_INTR_REMAP
2670 if (intr_remapping_enabled)
2671 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2672#endif
fcfd636a 2673 clear_IO_APIC_pin(apic1, pin1);
691874fa 2674 if (!no_pin1)
49a66a0b
MR		 2675 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2676 "8254 timer not connected to IO-APIC\n");
1da177e4 2677
49a66a0b
MR		 2678 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2679 "(IRQ0) through the 8259A ...\n");
2680 apic_printk(APIC_QUIET, KERN_INFO
2681 "..... (found apic %d pin %d) ...\n", apic2, pin2);
1da177e4
LT		 2682 /*
2683 * legacy devices should be connected to IO APIC #0
2684 */
691874fa 2685 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
497c9a19 2686 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
24742ece 2687 unmask_IO_APIC_irq(0);
ecd29476 2688 enable_8259A_irq(0);
1da177e4 2689 if (timer_irq_works()) {
49a66a0b 2690 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
35542c5e 2691 timer_through_8259 = 1;
1da177e4 2692 if (nmi_watchdog == NMI_IO_APIC) {
60134ebe 2693 disable_8259A_irq(0);
1da177e4 2694 setup_nmi();
60134ebe 2695 enable_8259A_irq(0);
1da177e4 2696 }
4aae0702 2697 goto out;
1da177e4
LT		 2698 }
2699 /*
2700 * Cleanup, just in case ...
2701 */
ecd29476 2702 disable_8259A_irq(0);
fcfd636a 2703 clear_IO_APIC_pin(apic2, pin2);
49a66a0b 2704 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
1da177e4 2705 }
1da177e4
LT		 2706
2707 if (nmi_watchdog == NMI_IO_APIC) {
49a66a0b
MR		 2708 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2709 "through the IO-APIC - disabling NMI Watchdog!\n");
067fa0ff 2710 nmi_watchdog = NMI_NONE;
1da177e4 2711 }
54168ed7 2712#ifdef CONFIG_X86_32
d11d5794 2713 timer_ack = 0;
54168ed7 2714#endif
1da177e4 2715
49a66a0b
MR		 2716 apic_printk(APIC_QUIET, KERN_INFO
2717 "...trying to set up timer as Virtual Wire IRQ...\n");
1da177e4 2718
497c9a19
YL		 2719 lapic_register_intr(0);
2720 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
1da177e4
LT		 2721 enable_8259A_irq(0);
2722
2723 if (timer_irq_works()) {
49a66a0b 2724 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
4aae0702 2725 goto out;
1da177e4 2726 }
e67465f1 2727 disable_8259A_irq(0);
497c9a19 2728 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
49a66a0b 2729 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
1da177e4 2730
49a66a0b
MR		 2731 apic_printk(APIC_QUIET, KERN_INFO
2732 "...trying to set up timer as ExtINT IRQ...\n");
1da177e4 2733
1da177e4
LT		 2734 init_8259A(0);
2735 make_8259A_irq(0);
593f4a78 2736 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1da177e4
LT		 2737
2738 unlock_ExtINT_logic();
2739
2740 if (timer_irq_works()) {
49a66a0b 2741 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
4aae0702 2742 goto out;
1da177e4 2743 }
49a66a0b 2744 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
1da177e4 2745 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
49a66a0b 2746 "report. Then try booting with the 'noapic' option.\n");
4aae0702
IM		 2747out:
2748 local_irq_restore(flags);
1da177e4
LT		 2749}
2750
2751/*
af174783
MR		 2752 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2753 * to devices. However there may be an I/O APIC pin available for
2754 * this interrupt regardless. The pin may be left unconnected, but
2755 * typically it will be reused as an ExtINT cascade interrupt for
2756 * the master 8259A. In the MPS case such a pin will normally be
2757 * reported as an ExtINT interrupt in the MP table. With ACPI
2758 * there is no provision for ExtINT interrupts, and in the absence
2759 * of an override it would be treated as an ordinary ISA I/O APIC
2760 * interrupt, that is edge-triggered and unmasked by default. We
2761 * used to do this, but it caused problems on some systems because
2762 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2763 * the same ExtINT cascade interrupt to drive the local APIC of the
2764 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2765 * the I/O APIC in all cases now. No actual device should request
2766 * it anyway. --macro
1da177e4
LT		 2767 */
2768#define PIC_IRQS (1 << PIC_CASCADE_IR)
2769
2770void __init setup_IO_APIC(void)
2771{
54168ed7
IM		 2772
2773#ifdef CONFIG_X86_32
1da177e4 2774 enable_IO_APIC();
54168ed7
IM		 2775#else
2776 /*
2777 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2778 */
2779#endif
1da177e4 2780
af174783 2781 io_apic_irqs = ~PIC_IRQS;
1da177e4 2782
54168ed7 2783 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
d6c88a50 2784 /*
54168ed7
IM		 2785 * Set up IO-APIC IRQ routing.
2786 */
2787#ifdef CONFIG_X86_32
d6c88a50
TG		 2788 if (!acpi_ioapic)
2789 setup_ioapic_ids_from_mpc();
54168ed7 2790#endif
1da177e4
LT		 2791 sync_Arb_IDs();
2792 setup_IO_APIC_irqs();
2793 init_IO_APIC_traps();
1e4c85f9 2794 check_timer();
1da177e4
LT		 2795}
2796
2797/*
54168ed7
IM		 2798 * Called after all the initialization is done. If we didnt find any
2799 * APIC bugs then we can allow the modify fast path
1da177e4 2800 */
36062448 2801
1da177e4
LT		 2802static int __init io_apic_bug_finalize(void)
2803{
d6c88a50
TG		 2804 if (sis_apic_bug == -1)
2805 sis_apic_bug = 0;
2806 return 0;
1da177e4
LT		 2807}
2808
2809late_initcall(io_apic_bug_finalize);
2810
2811struct sysfs_ioapic_data {
2812 struct sys_device dev;
2813 struct IO_APIC_route_entry entry[0];
2814};
54168ed7 2815static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1da177e4 2816
438510f6 2817static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1da177e4
LT		 2818{
2819 struct IO_APIC_route_entry *entry;
2820 struct sysfs_ioapic_data *data;
1da177e4 2821 int i;
36062448 2822
1da177e4
LT		 2823 data = container_of(dev, struct sysfs_ioapic_data, dev);
2824 entry = data->entry;
54168ed7
IM		 2825 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
2826 *entry = ioapic_read_entry(dev->id, i);
1da177e4
LT		 2827
2828 return 0;
2829}
2830
2831static int ioapic_resume(struct sys_device *dev)
2832{
2833 struct IO_APIC_route_entry *entry;
2834 struct sysfs_ioapic_data *data;
2835 unsigned long flags;
2836 union IO_APIC_reg_00 reg_00;
2837 int i;
36062448 2838
1da177e4
LT		 2839 data = container_of(dev, struct sysfs_ioapic_data, dev);
2840 entry = data->entry;
2841
2842 spin_lock_irqsave(&ioapic_lock, flags);
2843 reg_00.raw = io_apic_read(dev->id, 0);
ec2cd0a2
AS		 2844 if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) {
2845 reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid;
1da177e4
LT		 2846 io_apic_write(dev->id, 0, reg_00.raw);
2847 }
1da177e4 2848 spin_unlock_irqrestore(&ioapic_lock, flags);
36062448 2849 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
cf4c6a2f 2850 ioapic_write_entry(dev->id, i, entry[i]);
1da177e4
LT		 2851
2852 return 0;
2853}
2854
2855static struct sysdev_class ioapic_sysdev_class = {
af5ca3f4 2856 .name = "ioapic",
1da177e4
LT		 2857 .suspend = ioapic_suspend,
2858 .resume = ioapic_resume,
2859};
2860
2861static int __init ioapic_init_sysfs(void)
2862{
54168ed7
IM		 2863 struct sys_device * dev;
2864 int i, size, error;
1da177e4
LT		 2865
2866 error = sysdev_class_register(&ioapic_sysdev_class);
2867 if (error)
2868 return error;
2869
54168ed7 2870 for (i = 0; i < nr_ioapics; i++ ) {
36062448 2871 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1da177e4 2872 * sizeof(struct IO_APIC_route_entry);
25556c16 2873 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
1da177e4
LT		 2874 if (!mp_ioapic_data[i]) {
2875 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2876 continue;
2877 }
1da177e4 2878 dev = &mp_ioapic_data[i]->dev;
36062448 2879 dev->id = i;
1da177e4
LT		 2880 dev->cls = &ioapic_sysdev_class;
2881 error = sysdev_register(dev);
2882 if (error) {
2883 kfree(mp_ioapic_data[i]);
2884 mp_ioapic_data[i] = NULL;
2885 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2886 continue;
2887 }
2888 }
2889
2890 return 0;
2891}
2892
2893device_initcall(ioapic_init_sysfs);
2894
3fc471ed 2895/*
95d77884 2896 * Dynamic irq allocate and deallocation
3fc471ed 2897 */
199751d7 2898unsigned int create_irq_nr(unsigned int irq_want)
3fc471ed 2899{
ace80ab7 2900 /* Allocate an unused irq */
54168ed7
IM		 2901 unsigned int irq;
2902 unsigned int new;
3fc471ed 2903 unsigned long flags;
da51a821 2904 struct irq_cfg *cfg_new;
3fc471ed 2905
199751d7
YL		 2906 irq_want = nr_irqs - 1;
2907
2908 irq = 0;
ace80ab7 2909 spin_lock_irqsave(&vector_lock, flags);
54168ed7 2910 for (new = irq_want; new > 0; new--) {
ace80ab7
EB		 2911 if (platform_legacy_irq(new))
2912 continue;
da51a821
YL		 2913 cfg_new = irq_cfg(new);
2914 if (cfg_new && cfg_new->vector != 0)
ace80ab7 2915 continue;
047c8fdb 2916 /* check if need to create one */
da51a821
YL		 2917 if (!cfg_new)
2918 cfg_new = irq_cfg_alloc(new);
497c9a19 2919 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
ace80ab7
EB		 2920 irq = new;
2921 break;
2922 }
2923 spin_unlock_irqrestore(&vector_lock, flags);
3fc471ed 2924
199751d7 2925 if (irq > 0) {
3fc471ed
EB		 2926 dynamic_irq_init(irq);
2927 }
2928 return irq;
2929}
2930
199751d7
YL		 2931int create_irq(void)
2932{
54168ed7
IM		 2933 int irq;
2934
2935 irq = create_irq_nr(nr_irqs - 1);
2936
2937 if (irq == 0)
2938 irq = -1;
2939
2940 return irq;
199751d7
YL		 2941}
2942
3fc471ed
EB		 2943void destroy_irq(unsigned int irq)
2944{
2945 unsigned long flags;
3fc471ed
EB		 2946
2947 dynamic_irq_cleanup(irq);
2948
54168ed7
IM		 2949#ifdef CONFIG_INTR_REMAP
2950 free_irte(irq);
2951#endif
3fc471ed 2952 spin_lock_irqsave(&vector_lock, flags);
497c9a19 2953 __clear_irq_vector(irq);
3fc471ed
EB		 2954 spin_unlock_irqrestore(&vector_lock, flags);
2955}
3fc471ed 2956
2d3fcc1c 2957/*
27b46d76 2958 * MSI message composition
2d3fcc1c
EB		 2959 */
2960#ifdef CONFIG_PCI_MSI
3b7d1921 2961static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2d3fcc1c 2962{
497c9a19
YL		 2963 struct irq_cfg *cfg;
2964 int err;
2d3fcc1c 2965 unsigned dest;
497c9a19 2966 cpumask_t tmp;
2d3fcc1c 2967
497c9a19
YL		 2968 tmp = TARGET_CPUS;
2969 err = assign_irq_vector(irq, tmp);
2970 if (err)
2971 return err;
2d3fcc1c 2972
497c9a19
YL		 2973 cfg = irq_cfg(irq);
2974 cpus_and(tmp, cfg->domain, tmp);
2975 dest = cpu_mask_to_apicid(tmp);
2976
54168ed7
IM		 2977#ifdef CONFIG_INTR_REMAP
2978 if (irq_remapped(irq)) {
2979 struct irte irte;
2980 int ir_index;
2981 u16 sub_handle;
2982
2983 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
2984 BUG_ON(ir_index == -1);
2985
2986 memset (&irte, 0, sizeof(irte));
2987
2988 irte.present = 1;
2989 irte.dst_mode = INT_DEST_MODE;
2990 irte.trigger_mode = 0; /* edge */
2991 irte.dlvry_mode = INT_DELIVERY_MODE;
2992 irte.vector = cfg->vector;
2993 irte.dest_id = IRTE_DEST(dest);
2994
2995 modify_irte(irq, &irte);
2996
2997 msg->address_hi = MSI_ADDR_BASE_HI;
2998 msg->data = sub_handle;
2999 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3000 MSI_ADDR_IR_SHV |
3001 MSI_ADDR_IR_INDEX1(ir_index) |
3002 MSI_ADDR_IR_INDEX2(ir_index);
3003 } else
3004#endif
3005 {
3006 msg->address_hi = MSI_ADDR_BASE_HI;
3007 msg->address_lo =
3008 MSI_ADDR_BASE_LO |
3009 ((INT_DEST_MODE == 0) ?
3010 MSI_ADDR_DEST_MODE_PHYSICAL:
3011 MSI_ADDR_DEST_MODE_LOGICAL) |
3012 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3013 MSI_ADDR_REDIRECTION_CPU:
3014 MSI_ADDR_REDIRECTION_LOWPRI) |
3015 MSI_ADDR_DEST_ID(dest);
497c9a19 3016
54168ed7
IM		 3017 msg->data =
3018 MSI_DATA_TRIGGER_EDGE |
3019 MSI_DATA_LEVEL_ASSERT |
3020 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3021 MSI_DATA_DELIVERY_FIXED:
3022 MSI_DATA_DELIVERY_LOWPRI) |
3023 MSI_DATA_VECTOR(cfg->vector);
3024 }
497c9a19 3025 return err;
2d3fcc1c
EB		 3026}
3027
3b7d1921
EB		 3028#ifdef CONFIG_SMP
3029static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2d3fcc1c 3030{
497c9a19 3031 struct irq_cfg *cfg;
3b7d1921
EB		 3032 struct msi_msg msg;
3033 unsigned int dest;
3034 cpumask_t tmp;
54168ed7 3035 struct irq_desc *desc;
3b7d1921
EB		 3036
3037 cpus_and(tmp, mask, cpu_online_map);
3038 if (cpus_empty(tmp))
497c9a19 3039 return;
2d3fcc1c 3040
497c9a19 3041 if (assign_irq_vector(irq, mask))
3b7d1921 3042 return;
2d3fcc1c 3043
497c9a19
YL		 3044 cfg = irq_cfg(irq);
3045 cpus_and(tmp, cfg->domain, mask);
3046 dest = cpu_mask_to_apicid(tmp);
3b7d1921
EB		 3047
3048 read_msi_msg(irq, &msg);
3049
3050 msg.data &= ~MSI_DATA_VECTOR_MASK;
497c9a19 3051 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3b7d1921
EB		 3052 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3053 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3054
3055 write_msi_msg(irq, &msg);
54168ed7
IM		 3056 desc = irq_to_desc(irq);
3057 desc->affinity = mask;
2d3fcc1c 3058}
54168ed7
IM		 3059
3060#ifdef CONFIG_INTR_REMAP
3061/*
3062 * Migrate the MSI irq to another cpumask. This migration is
3063 * done in the process context using interrupt-remapping hardware.
3064 */
3065static void ir_set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
3066{
3067 struct irq_cfg *cfg;
3068 unsigned int dest;
3069 cpumask_t tmp, cleanup_mask;
3070 struct irte irte;
3071 struct irq_desc *desc;
3072
3073 cpus_and(tmp, mask, cpu_online_map);
3074 if (cpus_empty(tmp))
3075 return;
3076
3077 if (get_irte(irq, &irte))
3078 return;
3079
3080 if (assign_irq_vector(irq, mask))
3081 return;
3082
3083 cfg = irq_cfg(irq);
3084 cpus_and(tmp, cfg->domain, mask);
3085 dest = cpu_mask_to_apicid(tmp);
3086
3087 irte.vector = cfg->vector;
3088 irte.dest_id = IRTE_DEST(dest);
3089
3090 /*
3091 * atomically update the IRTE with the new destination and vector.
3092 */
3093 modify_irte(irq, &irte);
3094
3095 /*
3096 * After this point, all the interrupts will start arriving
3097 * at the new destination. So, time to cleanup the previous
3098 * vector allocation.
3099 */
3100 if (cfg->move_in_progress) {
3101 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
3102 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
3103 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
3104 cfg->move_in_progress = 0;
3105 }
3106
3107 desc = irq_to_desc(irq);
3108 desc->affinity = mask;
3109}
3110#endif
3b7d1921 3111#endif /* CONFIG_SMP */
2d3fcc1c 3112
3b7d1921
EB		 3113/*
3114 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3115 * which implement the MSI or MSI-X Capability Structure.
3116 */
3117static struct irq_chip msi_chip = {
3118 .name = "PCI-MSI",
3119 .unmask = unmask_msi_irq,
3120 .mask = mask_msi_irq,
1d025192 3121 .ack = ack_apic_edge,
3b7d1921
EB		 3122#ifdef CONFIG_SMP
3123 .set_affinity = set_msi_irq_affinity,
3124#endif
3125 .retrigger = ioapic_retrigger_irq,
2d3fcc1c
EB		 3126};
3127
54168ed7
IM		 3128#ifdef CONFIG_INTR_REMAP
3129static struct irq_chip msi_ir_chip = {
3130 .name = "IR-PCI-MSI",
3131 .unmask = unmask_msi_irq,
3132 .mask = mask_msi_irq,
3133 .ack = ack_x2apic_edge,
3134#ifdef CONFIG_SMP
3135 .set_affinity = ir_set_msi_irq_affinity,
3136#endif
3137 .retrigger = ioapic_retrigger_irq,
3138};
3139
3140/*
3141 * Map the PCI dev to the corresponding remapping hardware unit
3142 * and allocate 'nvec' consecutive interrupt-remapping table entries
3143 * in it.
3144 */
3145static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3146{
3147 struct intel_iommu *iommu;
3148 int index;
3149
3150 iommu = map_dev_to_ir(dev);
3151 if (!iommu) {
3152 printk(KERN_ERR
3153 "Unable to map PCI %s to iommu\n", pci_name(dev));
3154 return -ENOENT;
3155 }
3156
3157 index = alloc_irte(iommu, irq, nvec);
3158 if (index < 0) {
3159 printk(KERN_ERR
3160 "Unable to allocate %d IRTE for PCI %s\n", nvec,
d6c88a50 3161 pci_name(dev));
54168ed7
IM		 3162 return -ENOSPC;
3163 }
3164 return index;
3165}
3166#endif
1d025192
YL		 3167
3168static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc, int irq)
3169{
3170 int ret;
3171 struct msi_msg msg;
3172
3173 ret = msi_compose_msg(dev, irq, &msg);
3174 if (ret < 0)
3175 return ret;
3176
3177 set_irq_msi(irq, desc);
3178 write_msi_msg(irq, &msg);
3179
54168ed7
IM		 3180#ifdef CONFIG_INTR_REMAP
3181 if (irq_remapped(irq)) {
3182 struct irq_desc *desc = irq_to_desc(irq);
3183 /*
3184 * irq migration in process context
3185 */
3186 desc->status |= IRQ_MOVE_PCNTXT;
3187 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3188 } else
3189#endif
3190 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
1d025192 3191
c81bba49
YL		 3192 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3193
1d025192
YL		 3194 return 0;
3195}
3196
199751d7
YL		 3197static unsigned int build_irq_for_pci_dev(struct pci_dev *dev)
3198{
3199 unsigned int irq;
3200
3201 irq = dev->bus->number;
3202 irq <<= 8;
3203 irq |= dev->devfn;
3204 irq <<= 12;
3205
3206 return irq;
3207}
3208
f7feaca7 3209int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
3b7d1921 3210{
54168ed7
IM		 3211 unsigned int irq;
3212 int ret;
199751d7
YL		 3213 unsigned int irq_want;
3214
3215 irq_want = build_irq_for_pci_dev(dev) + 0x100;
3216
3217 irq = create_irq_nr(irq_want);
199751d7
YL		 3218 if (irq == 0)
3219 return -1;
f7feaca7 3220
54168ed7
IM		 3221#ifdef CONFIG_INTR_REMAP
3222 if (!intr_remapping_enabled)
3223 goto no_ir;
3224
3225 ret = msi_alloc_irte(dev, irq, 1);
3226 if (ret < 0)
3227 goto error;
3228no_ir:
3229#endif
1d025192 3230 ret = setup_msi_irq(dev, desc, irq);
f7feaca7
EB		 3231 if (ret < 0) {
3232 destroy_irq(irq);
3b7d1921 3233 return ret;
54168ed7 3234 }
7fe3730d 3235 return 0;
54168ed7
IM		 3236
3237#ifdef CONFIG_INTR_REMAP
3238error:
3239 destroy_irq(irq);
3240 return ret;
3241#endif
3b7d1921
EB		 3242}
3243
047c8fdb
YL		 3244int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3245{
54168ed7
IM		 3246 unsigned int irq;
3247 int ret, sub_handle;
3248 struct msi_desc *desc;
3249 unsigned int irq_want;
3250
3251#ifdef CONFIG_INTR_REMAP
3252 struct intel_iommu *iommu = 0;
3253 int index = 0;
3254#endif
3255
3256 irq_want = build_irq_for_pci_dev(dev) + 0x100;
3257 sub_handle = 0;
3258 list_for_each_entry(desc, &dev->msi_list, list) {
3259 irq = create_irq_nr(irq_want--);
3260 if (irq == 0)
3261 return -1;
3262#ifdef CONFIG_INTR_REMAP
3263 if (!intr_remapping_enabled)
3264 goto no_ir;
3265
3266 if (!sub_handle) {
3267 /*
3268 * allocate the consecutive block of IRTE's
3269 * for 'nvec'
3270 */
3271 index = msi_alloc_irte(dev, irq, nvec);
3272 if (index < 0) {
3273 ret = index;
3274 goto error;
3275 }
3276 } else {
3277 iommu = map_dev_to_ir(dev);
3278 if (!iommu) {
3279 ret = -ENOENT;
3280 goto error;
3281 }
3282 /*
3283 * setup the mapping between the irq and the IRTE
3284 * base index, the sub_handle pointing to the
3285 * appropriate interrupt remap table entry.
3286 */
3287 set_irte_irq(irq, iommu, index, sub_handle);
3288 }
3289no_ir:
3290#endif
3291 ret = setup_msi_irq(dev, desc, irq);
3292 if (ret < 0)
3293 goto error;
3294 sub_handle++;
3295 }
3296 return 0;
047c8fdb
YL		 3297
3298error:
54168ed7
IM		 3299 destroy_irq(irq);
3300 return ret;
047c8fdb
YL		 3301}
3302
3b7d1921
EB		 3303void arch_teardown_msi_irq(unsigned int irq)
3304{
f7feaca7 3305 destroy_irq(irq);
3b7d1921
EB		 3306}
3307
54168ed7
IM		 3308#ifdef CONFIG_DMAR
3309#ifdef CONFIG_SMP
3310static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask)
3311{
3312 struct irq_cfg *cfg;
3313 struct msi_msg msg;
3314 unsigned int dest;
3315 cpumask_t tmp;
3316 struct irq_desc *desc;
3317
3318 cpus_and(tmp, mask, cpu_online_map);
3319 if (cpus_empty(tmp))
3320 return;
3321
3322 if (assign_irq_vector(irq, mask))
3323 return;
3324
3325 cfg = irq_cfg(irq);
3326 cpus_and(tmp, cfg->domain, mask);
3327 dest = cpu_mask_to_apicid(tmp);
3328
3329 dmar_msi_read(irq, &msg);
3330
3331 msg.data &= ~MSI_DATA_VECTOR_MASK;
3332 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3333 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3334 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3335
3336 dmar_msi_write(irq, &msg);
3337 desc = irq_to_desc(irq);
3338 desc->affinity = mask;
3339}
3340#endif /* CONFIG_SMP */
3341
3342struct irq_chip dmar_msi_type = {
3343 .name = "DMAR_MSI",
3344 .unmask = dmar_msi_unmask,
3345 .mask = dmar_msi_mask,
3346 .ack = ack_apic_edge,
3347#ifdef CONFIG_SMP
3348 .set_affinity = dmar_msi_set_affinity,
3349#endif
3350 .retrigger = ioapic_retrigger_irq,
3351};
3352
3353int arch_setup_dmar_msi(unsigned int irq)
3354{
3355 int ret;
3356 struct msi_msg msg;
2d3fcc1c 3357
54168ed7
IM		 3358 ret = msi_compose_msg(NULL, irq, &msg);
3359 if (ret < 0)
3360 return ret;
3361 dmar_msi_write(irq, &msg);
3362 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3363 "edge");
3364 return 0;
3365}
3366#endif
3367
58ac1e76 3368#ifdef CONFIG_HPET_TIMER
3369
3370#ifdef CONFIG_SMP
3371static void hpet_msi_set_affinity(unsigned int irq, cpumask_t mask)
3372{
3373 struct irq_cfg *cfg;
3374 struct irq_desc *desc;
3375 struct msi_msg msg;
3376 unsigned int dest;
3377 cpumask_t tmp;
3378
3379 cpus_and(tmp, mask, cpu_online_map);
3380 if (cpus_empty(tmp))
3381 return;
3382
3383 if (assign_irq_vector(irq, mask))
3384 return;
3385
3386 cfg = irq_cfg(irq);
3387 cpus_and(tmp, cfg->domain, mask);
3388 dest = cpu_mask_to_apicid(tmp);
3389
3390 hpet_msi_read(irq, &msg);
3391
3392 msg.data &= ~MSI_DATA_VECTOR_MASK;
3393 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3394 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3395 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3396
3397 hpet_msi_write(irq, &msg);
3398 desc = irq_to_desc(irq);
3399 desc->affinity = mask;
3400}
3401#endif /* CONFIG_SMP */
3402
3403struct irq_chip hpet_msi_type = {
3404 .name = "HPET_MSI",
3405 .unmask = hpet_msi_unmask,
3406 .mask = hpet_msi_mask,
3407 .ack = ack_apic_edge,
3408#ifdef CONFIG_SMP
3409 .set_affinity = hpet_msi_set_affinity,
3410#endif
3411 .retrigger = ioapic_retrigger_irq,
3412};
3413
3414int arch_setup_hpet_msi(unsigned int irq)
3415{
3416 int ret;
3417 struct msi_msg msg;
3418
3419 ret = msi_compose_msg(NULL, irq, &msg);
3420 if (ret < 0)
3421 return ret;
3422
3423 hpet_msi_write(irq, &msg);
3424 set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq,
3425 "edge");
c81bba49 3426
58ac1e76 3427 return 0;
3428}
3429#endif
3430
54168ed7 3431#endif /* CONFIG_PCI_MSI */
8b955b0d
EB		 3432/*
3433 * Hypertransport interrupt support
3434 */
3435#ifdef CONFIG_HT_IRQ
3436
3437#ifdef CONFIG_SMP
3438
497c9a19 3439static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
8b955b0d 3440{
ec68307c
EB		 3441 struct ht_irq_msg msg;
3442 fetch_ht_irq_msg(irq, &msg);
8b955b0d 3443
497c9a19 3444 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
ec68307c 3445 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
8b955b0d 3446
497c9a19 3447 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
ec68307c 3448 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
8b955b0d 3449
ec68307c 3450 write_ht_irq_msg(irq, &msg);
8b955b0d
EB		 3451}
3452
3453static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
3454{
497c9a19 3455 struct irq_cfg *cfg;
8b955b0d
EB		 3456 unsigned int dest;
3457 cpumask_t tmp;
54168ed7 3458 struct irq_desc *desc;
8b955b0d
EB		 3459
3460 cpus_and(tmp, mask, cpu_online_map);
3461 if (cpus_empty(tmp))
497c9a19 3462 return;
8b955b0d 3463
497c9a19
YL		 3464 if (assign_irq_vector(irq, mask))
3465 return;
8b955b0d 3466
497c9a19
YL		 3467 cfg = irq_cfg(irq);
3468 cpus_and(tmp, cfg->domain, mask);
3469 dest = cpu_mask_to_apicid(tmp);
8b955b0d 3470
497c9a19 3471 target_ht_irq(irq, dest, cfg->vector);
54168ed7
IM		 3472 desc = irq_to_desc(irq);
3473 desc->affinity = mask;
8b955b0d
EB		 3474}
3475#endif
3476
c37e108d 3477static struct irq_chip ht_irq_chip = {
8b955b0d
EB		 3478 .name = "PCI-HT",
3479 .mask = mask_ht_irq,
3480 .unmask = unmask_ht_irq,
1d025192 3481 .ack = ack_apic_edge,
8b955b0d
EB		 3482#ifdef CONFIG_SMP
3483 .set_affinity = set_ht_irq_affinity,
3484#endif
3485 .retrigger = ioapic_retrigger_irq,
3486};
3487
3488int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3489{
497c9a19
YL		 3490 struct irq_cfg *cfg;
3491 int err;
3492 cpumask_t tmp;
8b955b0d 3493
497c9a19
YL		 3494 tmp = TARGET_CPUS;
3495 err = assign_irq_vector(irq, tmp);
54168ed7 3496 if (!err) {
ec68307c 3497 struct ht_irq_msg msg;
8b955b0d 3498 unsigned dest;
8b955b0d 3499
497c9a19
YL		 3500 cfg = irq_cfg(irq);
3501 cpus_and(tmp, cfg->domain, tmp);
8b955b0d
EB		 3502 dest = cpu_mask_to_apicid(tmp);
3503
ec68307c 3504 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
8b955b0d 3505
ec68307c
EB		 3506 msg.address_lo =
3507 HT_IRQ_LOW_BASE |
8b955b0d 3508 HT_IRQ_LOW_DEST_ID(dest) |
497c9a19 3509 HT_IRQ_LOW_VECTOR(cfg->vector) |
8b955b0d
EB		 3510 ((INT_DEST_MODE == 0) ?
3511 HT_IRQ_LOW_DM_PHYSICAL :
3512 HT_IRQ_LOW_DM_LOGICAL) |
3513 HT_IRQ_LOW_RQEOI_EDGE |
3514 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3515 HT_IRQ_LOW_MT_FIXED :
3516 HT_IRQ_LOW_MT_ARBITRATED) |
3517 HT_IRQ_LOW_IRQ_MASKED;
3518
ec68307c 3519 write_ht_irq_msg(irq, &msg);
8b955b0d 3520
a460e745
IM		 3521 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3522 handle_edge_irq, "edge");
c81bba49
YL		 3523
3524 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
8b955b0d 3525 }
497c9a19 3526 return err;
8b955b0d
EB		 3527}
3528#endif /* CONFIG_HT_IRQ */
3529
4173a0e7
DN		 3530#ifdef CONFIG_X86_64
3531/*
3532 * Re-target the irq to the specified CPU and enable the specified MMR located
3533 * on the specified blade to allow the sending of MSIs to the specified CPU.
3534 */
3535int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
3536 unsigned long mmr_offset)
3537{
3538 const cpumask_t *eligible_cpu = get_cpu_mask(cpu);
3539 struct irq_cfg *cfg;
3540 int mmr_pnode;
3541 unsigned long mmr_value;
3542 struct uv_IO_APIC_route_entry *entry;
3543 unsigned long flags;
3544 int err;
3545
3546 err = assign_irq_vector(irq, *eligible_cpu);
3547 if (err != 0)
3548 return err;
3549
3550 spin_lock_irqsave(&vector_lock, flags);
3551 set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq,
3552 irq_name);
3553 spin_unlock_irqrestore(&vector_lock, flags);
3554
3555 cfg = irq_cfg(irq);
3556
3557 mmr_value = 0;
3558 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3559 BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3560
3561 entry->vector = cfg->vector;
3562 entry->delivery_mode = INT_DELIVERY_MODE;
3563 entry->dest_mode = INT_DEST_MODE;
3564 entry->polarity = 0;
3565 entry->trigger = 0;
3566 entry->mask = 0;
3567 entry->dest = cpu_mask_to_apicid(*eligible_cpu);
3568
3569 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3570 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3571
3572 return irq;
3573}
3574
3575/*
3576 * Disable the specified MMR located on the specified blade so that MSIs are
3577 * longer allowed to be sent.
3578 */
3579void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset)
3580{
3581 unsigned long mmr_value;
3582 struct uv_IO_APIC_route_entry *entry;
3583 int mmr_pnode;
3584
3585 mmr_value = 0;
3586 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3587 BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3588
3589 entry->mask = 1;
3590
3591 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3592 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3593}
3594#endif /* CONFIG_X86_64 */
3595
9d6a4d08
YL		 3596int __init io_apic_get_redir_entries (int ioapic)
3597{
3598 union IO_APIC_reg_01 reg_01;
3599 unsigned long flags;
3600
3601 spin_lock_irqsave(&ioapic_lock, flags);
3602 reg_01.raw = io_apic_read(ioapic, 1);
3603 spin_unlock_irqrestore(&ioapic_lock, flags);
3604
3605 return reg_01.bits.entries;
3606}
3607
3608int __init probe_nr_irqs(void)
3609{
a1967d64 3610 return NR_IRQS;
9d6a4d08
YL		 3611}
3612
1da177e4 3613/* --------------------------------------------------------------------------
54168ed7 3614 ACPI-based IOAPIC Configuration
1da177e4
LT		 3615 -------------------------------------------------------------------------- */
3616
888ba6c6 3617#ifdef CONFIG_ACPI
1da177e4 3618
54168ed7 3619#ifdef CONFIG_X86_32
36062448 3620int __init io_apic_get_unique_id(int ioapic, int apic_id)
1da177e4
LT		 3621{
3622 union IO_APIC_reg_00 reg_00;
3623 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3624 physid_mask_t tmp;
3625 unsigned long flags;
3626 int i = 0;
3627
3628 /*
36062448
PC		 3629 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3630 * buses (one for LAPICs, one for IOAPICs), where predecessors only
1da177e4 3631 * supports up to 16 on one shared APIC bus.
36062448 3632 *
1da177e4
LT		 3633 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3634 * advantage of new APIC bus architecture.
3635 */
3636
3637 if (physids_empty(apic_id_map))
3638 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
3639
3640 spin_lock_irqsave(&ioapic_lock, flags);
3641 reg_00.raw = io_apic_read(ioapic, 0);
3642 spin_unlock_irqrestore(&ioapic_lock, flags);
3643
3644 if (apic_id >= get_physical_broadcast()) {
3645 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3646 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3647 apic_id = reg_00.bits.ID;
3648 }
3649
3650 /*
36062448 3651 * Every APIC in a system must have a unique ID or we get lots of nice
1da177e4
LT		 3652 * 'stuck on smp_invalidate_needed IPI wait' messages.
3653 */
3654 if (check_apicid_used(apic_id_map, apic_id)) {
3655
3656 for (i = 0; i < get_physical_broadcast(); i++) {
3657 if (!check_apicid_used(apic_id_map, i))
3658 break;
3659 }
3660
3661 if (i == get_physical_broadcast())
3662 panic("Max apic_id exceeded!\n");
3663
3664 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3665 "trying %d\n", ioapic, apic_id, i);
3666
3667 apic_id = i;
36062448 3668 }
1da177e4
LT		 3669
3670 tmp = apicid_to_cpu_present(apic_id);
3671 physids_or(apic_id_map, apic_id_map, tmp);
3672
3673 if (reg_00.bits.ID != apic_id) {
3674 reg_00.bits.ID = apic_id;
3675
3676 spin_lock_irqsave(&ioapic_lock, flags);
3677 io_apic_write(ioapic, 0, reg_00.raw);
3678 reg_00.raw = io_apic_read(ioapic, 0);
3679 spin_unlock_irqrestore(&ioapic_lock, flags);
3680
3681 /* Sanity check */
6070f9ec
AD		 3682 if (reg_00.bits.ID != apic_id) {
3683 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3684 return -1;
3685 }
1da177e4
LT		 3686 }
3687
3688 apic_printk(APIC_VERBOSE, KERN_INFO
3689 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3690
3691 return apic_id;
3692}
3693
36062448 3694int __init io_apic_get_version(int ioapic)
1da177e4
LT		 3695{
3696 union IO_APIC_reg_01 reg_01;
3697 unsigned long flags;
3698
3699 spin_lock_irqsave(&ioapic_lock, flags);
3700 reg_01.raw = io_apic_read(ioapic, 1);
3701 spin_unlock_irqrestore(&ioapic_lock, flags);
3702
3703 return reg_01.bits.version;
3704}
54168ed7 3705#endif
1da177e4 3706
54168ed7 3707int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
1da177e4 3708{
1da177e4 3709 if (!IO_APIC_IRQ(irq)) {
54168ed7 3710 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
1da177e4
LT		 3711 ioapic);
3712 return -EINVAL;
3713 }
3714
1da177e4
LT		 3715 /*
3716 * IRQs < 16 are already in the irq_2_pin[] map
3717 */
3718 if (irq >= 16)
3719 add_pin_to_irq(irq, ioapic, pin);
3720
497c9a19 3721 setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
1da177e4
LT		 3722
3723 return 0;
3724}
3725
54168ed7 3726
61fd47e0
SL		 3727int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
3728{
3729 int i;
3730
3731 if (skip_ioapic_setup)
3732 return -1;
3733
3734 for (i = 0; i < mp_irq_entries; i++)
2fddb6e2
AS		 3735 if (mp_irqs[i].mp_irqtype == mp_INT &&
3736 mp_irqs[i].mp_srcbusirq == bus_irq)
61fd47e0
SL		 3737 break;
3738 if (i >= mp_irq_entries)
3739 return -1;
3740
3741 *trigger = irq_trigger(i);
3742 *polarity = irq_polarity(i);
3743 return 0;
3744}
3745
888ba6c6 3746#endif /* CONFIG_ACPI */
1a3f239d 3747
497c9a19
YL		 3748/*
3749 * This function currently is only a helper for the i386 smp boot process where
3750 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3751 * so mask in all cases should simply be TARGET_CPUS
3752 */
3753#ifdef CONFIG_SMP
3754void __init setup_ioapic_dest(void)
3755{
3756 int pin, ioapic, irq, irq_entry;
6c2e9403 3757 struct irq_desc *desc;
497c9a19 3758 struct irq_cfg *cfg;
6c2e9403 3759 cpumask_t mask;
497c9a19
YL		 3760
3761 if (skip_ioapic_setup == 1)
3762 return;
3763
3764 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
3765 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
3766 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
3767 if (irq_entry == -1)
3768 continue;
3769 irq = pin_2_irq(irq_entry, ioapic, pin);
3770
3771 /* setup_IO_APIC_irqs could fail to get vector for some device
3772 * when you have too many devices, because at that time only boot
3773 * cpu is online.
3774 */
3775 cfg = irq_cfg(irq);
6c2e9403 3776 if (!cfg->vector) {
497c9a19
YL		 3777 setup_IO_APIC_irq(ioapic, pin, irq,
3778 irq_trigger(irq_entry),
3779 irq_polarity(irq_entry));
6c2e9403
TG		 3780 continue;
3781
3782 }
3783
3784 /*
3785 * Honour affinities which have been set in early boot
3786 */
3787 desc = irq_to_desc(irq);
3788 if (desc->status &
3789 (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
3790 mask = desc->affinity;
3791 else
3792 mask = TARGET_CPUS;
3793
54168ed7 3794#ifdef CONFIG_INTR_REMAP
6c2e9403
TG		 3795 if (intr_remapping_enabled)
3796 set_ir_ioapic_affinity_irq(irq, mask);
54168ed7 3797 else
6c2e9403
TG		 3798#endif
3799 set_ioapic_affinity_irq(irq, mask);
497c9a19
YL		 3800 }
3801
3802 }
3803}
3804#endif
3805
54168ed7
IM		 3806#define IOAPIC_RESOURCE_NAME_SIZE 11
3807
3808static struct resource *ioapic_resources;
3809
3810static struct resource * __init ioapic_setup_resources(void)
3811{
3812 unsigned long n;
3813 struct resource *res;
3814 char *mem;
3815 int i;
3816
3817 if (nr_ioapics <= 0)
3818 return NULL;
3819
3820 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
3821 n *= nr_ioapics;
3822
3823 mem = alloc_bootmem(n);
3824 res = (void *)mem;
3825
3826 if (mem != NULL) {
3827 mem += sizeof(struct resource) * nr_ioapics;
3828
3829 for (i = 0; i < nr_ioapics; i++) {
3830 res[i].name = mem;
3831 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
3832 sprintf(mem, "IOAPIC %u", i);
3833 mem += IOAPIC_RESOURCE_NAME_SIZE;
3834 }
3835 }
3836
3837 ioapic_resources = res;
3838
3839 return res;
3840}
54168ed7 3841
f3294a33
YL		 3842void __init ioapic_init_mappings(void)
3843{
3844 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
54168ed7 3845 struct resource *ioapic_res;
d6c88a50 3846 int i;
f3294a33 3847
d6c88a50 3848 irq_2_pin_init();
54168ed7 3849 ioapic_res = ioapic_setup_resources();
f3294a33
YL		 3850 for (i = 0; i < nr_ioapics; i++) {
3851 if (smp_found_config) {
3852 ioapic_phys = mp_ioapics[i].mp_apicaddr;
54168ed7 3853#ifdef CONFIG_X86_32
d6c88a50
TG		 3854 if (!ioapic_phys) {
3855 printk(KERN_ERR
3856 "WARNING: bogus zero IO-APIC "
3857 "address found in MPTABLE, "
3858 "disabling IO/APIC support!\n");
3859 smp_found_config = 0;
3860 skip_ioapic_setup = 1;
3861 goto fake_ioapic_page;
3862 }
54168ed7 3863#endif
f3294a33 3864 } else {
54168ed7 3865#ifdef CONFIG_X86_32
f3294a33 3866fake_ioapic_page:
54168ed7 3867#endif
f3294a33 3868 ioapic_phys = (unsigned long)
54168ed7 3869 alloc_bootmem_pages(PAGE_SIZE);
f3294a33
YL		 3870 ioapic_phys = __pa(ioapic_phys);
3871 }
3872 set_fixmap_nocache(idx, ioapic_phys);
54168ed7
IM		 3873 apic_printk(APIC_VERBOSE,
3874 "mapped IOAPIC to %08lx (%08lx)\n",
3875 __fix_to_virt(idx), ioapic_phys);
f3294a33 3876 idx++;
54168ed7 3877
54168ed7
IM		 3878 if (ioapic_res != NULL) {
3879 ioapic_res->start = ioapic_phys;
3880 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
3881 ioapic_res++;
3882 }
f3294a33
YL		 3883 }
3884}
3885
54168ed7
IM		 3886static int __init ioapic_insert_resources(void)
3887{
3888 int i;
3889 struct resource *r = ioapic_resources;
3890
3891 if (!r) {
3892 printk(KERN_ERR
3893 "IO APIC resources could be not be allocated.\n");
3894 return -1;
3895 }
3896
3897 for (i = 0; i < nr_ioapics; i++) {
3898 insert_resource(&iomem_resource, r);
3899 r++;
3900 }
3901
3902 return 0;
3903}
3904
3905/* Insert the IO APIC resources after PCI initialization has occured to handle
3906 * IO APICS that are mapped in on a BAR in PCI space. */
3907late_initcall(ioapic_insert_resources);
Linux kernel - Deliverables
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