Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
4 | * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo | |
5 | * | |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
d4057bdb | 28 | #include <linux/pci.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
1da177e4 | 33 | #include <linux/sysdev.h> |
3b7d1921 | 34 | #include <linux/msi.h> |
95d77884 | 35 | #include <linux/htirq.h> |
7dfb7103 | 36 | #include <linux/freezer.h> |
f26d6a2b | 37 | #include <linux/kthread.h> |
54168ed7 | 38 | #include <linux/jiffies.h> /* time_after() */ |
d4057bdb YL |
39 | #ifdef CONFIG_ACPI |
40 | #include <acpi/acpi_bus.h> | |
41 | #endif | |
42 | #include <linux/bootmem.h> | |
43 | #include <linux/dmar.h> | |
58ac1e76 | 44 | #include <linux/hpet.h> |
54d5d424 | 45 | |
d4057bdb | 46 | #include <asm/idle.h> |
1da177e4 LT |
47 | #include <asm/io.h> |
48 | #include <asm/smp.h> | |
49 | #include <asm/desc.h> | |
d4057bdb YL |
50 | #include <asm/proto.h> |
51 | #include <asm/acpi.h> | |
52 | #include <asm/dma.h> | |
1da177e4 | 53 | #include <asm/timer.h> |
306e440d | 54 | #include <asm/i8259.h> |
3e4ff115 | 55 | #include <asm/nmi.h> |
2d3fcc1c | 56 | #include <asm/msidef.h> |
8b955b0d | 57 | #include <asm/hypertransport.h> |
a4dbc34d | 58 | #include <asm/setup.h> |
d4057bdb | 59 | #include <asm/irq_remapping.h> |
58ac1e76 | 60 | #include <asm/hpet.h> |
4173a0e7 DN |
61 | #include <asm/uv/uv_hub.h> |
62 | #include <asm/uv/uv_irq.h> | |
1da177e4 | 63 | |
497c9a19 | 64 | #include <mach_ipi.h> |
1da177e4 | 65 | #include <mach_apic.h> |
874c4fe3 | 66 | #include <mach_apicdef.h> |
1da177e4 | 67 | |
32f71aff MR |
68 | #define __apicdebuginit(type) static type __init |
69 | ||
1da177e4 | 70 | /* |
54168ed7 IM |
71 | * Is the SiS APIC rmw bug present ? |
72 | * -1 = don't know, 0 = no, 1 = yes | |
1da177e4 LT |
73 | */ |
74 | int sis_apic_bug = -1; | |
75 | ||
efa2559f YL |
76 | static DEFINE_SPINLOCK(ioapic_lock); |
77 | static DEFINE_SPINLOCK(vector_lock); | |
78 | ||
1da177e4 LT |
79 | /* |
80 | * # of IRQ routing registers | |
81 | */ | |
82 | int nr_ioapic_registers[MAX_IO_APICS]; | |
83 | ||
9f640ccb | 84 | /* I/O APIC entries */ |
ec2cd0a2 | 85 | struct mp_config_ioapic mp_ioapics[MAX_IO_APICS]; |
9f640ccb AS |
86 | int nr_ioapics; |
87 | ||
584f734d | 88 | /* MP IRQ source entries */ |
2fddb6e2 | 89 | struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
90 | |
91 | /* # of MP IRQ source entries */ | |
92 | int mp_irq_entries; | |
93 | ||
8732fc4b AS |
94 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
95 | int mp_bus_id_to_type[MAX_MP_BUSSES]; | |
96 | #endif | |
97 | ||
98 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
99 | ||
efa2559f YL |
100 | int skip_ioapic_setup; |
101 | ||
54168ed7 | 102 | static int __init parse_noapic(char *str) |
efa2559f YL |
103 | { |
104 | /* disable IO-APIC */ | |
105 | disable_ioapic_setup(); | |
106 | return 0; | |
107 | } | |
108 | early_param("noapic", parse_noapic); | |
66759a01 | 109 | |
0f978f45 | 110 | struct irq_pin_list; |
0b8f1efa YL |
111 | |
112 | /* | |
113 | * This is performance-critical, we want to do it O(1) | |
114 | * | |
115 | * the indexing order of this array favors 1:1 mappings | |
116 | * between pins and IRQs. | |
117 | */ | |
118 | ||
119 | struct irq_pin_list { | |
120 | int apic, pin; | |
121 | struct irq_pin_list *next; | |
122 | }; | |
123 | ||
124 | static struct irq_pin_list *get_one_free_irq_2_pin(int cpu) | |
125 | { | |
126 | struct irq_pin_list *pin; | |
127 | int node; | |
128 | ||
129 | node = cpu_to_node(cpu); | |
130 | ||
131 | pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node); | |
132 | printk(KERN_DEBUG " alloc irq_2_pin on cpu %d node %d\n", cpu, node); | |
133 | ||
134 | return pin; | |
135 | } | |
136 | ||
a1420f39 | 137 | struct irq_cfg { |
0f978f45 | 138 | struct irq_pin_list *irq_2_pin; |
22f65d31 MT |
139 | cpumask_var_t domain; |
140 | cpumask_var_t old_domain; | |
497c9a19 | 141 | unsigned move_cleanup_count; |
a1420f39 | 142 | u8 vector; |
497c9a19 | 143 | u8 move_in_progress : 1; |
48a1b10a YL |
144 | #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC |
145 | u8 move_desc_pending : 1; | |
146 | #endif | |
a1420f39 YL |
147 | }; |
148 | ||
a1420f39 | 149 | /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */ |
0b8f1efa YL |
150 | #ifdef CONFIG_SPARSE_IRQ |
151 | static struct irq_cfg irq_cfgx[] = { | |
152 | #else | |
d6c88a50 | 153 | static struct irq_cfg irq_cfgx[NR_IRQS] = { |
0b8f1efa | 154 | #endif |
22f65d31 MT |
155 | [0] = { .vector = IRQ0_VECTOR, }, |
156 | [1] = { .vector = IRQ1_VECTOR, }, | |
157 | [2] = { .vector = IRQ2_VECTOR, }, | |
158 | [3] = { .vector = IRQ3_VECTOR, }, | |
159 | [4] = { .vector = IRQ4_VECTOR, }, | |
160 | [5] = { .vector = IRQ5_VECTOR, }, | |
161 | [6] = { .vector = IRQ6_VECTOR, }, | |
162 | [7] = { .vector = IRQ7_VECTOR, }, | |
163 | [8] = { .vector = IRQ8_VECTOR, }, | |
164 | [9] = { .vector = IRQ9_VECTOR, }, | |
165 | [10] = { .vector = IRQ10_VECTOR, }, | |
166 | [11] = { .vector = IRQ11_VECTOR, }, | |
167 | [12] = { .vector = IRQ12_VECTOR, }, | |
168 | [13] = { .vector = IRQ13_VECTOR, }, | |
169 | [14] = { .vector = IRQ14_VECTOR, }, | |
170 | [15] = { .vector = IRQ15_VECTOR, }, | |
a1420f39 YL |
171 | }; |
172 | ||
0b8f1efa | 173 | void __init arch_early_irq_init(void) |
8f09cd20 | 174 | { |
0b8f1efa YL |
175 | struct irq_cfg *cfg; |
176 | struct irq_desc *desc; | |
177 | int count; | |
178 | int i; | |
d6c88a50 | 179 | |
0b8f1efa YL |
180 | cfg = irq_cfgx; |
181 | count = ARRAY_SIZE(irq_cfgx); | |
8f09cd20 | 182 | |
0b8f1efa YL |
183 | for (i = 0; i < count; i++) { |
184 | desc = irq_to_desc(i); | |
185 | desc->chip_data = &cfg[i]; | |
22f65d31 MT |
186 | alloc_bootmem_cpumask_var(&cfg[i].domain); |
187 | alloc_bootmem_cpumask_var(&cfg[i].old_domain); | |
188 | if (i < NR_IRQS_LEGACY) | |
189 | cpumask_setall(cfg[i].domain); | |
0b8f1efa | 190 | } |
8f09cd20 | 191 | } |
d6c88a50 | 192 | |
0b8f1efa YL |
193 | #ifdef CONFIG_SPARSE_IRQ |
194 | static struct irq_cfg *irq_cfg(unsigned int irq) | |
8f09cd20 | 195 | { |
0b8f1efa YL |
196 | struct irq_cfg *cfg = NULL; |
197 | struct irq_desc *desc; | |
1da177e4 | 198 | |
0b8f1efa YL |
199 | desc = irq_to_desc(irq); |
200 | if (desc) | |
201 | cfg = desc->chip_data; | |
0f978f45 | 202 | |
0b8f1efa | 203 | return cfg; |
8f09cd20 YL |
204 | } |
205 | ||
0b8f1efa | 206 | static struct irq_cfg *get_one_free_irq_cfg(int cpu) |
0f978f45 | 207 | { |
0b8f1efa YL |
208 | struct irq_cfg *cfg; |
209 | int node; | |
d6c88a50 | 210 | |
0b8f1efa | 211 | node = cpu_to_node(cpu); |
1da177e4 | 212 | |
0b8f1efa | 213 | cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node); |
22f65d31 MT |
214 | if (cfg) { |
215 | /* FIXME: needs alloc_cpumask_var_node() */ | |
216 | if (!alloc_cpumask_var(&cfg->domain, GFP_ATOMIC)) { | |
217 | kfree(cfg); | |
218 | cfg = NULL; | |
219 | } else if (!alloc_cpumask_var(&cfg->old_domain, GFP_ATOMIC)) { | |
220 | free_cpumask_var(cfg->domain); | |
221 | kfree(cfg); | |
222 | cfg = NULL; | |
223 | } else { | |
224 | cpumask_clear(cfg->domain); | |
225 | cpumask_clear(cfg->old_domain); | |
226 | } | |
227 | } | |
0b8f1efa | 228 | printk(KERN_DEBUG " alloc irq_cfg on cpu %d node %d\n", cpu, node); |
0f978f45 | 229 | |
0b8f1efa | 230 | return cfg; |
0f978f45 | 231 | } |
d6c88a50 | 232 | |
0b8f1efa | 233 | void arch_init_chip_data(struct irq_desc *desc, int cpu) |
0f978f45 | 234 | { |
0b8f1efa | 235 | struct irq_cfg *cfg; |
0f978f45 | 236 | |
0b8f1efa YL |
237 | cfg = desc->chip_data; |
238 | if (!cfg) { | |
239 | desc->chip_data = get_one_free_irq_cfg(cpu); | |
240 | if (!desc->chip_data) { | |
241 | printk(KERN_ERR "can not alloc irq_cfg\n"); | |
242 | BUG_ON(1); | |
243 | } | |
244 | } | |
0f978f45 | 245 | } |
0f978f45 | 246 | |
48a1b10a YL |
247 | #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC |
248 | ||
249 | static void | |
250 | init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int cpu) | |
251 | { | |
252 | struct irq_pin_list *old_entry, *head, *tail, *entry; | |
253 | ||
254 | cfg->irq_2_pin = NULL; | |
255 | old_entry = old_cfg->irq_2_pin; | |
256 | if (!old_entry) | |
257 | return; | |
258 | ||
259 | entry = get_one_free_irq_2_pin(cpu); | |
260 | if (!entry) | |
261 | return; | |
262 | ||
263 | entry->apic = old_entry->apic; | |
264 | entry->pin = old_entry->pin; | |
265 | head = entry; | |
266 | tail = entry; | |
267 | old_entry = old_entry->next; | |
268 | while (old_entry) { | |
269 | entry = get_one_free_irq_2_pin(cpu); | |
270 | if (!entry) { | |
271 | entry = head; | |
272 | while (entry) { | |
273 | head = entry->next; | |
274 | kfree(entry); | |
275 | entry = head; | |
276 | } | |
277 | /* still use the old one */ | |
278 | return; | |
279 | } | |
280 | entry->apic = old_entry->apic; | |
281 | entry->pin = old_entry->pin; | |
282 | tail->next = entry; | |
283 | tail = entry; | |
284 | old_entry = old_entry->next; | |
285 | } | |
286 | ||
287 | tail->next = NULL; | |
288 | cfg->irq_2_pin = head; | |
289 | } | |
290 | ||
291 | static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg) | |
292 | { | |
293 | struct irq_pin_list *entry, *next; | |
294 | ||
295 | if (old_cfg->irq_2_pin == cfg->irq_2_pin) | |
296 | return; | |
297 | ||
298 | entry = old_cfg->irq_2_pin; | |
299 | ||
300 | while (entry) { | |
301 | next = entry->next; | |
302 | kfree(entry); | |
303 | entry = next; | |
304 | } | |
305 | old_cfg->irq_2_pin = NULL; | |
306 | } | |
307 | ||
308 | void arch_init_copy_chip_data(struct irq_desc *old_desc, | |
309 | struct irq_desc *desc, int cpu) | |
310 | { | |
311 | struct irq_cfg *cfg; | |
312 | struct irq_cfg *old_cfg; | |
313 | ||
314 | cfg = get_one_free_irq_cfg(cpu); | |
315 | ||
316 | if (!cfg) | |
317 | return; | |
318 | ||
319 | desc->chip_data = cfg; | |
320 | ||
321 | old_cfg = old_desc->chip_data; | |
322 | ||
323 | memcpy(cfg, old_cfg, sizeof(struct irq_cfg)); | |
324 | ||
325 | init_copy_irq_2_pin(old_cfg, cfg, cpu); | |
326 | } | |
327 | ||
328 | static void free_irq_cfg(struct irq_cfg *old_cfg) | |
329 | { | |
330 | kfree(old_cfg); | |
331 | } | |
332 | ||
333 | void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc) | |
334 | { | |
335 | struct irq_cfg *old_cfg, *cfg; | |
336 | ||
337 | old_cfg = old_desc->chip_data; | |
338 | cfg = desc->chip_data; | |
339 | ||
340 | if (old_cfg == cfg) | |
341 | return; | |
342 | ||
343 | if (old_cfg) { | |
344 | free_irq_2_pin(old_cfg, cfg); | |
345 | free_irq_cfg(old_cfg); | |
346 | old_desc->chip_data = NULL; | |
347 | } | |
348 | } | |
349 | ||
d733e00d IM |
350 | static void |
351 | set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask) | |
48a1b10a YL |
352 | { |
353 | struct irq_cfg *cfg = desc->chip_data; | |
354 | ||
355 | if (!cfg->move_in_progress) { | |
356 | /* it means that domain is not changed */ | |
d733e00d | 357 | if (!cpumask_intersects(&desc->affinity, mask)) |
48a1b10a YL |
358 | cfg->move_desc_pending = 1; |
359 | } | |
360 | } | |
361 | #endif | |
362 | ||
0b8f1efa YL |
363 | #else |
364 | static struct irq_cfg *irq_cfg(unsigned int irq) | |
0f978f45 | 365 | { |
0b8f1efa | 366 | return irq < nr_irqs ? irq_cfgx + irq : NULL; |
0f978f45 | 367 | } |
0f978f45 | 368 | |
0b8f1efa | 369 | #endif |
301e6190 | 370 | |
48a1b10a | 371 | #ifndef CONFIG_NUMA_MIGRATE_IRQ_DESC |
e7986739 MT |
372 | static inline void |
373 | set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask) | |
3145e941 | 374 | { |
0f978f45 | 375 | } |
48a1b10a | 376 | #endif |
1da177e4 | 377 | |
130fe05d LT |
378 | struct io_apic { |
379 | unsigned int index; | |
380 | unsigned int unused[3]; | |
381 | unsigned int data; | |
382 | }; | |
383 | ||
384 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
385 | { | |
386 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
ec2cd0a2 | 387 | + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK); |
130fe05d LT |
388 | } |
389 | ||
390 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) | |
391 | { | |
392 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
393 | writel(reg, &io_apic->index); | |
394 | return readl(&io_apic->data); | |
395 | } | |
396 | ||
397 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) | |
398 | { | |
399 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
400 | writel(reg, &io_apic->index); | |
401 | writel(value, &io_apic->data); | |
402 | } | |
403 | ||
404 | /* | |
405 | * Re-write a value: to be used for read-modify-write | |
406 | * cycles where the read already set up the index register. | |
407 | * | |
408 | * Older SiS APIC requires we rewrite the index register | |
409 | */ | |
410 | static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) | |
411 | { | |
54168ed7 | 412 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
d6c88a50 TG |
413 | |
414 | if (sis_apic_bug) | |
415 | writel(reg, &io_apic->index); | |
130fe05d LT |
416 | writel(value, &io_apic->data); |
417 | } | |
418 | ||
3145e941 | 419 | static bool io_apic_level_ack_pending(struct irq_cfg *cfg) |
047c8fdb YL |
420 | { |
421 | struct irq_pin_list *entry; | |
422 | unsigned long flags; | |
047c8fdb YL |
423 | |
424 | spin_lock_irqsave(&ioapic_lock, flags); | |
425 | entry = cfg->irq_2_pin; | |
426 | for (;;) { | |
427 | unsigned int reg; | |
428 | int pin; | |
429 | ||
430 | if (!entry) | |
431 | break; | |
432 | pin = entry->pin; | |
433 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
434 | /* Is the remote IRR bit set? */ | |
435 | if (reg & IO_APIC_REDIR_REMOTE_IRR) { | |
436 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
437 | return true; | |
438 | } | |
439 | if (!entry->next) | |
440 | break; | |
441 | entry = entry->next; | |
442 | } | |
443 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
444 | ||
445 | return false; | |
446 | } | |
047c8fdb | 447 | |
cf4c6a2f AK |
448 | union entry_union { |
449 | struct { u32 w1, w2; }; | |
450 | struct IO_APIC_route_entry entry; | |
451 | }; | |
452 | ||
453 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) | |
454 | { | |
455 | union entry_union eu; | |
456 | unsigned long flags; | |
457 | spin_lock_irqsave(&ioapic_lock, flags); | |
458 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); | |
459 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
460 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
461 | return eu.entry; | |
462 | } | |
463 | ||
f9dadfa7 LT |
464 | /* |
465 | * When we write a new IO APIC routing entry, we need to write the high | |
466 | * word first! If the mask bit in the low word is clear, we will enable | |
467 | * the interrupt, and we need to make sure the entry is fully populated | |
468 | * before that happens. | |
469 | */ | |
d15512f4 AK |
470 | static void |
471 | __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
cf4c6a2f | 472 | { |
cf4c6a2f AK |
473 | union entry_union eu; |
474 | eu.entry = e; | |
f9dadfa7 LT |
475 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
476 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
477 | } |
478 | ||
479 | static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
480 | { | |
481 | unsigned long flags; | |
482 | spin_lock_irqsave(&ioapic_lock, flags); | |
483 | __ioapic_write_entry(apic, pin, e); | |
f9dadfa7 LT |
484 | spin_unlock_irqrestore(&ioapic_lock, flags); |
485 | } | |
486 | ||
487 | /* | |
488 | * When we mask an IO APIC routing entry, we need to write the low | |
489 | * word first, in order to set the mask bit before we change the | |
490 | * high bits! | |
491 | */ | |
492 | static void ioapic_mask_entry(int apic, int pin) | |
493 | { | |
494 | unsigned long flags; | |
495 | union entry_union eu = { .entry.mask = 1 }; | |
496 | ||
cf4c6a2f AK |
497 | spin_lock_irqsave(&ioapic_lock, flags); |
498 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
499 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
500 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
501 | } | |
502 | ||
497c9a19 | 503 | #ifdef CONFIG_SMP |
22f65d31 MT |
504 | static void send_cleanup_vector(struct irq_cfg *cfg) |
505 | { | |
506 | cpumask_var_t cleanup_mask; | |
507 | ||
508 | if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) { | |
509 | unsigned int i; | |
510 | cfg->move_cleanup_count = 0; | |
511 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) | |
512 | cfg->move_cleanup_count++; | |
513 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) | |
514 | send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR); | |
515 | } else { | |
516 | cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask); | |
517 | cfg->move_cleanup_count = cpumask_weight(cleanup_mask); | |
518 | send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); | |
519 | free_cpumask_var(cleanup_mask); | |
520 | } | |
521 | cfg->move_in_progress = 0; | |
522 | } | |
523 | ||
3145e941 | 524 | static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg) |
497c9a19 YL |
525 | { |
526 | int apic, pin; | |
497c9a19 | 527 | struct irq_pin_list *entry; |
3145e941 | 528 | u8 vector = cfg->vector; |
497c9a19 | 529 | |
497c9a19 YL |
530 | entry = cfg->irq_2_pin; |
531 | for (;;) { | |
532 | unsigned int reg; | |
533 | ||
534 | if (!entry) | |
535 | break; | |
536 | ||
537 | apic = entry->apic; | |
538 | pin = entry->pin; | |
54168ed7 IM |
539 | #ifdef CONFIG_INTR_REMAP |
540 | /* | |
541 | * With interrupt-remapping, destination information comes | |
542 | * from interrupt-remapping table entry. | |
543 | */ | |
544 | if (!irq_remapped(irq)) | |
545 | io_apic_write(apic, 0x11 + pin*2, dest); | |
546 | #else | |
497c9a19 | 547 | io_apic_write(apic, 0x11 + pin*2, dest); |
54168ed7 | 548 | #endif |
497c9a19 YL |
549 | reg = io_apic_read(apic, 0x10 + pin*2); |
550 | reg &= ~IO_APIC_REDIR_VECTOR_MASK; | |
551 | reg |= vector; | |
54168ed7 | 552 | io_apic_modify(apic, 0x10 + pin*2, reg); |
497c9a19 YL |
553 | if (!entry->next) |
554 | break; | |
555 | entry = entry->next; | |
556 | } | |
557 | } | |
efa2559f | 558 | |
e7986739 MT |
559 | static int |
560 | assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask); | |
efa2559f | 561 | |
22f65d31 MT |
562 | /* |
563 | * Either sets desc->affinity to a valid value, and returns cpu_mask_to_apicid | |
564 | * of that, or returns BAD_APICID and leaves desc->affinity untouched. | |
565 | */ | |
566 | static unsigned int | |
567 | set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask) | |
497c9a19 YL |
568 | { |
569 | struct irq_cfg *cfg; | |
3145e941 | 570 | unsigned int irq; |
497c9a19 | 571 | |
0de26520 | 572 | if (!cpumask_intersects(mask, cpu_online_mask)) |
22f65d31 | 573 | return BAD_APICID; |
497c9a19 | 574 | |
3145e941 YL |
575 | irq = desc->irq; |
576 | cfg = desc->chip_data; | |
e7986739 | 577 | if (assign_irq_vector(irq, cfg, mask)) |
22f65d31 | 578 | return BAD_APICID; |
497c9a19 | 579 | |
22f65d31 | 580 | cpumask_and(&desc->affinity, cfg->domain, mask); |
e7986739 | 581 | set_extra_move_desc(desc, mask); |
22f65d31 MT |
582 | return cpu_mask_to_apicid_and(&desc->affinity, cpu_online_mask); |
583 | } | |
3145e941 | 584 | |
22f65d31 MT |
585 | static void |
586 | set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask) | |
587 | { | |
588 | struct irq_cfg *cfg; | |
589 | unsigned long flags; | |
590 | unsigned int dest; | |
591 | unsigned int irq; | |
592 | ||
593 | irq = desc->irq; | |
594 | cfg = desc->chip_data; | |
497c9a19 YL |
595 | |
596 | spin_lock_irqsave(&ioapic_lock, flags); | |
22f65d31 MT |
597 | dest = set_desc_affinity(desc, mask); |
598 | if (dest != BAD_APICID) { | |
599 | /* Only the high 8 bits are valid. */ | |
600 | dest = SET_APIC_LOGICAL_ID(dest); | |
601 | __target_IO_APIC_irq(irq, dest, cfg); | |
602 | } | |
497c9a19 YL |
603 | spin_unlock_irqrestore(&ioapic_lock, flags); |
604 | } | |
3145e941 | 605 | |
22f65d31 MT |
606 | static void |
607 | set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask) | |
3145e941 YL |
608 | { |
609 | struct irq_desc *desc; | |
610 | ||
611 | desc = irq_to_desc(irq); | |
612 | ||
613 | set_ioapic_affinity_irq_desc(desc, mask); | |
614 | } | |
497c9a19 YL |
615 | #endif /* CONFIG_SMP */ |
616 | ||
1da177e4 LT |
617 | /* |
618 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
619 | * shared ISA-space IRQs, so we have to support them. We are super | |
620 | * fast in the common case, and fast for shared ISA-space IRQs. | |
621 | */ | |
3145e941 | 622 | static void add_pin_to_irq_cpu(struct irq_cfg *cfg, int cpu, int apic, int pin) |
1da177e4 | 623 | { |
0f978f45 YL |
624 | struct irq_pin_list *entry; |
625 | ||
0f978f45 YL |
626 | entry = cfg->irq_2_pin; |
627 | if (!entry) { | |
0b8f1efa YL |
628 | entry = get_one_free_irq_2_pin(cpu); |
629 | if (!entry) { | |
630 | printk(KERN_ERR "can not alloc irq_2_pin to add %d - %d\n", | |
631 | apic, pin); | |
632 | return; | |
633 | } | |
0f978f45 YL |
634 | cfg->irq_2_pin = entry; |
635 | entry->apic = apic; | |
636 | entry->pin = pin; | |
0f978f45 YL |
637 | return; |
638 | } | |
1da177e4 | 639 | |
0f978f45 YL |
640 | while (entry->next) { |
641 | /* not again, please */ | |
642 | if (entry->apic == apic && entry->pin == pin) | |
643 | return; | |
1da177e4 | 644 | |
0f978f45 | 645 | entry = entry->next; |
1da177e4 | 646 | } |
0f978f45 | 647 | |
0b8f1efa | 648 | entry->next = get_one_free_irq_2_pin(cpu); |
0f978f45 | 649 | entry = entry->next; |
1da177e4 LT |
650 | entry->apic = apic; |
651 | entry->pin = pin; | |
652 | } | |
653 | ||
654 | /* | |
655 | * Reroute an IRQ to a different pin. | |
656 | */ | |
3145e941 | 657 | static void __init replace_pin_at_irq_cpu(struct irq_cfg *cfg, int cpu, |
1da177e4 LT |
658 | int oldapic, int oldpin, |
659 | int newapic, int newpin) | |
660 | { | |
0f978f45 YL |
661 | struct irq_pin_list *entry = cfg->irq_2_pin; |
662 | int replaced = 0; | |
1da177e4 | 663 | |
0f978f45 | 664 | while (entry) { |
1da177e4 LT |
665 | if (entry->apic == oldapic && entry->pin == oldpin) { |
666 | entry->apic = newapic; | |
667 | entry->pin = newpin; | |
0f978f45 YL |
668 | replaced = 1; |
669 | /* every one is different, right? */ | |
1da177e4 | 670 | break; |
0f978f45 YL |
671 | } |
672 | entry = entry->next; | |
1da177e4 | 673 | } |
0f978f45 YL |
674 | |
675 | /* why? call replace before add? */ | |
676 | if (!replaced) | |
3145e941 | 677 | add_pin_to_irq_cpu(cfg, cpu, newapic, newpin); |
1da177e4 LT |
678 | } |
679 | ||
3145e941 | 680 | static inline void io_apic_modify_irq(struct irq_cfg *cfg, |
87783be4 CG |
681 | int mask_and, int mask_or, |
682 | void (*final)(struct irq_pin_list *entry)) | |
683 | { | |
684 | int pin; | |
87783be4 | 685 | struct irq_pin_list *entry; |
047c8fdb | 686 | |
87783be4 CG |
687 | for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) { |
688 | unsigned int reg; | |
689 | pin = entry->pin; | |
690 | reg = io_apic_read(entry->apic, 0x10 + pin * 2); | |
691 | reg &= mask_and; | |
692 | reg |= mask_or; | |
693 | io_apic_modify(entry->apic, 0x10 + pin * 2, reg); | |
694 | if (final) | |
695 | final(entry); | |
696 | } | |
697 | } | |
047c8fdb | 698 | |
3145e941 | 699 | static void __unmask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 700 | { |
3145e941 | 701 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL); |
87783be4 | 702 | } |
047c8fdb | 703 | |
4e738e2f | 704 | #ifdef CONFIG_X86_64 |
87783be4 | 705 | void io_apic_sync(struct irq_pin_list *entry) |
1da177e4 | 706 | { |
87783be4 CG |
707 | /* |
708 | * Synchronize the IO-APIC and the CPU by doing | |
709 | * a dummy read from the IO-APIC | |
710 | */ | |
711 | struct io_apic __iomem *io_apic; | |
712 | io_apic = io_apic_base(entry->apic); | |
4e738e2f | 713 | readl(&io_apic->data); |
1da177e4 LT |
714 | } |
715 | ||
3145e941 | 716 | static void __mask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 717 | { |
3145e941 | 718 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync); |
87783be4 CG |
719 | } |
720 | #else /* CONFIG_X86_32 */ | |
3145e941 | 721 | static void __mask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 722 | { |
3145e941 | 723 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, NULL); |
87783be4 | 724 | } |
1da177e4 | 725 | |
3145e941 | 726 | static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 727 | { |
3145e941 | 728 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER, |
87783be4 CG |
729 | IO_APIC_REDIR_MASKED, NULL); |
730 | } | |
1da177e4 | 731 | |
3145e941 | 732 | static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 733 | { |
3145e941 | 734 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, |
87783be4 CG |
735 | IO_APIC_REDIR_LEVEL_TRIGGER, NULL); |
736 | } | |
737 | #endif /* CONFIG_X86_32 */ | |
047c8fdb | 738 | |
3145e941 | 739 | static void mask_IO_APIC_irq_desc(struct irq_desc *desc) |
1da177e4 | 740 | { |
3145e941 | 741 | struct irq_cfg *cfg = desc->chip_data; |
1da177e4 LT |
742 | unsigned long flags; |
743 | ||
3145e941 YL |
744 | BUG_ON(!cfg); |
745 | ||
1da177e4 | 746 | spin_lock_irqsave(&ioapic_lock, flags); |
3145e941 | 747 | __mask_IO_APIC_irq(cfg); |
1da177e4 LT |
748 | spin_unlock_irqrestore(&ioapic_lock, flags); |
749 | } | |
750 | ||
3145e941 | 751 | static void unmask_IO_APIC_irq_desc(struct irq_desc *desc) |
1da177e4 | 752 | { |
3145e941 | 753 | struct irq_cfg *cfg = desc->chip_data; |
1da177e4 LT |
754 | unsigned long flags; |
755 | ||
756 | spin_lock_irqsave(&ioapic_lock, flags); | |
3145e941 | 757 | __unmask_IO_APIC_irq(cfg); |
1da177e4 LT |
758 | spin_unlock_irqrestore(&ioapic_lock, flags); |
759 | } | |
760 | ||
3145e941 YL |
761 | static void mask_IO_APIC_irq(unsigned int irq) |
762 | { | |
763 | struct irq_desc *desc = irq_to_desc(irq); | |
764 | ||
765 | mask_IO_APIC_irq_desc(desc); | |
766 | } | |
767 | static void unmask_IO_APIC_irq(unsigned int irq) | |
768 | { | |
769 | struct irq_desc *desc = irq_to_desc(irq); | |
770 | ||
771 | unmask_IO_APIC_irq_desc(desc); | |
772 | } | |
773 | ||
1da177e4 LT |
774 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) |
775 | { | |
776 | struct IO_APIC_route_entry entry; | |
36062448 | 777 | |
1da177e4 | 778 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 779 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
780 | if (entry.delivery_mode == dest_SMI) |
781 | return; | |
1da177e4 LT |
782 | /* |
783 | * Disable it in the IO-APIC irq-routing table: | |
784 | */ | |
f9dadfa7 | 785 | ioapic_mask_entry(apic, pin); |
1da177e4 LT |
786 | } |
787 | ||
54168ed7 | 788 | static void clear_IO_APIC (void) |
1da177e4 LT |
789 | { |
790 | int apic, pin; | |
791 | ||
792 | for (apic = 0; apic < nr_ioapics; apic++) | |
793 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) | |
794 | clear_IO_APIC_pin(apic, pin); | |
795 | } | |
796 | ||
54168ed7 | 797 | #if !defined(CONFIG_SMP) && defined(CONFIG_X86_32) |
75604d7f | 798 | void send_IPI_self(int vector) |
1da177e4 LT |
799 | { |
800 | unsigned int cfg; | |
801 | ||
802 | /* | |
803 | * Wait for idle. | |
804 | */ | |
805 | apic_wait_icr_idle(); | |
806 | cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL; | |
807 | /* | |
808 | * Send the IPI. The write to APIC_ICR fires this off. | |
809 | */ | |
593f4a78 | 810 | apic_write(APIC_ICR, cfg); |
1da177e4 | 811 | } |
54168ed7 | 812 | #endif /* !CONFIG_SMP && CONFIG_X86_32*/ |
1da177e4 | 813 | |
54168ed7 | 814 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
815 | /* |
816 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
817 | * specific CPU-side IRQs. | |
818 | */ | |
819 | ||
820 | #define MAX_PIRQS 8 | |
821 | static int pirq_entries [MAX_PIRQS]; | |
822 | static int pirqs_enabled; | |
1da177e4 | 823 | |
1da177e4 LT |
824 | static int __init ioapic_pirq_setup(char *str) |
825 | { | |
826 | int i, max; | |
827 | int ints[MAX_PIRQS+1]; | |
828 | ||
829 | get_options(str, ARRAY_SIZE(ints), ints); | |
830 | ||
831 | for (i = 0; i < MAX_PIRQS; i++) | |
832 | pirq_entries[i] = -1; | |
833 | ||
834 | pirqs_enabled = 1; | |
835 | apic_printk(APIC_VERBOSE, KERN_INFO | |
836 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
837 | max = MAX_PIRQS; | |
838 | if (ints[0] < MAX_PIRQS) | |
839 | max = ints[0]; | |
840 | ||
841 | for (i = 0; i < max; i++) { | |
842 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
843 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
844 | /* | |
845 | * PIRQs are mapped upside down, usually. | |
846 | */ | |
847 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
848 | } | |
849 | return 1; | |
850 | } | |
851 | ||
852 | __setup("pirq=", ioapic_pirq_setup); | |
54168ed7 IM |
853 | #endif /* CONFIG_X86_32 */ |
854 | ||
855 | #ifdef CONFIG_INTR_REMAP | |
856 | /* I/O APIC RTE contents at the OS boot up */ | |
857 | static struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS]; | |
858 | ||
859 | /* | |
860 | * Saves and masks all the unmasked IO-APIC RTE's | |
861 | */ | |
862 | int save_mask_IO_APIC_setup(void) | |
863 | { | |
864 | union IO_APIC_reg_01 reg_01; | |
865 | unsigned long flags; | |
866 | int apic, pin; | |
867 | ||
868 | /* | |
869 | * The number of IO-APIC IRQ registers (== #pins): | |
870 | */ | |
871 | for (apic = 0; apic < nr_ioapics; apic++) { | |
872 | spin_lock_irqsave(&ioapic_lock, flags); | |
873 | reg_01.raw = io_apic_read(apic, 1); | |
874 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
875 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; | |
876 | } | |
877 | ||
878 | for (apic = 0; apic < nr_ioapics; apic++) { | |
879 | early_ioapic_entries[apic] = | |
880 | kzalloc(sizeof(struct IO_APIC_route_entry) * | |
881 | nr_ioapic_registers[apic], GFP_KERNEL); | |
882 | if (!early_ioapic_entries[apic]) | |
5ffa4eb2 | 883 | goto nomem; |
54168ed7 IM |
884 | } |
885 | ||
886 | for (apic = 0; apic < nr_ioapics; apic++) | |
887 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
888 | struct IO_APIC_route_entry entry; | |
889 | ||
890 | entry = early_ioapic_entries[apic][pin] = | |
891 | ioapic_read_entry(apic, pin); | |
892 | if (!entry.mask) { | |
893 | entry.mask = 1; | |
894 | ioapic_write_entry(apic, pin, entry); | |
895 | } | |
896 | } | |
5ffa4eb2 | 897 | |
54168ed7 | 898 | return 0; |
5ffa4eb2 CG |
899 | |
900 | nomem: | |
c1370b49 CG |
901 | while (apic >= 0) |
902 | kfree(early_ioapic_entries[apic--]); | |
5ffa4eb2 CG |
903 | memset(early_ioapic_entries, 0, |
904 | ARRAY_SIZE(early_ioapic_entries)); | |
905 | ||
906 | return -ENOMEM; | |
54168ed7 IM |
907 | } |
908 | ||
909 | void restore_IO_APIC_setup(void) | |
910 | { | |
911 | int apic, pin; | |
912 | ||
5ffa4eb2 CG |
913 | for (apic = 0; apic < nr_ioapics; apic++) { |
914 | if (!early_ioapic_entries[apic]) | |
915 | break; | |
54168ed7 IM |
916 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
917 | ioapic_write_entry(apic, pin, | |
918 | early_ioapic_entries[apic][pin]); | |
5ffa4eb2 CG |
919 | kfree(early_ioapic_entries[apic]); |
920 | early_ioapic_entries[apic] = NULL; | |
921 | } | |
54168ed7 IM |
922 | } |
923 | ||
924 | void reinit_intr_remapped_IO_APIC(int intr_remapping) | |
925 | { | |
926 | /* | |
927 | * for now plain restore of previous settings. | |
928 | * TBD: In the case of OS enabling interrupt-remapping, | |
929 | * IO-APIC RTE's need to be setup to point to interrupt-remapping | |
930 | * table entries. for now, do a plain restore, and wait for | |
931 | * the setup_IO_APIC_irqs() to do proper initialization. | |
932 | */ | |
933 | restore_IO_APIC_setup(); | |
934 | } | |
935 | #endif | |
1da177e4 LT |
936 | |
937 | /* | |
938 | * Find the IRQ entry number of a certain pin. | |
939 | */ | |
940 | static int find_irq_entry(int apic, int pin, int type) | |
941 | { | |
942 | int i; | |
943 | ||
944 | for (i = 0; i < mp_irq_entries; i++) | |
2fddb6e2 AS |
945 | if (mp_irqs[i].mp_irqtype == type && |
946 | (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid || | |
947 | mp_irqs[i].mp_dstapic == MP_APIC_ALL) && | |
948 | mp_irqs[i].mp_dstirq == pin) | |
1da177e4 LT |
949 | return i; |
950 | ||
951 | return -1; | |
952 | } | |
953 | ||
954 | /* | |
955 | * Find the pin to which IRQ[irq] (ISA) is connected | |
956 | */ | |
fcfd636a | 957 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
958 | { |
959 | int i; | |
960 | ||
961 | for (i = 0; i < mp_irq_entries; i++) { | |
2fddb6e2 | 962 | int lbus = mp_irqs[i].mp_srcbus; |
1da177e4 | 963 | |
d27e2b8e | 964 | if (test_bit(lbus, mp_bus_not_pci) && |
2fddb6e2 AS |
965 | (mp_irqs[i].mp_irqtype == type) && |
966 | (mp_irqs[i].mp_srcbusirq == irq)) | |
1da177e4 | 967 | |
2fddb6e2 | 968 | return mp_irqs[i].mp_dstirq; |
1da177e4 LT |
969 | } |
970 | return -1; | |
971 | } | |
972 | ||
fcfd636a EB |
973 | static int __init find_isa_irq_apic(int irq, int type) |
974 | { | |
975 | int i; | |
976 | ||
977 | for (i = 0; i < mp_irq_entries; i++) { | |
2fddb6e2 | 978 | int lbus = mp_irqs[i].mp_srcbus; |
fcfd636a | 979 | |
73b2961b | 980 | if (test_bit(lbus, mp_bus_not_pci) && |
2fddb6e2 AS |
981 | (mp_irqs[i].mp_irqtype == type) && |
982 | (mp_irqs[i].mp_srcbusirq == irq)) | |
fcfd636a EB |
983 | break; |
984 | } | |
985 | if (i < mp_irq_entries) { | |
986 | int apic; | |
54168ed7 | 987 | for(apic = 0; apic < nr_ioapics; apic++) { |
2fddb6e2 | 988 | if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic) |
fcfd636a EB |
989 | return apic; |
990 | } | |
991 | } | |
992 | ||
993 | return -1; | |
994 | } | |
995 | ||
1da177e4 LT |
996 | /* |
997 | * Find a specific PCI IRQ entry. | |
998 | * Not an __init, possibly needed by modules | |
999 | */ | |
1000 | static int pin_2_irq(int idx, int apic, int pin); | |
1001 | ||
1002 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin) | |
1003 | { | |
1004 | int apic, i, best_guess = -1; | |
1005 | ||
54168ed7 IM |
1006 | apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", |
1007 | bus, slot, pin); | |
ce6444d3 | 1008 | if (test_bit(bus, mp_bus_not_pci)) { |
54168ed7 | 1009 | apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus); |
1da177e4 LT |
1010 | return -1; |
1011 | } | |
1012 | for (i = 0; i < mp_irq_entries; i++) { | |
2fddb6e2 | 1013 | int lbus = mp_irqs[i].mp_srcbus; |
1da177e4 LT |
1014 | |
1015 | for (apic = 0; apic < nr_ioapics; apic++) | |
2fddb6e2 AS |
1016 | if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic || |
1017 | mp_irqs[i].mp_dstapic == MP_APIC_ALL) | |
1da177e4 LT |
1018 | break; |
1019 | ||
47cab822 | 1020 | if (!test_bit(lbus, mp_bus_not_pci) && |
2fddb6e2 | 1021 | !mp_irqs[i].mp_irqtype && |
1da177e4 | 1022 | (bus == lbus) && |
2fddb6e2 | 1023 | (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) { |
54168ed7 | 1024 | int irq = pin_2_irq(i,apic,mp_irqs[i].mp_dstirq); |
1da177e4 LT |
1025 | |
1026 | if (!(apic || IO_APIC_IRQ(irq))) | |
1027 | continue; | |
1028 | ||
2fddb6e2 | 1029 | if (pin == (mp_irqs[i].mp_srcbusirq & 3)) |
1da177e4 LT |
1030 | return irq; |
1031 | /* | |
1032 | * Use the first all-but-pin matching entry as a | |
1033 | * best-guess fuzzy result for broken mptables. | |
1034 | */ | |
1035 | if (best_guess < 0) | |
1036 | best_guess = irq; | |
1037 | } | |
1038 | } | |
1039 | return best_guess; | |
1040 | } | |
54168ed7 | 1041 | |
129f6946 | 1042 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); |
1da177e4 | 1043 | |
c0a282c2 | 1044 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
1da177e4 LT |
1045 | /* |
1046 | * EISA Edge/Level control register, ELCR | |
1047 | */ | |
1048 | static int EISA_ELCR(unsigned int irq) | |
1049 | { | |
99d093d1 | 1050 | if (irq < NR_IRQS_LEGACY) { |
1da177e4 LT |
1051 | unsigned int port = 0x4d0 + (irq >> 3); |
1052 | return (inb(port) >> (irq & 7)) & 1; | |
1053 | } | |
1054 | apic_printk(APIC_VERBOSE, KERN_INFO | |
1055 | "Broken MPtable reports ISA irq %d\n", irq); | |
1056 | return 0; | |
1057 | } | |
54168ed7 | 1058 | |
c0a282c2 | 1059 | #endif |
1da177e4 | 1060 | |
6728801d AS |
1061 | /* ISA interrupts are always polarity zero edge triggered, |
1062 | * when listed as conforming in the MP table. */ | |
1063 | ||
1064 | #define default_ISA_trigger(idx) (0) | |
1065 | #define default_ISA_polarity(idx) (0) | |
1066 | ||
1da177e4 LT |
1067 | /* EISA interrupts are always polarity zero and can be edge or level |
1068 | * trigger depending on the ELCR value. If an interrupt is listed as | |
1069 | * EISA conforming in the MP table, that means its trigger type must | |
1070 | * be read in from the ELCR */ | |
1071 | ||
2fddb6e2 | 1072 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq)) |
6728801d | 1073 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
1074 | |
1075 | /* PCI interrupts are always polarity one level triggered, | |
1076 | * when listed as conforming in the MP table. */ | |
1077 | ||
1078 | #define default_PCI_trigger(idx) (1) | |
1079 | #define default_PCI_polarity(idx) (1) | |
1080 | ||
1081 | /* MCA interrupts are always polarity zero level triggered, | |
1082 | * when listed as conforming in the MP table. */ | |
1083 | ||
1084 | #define default_MCA_trigger(idx) (1) | |
6728801d | 1085 | #define default_MCA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 | 1086 | |
61fd47e0 | 1087 | static int MPBIOS_polarity(int idx) |
1da177e4 | 1088 | { |
2fddb6e2 | 1089 | int bus = mp_irqs[idx].mp_srcbus; |
1da177e4 LT |
1090 | int polarity; |
1091 | ||
1092 | /* | |
1093 | * Determine IRQ line polarity (high active or low active): | |
1094 | */ | |
54168ed7 | 1095 | switch (mp_irqs[idx].mp_irqflag & 3) |
36062448 | 1096 | { |
54168ed7 IM |
1097 | case 0: /* conforms, ie. bus-type dependent polarity */ |
1098 | if (test_bit(bus, mp_bus_not_pci)) | |
1099 | polarity = default_ISA_polarity(idx); | |
1100 | else | |
1101 | polarity = default_PCI_polarity(idx); | |
1102 | break; | |
1103 | case 1: /* high active */ | |
1104 | { | |
1105 | polarity = 0; | |
1106 | break; | |
1107 | } | |
1108 | case 2: /* reserved */ | |
1109 | { | |
1110 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1111 | polarity = 1; | |
1112 | break; | |
1113 | } | |
1114 | case 3: /* low active */ | |
1115 | { | |
1116 | polarity = 1; | |
1117 | break; | |
1118 | } | |
1119 | default: /* invalid */ | |
1120 | { | |
1121 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1122 | polarity = 1; | |
1123 | break; | |
1124 | } | |
1da177e4 LT |
1125 | } |
1126 | return polarity; | |
1127 | } | |
1128 | ||
1129 | static int MPBIOS_trigger(int idx) | |
1130 | { | |
2fddb6e2 | 1131 | int bus = mp_irqs[idx].mp_srcbus; |
1da177e4 LT |
1132 | int trigger; |
1133 | ||
1134 | /* | |
1135 | * Determine IRQ trigger mode (edge or level sensitive): | |
1136 | */ | |
54168ed7 | 1137 | switch ((mp_irqs[idx].mp_irqflag>>2) & 3) |
1da177e4 | 1138 | { |
54168ed7 IM |
1139 | case 0: /* conforms, ie. bus-type dependent */ |
1140 | if (test_bit(bus, mp_bus_not_pci)) | |
1141 | trigger = default_ISA_trigger(idx); | |
1142 | else | |
1143 | trigger = default_PCI_trigger(idx); | |
c0a282c2 | 1144 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
54168ed7 IM |
1145 | switch (mp_bus_id_to_type[bus]) { |
1146 | case MP_BUS_ISA: /* ISA pin */ | |
1147 | { | |
1148 | /* set before the switch */ | |
1149 | break; | |
1150 | } | |
1151 | case MP_BUS_EISA: /* EISA pin */ | |
1152 | { | |
1153 | trigger = default_EISA_trigger(idx); | |
1154 | break; | |
1155 | } | |
1156 | case MP_BUS_PCI: /* PCI pin */ | |
1157 | { | |
1158 | /* set before the switch */ | |
1159 | break; | |
1160 | } | |
1161 | case MP_BUS_MCA: /* MCA pin */ | |
1162 | { | |
1163 | trigger = default_MCA_trigger(idx); | |
1164 | break; | |
1165 | } | |
1166 | default: | |
1167 | { | |
1168 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1169 | trigger = 1; | |
1170 | break; | |
1171 | } | |
1172 | } | |
1173 | #endif | |
1da177e4 | 1174 | break; |
54168ed7 | 1175 | case 1: /* edge */ |
1da177e4 | 1176 | { |
54168ed7 | 1177 | trigger = 0; |
1da177e4 LT |
1178 | break; |
1179 | } | |
54168ed7 | 1180 | case 2: /* reserved */ |
1da177e4 | 1181 | { |
54168ed7 IM |
1182 | printk(KERN_WARNING "broken BIOS!!\n"); |
1183 | trigger = 1; | |
1da177e4 LT |
1184 | break; |
1185 | } | |
54168ed7 | 1186 | case 3: /* level */ |
1da177e4 | 1187 | { |
54168ed7 | 1188 | trigger = 1; |
1da177e4 LT |
1189 | break; |
1190 | } | |
54168ed7 | 1191 | default: /* invalid */ |
1da177e4 LT |
1192 | { |
1193 | printk(KERN_WARNING "broken BIOS!!\n"); | |
54168ed7 | 1194 | trigger = 0; |
1da177e4 LT |
1195 | break; |
1196 | } | |
1197 | } | |
1198 | return trigger; | |
1199 | } | |
1200 | ||
1201 | static inline int irq_polarity(int idx) | |
1202 | { | |
1203 | return MPBIOS_polarity(idx); | |
1204 | } | |
1205 | ||
1206 | static inline int irq_trigger(int idx) | |
1207 | { | |
1208 | return MPBIOS_trigger(idx); | |
1209 | } | |
1210 | ||
efa2559f | 1211 | int (*ioapic_renumber_irq)(int ioapic, int irq); |
1da177e4 LT |
1212 | static int pin_2_irq(int idx, int apic, int pin) |
1213 | { | |
1214 | int irq, i; | |
2fddb6e2 | 1215 | int bus = mp_irqs[idx].mp_srcbus; |
1da177e4 LT |
1216 | |
1217 | /* | |
1218 | * Debugging check, we are in big trouble if this message pops up! | |
1219 | */ | |
2fddb6e2 | 1220 | if (mp_irqs[idx].mp_dstirq != pin) |
1da177e4 LT |
1221 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); |
1222 | ||
54168ed7 | 1223 | if (test_bit(bus, mp_bus_not_pci)) { |
2fddb6e2 | 1224 | irq = mp_irqs[idx].mp_srcbusirq; |
54168ed7 | 1225 | } else { |
643befed AS |
1226 | /* |
1227 | * PCI IRQs are mapped in order | |
1228 | */ | |
1229 | i = irq = 0; | |
1230 | while (i < apic) | |
1231 | irq += nr_ioapic_registers[i++]; | |
1232 | irq += pin; | |
d6c88a50 | 1233 | /* |
54168ed7 IM |
1234 | * For MPS mode, so far only needed by ES7000 platform |
1235 | */ | |
d6c88a50 TG |
1236 | if (ioapic_renumber_irq) |
1237 | irq = ioapic_renumber_irq(apic, irq); | |
1da177e4 LT |
1238 | } |
1239 | ||
54168ed7 | 1240 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1241 | /* |
1242 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
1243 | */ | |
1244 | if ((pin >= 16) && (pin <= 23)) { | |
1245 | if (pirq_entries[pin-16] != -1) { | |
1246 | if (!pirq_entries[pin-16]) { | |
1247 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1248 | "disabling PIRQ%d\n", pin-16); | |
1249 | } else { | |
1250 | irq = pirq_entries[pin-16]; | |
1251 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1252 | "using PIRQ%d -> IRQ %d\n", | |
1253 | pin-16, irq); | |
1254 | } | |
1255 | } | |
1256 | } | |
54168ed7 IM |
1257 | #endif |
1258 | ||
1da177e4 LT |
1259 | return irq; |
1260 | } | |
1261 | ||
497c9a19 YL |
1262 | void lock_vector_lock(void) |
1263 | { | |
1264 | /* Used to the online set of cpus does not change | |
1265 | * during assign_irq_vector. | |
1266 | */ | |
1267 | spin_lock(&vector_lock); | |
1268 | } | |
1da177e4 | 1269 | |
497c9a19 | 1270 | void unlock_vector_lock(void) |
1da177e4 | 1271 | { |
497c9a19 YL |
1272 | spin_unlock(&vector_lock); |
1273 | } | |
1da177e4 | 1274 | |
e7986739 MT |
1275 | static int |
1276 | __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
497c9a19 | 1277 | { |
047c8fdb YL |
1278 | /* |
1279 | * NOTE! The local APIC isn't very good at handling | |
1280 | * multiple interrupts at the same interrupt level. | |
1281 | * As the interrupt level is determined by taking the | |
1282 | * vector number and shifting that right by 4, we | |
1283 | * want to spread these out a bit so that they don't | |
1284 | * all fall in the same interrupt level. | |
1285 | * | |
1286 | * Also, we've got to be careful not to trash gate | |
1287 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
1288 | */ | |
54168ed7 IM |
1289 | static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0; |
1290 | unsigned int old_vector; | |
22f65d31 MT |
1291 | int cpu, err; |
1292 | cpumask_var_t tmp_mask; | |
ace80ab7 | 1293 | |
3145e941 YL |
1294 | if ((cfg->move_in_progress) || cfg->move_cleanup_count) |
1295 | return -EBUSY; | |
8339f000 | 1296 | |
22f65d31 MT |
1297 | if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC)) |
1298 | return -ENOMEM; | |
1299 | ||
54168ed7 IM |
1300 | old_vector = cfg->vector; |
1301 | if (old_vector) { | |
22f65d31 MT |
1302 | cpumask_and(tmp_mask, mask, cpu_online_mask); |
1303 | cpumask_and(tmp_mask, cfg->domain, tmp_mask); | |
1304 | if (!cpumask_empty(tmp_mask)) { | |
1305 | free_cpumask_var(tmp_mask); | |
54168ed7 | 1306 | return 0; |
22f65d31 | 1307 | } |
54168ed7 | 1308 | } |
497c9a19 | 1309 | |
e7986739 | 1310 | /* Only try and allocate irqs on cpus that are present */ |
22f65d31 MT |
1311 | err = -ENOSPC; |
1312 | for_each_cpu_and(cpu, mask, cpu_online_mask) { | |
54168ed7 IM |
1313 | int new_cpu; |
1314 | int vector, offset; | |
497c9a19 | 1315 | |
22f65d31 | 1316 | vector_allocation_domain(cpu, tmp_mask); |
497c9a19 | 1317 | |
54168ed7 IM |
1318 | vector = current_vector; |
1319 | offset = current_offset; | |
497c9a19 | 1320 | next: |
54168ed7 IM |
1321 | vector += 8; |
1322 | if (vector >= first_system_vector) { | |
e7986739 | 1323 | /* If out of vectors on large boxen, must share them. */ |
54168ed7 IM |
1324 | offset = (offset + 1) % 8; |
1325 | vector = FIRST_DEVICE_VECTOR + offset; | |
1326 | } | |
1327 | if (unlikely(current_vector == vector)) | |
1328 | continue; | |
047c8fdb | 1329 | #ifdef CONFIG_X86_64 |
54168ed7 IM |
1330 | if (vector == IA32_SYSCALL_VECTOR) |
1331 | goto next; | |
047c8fdb | 1332 | #else |
54168ed7 IM |
1333 | if (vector == SYSCALL_VECTOR) |
1334 | goto next; | |
047c8fdb | 1335 | #endif |
22f65d31 | 1336 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1337 | if (per_cpu(vector_irq, new_cpu)[vector] != -1) |
1338 | goto next; | |
1339 | /* Found one! */ | |
1340 | current_vector = vector; | |
1341 | current_offset = offset; | |
1342 | if (old_vector) { | |
1343 | cfg->move_in_progress = 1; | |
22f65d31 | 1344 | cpumask_copy(cfg->old_domain, cfg->domain); |
7a959cff | 1345 | } |
22f65d31 | 1346 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1347 | per_cpu(vector_irq, new_cpu)[vector] = irq; |
1348 | cfg->vector = vector; | |
22f65d31 MT |
1349 | cpumask_copy(cfg->domain, tmp_mask); |
1350 | err = 0; | |
1351 | break; | |
54168ed7 | 1352 | } |
22f65d31 MT |
1353 | free_cpumask_var(tmp_mask); |
1354 | return err; | |
497c9a19 YL |
1355 | } |
1356 | ||
e7986739 MT |
1357 | static int |
1358 | assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
497c9a19 YL |
1359 | { |
1360 | int err; | |
ace80ab7 | 1361 | unsigned long flags; |
ace80ab7 EB |
1362 | |
1363 | spin_lock_irqsave(&vector_lock, flags); | |
3145e941 | 1364 | err = __assign_irq_vector(irq, cfg, mask); |
26a3c49c | 1365 | spin_unlock_irqrestore(&vector_lock, flags); |
497c9a19 YL |
1366 | return err; |
1367 | } | |
1368 | ||
3145e941 | 1369 | static void __clear_irq_vector(int irq, struct irq_cfg *cfg) |
497c9a19 | 1370 | { |
497c9a19 YL |
1371 | int cpu, vector; |
1372 | ||
497c9a19 YL |
1373 | BUG_ON(!cfg->vector); |
1374 | ||
1375 | vector = cfg->vector; | |
22f65d31 | 1376 | for_each_cpu_and(cpu, cfg->domain, cpu_online_mask) |
497c9a19 YL |
1377 | per_cpu(vector_irq, cpu)[vector] = -1; |
1378 | ||
1379 | cfg->vector = 0; | |
22f65d31 | 1380 | cpumask_clear(cfg->domain); |
0ca4b6b0 MW |
1381 | |
1382 | if (likely(!cfg->move_in_progress)) | |
1383 | return; | |
22f65d31 | 1384 | for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) { |
0ca4b6b0 MW |
1385 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; |
1386 | vector++) { | |
1387 | if (per_cpu(vector_irq, cpu)[vector] != irq) | |
1388 | continue; | |
1389 | per_cpu(vector_irq, cpu)[vector] = -1; | |
1390 | break; | |
1391 | } | |
1392 | } | |
1393 | cfg->move_in_progress = 0; | |
497c9a19 YL |
1394 | } |
1395 | ||
1396 | void __setup_vector_irq(int cpu) | |
1397 | { | |
1398 | /* Initialize vector_irq on a new cpu */ | |
1399 | /* This function must be called with vector_lock held */ | |
1400 | int irq, vector; | |
1401 | struct irq_cfg *cfg; | |
0b8f1efa | 1402 | struct irq_desc *desc; |
497c9a19 YL |
1403 | |
1404 | /* Mark the inuse vectors */ | |
0b8f1efa YL |
1405 | for_each_irq_desc(irq, desc) { |
1406 | if (!desc) | |
1407 | continue; | |
1408 | cfg = desc->chip_data; | |
22f65d31 | 1409 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 YL |
1410 | continue; |
1411 | vector = cfg->vector; | |
497c9a19 YL |
1412 | per_cpu(vector_irq, cpu)[vector] = irq; |
1413 | } | |
1414 | /* Mark the free vectors */ | |
1415 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
1416 | irq = per_cpu(vector_irq, cpu)[vector]; | |
1417 | if (irq < 0) | |
1418 | continue; | |
1419 | ||
1420 | cfg = irq_cfg(irq); | |
22f65d31 | 1421 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 | 1422 | per_cpu(vector_irq, cpu)[vector] = -1; |
54168ed7 | 1423 | } |
1da177e4 | 1424 | } |
3fde6900 | 1425 | |
f5b9ed7a | 1426 | static struct irq_chip ioapic_chip; |
54168ed7 IM |
1427 | #ifdef CONFIG_INTR_REMAP |
1428 | static struct irq_chip ir_ioapic_chip; | |
1429 | #endif | |
1da177e4 | 1430 | |
54168ed7 IM |
1431 | #define IOAPIC_AUTO -1 |
1432 | #define IOAPIC_EDGE 0 | |
1433 | #define IOAPIC_LEVEL 1 | |
1da177e4 | 1434 | |
047c8fdb | 1435 | #ifdef CONFIG_X86_32 |
1d025192 YL |
1436 | static inline int IO_APIC_irq_trigger(int irq) |
1437 | { | |
d6c88a50 | 1438 | int apic, idx, pin; |
1d025192 | 1439 | |
d6c88a50 TG |
1440 | for (apic = 0; apic < nr_ioapics; apic++) { |
1441 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1442 | idx = find_irq_entry(apic, pin, mp_INT); | |
1443 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin))) | |
1444 | return irq_trigger(idx); | |
1445 | } | |
1446 | } | |
1447 | /* | |
54168ed7 IM |
1448 | * nonexistent IRQs are edge default |
1449 | */ | |
d6c88a50 | 1450 | return 0; |
1d025192 | 1451 | } |
047c8fdb YL |
1452 | #else |
1453 | static inline int IO_APIC_irq_trigger(int irq) | |
1454 | { | |
54168ed7 | 1455 | return 1; |
047c8fdb YL |
1456 | } |
1457 | #endif | |
1d025192 | 1458 | |
3145e941 | 1459 | static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger) |
1da177e4 | 1460 | { |
199751d7 | 1461 | |
6ebcc00e | 1462 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
047c8fdb | 1463 | trigger == IOAPIC_LEVEL) |
08678b08 | 1464 | desc->status |= IRQ_LEVEL; |
047c8fdb YL |
1465 | else |
1466 | desc->status &= ~IRQ_LEVEL; | |
1467 | ||
54168ed7 IM |
1468 | #ifdef CONFIG_INTR_REMAP |
1469 | if (irq_remapped(irq)) { | |
1470 | desc->status |= IRQ_MOVE_PCNTXT; | |
1471 | if (trigger) | |
1472 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1473 | handle_fasteoi_irq, | |
1474 | "fasteoi"); | |
1475 | else | |
1476 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1477 | handle_edge_irq, "edge"); | |
1478 | return; | |
1479 | } | |
1480 | #endif | |
047c8fdb YL |
1481 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
1482 | trigger == IOAPIC_LEVEL) | |
a460e745 | 1483 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 IM |
1484 | handle_fasteoi_irq, |
1485 | "fasteoi"); | |
047c8fdb | 1486 | else |
a460e745 | 1487 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 | 1488 | handle_edge_irq, "edge"); |
1da177e4 LT |
1489 | } |
1490 | ||
497c9a19 YL |
1491 | static int setup_ioapic_entry(int apic, int irq, |
1492 | struct IO_APIC_route_entry *entry, | |
1493 | unsigned int destination, int trigger, | |
1494 | int polarity, int vector) | |
1da177e4 | 1495 | { |
497c9a19 YL |
1496 | /* |
1497 | * add it to the IO-APIC irq-routing table: | |
1498 | */ | |
1499 | memset(entry,0,sizeof(*entry)); | |
1500 | ||
54168ed7 IM |
1501 | #ifdef CONFIG_INTR_REMAP |
1502 | if (intr_remapping_enabled) { | |
1503 | struct intel_iommu *iommu = map_ioapic_to_ir(apic); | |
1504 | struct irte irte; | |
1505 | struct IR_IO_APIC_route_entry *ir_entry = | |
1506 | (struct IR_IO_APIC_route_entry *) entry; | |
1507 | int index; | |
1508 | ||
1509 | if (!iommu) | |
1510 | panic("No mapping iommu for ioapic %d\n", apic); | |
1511 | ||
1512 | index = alloc_irte(iommu, irq, 1); | |
1513 | if (index < 0) | |
1514 | panic("Failed to allocate IRTE for ioapic %d\n", apic); | |
1515 | ||
1516 | memset(&irte, 0, sizeof(irte)); | |
1517 | ||
1518 | irte.present = 1; | |
1519 | irte.dst_mode = INT_DEST_MODE; | |
1520 | irte.trigger_mode = trigger; | |
1521 | irte.dlvry_mode = INT_DELIVERY_MODE; | |
1522 | irte.vector = vector; | |
1523 | irte.dest_id = IRTE_DEST(destination); | |
1524 | ||
1525 | modify_irte(irq, &irte); | |
1526 | ||
1527 | ir_entry->index2 = (index >> 15) & 0x1; | |
1528 | ir_entry->zero = 0; | |
1529 | ir_entry->format = 1; | |
1530 | ir_entry->index = (index & 0x7fff); | |
1531 | } else | |
1532 | #endif | |
1533 | { | |
1534 | entry->delivery_mode = INT_DELIVERY_MODE; | |
1535 | entry->dest_mode = INT_DEST_MODE; | |
1536 | entry->dest = destination; | |
1537 | } | |
497c9a19 | 1538 | |
54168ed7 | 1539 | entry->mask = 0; /* enable IRQ */ |
497c9a19 YL |
1540 | entry->trigger = trigger; |
1541 | entry->polarity = polarity; | |
1542 | entry->vector = vector; | |
1543 | ||
1544 | /* Mask level triggered irqs. | |
1545 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. | |
1546 | */ | |
1547 | if (trigger) | |
1548 | entry->mask = 1; | |
497c9a19 YL |
1549 | return 0; |
1550 | } | |
1551 | ||
3145e941 | 1552 | static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq, struct irq_desc *desc, |
54168ed7 | 1553 | int trigger, int polarity) |
497c9a19 YL |
1554 | { |
1555 | struct irq_cfg *cfg; | |
1da177e4 | 1556 | struct IO_APIC_route_entry entry; |
22f65d31 | 1557 | unsigned int dest; |
497c9a19 YL |
1558 | |
1559 | if (!IO_APIC_IRQ(irq)) | |
1560 | return; | |
1561 | ||
3145e941 | 1562 | cfg = desc->chip_data; |
497c9a19 | 1563 | |
22f65d31 | 1564 | if (assign_irq_vector(irq, cfg, TARGET_CPUS)) |
497c9a19 YL |
1565 | return; |
1566 | ||
22f65d31 | 1567 | dest = cpu_mask_to_apicid_and(cfg->domain, TARGET_CPUS); |
497c9a19 YL |
1568 | |
1569 | apic_printk(APIC_VERBOSE,KERN_DEBUG | |
1570 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " | |
1571 | "IRQ %d Mode:%i Active:%i)\n", | |
1572 | apic, mp_ioapics[apic].mp_apicid, pin, cfg->vector, | |
1573 | irq, trigger, polarity); | |
1574 | ||
1575 | ||
1576 | if (setup_ioapic_entry(mp_ioapics[apic].mp_apicid, irq, &entry, | |
22f65d31 | 1577 | dest, trigger, polarity, cfg->vector)) { |
497c9a19 YL |
1578 | printk("Failed to setup ioapic entry for ioapic %d, pin %d\n", |
1579 | mp_ioapics[apic].mp_apicid, pin); | |
3145e941 | 1580 | __clear_irq_vector(irq, cfg); |
497c9a19 YL |
1581 | return; |
1582 | } | |
1583 | ||
3145e941 | 1584 | ioapic_register_intr(irq, desc, trigger); |
99d093d1 | 1585 | if (irq < NR_IRQS_LEGACY) |
497c9a19 YL |
1586 | disable_8259A_irq(irq); |
1587 | ||
1588 | ioapic_write_entry(apic, pin, entry); | |
1589 | } | |
1590 | ||
1591 | static void __init setup_IO_APIC_irqs(void) | |
1592 | { | |
3c2cbd24 CG |
1593 | int apic, pin, idx, irq; |
1594 | int notcon = 0; | |
0b8f1efa | 1595 | struct irq_desc *desc; |
3145e941 | 1596 | struct irq_cfg *cfg; |
0b8f1efa | 1597 | int cpu = boot_cpu_id; |
1da177e4 LT |
1598 | |
1599 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1600 | ||
1601 | for (apic = 0; apic < nr_ioapics; apic++) { | |
3c2cbd24 | 1602 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
20d225b9 | 1603 | |
3c2cbd24 CG |
1604 | idx = find_irq_entry(apic, pin, mp_INT); |
1605 | if (idx == -1) { | |
2a554fb1 | 1606 | if (!notcon) { |
3c2cbd24 | 1607 | notcon = 1; |
2a554fb1 CG |
1608 | apic_printk(APIC_VERBOSE, |
1609 | KERN_DEBUG " %d-%d", | |
1610 | mp_ioapics[apic].mp_apicid, | |
1611 | pin); | |
1612 | } else | |
1613 | apic_printk(APIC_VERBOSE, " %d-%d", | |
1614 | mp_ioapics[apic].mp_apicid, | |
1615 | pin); | |
3c2cbd24 CG |
1616 | continue; |
1617 | } | |
56ffa1a0 CG |
1618 | if (notcon) { |
1619 | apic_printk(APIC_VERBOSE, | |
1620 | " (apicid-pin) not connected\n"); | |
1621 | notcon = 0; | |
1622 | } | |
3c2cbd24 CG |
1623 | |
1624 | irq = pin_2_irq(idx, apic, pin); | |
54168ed7 | 1625 | #ifdef CONFIG_X86_32 |
3c2cbd24 CG |
1626 | if (multi_timer_check(apic, irq)) |
1627 | continue; | |
54168ed7 | 1628 | #endif |
0b8f1efa YL |
1629 | desc = irq_to_desc_alloc_cpu(irq, cpu); |
1630 | if (!desc) { | |
1631 | printk(KERN_INFO "can not get irq_desc for %d\n", irq); | |
1632 | continue; | |
1633 | } | |
3145e941 YL |
1634 | cfg = desc->chip_data; |
1635 | add_pin_to_irq_cpu(cfg, cpu, apic, pin); | |
36062448 | 1636 | |
3145e941 | 1637 | setup_IO_APIC_irq(apic, pin, irq, desc, |
3c2cbd24 CG |
1638 | irq_trigger(idx), irq_polarity(idx)); |
1639 | } | |
1da177e4 LT |
1640 | } |
1641 | ||
3c2cbd24 CG |
1642 | if (notcon) |
1643 | apic_printk(APIC_VERBOSE, | |
2a554fb1 | 1644 | " (apicid-pin) not connected\n"); |
1da177e4 LT |
1645 | } |
1646 | ||
1647 | /* | |
f7633ce5 | 1648 | * Set up the timer pin, possibly with the 8259A-master behind. |
1da177e4 | 1649 | */ |
f7633ce5 MR |
1650 | static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin, |
1651 | int vector) | |
1da177e4 LT |
1652 | { |
1653 | struct IO_APIC_route_entry entry; | |
1da177e4 | 1654 | |
54168ed7 IM |
1655 | #ifdef CONFIG_INTR_REMAP |
1656 | if (intr_remapping_enabled) | |
1657 | return; | |
1658 | #endif | |
1659 | ||
36062448 | 1660 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
1661 | |
1662 | /* | |
1663 | * We use logical delivery to get the timer IRQ | |
1664 | * to the first CPU. | |
1665 | */ | |
1666 | entry.dest_mode = INT_DEST_MODE; | |
03be7505 | 1667 | entry.mask = 1; /* mask IRQ now */ |
d83e94ac | 1668 | entry.dest = cpu_mask_to_apicid(TARGET_CPUS); |
1da177e4 LT |
1669 | entry.delivery_mode = INT_DELIVERY_MODE; |
1670 | entry.polarity = 0; | |
1671 | entry.trigger = 0; | |
1672 | entry.vector = vector; | |
1673 | ||
1674 | /* | |
1675 | * The timer IRQ doesn't have to know that behind the | |
f7633ce5 | 1676 | * scene we may have a 8259A-master in AEOI mode ... |
1da177e4 | 1677 | */ |
54168ed7 | 1678 | set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge"); |
1da177e4 LT |
1679 | |
1680 | /* | |
1681 | * Add it to the IO-APIC irq-routing table: | |
1682 | */ | |
cf4c6a2f | 1683 | ioapic_write_entry(apic, pin, entry); |
1da177e4 LT |
1684 | } |
1685 | ||
32f71aff MR |
1686 | |
1687 | __apicdebuginit(void) print_IO_APIC(void) | |
1da177e4 LT |
1688 | { |
1689 | int apic, i; | |
1690 | union IO_APIC_reg_00 reg_00; | |
1691 | union IO_APIC_reg_01 reg_01; | |
1692 | union IO_APIC_reg_02 reg_02; | |
1693 | union IO_APIC_reg_03 reg_03; | |
1694 | unsigned long flags; | |
0f978f45 | 1695 | struct irq_cfg *cfg; |
0b8f1efa | 1696 | struct irq_desc *desc; |
8f09cd20 | 1697 | unsigned int irq; |
1da177e4 LT |
1698 | |
1699 | if (apic_verbosity == APIC_QUIET) | |
1700 | return; | |
1701 | ||
36062448 | 1702 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); |
1da177e4 LT |
1703 | for (i = 0; i < nr_ioapics; i++) |
1704 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", | |
ec2cd0a2 | 1705 | mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]); |
1da177e4 LT |
1706 | |
1707 | /* | |
1708 | * We are a bit conservative about what we expect. We have to | |
1709 | * know about every hardware change ASAP. | |
1710 | */ | |
1711 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1712 | ||
1713 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1714 | ||
1715 | spin_lock_irqsave(&ioapic_lock, flags); | |
1716 | reg_00.raw = io_apic_read(apic, 0); | |
1717 | reg_01.raw = io_apic_read(apic, 1); | |
1718 | if (reg_01.bits.version >= 0x10) | |
1719 | reg_02.raw = io_apic_read(apic, 2); | |
d6c88a50 TG |
1720 | if (reg_01.bits.version >= 0x20) |
1721 | reg_03.raw = io_apic_read(apic, 3); | |
1da177e4 LT |
1722 | spin_unlock_irqrestore(&ioapic_lock, flags); |
1723 | ||
54168ed7 | 1724 | printk("\n"); |
ec2cd0a2 | 1725 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
1726 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1727 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1728 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1729 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 | 1730 | |
54168ed7 | 1731 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); |
1da177e4 | 1732 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); |
1da177e4 LT |
1733 | |
1734 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
1735 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); | |
1da177e4 LT |
1736 | |
1737 | /* | |
1738 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1739 | * but the value of reg_02 is read as the previous read register | |
1740 | * value, so ignore it if reg_02 == reg_01. | |
1741 | */ | |
1742 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1743 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1744 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1745 | } |
1746 | ||
1747 | /* | |
1748 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1749 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1750 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1751 | */ | |
1752 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1753 | reg_03.raw != reg_01.raw) { | |
1754 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1755 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1756 | } |
1757 | ||
1758 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1759 | ||
d83e94ac YL |
1760 | printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol" |
1761 | " Stat Dmod Deli Vect: \n"); | |
1da177e4 LT |
1762 | |
1763 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
1764 | struct IO_APIC_route_entry entry; | |
1765 | ||
cf4c6a2f | 1766 | entry = ioapic_read_entry(apic, i); |
1da177e4 | 1767 | |
54168ed7 IM |
1768 | printk(KERN_DEBUG " %02x %03X ", |
1769 | i, | |
1770 | entry.dest | |
1771 | ); | |
1da177e4 LT |
1772 | |
1773 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", | |
1774 | entry.mask, | |
1775 | entry.trigger, | |
1776 | entry.irr, | |
1777 | entry.polarity, | |
1778 | entry.delivery_status, | |
1779 | entry.dest_mode, | |
1780 | entry.delivery_mode, | |
1781 | entry.vector | |
1782 | ); | |
1783 | } | |
1784 | } | |
1da177e4 | 1785 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
0b8f1efa YL |
1786 | for_each_irq_desc(irq, desc) { |
1787 | struct irq_pin_list *entry; | |
1788 | ||
1789 | if (!desc) | |
1790 | continue; | |
1791 | cfg = desc->chip_data; | |
1792 | entry = cfg->irq_2_pin; | |
0f978f45 | 1793 | if (!entry) |
1da177e4 | 1794 | continue; |
8f09cd20 | 1795 | printk(KERN_DEBUG "IRQ%d ", irq); |
1da177e4 LT |
1796 | for (;;) { |
1797 | printk("-> %d:%d", entry->apic, entry->pin); | |
1798 | if (!entry->next) | |
1799 | break; | |
0f978f45 | 1800 | entry = entry->next; |
1da177e4 LT |
1801 | } |
1802 | printk("\n"); | |
1803 | } | |
1804 | ||
1805 | printk(KERN_INFO ".................................... done.\n"); | |
1806 | ||
1807 | return; | |
1808 | } | |
1809 | ||
32f71aff | 1810 | __apicdebuginit(void) print_APIC_bitfield(int base) |
1da177e4 LT |
1811 | { |
1812 | unsigned int v; | |
1813 | int i, j; | |
1814 | ||
1815 | if (apic_verbosity == APIC_QUIET) | |
1816 | return; | |
1817 | ||
1818 | printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG); | |
1819 | for (i = 0; i < 8; i++) { | |
1820 | v = apic_read(base + i*0x10); | |
1821 | for (j = 0; j < 32; j++) { | |
1822 | if (v & (1<<j)) | |
1823 | printk("1"); | |
1824 | else | |
1825 | printk("0"); | |
1826 | } | |
1827 | printk("\n"); | |
1828 | } | |
1829 | } | |
1830 | ||
32f71aff | 1831 | __apicdebuginit(void) print_local_APIC(void *dummy) |
1da177e4 LT |
1832 | { |
1833 | unsigned int v, ver, maxlvt; | |
7ab6af7a | 1834 | u64 icr; |
1da177e4 LT |
1835 | |
1836 | if (apic_verbosity == APIC_QUIET) | |
1837 | return; | |
1838 | ||
1839 | printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", | |
1840 | smp_processor_id(), hard_smp_processor_id()); | |
66823114 | 1841 | v = apic_read(APIC_ID); |
54168ed7 | 1842 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
1da177e4 LT |
1843 | v = apic_read(APIC_LVR); |
1844 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1845 | ver = GET_APIC_VERSION(v); | |
e05d723f | 1846 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1847 | |
1848 | v = apic_read(APIC_TASKPRI); | |
1849 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1850 | ||
54168ed7 | 1851 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
a11b5abe YL |
1852 | if (!APIC_XAPIC(ver)) { |
1853 | v = apic_read(APIC_ARBPRI); | |
1854 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1855 | v & APIC_ARBPRI_MASK); | |
1856 | } | |
1da177e4 LT |
1857 | v = apic_read(APIC_PROCPRI); |
1858 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1859 | } | |
1860 | ||
a11b5abe YL |
1861 | /* |
1862 | * Remote read supported only in the 82489DX and local APIC for | |
1863 | * Pentium processors. | |
1864 | */ | |
1865 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
1866 | v = apic_read(APIC_RRR); | |
1867 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1868 | } | |
1869 | ||
1da177e4 LT |
1870 | v = apic_read(APIC_LDR); |
1871 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
a11b5abe YL |
1872 | if (!x2apic_enabled()) { |
1873 | v = apic_read(APIC_DFR); | |
1874 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1875 | } | |
1da177e4 LT |
1876 | v = apic_read(APIC_SPIV); |
1877 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1878 | ||
1879 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
1880 | print_APIC_bitfield(APIC_ISR); | |
1881 | printk(KERN_DEBUG "... APIC TMR field:\n"); | |
1882 | print_APIC_bitfield(APIC_TMR); | |
1883 | printk(KERN_DEBUG "... APIC IRR field:\n"); | |
1884 | print_APIC_bitfield(APIC_IRR); | |
1885 | ||
54168ed7 IM |
1886 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
1887 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1da177e4 | 1888 | apic_write(APIC_ESR, 0); |
54168ed7 | 1889 | |
1da177e4 LT |
1890 | v = apic_read(APIC_ESR); |
1891 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1892 | } | |
1893 | ||
7ab6af7a | 1894 | icr = apic_icr_read(); |
0c425cec IM |
1895 | printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr); |
1896 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
1da177e4 LT |
1897 | |
1898 | v = apic_read(APIC_LVTT); | |
1899 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1900 | ||
1901 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1902 | v = apic_read(APIC_LVTPC); | |
1903 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1904 | } | |
1905 | v = apic_read(APIC_LVT0); | |
1906 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1907 | v = apic_read(APIC_LVT1); | |
1908 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1909 | ||
1910 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1911 | v = apic_read(APIC_LVTERR); | |
1912 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1913 | } | |
1914 | ||
1915 | v = apic_read(APIC_TMICT); | |
1916 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1917 | v = apic_read(APIC_TMCCT); | |
1918 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1919 | v = apic_read(APIC_TDCR); | |
1920 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
1921 | printk("\n"); | |
1922 | } | |
1923 | ||
32f71aff | 1924 | __apicdebuginit(void) print_all_local_APICs(void) |
1da177e4 | 1925 | { |
ffd5aae7 YL |
1926 | int cpu; |
1927 | ||
1928 | preempt_disable(); | |
1929 | for_each_online_cpu(cpu) | |
1930 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); | |
1931 | preempt_enable(); | |
1da177e4 LT |
1932 | } |
1933 | ||
32f71aff | 1934 | __apicdebuginit(void) print_PIC(void) |
1da177e4 | 1935 | { |
1da177e4 LT |
1936 | unsigned int v; |
1937 | unsigned long flags; | |
1938 | ||
1939 | if (apic_verbosity == APIC_QUIET) | |
1940 | return; | |
1941 | ||
1942 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1943 | ||
1944 | spin_lock_irqsave(&i8259A_lock, flags); | |
1945 | ||
1946 | v = inb(0xa1) << 8 | inb(0x21); | |
1947 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1948 | ||
1949 | v = inb(0xa0) << 8 | inb(0x20); | |
1950 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1951 | ||
54168ed7 IM |
1952 | outb(0x0b,0xa0); |
1953 | outb(0x0b,0x20); | |
1da177e4 | 1954 | v = inb(0xa0) << 8 | inb(0x20); |
54168ed7 IM |
1955 | outb(0x0a,0xa0); |
1956 | outb(0x0a,0x20); | |
1da177e4 LT |
1957 | |
1958 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
1959 | ||
1960 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1961 | ||
1962 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1963 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1964 | } | |
1965 | ||
32f71aff MR |
1966 | __apicdebuginit(int) print_all_ICs(void) |
1967 | { | |
1968 | print_PIC(); | |
1969 | print_all_local_APICs(); | |
1970 | print_IO_APIC(); | |
1971 | ||
1972 | return 0; | |
1973 | } | |
1974 | ||
1975 | fs_initcall(print_all_ICs); | |
1976 | ||
1da177e4 | 1977 | |
efa2559f YL |
1978 | /* Where if anywhere is the i8259 connect in external int mode */ |
1979 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
1980 | ||
54168ed7 | 1981 | void __init enable_IO_APIC(void) |
1da177e4 LT |
1982 | { |
1983 | union IO_APIC_reg_01 reg_01; | |
fcfd636a | 1984 | int i8259_apic, i8259_pin; |
54168ed7 | 1985 | int apic; |
1da177e4 LT |
1986 | unsigned long flags; |
1987 | ||
54168ed7 IM |
1988 | #ifdef CONFIG_X86_32 |
1989 | int i; | |
1da177e4 LT |
1990 | if (!pirqs_enabled) |
1991 | for (i = 0; i < MAX_PIRQS; i++) | |
1992 | pirq_entries[i] = -1; | |
54168ed7 | 1993 | #endif |
1da177e4 LT |
1994 | |
1995 | /* | |
1996 | * The number of IO-APIC IRQ registers (== #pins): | |
1997 | */ | |
fcfd636a | 1998 | for (apic = 0; apic < nr_ioapics; apic++) { |
1da177e4 | 1999 | spin_lock_irqsave(&ioapic_lock, flags); |
fcfd636a | 2000 | reg_01.raw = io_apic_read(apic, 1); |
1da177e4 | 2001 | spin_unlock_irqrestore(&ioapic_lock, flags); |
fcfd636a EB |
2002 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; |
2003 | } | |
54168ed7 | 2004 | for(apic = 0; apic < nr_ioapics; apic++) { |
fcfd636a EB |
2005 | int pin; |
2006 | /* See if any of the pins is in ExtINT mode */ | |
1008fddc | 2007 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
fcfd636a | 2008 | struct IO_APIC_route_entry entry; |
cf4c6a2f | 2009 | entry = ioapic_read_entry(apic, pin); |
fcfd636a | 2010 | |
fcfd636a EB |
2011 | /* If the interrupt line is enabled and in ExtInt mode |
2012 | * I have found the pin where the i8259 is connected. | |
2013 | */ | |
2014 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
2015 | ioapic_i8259.apic = apic; | |
2016 | ioapic_i8259.pin = pin; | |
2017 | goto found_i8259; | |
2018 | } | |
2019 | } | |
2020 | } | |
2021 | found_i8259: | |
2022 | /* Look to see what if the MP table has reported the ExtINT */ | |
2023 | /* If we could not find the appropriate pin by looking at the ioapic | |
2024 | * the i8259 probably is not connected the ioapic but give the | |
2025 | * mptable a chance anyway. | |
2026 | */ | |
2027 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
2028 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
2029 | /* Trust the MP table if nothing is setup in the hardware */ | |
2030 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
2031 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
2032 | ioapic_i8259.pin = i8259_pin; | |
2033 | ioapic_i8259.apic = i8259_apic; | |
2034 | } | |
2035 | /* Complain if the MP table and the hardware disagree */ | |
2036 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
2037 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
2038 | { | |
2039 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
2040 | } |
2041 | ||
2042 | /* | |
2043 | * Do not trust the IO-APIC being empty at bootup | |
2044 | */ | |
2045 | clear_IO_APIC(); | |
2046 | } | |
2047 | ||
2048 | /* | |
2049 | * Not an __init, needed by the reboot code | |
2050 | */ | |
2051 | void disable_IO_APIC(void) | |
2052 | { | |
2053 | /* | |
2054 | * Clear the IO-APIC before rebooting: | |
2055 | */ | |
2056 | clear_IO_APIC(); | |
2057 | ||
650927ef | 2058 | /* |
0b968d23 | 2059 | * If the i8259 is routed through an IOAPIC |
650927ef | 2060 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 2061 | * so legacy interrupts can be delivered. |
650927ef | 2062 | */ |
fcfd636a | 2063 | if (ioapic_i8259.pin != -1) { |
650927ef | 2064 | struct IO_APIC_route_entry entry; |
650927ef EB |
2065 | |
2066 | memset(&entry, 0, sizeof(entry)); | |
2067 | entry.mask = 0; /* Enabled */ | |
2068 | entry.trigger = 0; /* Edge */ | |
2069 | entry.irr = 0; | |
2070 | entry.polarity = 0; /* High */ | |
2071 | entry.delivery_status = 0; | |
2072 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 2073 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 2074 | entry.vector = 0; |
54168ed7 | 2075 | entry.dest = read_apic_id(); |
650927ef EB |
2076 | |
2077 | /* | |
2078 | * Add it to the IO-APIC irq-routing table: | |
2079 | */ | |
cf4c6a2f | 2080 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 2081 | } |
54168ed7 | 2082 | |
fcfd636a | 2083 | disconnect_bsp_APIC(ioapic_i8259.pin != -1); |
1da177e4 LT |
2084 | } |
2085 | ||
54168ed7 | 2086 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
2087 | /* |
2088 | * function to set the IO-APIC physical IDs based on the | |
2089 | * values stored in the MPC table. | |
2090 | * | |
2091 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
2092 | */ | |
2093 | ||
1da177e4 LT |
2094 | static void __init setup_ioapic_ids_from_mpc(void) |
2095 | { | |
2096 | union IO_APIC_reg_00 reg_00; | |
2097 | physid_mask_t phys_id_present_map; | |
2098 | int apic; | |
2099 | int i; | |
2100 | unsigned char old_id; | |
2101 | unsigned long flags; | |
2102 | ||
a4dbc34d | 2103 | if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids()) |
d49c4288 | 2104 | return; |
d49c4288 | 2105 | |
ca05fea6 NP |
2106 | /* |
2107 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
2108 | * no meaning without the serial APIC bus. | |
2109 | */ | |
7c5c1e42 SL |
2110 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
2111 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
ca05fea6 | 2112 | return; |
1da177e4 LT |
2113 | /* |
2114 | * This is broken; anything with a real cpu count has to | |
2115 | * circumvent this idiocy regardless. | |
2116 | */ | |
2117 | phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map); | |
2118 | ||
2119 | /* | |
2120 | * Set the IOAPIC ID to the value stored in the MPC table. | |
2121 | */ | |
2122 | for (apic = 0; apic < nr_ioapics; apic++) { | |
2123 | ||
2124 | /* Read the register 0 value */ | |
2125 | spin_lock_irqsave(&ioapic_lock, flags); | |
2126 | reg_00.raw = io_apic_read(apic, 0); | |
2127 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
36062448 | 2128 | |
ec2cd0a2 | 2129 | old_id = mp_ioapics[apic].mp_apicid; |
1da177e4 | 2130 | |
ec2cd0a2 | 2131 | if (mp_ioapics[apic].mp_apicid >= get_physical_broadcast()) { |
1da177e4 | 2132 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
ec2cd0a2 | 2133 | apic, mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
2134 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
2135 | reg_00.bits.ID); | |
ec2cd0a2 | 2136 | mp_ioapics[apic].mp_apicid = reg_00.bits.ID; |
1da177e4 LT |
2137 | } |
2138 | ||
1da177e4 LT |
2139 | /* |
2140 | * Sanity check, is the ID really free? Every APIC in a | |
2141 | * system must have a unique ID or we get lots of nice | |
2142 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
2143 | */ | |
2144 | if (check_apicid_used(phys_id_present_map, | |
ec2cd0a2 | 2145 | mp_ioapics[apic].mp_apicid)) { |
1da177e4 | 2146 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
ec2cd0a2 | 2147 | apic, mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
2148 | for (i = 0; i < get_physical_broadcast(); i++) |
2149 | if (!physid_isset(i, phys_id_present_map)) | |
2150 | break; | |
2151 | if (i >= get_physical_broadcast()) | |
2152 | panic("Max APIC ID exceeded!\n"); | |
2153 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
2154 | i); | |
2155 | physid_set(i, phys_id_present_map); | |
ec2cd0a2 | 2156 | mp_ioapics[apic].mp_apicid = i; |
1da177e4 LT |
2157 | } else { |
2158 | physid_mask_t tmp; | |
ec2cd0a2 | 2159 | tmp = apicid_to_cpu_present(mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
2160 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
2161 | "phys_id_present_map\n", | |
ec2cd0a2 | 2162 | mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
2163 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
2164 | } | |
2165 | ||
2166 | ||
2167 | /* | |
2168 | * We need to adjust the IRQ routing table | |
2169 | * if the ID changed. | |
2170 | */ | |
ec2cd0a2 | 2171 | if (old_id != mp_ioapics[apic].mp_apicid) |
1da177e4 | 2172 | for (i = 0; i < mp_irq_entries; i++) |
2fddb6e2 AS |
2173 | if (mp_irqs[i].mp_dstapic == old_id) |
2174 | mp_irqs[i].mp_dstapic | |
ec2cd0a2 | 2175 | = mp_ioapics[apic].mp_apicid; |
1da177e4 LT |
2176 | |
2177 | /* | |
2178 | * Read the right value from the MPC table and | |
2179 | * write it into the ID register. | |
36062448 | 2180 | */ |
1da177e4 LT |
2181 | apic_printk(APIC_VERBOSE, KERN_INFO |
2182 | "...changing IO-APIC physical APIC ID to %d ...", | |
ec2cd0a2 | 2183 | mp_ioapics[apic].mp_apicid); |
1da177e4 | 2184 | |
ec2cd0a2 | 2185 | reg_00.bits.ID = mp_ioapics[apic].mp_apicid; |
1da177e4 | 2186 | spin_lock_irqsave(&ioapic_lock, flags); |
a2d332fa YL |
2187 | io_apic_write(apic, 0, reg_00.raw); |
2188 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1da177e4 LT |
2189 | |
2190 | /* | |
2191 | * Sanity check | |
2192 | */ | |
2193 | spin_lock_irqsave(&ioapic_lock, flags); | |
2194 | reg_00.raw = io_apic_read(apic, 0); | |
2195 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
ec2cd0a2 | 2196 | if (reg_00.bits.ID != mp_ioapics[apic].mp_apicid) |
1da177e4 LT |
2197 | printk("could not set ID!\n"); |
2198 | else | |
2199 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
2200 | } | |
2201 | } | |
54168ed7 | 2202 | #endif |
1da177e4 | 2203 | |
7ce0bcfd | 2204 | int no_timer_check __initdata; |
8542b200 ZA |
2205 | |
2206 | static int __init notimercheck(char *s) | |
2207 | { | |
2208 | no_timer_check = 1; | |
2209 | return 1; | |
2210 | } | |
2211 | __setup("no_timer_check", notimercheck); | |
2212 | ||
1da177e4 LT |
2213 | /* |
2214 | * There is a nasty bug in some older SMP boards, their mptable lies | |
2215 | * about the timer IRQ. We do the following to work around the situation: | |
2216 | * | |
2217 | * - timer IRQ defaults to IO-APIC IRQ | |
2218 | * - if this function detects that timer IRQs are defunct, then we fall | |
2219 | * back to ISA timer IRQs | |
2220 | */ | |
f0a7a5c9 | 2221 | static int __init timer_irq_works(void) |
1da177e4 LT |
2222 | { |
2223 | unsigned long t1 = jiffies; | |
4aae0702 | 2224 | unsigned long flags; |
1da177e4 | 2225 | |
8542b200 ZA |
2226 | if (no_timer_check) |
2227 | return 1; | |
2228 | ||
4aae0702 | 2229 | local_save_flags(flags); |
1da177e4 LT |
2230 | local_irq_enable(); |
2231 | /* Let ten ticks pass... */ | |
2232 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 2233 | local_irq_restore(flags); |
1da177e4 LT |
2234 | |
2235 | /* | |
2236 | * Expect a few ticks at least, to be sure some possible | |
2237 | * glue logic does not lock up after one or two first | |
2238 | * ticks in a non-ExtINT mode. Also the local APIC | |
2239 | * might have cached one ExtINT interrupt. Finally, at | |
2240 | * least one tick may be lost due to delays. | |
2241 | */ | |
54168ed7 IM |
2242 | |
2243 | /* jiffies wrap? */ | |
1d16b53e | 2244 | if (time_after(jiffies, t1 + 4)) |
1da177e4 | 2245 | return 1; |
1da177e4 LT |
2246 | return 0; |
2247 | } | |
2248 | ||
2249 | /* | |
2250 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
2251 | * number of pending IRQ events unhandled. These cases are very rare, | |
2252 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
2253 | * better to do it this way as thus we do not have to be aware of | |
2254 | * 'pending' interrupts in the IRQ path, except at this point. | |
2255 | */ | |
2256 | /* | |
2257 | * Edge triggered needs to resend any interrupt | |
2258 | * that was delayed but this is now handled in the device | |
2259 | * independent code. | |
2260 | */ | |
2261 | ||
2262 | /* | |
2263 | * Starting up a edge-triggered IO-APIC interrupt is | |
2264 | * nasty - we need to make sure that we get the edge. | |
2265 | * If it is already asserted for some reason, we need | |
2266 | * return 1 to indicate that is was pending. | |
2267 | * | |
2268 | * This is not complete - we should be able to fake | |
2269 | * an edge even if it isn't on the 8259A... | |
2270 | */ | |
54168ed7 | 2271 | |
f5b9ed7a | 2272 | static unsigned int startup_ioapic_irq(unsigned int irq) |
1da177e4 LT |
2273 | { |
2274 | int was_pending = 0; | |
2275 | unsigned long flags; | |
0b8f1efa | 2276 | struct irq_cfg *cfg; |
1da177e4 LT |
2277 | |
2278 | spin_lock_irqsave(&ioapic_lock, flags); | |
99d093d1 | 2279 | if (irq < NR_IRQS_LEGACY) { |
1da177e4 LT |
2280 | disable_8259A_irq(irq); |
2281 | if (i8259A_irq_pending(irq)) | |
2282 | was_pending = 1; | |
2283 | } | |
0b8f1efa | 2284 | cfg = irq_cfg(irq); |
3145e941 | 2285 | __unmask_IO_APIC_irq(cfg); |
1da177e4 LT |
2286 | spin_unlock_irqrestore(&ioapic_lock, flags); |
2287 | ||
2288 | return was_pending; | |
2289 | } | |
2290 | ||
54168ed7 | 2291 | #ifdef CONFIG_X86_64 |
ace80ab7 | 2292 | static int ioapic_retrigger_irq(unsigned int irq) |
1da177e4 | 2293 | { |
54168ed7 IM |
2294 | |
2295 | struct irq_cfg *cfg = irq_cfg(irq); | |
2296 | unsigned long flags; | |
2297 | ||
2298 | spin_lock_irqsave(&vector_lock, flags); | |
22f65d31 | 2299 | send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector); |
54168ed7 | 2300 | spin_unlock_irqrestore(&vector_lock, flags); |
c0ad90a3 IM |
2301 | |
2302 | return 1; | |
2303 | } | |
54168ed7 IM |
2304 | #else |
2305 | static int ioapic_retrigger_irq(unsigned int irq) | |
497c9a19 | 2306 | { |
d6c88a50 | 2307 | send_IPI_self(irq_cfg(irq)->vector); |
497c9a19 | 2308 | |
d6c88a50 | 2309 | return 1; |
54168ed7 IM |
2310 | } |
2311 | #endif | |
497c9a19 | 2312 | |
54168ed7 IM |
2313 | /* |
2314 | * Level and edge triggered IO-APIC interrupts need different handling, | |
2315 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be | |
2316 | * handled with the level-triggered descriptor, but that one has slightly | |
2317 | * more overhead. Level-triggered interrupts cannot be handled with the | |
2318 | * edge-triggered handler, without risking IRQ storms and other ugly | |
2319 | * races. | |
2320 | */ | |
497c9a19 | 2321 | |
54168ed7 | 2322 | #ifdef CONFIG_SMP |
497c9a19 | 2323 | |
54168ed7 IM |
2324 | #ifdef CONFIG_INTR_REMAP |
2325 | static void ir_irq_migration(struct work_struct *work); | |
497c9a19 | 2326 | |
54168ed7 | 2327 | static DECLARE_DELAYED_WORK(ir_migration_work, ir_irq_migration); |
497c9a19 | 2328 | |
54168ed7 IM |
2329 | /* |
2330 | * Migrate the IO-APIC irq in the presence of intr-remapping. | |
2331 | * | |
2332 | * For edge triggered, irq migration is a simple atomic update(of vector | |
2333 | * and cpu destination) of IRTE and flush the hardware cache. | |
2334 | * | |
2335 | * For level triggered, we need to modify the io-apic RTE aswell with the update | |
2336 | * vector information, along with modifying IRTE with vector and destination. | |
2337 | * So irq migration for level triggered is little bit more complex compared to | |
2338 | * edge triggered migration. But the good news is, we use the same algorithm | |
2339 | * for level triggered migration as we have today, only difference being, | |
2340 | * we now initiate the irq migration from process context instead of the | |
2341 | * interrupt context. | |
2342 | * | |
2343 | * In future, when we do a directed EOI (combined with cpu EOI broadcast | |
2344 | * suppression) to the IO-APIC, level triggered irq migration will also be | |
2345 | * as simple as edge triggered migration and we can do the irq migration | |
2346 | * with a simple atomic update to IO-APIC RTE. | |
2347 | */ | |
e7986739 MT |
2348 | static void |
2349 | migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask) | |
497c9a19 | 2350 | { |
54168ed7 | 2351 | struct irq_cfg *cfg; |
54168ed7 IM |
2352 | struct irte irte; |
2353 | int modify_ioapic_rte; | |
2354 | unsigned int dest; | |
2355 | unsigned long flags; | |
3145e941 | 2356 | unsigned int irq; |
497c9a19 | 2357 | |
22f65d31 | 2358 | if (!cpumask_intersects(mask, cpu_online_mask)) |
497c9a19 YL |
2359 | return; |
2360 | ||
3145e941 | 2361 | irq = desc->irq; |
54168ed7 IM |
2362 | if (get_irte(irq, &irte)) |
2363 | return; | |
497c9a19 | 2364 | |
3145e941 YL |
2365 | cfg = desc->chip_data; |
2366 | if (assign_irq_vector(irq, cfg, mask)) | |
54168ed7 IM |
2367 | return; |
2368 | ||
3145e941 YL |
2369 | set_extra_move_desc(desc, mask); |
2370 | ||
22f65d31 | 2371 | dest = cpu_mask_to_apicid_and(cfg->domain, mask); |
54168ed7 | 2372 | |
54168ed7 IM |
2373 | modify_ioapic_rte = desc->status & IRQ_LEVEL; |
2374 | if (modify_ioapic_rte) { | |
2375 | spin_lock_irqsave(&ioapic_lock, flags); | |
3145e941 | 2376 | __target_IO_APIC_irq(irq, dest, cfg); |
54168ed7 IM |
2377 | spin_unlock_irqrestore(&ioapic_lock, flags); |
2378 | } | |
2379 | ||
2380 | irte.vector = cfg->vector; | |
2381 | irte.dest_id = IRTE_DEST(dest); | |
2382 | ||
2383 | /* | |
2384 | * Modified the IRTE and flushes the Interrupt entry cache. | |
2385 | */ | |
2386 | modify_irte(irq, &irte); | |
2387 | ||
22f65d31 MT |
2388 | if (cfg->move_in_progress) |
2389 | send_cleanup_vector(cfg); | |
54168ed7 | 2390 | |
22f65d31 | 2391 | cpumask_copy(&desc->affinity, mask); |
54168ed7 IM |
2392 | } |
2393 | ||
3145e941 | 2394 | static int migrate_irq_remapped_level_desc(struct irq_desc *desc) |
54168ed7 IM |
2395 | { |
2396 | int ret = -1; | |
3145e941 | 2397 | struct irq_cfg *cfg = desc->chip_data; |
54168ed7 | 2398 | |
3145e941 | 2399 | mask_IO_APIC_irq_desc(desc); |
54168ed7 | 2400 | |
3145e941 | 2401 | if (io_apic_level_ack_pending(cfg)) { |
54168ed7 | 2402 | /* |
d6c88a50 | 2403 | * Interrupt in progress. Migrating irq now will change the |
54168ed7 IM |
2404 | * vector information in the IO-APIC RTE and that will confuse |
2405 | * the EOI broadcast performed by cpu. | |
2406 | * So, delay the irq migration to the next instance. | |
2407 | */ | |
2408 | schedule_delayed_work(&ir_migration_work, 1); | |
2409 | goto unmask; | |
2410 | } | |
2411 | ||
2412 | /* everthing is clear. we have right of way */ | |
e7986739 | 2413 | migrate_ioapic_irq_desc(desc, &desc->pending_mask); |
54168ed7 IM |
2414 | |
2415 | ret = 0; | |
2416 | desc->status &= ~IRQ_MOVE_PENDING; | |
22f65d31 | 2417 | cpumask_clear(&desc->pending_mask); |
54168ed7 IM |
2418 | |
2419 | unmask: | |
3145e941 YL |
2420 | unmask_IO_APIC_irq_desc(desc); |
2421 | ||
54168ed7 IM |
2422 | return ret; |
2423 | } | |
2424 | ||
2425 | static void ir_irq_migration(struct work_struct *work) | |
2426 | { | |
2427 | unsigned int irq; | |
2428 | struct irq_desc *desc; | |
2429 | ||
2430 | for_each_irq_desc(irq, desc) { | |
0b8f1efa YL |
2431 | if (!desc) |
2432 | continue; | |
2433 | ||
54168ed7 IM |
2434 | if (desc->status & IRQ_MOVE_PENDING) { |
2435 | unsigned long flags; | |
2436 | ||
2437 | spin_lock_irqsave(&desc->lock, flags); | |
2438 | if (!desc->chip->set_affinity || | |
2439 | !(desc->status & IRQ_MOVE_PENDING)) { | |
2440 | desc->status &= ~IRQ_MOVE_PENDING; | |
2441 | spin_unlock_irqrestore(&desc->lock, flags); | |
2442 | continue; | |
2443 | } | |
2444 | ||
0de26520 | 2445 | desc->chip->set_affinity(irq, &desc->pending_mask); |
54168ed7 IM |
2446 | spin_unlock_irqrestore(&desc->lock, flags); |
2447 | } | |
2448 | } | |
2449 | } | |
2450 | ||
2451 | /* | |
2452 | * Migrates the IRQ destination in the process context. | |
2453 | */ | |
968ea6d8 RR |
2454 | static void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc, |
2455 | const struct cpumask *mask) | |
54168ed7 | 2456 | { |
54168ed7 IM |
2457 | if (desc->status & IRQ_LEVEL) { |
2458 | desc->status |= IRQ_MOVE_PENDING; | |
0de26520 | 2459 | cpumask_copy(&desc->pending_mask, mask); |
3145e941 | 2460 | migrate_irq_remapped_level_desc(desc); |
54168ed7 IM |
2461 | return; |
2462 | } | |
2463 | ||
e7986739 | 2464 | migrate_ioapic_irq_desc(desc, mask); |
3145e941 | 2465 | } |
968ea6d8 RR |
2466 | static void set_ir_ioapic_affinity_irq(unsigned int irq, |
2467 | const struct cpumask *mask) | |
3145e941 YL |
2468 | { |
2469 | struct irq_desc *desc = irq_to_desc(irq); | |
2470 | ||
2471 | set_ir_ioapic_affinity_irq_desc(desc, mask); | |
54168ed7 IM |
2472 | } |
2473 | #endif | |
2474 | ||
2475 | asmlinkage void smp_irq_move_cleanup_interrupt(void) | |
2476 | { | |
2477 | unsigned vector, me; | |
2478 | ack_APIC_irq(); | |
2479 | #ifdef CONFIG_X86_64 | |
2480 | exit_idle(); | |
2481 | #endif | |
2482 | irq_enter(); | |
2483 | ||
2484 | me = smp_processor_id(); | |
2485 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
2486 | unsigned int irq; | |
2487 | struct irq_desc *desc; | |
2488 | struct irq_cfg *cfg; | |
2489 | irq = __get_cpu_var(vector_irq)[vector]; | |
2490 | ||
0b8f1efa YL |
2491 | if (irq == -1) |
2492 | continue; | |
2493 | ||
54168ed7 IM |
2494 | desc = irq_to_desc(irq); |
2495 | if (!desc) | |
2496 | continue; | |
2497 | ||
2498 | cfg = irq_cfg(irq); | |
2499 | spin_lock(&desc->lock); | |
2500 | if (!cfg->move_cleanup_count) | |
2501 | goto unlock; | |
2502 | ||
22f65d31 | 2503 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
54168ed7 IM |
2504 | goto unlock; |
2505 | ||
2506 | __get_cpu_var(vector_irq)[vector] = -1; | |
2507 | cfg->move_cleanup_count--; | |
2508 | unlock: | |
2509 | spin_unlock(&desc->lock); | |
2510 | } | |
2511 | ||
2512 | irq_exit(); | |
2513 | } | |
2514 | ||
3145e941 | 2515 | static void irq_complete_move(struct irq_desc **descp) |
54168ed7 | 2516 | { |
3145e941 YL |
2517 | struct irq_desc *desc = *descp; |
2518 | struct irq_cfg *cfg = desc->chip_data; | |
54168ed7 IM |
2519 | unsigned vector, me; |
2520 | ||
48a1b10a YL |
2521 | if (likely(!cfg->move_in_progress)) { |
2522 | #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC | |
2523 | if (likely(!cfg->move_desc_pending)) | |
2524 | return; | |
2525 | ||
2526 | /* domain is not change, but affinity is changed */ | |
2527 | me = smp_processor_id(); | |
2528 | if (cpu_isset(me, desc->affinity)) { | |
2529 | *descp = desc = move_irq_desc(desc, me); | |
2530 | /* get the new one */ | |
2531 | cfg = desc->chip_data; | |
2532 | cfg->move_desc_pending = 0; | |
2533 | } | |
2534 | #endif | |
54168ed7 | 2535 | return; |
48a1b10a | 2536 | } |
54168ed7 IM |
2537 | |
2538 | vector = ~get_irq_regs()->orig_ax; | |
2539 | me = smp_processor_id(); | |
48a1b10a YL |
2540 | #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC |
2541 | *descp = desc = move_irq_desc(desc, me); | |
2542 | /* get the new one */ | |
2543 | cfg = desc->chip_data; | |
2544 | #endif | |
2545 | ||
22f65d31 MT |
2546 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
2547 | send_cleanup_vector(cfg); | |
497c9a19 YL |
2548 | } |
2549 | #else | |
3145e941 | 2550 | static inline void irq_complete_move(struct irq_desc **descp) {} |
497c9a19 | 2551 | #endif |
3145e941 | 2552 | |
54168ed7 IM |
2553 | #ifdef CONFIG_INTR_REMAP |
2554 | static void ack_x2apic_level(unsigned int irq) | |
2555 | { | |
2556 | ack_x2APIC_irq(); | |
2557 | } | |
2558 | ||
2559 | static void ack_x2apic_edge(unsigned int irq) | |
2560 | { | |
2561 | ack_x2APIC_irq(); | |
2562 | } | |
3145e941 | 2563 | |
54168ed7 | 2564 | #endif |
497c9a19 | 2565 | |
1d025192 YL |
2566 | static void ack_apic_edge(unsigned int irq) |
2567 | { | |
3145e941 YL |
2568 | struct irq_desc *desc = irq_to_desc(irq); |
2569 | ||
2570 | irq_complete_move(&desc); | |
1d025192 YL |
2571 | move_native_irq(irq); |
2572 | ack_APIC_irq(); | |
2573 | } | |
2574 | ||
3eb2cce8 | 2575 | atomic_t irq_mis_count; |
3eb2cce8 | 2576 | |
047c8fdb YL |
2577 | static void ack_apic_level(unsigned int irq) |
2578 | { | |
3145e941 YL |
2579 | struct irq_desc *desc = irq_to_desc(irq); |
2580 | ||
3eb2cce8 YL |
2581 | #ifdef CONFIG_X86_32 |
2582 | unsigned long v; | |
2583 | int i; | |
2584 | #endif | |
3145e941 | 2585 | struct irq_cfg *cfg; |
54168ed7 | 2586 | int do_unmask_irq = 0; |
047c8fdb | 2587 | |
3145e941 | 2588 | irq_complete_move(&desc); |
047c8fdb | 2589 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
54168ed7 | 2590 | /* If we are moving the irq we need to mask it */ |
3145e941 | 2591 | if (unlikely(desc->status & IRQ_MOVE_PENDING)) { |
54168ed7 | 2592 | do_unmask_irq = 1; |
3145e941 | 2593 | mask_IO_APIC_irq_desc(desc); |
54168ed7 | 2594 | } |
047c8fdb YL |
2595 | #endif |
2596 | ||
3eb2cce8 YL |
2597 | #ifdef CONFIG_X86_32 |
2598 | /* | |
2599 | * It appears there is an erratum which affects at least version 0x11 | |
2600 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
2601 | * chipsets). Under certain conditions a level-triggered interrupt is | |
2602 | * erroneously delivered as edge-triggered one but the respective IRR | |
2603 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
2604 | * message but it will never arrive and further interrupts are blocked | |
2605 | * from the source. The exact reason is so far unknown, but the | |
2606 | * phenomenon was observed when two consecutive interrupt requests | |
2607 | * from a given source get delivered to the same CPU and the source is | |
2608 | * temporarily disabled in between. | |
2609 | * | |
2610 | * A workaround is to simulate an EOI message manually. We achieve it | |
2611 | * by setting the trigger mode to edge and then to level when the edge | |
2612 | * trigger mode gets detected in the TMR of a local APIC for a | |
2613 | * level-triggered interrupt. We mask the source for the time of the | |
2614 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
2615 | * The idea is from Manfred Spraul. --macro | |
2616 | */ | |
3145e941 YL |
2617 | cfg = desc->chip_data; |
2618 | i = cfg->vector; | |
3eb2cce8 YL |
2619 | |
2620 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); | |
2621 | #endif | |
2622 | ||
54168ed7 IM |
2623 | /* |
2624 | * We must acknowledge the irq before we move it or the acknowledge will | |
2625 | * not propagate properly. | |
2626 | */ | |
2627 | ack_APIC_irq(); | |
2628 | ||
2629 | /* Now we can move and renable the irq */ | |
2630 | if (unlikely(do_unmask_irq)) { | |
2631 | /* Only migrate the irq if the ack has been received. | |
2632 | * | |
2633 | * On rare occasions the broadcast level triggered ack gets | |
2634 | * delayed going to ioapics, and if we reprogram the | |
2635 | * vector while Remote IRR is still set the irq will never | |
2636 | * fire again. | |
2637 | * | |
2638 | * To prevent this scenario we read the Remote IRR bit | |
2639 | * of the ioapic. This has two effects. | |
2640 | * - On any sane system the read of the ioapic will | |
2641 | * flush writes (and acks) going to the ioapic from | |
2642 | * this cpu. | |
2643 | * - We get to see if the ACK has actually been delivered. | |
2644 | * | |
2645 | * Based on failed experiments of reprogramming the | |
2646 | * ioapic entry from outside of irq context starting | |
2647 | * with masking the ioapic entry and then polling until | |
2648 | * Remote IRR was clear before reprogramming the | |
2649 | * ioapic I don't trust the Remote IRR bit to be | |
2650 | * completey accurate. | |
2651 | * | |
2652 | * However there appears to be no other way to plug | |
2653 | * this race, so if the Remote IRR bit is not | |
2654 | * accurate and is causing problems then it is a hardware bug | |
2655 | * and you can go talk to the chipset vendor about it. | |
2656 | */ | |
3145e941 YL |
2657 | cfg = desc->chip_data; |
2658 | if (!io_apic_level_ack_pending(cfg)) | |
54168ed7 | 2659 | move_masked_irq(irq); |
3145e941 | 2660 | unmask_IO_APIC_irq_desc(desc); |
54168ed7 | 2661 | } |
1d025192 | 2662 | |
3eb2cce8 | 2663 | #ifdef CONFIG_X86_32 |
1d025192 YL |
2664 | if (!(v & (1 << (i & 0x1f)))) { |
2665 | atomic_inc(&irq_mis_count); | |
2666 | spin_lock(&ioapic_lock); | |
3145e941 YL |
2667 | __mask_and_edge_IO_APIC_irq(cfg); |
2668 | __unmask_and_level_IO_APIC_irq(cfg); | |
1d025192 YL |
2669 | spin_unlock(&ioapic_lock); |
2670 | } | |
047c8fdb | 2671 | #endif |
3eb2cce8 | 2672 | } |
1d025192 | 2673 | |
f5b9ed7a | 2674 | static struct irq_chip ioapic_chip __read_mostly = { |
d6c88a50 TG |
2675 | .name = "IO-APIC", |
2676 | .startup = startup_ioapic_irq, | |
2677 | .mask = mask_IO_APIC_irq, | |
2678 | .unmask = unmask_IO_APIC_irq, | |
2679 | .ack = ack_apic_edge, | |
2680 | .eoi = ack_apic_level, | |
54d5d424 | 2681 | #ifdef CONFIG_SMP |
d6c88a50 | 2682 | .set_affinity = set_ioapic_affinity_irq, |
54d5d424 | 2683 | #endif |
ace80ab7 | 2684 | .retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
2685 | }; |
2686 | ||
54168ed7 IM |
2687 | #ifdef CONFIG_INTR_REMAP |
2688 | static struct irq_chip ir_ioapic_chip __read_mostly = { | |
d6c88a50 TG |
2689 | .name = "IR-IO-APIC", |
2690 | .startup = startup_ioapic_irq, | |
2691 | .mask = mask_IO_APIC_irq, | |
2692 | .unmask = unmask_IO_APIC_irq, | |
2693 | .ack = ack_x2apic_edge, | |
2694 | .eoi = ack_x2apic_level, | |
54168ed7 | 2695 | #ifdef CONFIG_SMP |
d6c88a50 | 2696 | .set_affinity = set_ir_ioapic_affinity_irq, |
54168ed7 IM |
2697 | #endif |
2698 | .retrigger = ioapic_retrigger_irq, | |
2699 | }; | |
2700 | #endif | |
1da177e4 LT |
2701 | |
2702 | static inline void init_IO_APIC_traps(void) | |
2703 | { | |
2704 | int irq; | |
08678b08 | 2705 | struct irq_desc *desc; |
da51a821 | 2706 | struct irq_cfg *cfg; |
1da177e4 LT |
2707 | |
2708 | /* | |
2709 | * NOTE! The local APIC isn't very good at handling | |
2710 | * multiple interrupts at the same interrupt level. | |
2711 | * As the interrupt level is determined by taking the | |
2712 | * vector number and shifting that right by 4, we | |
2713 | * want to spread these out a bit so that they don't | |
2714 | * all fall in the same interrupt level. | |
2715 | * | |
2716 | * Also, we've got to be careful not to trash gate | |
2717 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
2718 | */ | |
0b8f1efa YL |
2719 | for_each_irq_desc(irq, desc) { |
2720 | if (!desc) | |
2721 | continue; | |
2722 | ||
2723 | cfg = desc->chip_data; | |
2724 | if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { | |
1da177e4 LT |
2725 | /* |
2726 | * Hmm.. We don't have an entry for this, | |
2727 | * so default to an old-fashioned 8259 | |
2728 | * interrupt if we can.. | |
2729 | */ | |
99d093d1 | 2730 | if (irq < NR_IRQS_LEGACY) |
1da177e4 | 2731 | make_8259A_irq(irq); |
0b8f1efa | 2732 | else |
1da177e4 | 2733 | /* Strange. Oh, well.. */ |
08678b08 | 2734 | desc->chip = &no_irq_chip; |
1da177e4 LT |
2735 | } |
2736 | } | |
2737 | } | |
2738 | ||
f5b9ed7a IM |
2739 | /* |
2740 | * The local APIC irq-chip implementation: | |
2741 | */ | |
1da177e4 | 2742 | |
36062448 | 2743 | static void mask_lapic_irq(unsigned int irq) |
1da177e4 LT |
2744 | { |
2745 | unsigned long v; | |
2746 | ||
2747 | v = apic_read(APIC_LVT0); | |
593f4a78 | 2748 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
2749 | } |
2750 | ||
36062448 | 2751 | static void unmask_lapic_irq(unsigned int irq) |
1da177e4 | 2752 | { |
f5b9ed7a | 2753 | unsigned long v; |
1da177e4 | 2754 | |
f5b9ed7a | 2755 | v = apic_read(APIC_LVT0); |
593f4a78 | 2756 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
f5b9ed7a | 2757 | } |
1da177e4 | 2758 | |
3145e941 | 2759 | static void ack_lapic_irq(unsigned int irq) |
1d025192 YL |
2760 | { |
2761 | ack_APIC_irq(); | |
2762 | } | |
2763 | ||
f5b9ed7a | 2764 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 2765 | .name = "local-APIC", |
f5b9ed7a IM |
2766 | .mask = mask_lapic_irq, |
2767 | .unmask = unmask_lapic_irq, | |
c88ac1df | 2768 | .ack = ack_lapic_irq, |
1da177e4 LT |
2769 | }; |
2770 | ||
3145e941 | 2771 | static void lapic_register_intr(int irq, struct irq_desc *desc) |
c88ac1df | 2772 | { |
08678b08 | 2773 | desc->status &= ~IRQ_LEVEL; |
c88ac1df MR |
2774 | set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
2775 | "edge"); | |
c88ac1df MR |
2776 | } |
2777 | ||
e9427101 | 2778 | static void __init setup_nmi(void) |
1da177e4 LT |
2779 | { |
2780 | /* | |
36062448 | 2781 | * Dirty trick to enable the NMI watchdog ... |
1da177e4 LT |
2782 | * We put the 8259A master into AEOI mode and |
2783 | * unmask on all local APICs LVT0 as NMI. | |
2784 | * | |
2785 | * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') | |
2786 | * is from Maciej W. Rozycki - so we do not have to EOI from | |
2787 | * the NMI handler or the timer interrupt. | |
36062448 | 2788 | */ |
1da177e4 LT |
2789 | apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ..."); |
2790 | ||
e9427101 | 2791 | enable_NMI_through_LVT0(); |
1da177e4 LT |
2792 | |
2793 | apic_printk(APIC_VERBOSE, " done.\n"); | |
2794 | } | |
2795 | ||
2796 | /* | |
2797 | * This looks a bit hackish but it's about the only one way of sending | |
2798 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2799 | * not support the ExtINT mode, unfortunately. We need to send these | |
2800 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2801 | * 8259A interrupt line asserted until INTA. --macro | |
2802 | */ | |
28acf285 | 2803 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2804 | { |
fcfd636a | 2805 | int apic, pin, i; |
1da177e4 LT |
2806 | struct IO_APIC_route_entry entry0, entry1; |
2807 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2808 | |
fcfd636a | 2809 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2810 | if (pin == -1) { |
2811 | WARN_ON_ONCE(1); | |
2812 | return; | |
2813 | } | |
fcfd636a | 2814 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2815 | if (apic == -1) { |
2816 | WARN_ON_ONCE(1); | |
1da177e4 | 2817 | return; |
956fb531 | 2818 | } |
1da177e4 | 2819 | |
cf4c6a2f | 2820 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2821 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2822 | |
2823 | memset(&entry1, 0, sizeof(entry1)); | |
2824 | ||
2825 | entry1.dest_mode = 0; /* physical delivery */ | |
2826 | entry1.mask = 0; /* unmask IRQ now */ | |
d83e94ac | 2827 | entry1.dest = hard_smp_processor_id(); |
1da177e4 LT |
2828 | entry1.delivery_mode = dest_ExtINT; |
2829 | entry1.polarity = entry0.polarity; | |
2830 | entry1.trigger = 0; | |
2831 | entry1.vector = 0; | |
2832 | ||
cf4c6a2f | 2833 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2834 | |
2835 | save_control = CMOS_READ(RTC_CONTROL); | |
2836 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2837 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2838 | RTC_FREQ_SELECT); | |
2839 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2840 | ||
2841 | i = 100; | |
2842 | while (i-- > 0) { | |
2843 | mdelay(10); | |
2844 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2845 | i -= 10; | |
2846 | } | |
2847 | ||
2848 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2849 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2850 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2851 | |
cf4c6a2f | 2852 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2853 | } |
2854 | ||
efa2559f | 2855 | static int disable_timer_pin_1 __initdata; |
047c8fdb | 2856 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
54168ed7 | 2857 | static int __init disable_timer_pin_setup(char *arg) |
efa2559f YL |
2858 | { |
2859 | disable_timer_pin_1 = 1; | |
2860 | return 0; | |
2861 | } | |
54168ed7 | 2862 | early_param("disable_timer_pin_1", disable_timer_pin_setup); |
efa2559f YL |
2863 | |
2864 | int timer_through_8259 __initdata; | |
2865 | ||
1da177e4 LT |
2866 | /* |
2867 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2868 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2869 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2870 | * fanatically on his truly buggy board. | |
54168ed7 IM |
2871 | * |
2872 | * FIXME: really need to revamp this for all platforms. | |
1da177e4 | 2873 | */ |
8542b200 | 2874 | static inline void __init check_timer(void) |
1da177e4 | 2875 | { |
3145e941 YL |
2876 | struct irq_desc *desc = irq_to_desc(0); |
2877 | struct irq_cfg *cfg = desc->chip_data; | |
2878 | int cpu = boot_cpu_id; | |
fcfd636a | 2879 | int apic1, pin1, apic2, pin2; |
4aae0702 | 2880 | unsigned long flags; |
047c8fdb YL |
2881 | unsigned int ver; |
2882 | int no_pin1 = 0; | |
4aae0702 IM |
2883 | |
2884 | local_irq_save(flags); | |
d4d25dec | 2885 | |
d6c88a50 TG |
2886 | ver = apic_read(APIC_LVR); |
2887 | ver = GET_APIC_VERSION(ver); | |
6e908947 | 2888 | |
1da177e4 LT |
2889 | /* |
2890 | * get/set the timer IRQ vector: | |
2891 | */ | |
2892 | disable_8259A_irq(0); | |
3145e941 | 2893 | assign_irq_vector(0, cfg, TARGET_CPUS); |
1da177e4 LT |
2894 | |
2895 | /* | |
d11d5794 MR |
2896 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2897 | * wire has to be disabled in the local APIC. Also | |
2898 | * timer interrupts need to be acknowledged manually in | |
2899 | * the 8259A for the i82489DX when using the NMI | |
2900 | * watchdog as that APIC treats NMIs as level-triggered. | |
2901 | * The AEOI mode will finish them in the 8259A | |
2902 | * automatically. | |
1da177e4 | 2903 | */ |
593f4a78 | 2904 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
1da177e4 | 2905 | init_8259A(1); |
54168ed7 | 2906 | #ifdef CONFIG_X86_32 |
d11d5794 | 2907 | timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver)); |
54168ed7 | 2908 | #endif |
1da177e4 | 2909 | |
fcfd636a EB |
2910 | pin1 = find_isa_irq_pin(0, mp_INT); |
2911 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2912 | pin2 = ioapic_i8259.pin; | |
2913 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2914 | |
49a66a0b MR |
2915 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
2916 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", | |
497c9a19 | 2917 | cfg->vector, apic1, pin1, apic2, pin2); |
1da177e4 | 2918 | |
691874fa MR |
2919 | /* |
2920 | * Some BIOS writers are clueless and report the ExtINTA | |
2921 | * I/O APIC input from the cascaded 8259A as the timer | |
2922 | * interrupt input. So just in case, if only one pin | |
2923 | * was found above, try it both directly and through the | |
2924 | * 8259A. | |
2925 | */ | |
2926 | if (pin1 == -1) { | |
54168ed7 IM |
2927 | #ifdef CONFIG_INTR_REMAP |
2928 | if (intr_remapping_enabled) | |
2929 | panic("BIOS bug: timer not connected to IO-APIC"); | |
2930 | #endif | |
691874fa MR |
2931 | pin1 = pin2; |
2932 | apic1 = apic2; | |
2933 | no_pin1 = 1; | |
2934 | } else if (pin2 == -1) { | |
2935 | pin2 = pin1; | |
2936 | apic2 = apic1; | |
2937 | } | |
2938 | ||
1da177e4 LT |
2939 | if (pin1 != -1) { |
2940 | /* | |
2941 | * Ok, does IRQ0 through the IOAPIC work? | |
2942 | */ | |
691874fa | 2943 | if (no_pin1) { |
3145e941 | 2944 | add_pin_to_irq_cpu(cfg, cpu, apic1, pin1); |
497c9a19 | 2945 | setup_timer_IRQ0_pin(apic1, pin1, cfg->vector); |
691874fa | 2946 | } |
3145e941 | 2947 | unmask_IO_APIC_irq_desc(desc); |
1da177e4 LT |
2948 | if (timer_irq_works()) { |
2949 | if (nmi_watchdog == NMI_IO_APIC) { | |
1da177e4 LT |
2950 | setup_nmi(); |
2951 | enable_8259A_irq(0); | |
1da177e4 | 2952 | } |
66759a01 CE |
2953 | if (disable_timer_pin_1 > 0) |
2954 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 2955 | goto out; |
1da177e4 | 2956 | } |
54168ed7 IM |
2957 | #ifdef CONFIG_INTR_REMAP |
2958 | if (intr_remapping_enabled) | |
2959 | panic("timer doesn't work through Interrupt-remapped IO-APIC"); | |
2960 | #endif | |
fcfd636a | 2961 | clear_IO_APIC_pin(apic1, pin1); |
691874fa | 2962 | if (!no_pin1) |
49a66a0b MR |
2963 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
2964 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 2965 | |
49a66a0b MR |
2966 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
2967 | "(IRQ0) through the 8259A ...\n"); | |
2968 | apic_printk(APIC_QUIET, KERN_INFO | |
2969 | "..... (found apic %d pin %d) ...\n", apic2, pin2); | |
1da177e4 LT |
2970 | /* |
2971 | * legacy devices should be connected to IO APIC #0 | |
2972 | */ | |
3145e941 | 2973 | replace_pin_at_irq_cpu(cfg, cpu, apic1, pin1, apic2, pin2); |
497c9a19 | 2974 | setup_timer_IRQ0_pin(apic2, pin2, cfg->vector); |
3145e941 | 2975 | unmask_IO_APIC_irq_desc(desc); |
ecd29476 | 2976 | enable_8259A_irq(0); |
1da177e4 | 2977 | if (timer_irq_works()) { |
49a66a0b | 2978 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
35542c5e | 2979 | timer_through_8259 = 1; |
1da177e4 | 2980 | if (nmi_watchdog == NMI_IO_APIC) { |
60134ebe | 2981 | disable_8259A_irq(0); |
1da177e4 | 2982 | setup_nmi(); |
60134ebe | 2983 | enable_8259A_irq(0); |
1da177e4 | 2984 | } |
4aae0702 | 2985 | goto out; |
1da177e4 LT |
2986 | } |
2987 | /* | |
2988 | * Cleanup, just in case ... | |
2989 | */ | |
ecd29476 | 2990 | disable_8259A_irq(0); |
fcfd636a | 2991 | clear_IO_APIC_pin(apic2, pin2); |
49a66a0b | 2992 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
1da177e4 | 2993 | } |
1da177e4 LT |
2994 | |
2995 | if (nmi_watchdog == NMI_IO_APIC) { | |
49a66a0b MR |
2996 | apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work " |
2997 | "through the IO-APIC - disabling NMI Watchdog!\n"); | |
067fa0ff | 2998 | nmi_watchdog = NMI_NONE; |
1da177e4 | 2999 | } |
54168ed7 | 3000 | #ifdef CONFIG_X86_32 |
d11d5794 | 3001 | timer_ack = 0; |
54168ed7 | 3002 | #endif |
1da177e4 | 3003 | |
49a66a0b MR |
3004 | apic_printk(APIC_QUIET, KERN_INFO |
3005 | "...trying to set up timer as Virtual Wire IRQ...\n"); | |
1da177e4 | 3006 | |
3145e941 | 3007 | lapic_register_intr(0, desc); |
497c9a19 | 3008 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ |
1da177e4 LT |
3009 | enable_8259A_irq(0); |
3010 | ||
3011 | if (timer_irq_works()) { | |
49a66a0b | 3012 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 3013 | goto out; |
1da177e4 | 3014 | } |
e67465f1 | 3015 | disable_8259A_irq(0); |
497c9a19 | 3016 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
49a66a0b | 3017 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
1da177e4 | 3018 | |
49a66a0b MR |
3019 | apic_printk(APIC_QUIET, KERN_INFO |
3020 | "...trying to set up timer as ExtINT IRQ...\n"); | |
1da177e4 | 3021 | |
1da177e4 LT |
3022 | init_8259A(0); |
3023 | make_8259A_irq(0); | |
593f4a78 | 3024 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
3025 | |
3026 | unlock_ExtINT_logic(); | |
3027 | ||
3028 | if (timer_irq_works()) { | |
49a66a0b | 3029 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 3030 | goto out; |
1da177e4 | 3031 | } |
49a66a0b | 3032 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
1da177e4 | 3033 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
49a66a0b | 3034 | "report. Then try booting with the 'noapic' option.\n"); |
4aae0702 IM |
3035 | out: |
3036 | local_irq_restore(flags); | |
1da177e4 LT |
3037 | } |
3038 | ||
3039 | /* | |
af174783 MR |
3040 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
3041 | * to devices. However there may be an I/O APIC pin available for | |
3042 | * this interrupt regardless. The pin may be left unconnected, but | |
3043 | * typically it will be reused as an ExtINT cascade interrupt for | |
3044 | * the master 8259A. In the MPS case such a pin will normally be | |
3045 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
3046 | * there is no provision for ExtINT interrupts, and in the absence | |
3047 | * of an override it would be treated as an ordinary ISA I/O APIC | |
3048 | * interrupt, that is edge-triggered and unmasked by default. We | |
3049 | * used to do this, but it caused problems on some systems because | |
3050 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
3051 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
3052 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
3053 | * the I/O APIC in all cases now. No actual device should request | |
3054 | * it anyway. --macro | |
1da177e4 LT |
3055 | */ |
3056 | #define PIC_IRQS (1 << PIC_CASCADE_IR) | |
3057 | ||
3058 | void __init setup_IO_APIC(void) | |
3059 | { | |
54168ed7 IM |
3060 | |
3061 | #ifdef CONFIG_X86_32 | |
1da177e4 | 3062 | enable_IO_APIC(); |
54168ed7 IM |
3063 | #else |
3064 | /* | |
3065 | * calling enable_IO_APIC() is moved to setup_local_APIC for BP | |
3066 | */ | |
3067 | #endif | |
1da177e4 | 3068 | |
af174783 | 3069 | io_apic_irqs = ~PIC_IRQS; |
1da177e4 | 3070 | |
54168ed7 | 3071 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); |
d6c88a50 | 3072 | /* |
54168ed7 IM |
3073 | * Set up IO-APIC IRQ routing. |
3074 | */ | |
3075 | #ifdef CONFIG_X86_32 | |
d6c88a50 TG |
3076 | if (!acpi_ioapic) |
3077 | setup_ioapic_ids_from_mpc(); | |
54168ed7 | 3078 | #endif |
1da177e4 LT |
3079 | sync_Arb_IDs(); |
3080 | setup_IO_APIC_irqs(); | |
3081 | init_IO_APIC_traps(); | |
1e4c85f9 | 3082 | check_timer(); |
1da177e4 LT |
3083 | } |
3084 | ||
3085 | /* | |
54168ed7 IM |
3086 | * Called after all the initialization is done. If we didnt find any |
3087 | * APIC bugs then we can allow the modify fast path | |
1da177e4 | 3088 | */ |
36062448 | 3089 | |
1da177e4 LT |
3090 | static int __init io_apic_bug_finalize(void) |
3091 | { | |
d6c88a50 TG |
3092 | if (sis_apic_bug == -1) |
3093 | sis_apic_bug = 0; | |
3094 | return 0; | |
1da177e4 LT |
3095 | } |
3096 | ||
3097 | late_initcall(io_apic_bug_finalize); | |
3098 | ||
3099 | struct sysfs_ioapic_data { | |
3100 | struct sys_device dev; | |
3101 | struct IO_APIC_route_entry entry[0]; | |
3102 | }; | |
54168ed7 | 3103 | static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS]; |
1da177e4 | 3104 | |
438510f6 | 3105 | static int ioapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
3106 | { |
3107 | struct IO_APIC_route_entry *entry; | |
3108 | struct sysfs_ioapic_data *data; | |
1da177e4 | 3109 | int i; |
36062448 | 3110 | |
1da177e4 LT |
3111 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
3112 | entry = data->entry; | |
54168ed7 IM |
3113 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) |
3114 | *entry = ioapic_read_entry(dev->id, i); | |
1da177e4 LT |
3115 | |
3116 | return 0; | |
3117 | } | |
3118 | ||
3119 | static int ioapic_resume(struct sys_device *dev) | |
3120 | { | |
3121 | struct IO_APIC_route_entry *entry; | |
3122 | struct sysfs_ioapic_data *data; | |
3123 | unsigned long flags; | |
3124 | union IO_APIC_reg_00 reg_00; | |
3125 | int i; | |
36062448 | 3126 | |
1da177e4 LT |
3127 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
3128 | entry = data->entry; | |
3129 | ||
3130 | spin_lock_irqsave(&ioapic_lock, flags); | |
3131 | reg_00.raw = io_apic_read(dev->id, 0); | |
ec2cd0a2 AS |
3132 | if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) { |
3133 | reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid; | |
1da177e4 LT |
3134 | io_apic_write(dev->id, 0, reg_00.raw); |
3135 | } | |
1da177e4 | 3136 | spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 3137 | for (i = 0; i < nr_ioapic_registers[dev->id]; i++) |
cf4c6a2f | 3138 | ioapic_write_entry(dev->id, i, entry[i]); |
1da177e4 LT |
3139 | |
3140 | return 0; | |
3141 | } | |
3142 | ||
3143 | static struct sysdev_class ioapic_sysdev_class = { | |
af5ca3f4 | 3144 | .name = "ioapic", |
1da177e4 LT |
3145 | .suspend = ioapic_suspend, |
3146 | .resume = ioapic_resume, | |
3147 | }; | |
3148 | ||
3149 | static int __init ioapic_init_sysfs(void) | |
3150 | { | |
54168ed7 IM |
3151 | struct sys_device * dev; |
3152 | int i, size, error; | |
1da177e4 LT |
3153 | |
3154 | error = sysdev_class_register(&ioapic_sysdev_class); | |
3155 | if (error) | |
3156 | return error; | |
3157 | ||
54168ed7 | 3158 | for (i = 0; i < nr_ioapics; i++ ) { |
36062448 | 3159 | size = sizeof(struct sys_device) + nr_ioapic_registers[i] |
1da177e4 | 3160 | * sizeof(struct IO_APIC_route_entry); |
25556c16 | 3161 | mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL); |
1da177e4 LT |
3162 | if (!mp_ioapic_data[i]) { |
3163 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3164 | continue; | |
3165 | } | |
1da177e4 | 3166 | dev = &mp_ioapic_data[i]->dev; |
36062448 | 3167 | dev->id = i; |
1da177e4 LT |
3168 | dev->cls = &ioapic_sysdev_class; |
3169 | error = sysdev_register(dev); | |
3170 | if (error) { | |
3171 | kfree(mp_ioapic_data[i]); | |
3172 | mp_ioapic_data[i] = NULL; | |
3173 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3174 | continue; | |
3175 | } | |
3176 | } | |
3177 | ||
3178 | return 0; | |
3179 | } | |
3180 | ||
3181 | device_initcall(ioapic_init_sysfs); | |
3182 | ||
3fc471ed | 3183 | /* |
95d77884 | 3184 | * Dynamic irq allocate and deallocation |
3fc471ed | 3185 | */ |
199751d7 | 3186 | unsigned int create_irq_nr(unsigned int irq_want) |
3fc471ed | 3187 | { |
ace80ab7 | 3188 | /* Allocate an unused irq */ |
54168ed7 IM |
3189 | unsigned int irq; |
3190 | unsigned int new; | |
3fc471ed | 3191 | unsigned long flags; |
0b8f1efa YL |
3192 | struct irq_cfg *cfg_new = NULL; |
3193 | int cpu = boot_cpu_id; | |
3194 | struct irq_desc *desc_new = NULL; | |
199751d7 YL |
3195 | |
3196 | irq = 0; | |
ace80ab7 | 3197 | spin_lock_irqsave(&vector_lock, flags); |
be5d5350 | 3198 | for (new = irq_want; new < NR_IRQS; new++) { |
ace80ab7 EB |
3199 | if (platform_legacy_irq(new)) |
3200 | continue; | |
0b8f1efa YL |
3201 | |
3202 | desc_new = irq_to_desc_alloc_cpu(new, cpu); | |
3203 | if (!desc_new) { | |
3204 | printk(KERN_INFO "can not get irq_desc for %d\n", new); | |
3205 | continue; | |
3206 | } | |
3207 | cfg_new = desc_new->chip_data; | |
3208 | ||
3209 | if (cfg_new->vector != 0) | |
ace80ab7 | 3210 | continue; |
3145e941 | 3211 | if (__assign_irq_vector(new, cfg_new, TARGET_CPUS) == 0) |
ace80ab7 EB |
3212 | irq = new; |
3213 | break; | |
3214 | } | |
3215 | spin_unlock_irqrestore(&vector_lock, flags); | |
3fc471ed | 3216 | |
199751d7 | 3217 | if (irq > 0) { |
3fc471ed | 3218 | dynamic_irq_init(irq); |
0b8f1efa YL |
3219 | /* restore it, in case dynamic_irq_init clear it */ |
3220 | if (desc_new) | |
3221 | desc_new->chip_data = cfg_new; | |
3fc471ed EB |
3222 | } |
3223 | return irq; | |
3224 | } | |
3225 | ||
be5d5350 | 3226 | static int nr_irqs_gsi = NR_IRQS_LEGACY; |
199751d7 YL |
3227 | int create_irq(void) |
3228 | { | |
be5d5350 | 3229 | unsigned int irq_want; |
54168ed7 IM |
3230 | int irq; |
3231 | ||
be5d5350 YL |
3232 | irq_want = nr_irqs_gsi; |
3233 | irq = create_irq_nr(irq_want); | |
54168ed7 IM |
3234 | |
3235 | if (irq == 0) | |
3236 | irq = -1; | |
3237 | ||
3238 | return irq; | |
199751d7 YL |
3239 | } |
3240 | ||
3fc471ed EB |
3241 | void destroy_irq(unsigned int irq) |
3242 | { | |
3243 | unsigned long flags; | |
0b8f1efa YL |
3244 | struct irq_cfg *cfg; |
3245 | struct irq_desc *desc; | |
3fc471ed | 3246 | |
0b8f1efa YL |
3247 | /* store it, in case dynamic_irq_cleanup clear it */ |
3248 | desc = irq_to_desc(irq); | |
3249 | cfg = desc->chip_data; | |
3fc471ed | 3250 | dynamic_irq_cleanup(irq); |
0b8f1efa YL |
3251 | /* connect back irq_cfg */ |
3252 | if (desc) | |
3253 | desc->chip_data = cfg; | |
3fc471ed | 3254 | |
54168ed7 IM |
3255 | #ifdef CONFIG_INTR_REMAP |
3256 | free_irte(irq); | |
3257 | #endif | |
3fc471ed | 3258 | spin_lock_irqsave(&vector_lock, flags); |
3145e941 | 3259 | __clear_irq_vector(irq, cfg); |
3fc471ed EB |
3260 | spin_unlock_irqrestore(&vector_lock, flags); |
3261 | } | |
3fc471ed | 3262 | |
2d3fcc1c | 3263 | /* |
27b46d76 | 3264 | * MSI message composition |
2d3fcc1c EB |
3265 | */ |
3266 | #ifdef CONFIG_PCI_MSI | |
3b7d1921 | 3267 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg) |
2d3fcc1c | 3268 | { |
497c9a19 YL |
3269 | struct irq_cfg *cfg; |
3270 | int err; | |
2d3fcc1c EB |
3271 | unsigned dest; |
3272 | ||
3145e941 | 3273 | cfg = irq_cfg(irq); |
22f65d31 | 3274 | err = assign_irq_vector(irq, cfg, TARGET_CPUS); |
497c9a19 YL |
3275 | if (err) |
3276 | return err; | |
2d3fcc1c | 3277 | |
22f65d31 | 3278 | dest = cpu_mask_to_apicid_and(cfg->domain, TARGET_CPUS); |
497c9a19 | 3279 | |
54168ed7 IM |
3280 | #ifdef CONFIG_INTR_REMAP |
3281 | if (irq_remapped(irq)) { | |
3282 | struct irte irte; | |
3283 | int ir_index; | |
3284 | u16 sub_handle; | |
3285 | ||
3286 | ir_index = map_irq_to_irte_handle(irq, &sub_handle); | |
3287 | BUG_ON(ir_index == -1); | |
3288 | ||
3289 | memset (&irte, 0, sizeof(irte)); | |
3290 | ||
3291 | irte.present = 1; | |
3292 | irte.dst_mode = INT_DEST_MODE; | |
3293 | irte.trigger_mode = 0; /* edge */ | |
3294 | irte.dlvry_mode = INT_DELIVERY_MODE; | |
3295 | irte.vector = cfg->vector; | |
3296 | irte.dest_id = IRTE_DEST(dest); | |
3297 | ||
3298 | modify_irte(irq, &irte); | |
3299 | ||
3300 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3301 | msg->data = sub_handle; | |
3302 | msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT | | |
3303 | MSI_ADDR_IR_SHV | | |
3304 | MSI_ADDR_IR_INDEX1(ir_index) | | |
3305 | MSI_ADDR_IR_INDEX2(ir_index); | |
3306 | } else | |
3307 | #endif | |
3308 | { | |
3309 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3310 | msg->address_lo = | |
3311 | MSI_ADDR_BASE_LO | | |
3312 | ((INT_DEST_MODE == 0) ? | |
3313 | MSI_ADDR_DEST_MODE_PHYSICAL: | |
3314 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
3315 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
3316 | MSI_ADDR_REDIRECTION_CPU: | |
3317 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
3318 | MSI_ADDR_DEST_ID(dest); | |
497c9a19 | 3319 | |
54168ed7 IM |
3320 | msg->data = |
3321 | MSI_DATA_TRIGGER_EDGE | | |
3322 | MSI_DATA_LEVEL_ASSERT | | |
3323 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
3324 | MSI_DATA_DELIVERY_FIXED: | |
3325 | MSI_DATA_DELIVERY_LOWPRI) | | |
3326 | MSI_DATA_VECTOR(cfg->vector); | |
3327 | } | |
497c9a19 | 3328 | return err; |
2d3fcc1c EB |
3329 | } |
3330 | ||
3b7d1921 | 3331 | #ifdef CONFIG_SMP |
0de26520 | 3332 | static void set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask) |
2d3fcc1c | 3333 | { |
3145e941 | 3334 | struct irq_desc *desc = irq_to_desc(irq); |
497c9a19 | 3335 | struct irq_cfg *cfg; |
3b7d1921 EB |
3336 | struct msi_msg msg; |
3337 | unsigned int dest; | |
3b7d1921 | 3338 | |
22f65d31 MT |
3339 | dest = set_desc_affinity(desc, mask); |
3340 | if (dest == BAD_APICID) | |
497c9a19 | 3341 | return; |
2d3fcc1c | 3342 | |
3145e941 | 3343 | cfg = desc->chip_data; |
3b7d1921 | 3344 | |
3145e941 | 3345 | read_msi_msg_desc(desc, &msg); |
3b7d1921 EB |
3346 | |
3347 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
497c9a19 | 3348 | msg.data |= MSI_DATA_VECTOR(cfg->vector); |
3b7d1921 EB |
3349 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; |
3350 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3351 | ||
3145e941 | 3352 | write_msi_msg_desc(desc, &msg); |
2d3fcc1c | 3353 | } |
54168ed7 IM |
3354 | #ifdef CONFIG_INTR_REMAP |
3355 | /* | |
3356 | * Migrate the MSI irq to another cpumask. This migration is | |
3357 | * done in the process context using interrupt-remapping hardware. | |
3358 | */ | |
e7986739 MT |
3359 | static void |
3360 | ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask) | |
54168ed7 | 3361 | { |
3145e941 | 3362 | struct irq_desc *desc = irq_to_desc(irq); |
54168ed7 IM |
3363 | struct irq_cfg *cfg; |
3364 | unsigned int dest; | |
54168ed7 | 3365 | struct irte irte; |
54168ed7 | 3366 | |
54168ed7 IM |
3367 | if (get_irte(irq, &irte)) |
3368 | return; | |
3369 | ||
22f65d31 MT |
3370 | dest = set_desc_affinity(desc, mask); |
3371 | if (dest == BAD_APICID) | |
54168ed7 IM |
3372 | return; |
3373 | ||
54168ed7 IM |
3374 | irte.vector = cfg->vector; |
3375 | irte.dest_id = IRTE_DEST(dest); | |
3376 | ||
3377 | /* | |
3378 | * atomically update the IRTE with the new destination and vector. | |
3379 | */ | |
3380 | modify_irte(irq, &irte); | |
3381 | ||
3382 | /* | |
3383 | * After this point, all the interrupts will start arriving | |
3384 | * at the new destination. So, time to cleanup the previous | |
3385 | * vector allocation. | |
3386 | */ | |
22f65d31 MT |
3387 | if (cfg->move_in_progress) |
3388 | send_cleanup_vector(cfg); | |
54168ed7 | 3389 | } |
3145e941 | 3390 | |
54168ed7 | 3391 | #endif |
3b7d1921 | 3392 | #endif /* CONFIG_SMP */ |
2d3fcc1c | 3393 | |
3b7d1921 EB |
3394 | /* |
3395 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
3396 | * which implement the MSI or MSI-X Capability Structure. | |
3397 | */ | |
3398 | static struct irq_chip msi_chip = { | |
3399 | .name = "PCI-MSI", | |
3400 | .unmask = unmask_msi_irq, | |
3401 | .mask = mask_msi_irq, | |
1d025192 | 3402 | .ack = ack_apic_edge, |
3b7d1921 EB |
3403 | #ifdef CONFIG_SMP |
3404 | .set_affinity = set_msi_irq_affinity, | |
3405 | #endif | |
3406 | .retrigger = ioapic_retrigger_irq, | |
2d3fcc1c EB |
3407 | }; |
3408 | ||
54168ed7 IM |
3409 | #ifdef CONFIG_INTR_REMAP |
3410 | static struct irq_chip msi_ir_chip = { | |
3411 | .name = "IR-PCI-MSI", | |
3412 | .unmask = unmask_msi_irq, | |
3413 | .mask = mask_msi_irq, | |
3414 | .ack = ack_x2apic_edge, | |
3415 | #ifdef CONFIG_SMP | |
3416 | .set_affinity = ir_set_msi_irq_affinity, | |
3417 | #endif | |
3418 | .retrigger = ioapic_retrigger_irq, | |
3419 | }; | |
3420 | ||
3421 | /* | |
3422 | * Map the PCI dev to the corresponding remapping hardware unit | |
3423 | * and allocate 'nvec' consecutive interrupt-remapping table entries | |
3424 | * in it. | |
3425 | */ | |
3426 | static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec) | |
3427 | { | |
3428 | struct intel_iommu *iommu; | |
3429 | int index; | |
3430 | ||
3431 | iommu = map_dev_to_ir(dev); | |
3432 | if (!iommu) { | |
3433 | printk(KERN_ERR | |
3434 | "Unable to map PCI %s to iommu\n", pci_name(dev)); | |
3435 | return -ENOENT; | |
3436 | } | |
3437 | ||
3438 | index = alloc_irte(iommu, irq, nvec); | |
3439 | if (index < 0) { | |
3440 | printk(KERN_ERR | |
3441 | "Unable to allocate %d IRTE for PCI %s\n", nvec, | |
d6c88a50 | 3442 | pci_name(dev)); |
54168ed7 IM |
3443 | return -ENOSPC; |
3444 | } | |
3445 | return index; | |
3446 | } | |
3447 | #endif | |
1d025192 | 3448 | |
3145e941 | 3449 | static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq) |
1d025192 YL |
3450 | { |
3451 | int ret; | |
3452 | struct msi_msg msg; | |
3453 | ||
3454 | ret = msi_compose_msg(dev, irq, &msg); | |
3455 | if (ret < 0) | |
3456 | return ret; | |
3457 | ||
3145e941 | 3458 | set_irq_msi(irq, msidesc); |
1d025192 YL |
3459 | write_msi_msg(irq, &msg); |
3460 | ||
54168ed7 IM |
3461 | #ifdef CONFIG_INTR_REMAP |
3462 | if (irq_remapped(irq)) { | |
3463 | struct irq_desc *desc = irq_to_desc(irq); | |
3464 | /* | |
3465 | * irq migration in process context | |
3466 | */ | |
3467 | desc->status |= IRQ_MOVE_PCNTXT; | |
3468 | set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge"); | |
3469 | } else | |
3470 | #endif | |
3471 | set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge"); | |
1d025192 | 3472 | |
c81bba49 YL |
3473 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq); |
3474 | ||
1d025192 YL |
3475 | return 0; |
3476 | } | |
3477 | ||
0b8f1efa | 3478 | int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc) |
3b7d1921 | 3479 | { |
54168ed7 IM |
3480 | unsigned int irq; |
3481 | int ret; | |
199751d7 YL |
3482 | unsigned int irq_want; |
3483 | ||
be5d5350 | 3484 | irq_want = nr_irqs_gsi; |
199751d7 | 3485 | irq = create_irq_nr(irq_want); |
199751d7 YL |
3486 | if (irq == 0) |
3487 | return -1; | |
f7feaca7 | 3488 | |
54168ed7 IM |
3489 | #ifdef CONFIG_INTR_REMAP |
3490 | if (!intr_remapping_enabled) | |
3491 | goto no_ir; | |
3492 | ||
3493 | ret = msi_alloc_irte(dev, irq, 1); | |
3494 | if (ret < 0) | |
3495 | goto error; | |
3496 | no_ir: | |
3497 | #endif | |
0b8f1efa | 3498 | ret = setup_msi_irq(dev, msidesc, irq); |
f7feaca7 EB |
3499 | if (ret < 0) { |
3500 | destroy_irq(irq); | |
3b7d1921 | 3501 | return ret; |
54168ed7 | 3502 | } |
7fe3730d | 3503 | return 0; |
54168ed7 IM |
3504 | |
3505 | #ifdef CONFIG_INTR_REMAP | |
3506 | error: | |
3507 | destroy_irq(irq); | |
3508 | return ret; | |
3509 | #endif | |
3b7d1921 EB |
3510 | } |
3511 | ||
047c8fdb YL |
3512 | int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
3513 | { | |
54168ed7 IM |
3514 | unsigned int irq; |
3515 | int ret, sub_handle; | |
0b8f1efa | 3516 | struct msi_desc *msidesc; |
54168ed7 IM |
3517 | unsigned int irq_want; |
3518 | ||
3519 | #ifdef CONFIG_INTR_REMAP | |
3520 | struct intel_iommu *iommu = 0; | |
3521 | int index = 0; | |
3522 | #endif | |
3523 | ||
be5d5350 | 3524 | irq_want = nr_irqs_gsi; |
54168ed7 | 3525 | sub_handle = 0; |
0b8f1efa YL |
3526 | list_for_each_entry(msidesc, &dev->msi_list, list) { |
3527 | irq = create_irq_nr(irq_want); | |
be5d5350 | 3528 | irq_want++; |
54168ed7 IM |
3529 | if (irq == 0) |
3530 | return -1; | |
3531 | #ifdef CONFIG_INTR_REMAP | |
3532 | if (!intr_remapping_enabled) | |
3533 | goto no_ir; | |
3534 | ||
3535 | if (!sub_handle) { | |
3536 | /* | |
3537 | * allocate the consecutive block of IRTE's | |
3538 | * for 'nvec' | |
3539 | */ | |
3540 | index = msi_alloc_irte(dev, irq, nvec); | |
3541 | if (index < 0) { | |
3542 | ret = index; | |
3543 | goto error; | |
3544 | } | |
3545 | } else { | |
3546 | iommu = map_dev_to_ir(dev); | |
3547 | if (!iommu) { | |
3548 | ret = -ENOENT; | |
3549 | goto error; | |
3550 | } | |
3551 | /* | |
3552 | * setup the mapping between the irq and the IRTE | |
3553 | * base index, the sub_handle pointing to the | |
3554 | * appropriate interrupt remap table entry. | |
3555 | */ | |
3556 | set_irte_irq(irq, iommu, index, sub_handle); | |
3557 | } | |
3558 | no_ir: | |
3559 | #endif | |
0b8f1efa | 3560 | ret = setup_msi_irq(dev, msidesc, irq); |
54168ed7 IM |
3561 | if (ret < 0) |
3562 | goto error; | |
3563 | sub_handle++; | |
3564 | } | |
3565 | return 0; | |
047c8fdb YL |
3566 | |
3567 | error: | |
54168ed7 IM |
3568 | destroy_irq(irq); |
3569 | return ret; | |
047c8fdb YL |
3570 | } |
3571 | ||
3b7d1921 EB |
3572 | void arch_teardown_msi_irq(unsigned int irq) |
3573 | { | |
f7feaca7 | 3574 | destroy_irq(irq); |
3b7d1921 EB |
3575 | } |
3576 | ||
54168ed7 IM |
3577 | #ifdef CONFIG_DMAR |
3578 | #ifdef CONFIG_SMP | |
22f65d31 | 3579 | static void dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask) |
54168ed7 | 3580 | { |
3145e941 | 3581 | struct irq_desc *desc = irq_to_desc(irq); |
54168ed7 IM |
3582 | struct irq_cfg *cfg; |
3583 | struct msi_msg msg; | |
3584 | unsigned int dest; | |
54168ed7 | 3585 | |
22f65d31 MT |
3586 | dest = set_desc_affinity(desc, mask); |
3587 | if (dest == BAD_APICID) | |
54168ed7 IM |
3588 | return; |
3589 | ||
3145e941 | 3590 | cfg = desc->chip_data; |
54168ed7 IM |
3591 | |
3592 | dmar_msi_read(irq, &msg); | |
3593 | ||
3594 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3595 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3596 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3597 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3598 | ||
3599 | dmar_msi_write(irq, &msg); | |
54168ed7 | 3600 | } |
3145e941 | 3601 | |
54168ed7 IM |
3602 | #endif /* CONFIG_SMP */ |
3603 | ||
3604 | struct irq_chip dmar_msi_type = { | |
3605 | .name = "DMAR_MSI", | |
3606 | .unmask = dmar_msi_unmask, | |
3607 | .mask = dmar_msi_mask, | |
3608 | .ack = ack_apic_edge, | |
3609 | #ifdef CONFIG_SMP | |
3610 | .set_affinity = dmar_msi_set_affinity, | |
3611 | #endif | |
3612 | .retrigger = ioapic_retrigger_irq, | |
3613 | }; | |
3614 | ||
3615 | int arch_setup_dmar_msi(unsigned int irq) | |
3616 | { | |
3617 | int ret; | |
3618 | struct msi_msg msg; | |
2d3fcc1c | 3619 | |
54168ed7 IM |
3620 | ret = msi_compose_msg(NULL, irq, &msg); |
3621 | if (ret < 0) | |
3622 | return ret; | |
3623 | dmar_msi_write(irq, &msg); | |
3624 | set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, | |
3625 | "edge"); | |
3626 | return 0; | |
3627 | } | |
3628 | #endif | |
3629 | ||
58ac1e76 | 3630 | #ifdef CONFIG_HPET_TIMER |
3631 | ||
3632 | #ifdef CONFIG_SMP | |
22f65d31 | 3633 | static void hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask) |
58ac1e76 | 3634 | { |
3145e941 | 3635 | struct irq_desc *desc = irq_to_desc(irq); |
58ac1e76 | 3636 | struct irq_cfg *cfg; |
58ac1e76 | 3637 | struct msi_msg msg; |
3638 | unsigned int dest; | |
58ac1e76 | 3639 | |
22f65d31 MT |
3640 | dest = set_desc_affinity(desc, mask); |
3641 | if (dest == BAD_APICID) | |
58ac1e76 | 3642 | return; |
3643 | ||
3145e941 | 3644 | cfg = desc->chip_data; |
58ac1e76 | 3645 | |
3646 | hpet_msi_read(irq, &msg); | |
3647 | ||
3648 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3649 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3650 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3651 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3652 | ||
3653 | hpet_msi_write(irq, &msg); | |
58ac1e76 | 3654 | } |
3145e941 | 3655 | |
58ac1e76 | 3656 | #endif /* CONFIG_SMP */ |
3657 | ||
3658 | struct irq_chip hpet_msi_type = { | |
3659 | .name = "HPET_MSI", | |
3660 | .unmask = hpet_msi_unmask, | |
3661 | .mask = hpet_msi_mask, | |
3662 | .ack = ack_apic_edge, | |
3663 | #ifdef CONFIG_SMP | |
3664 | .set_affinity = hpet_msi_set_affinity, | |
3665 | #endif | |
3666 | .retrigger = ioapic_retrigger_irq, | |
3667 | }; | |
3668 | ||
3669 | int arch_setup_hpet_msi(unsigned int irq) | |
3670 | { | |
3671 | int ret; | |
3672 | struct msi_msg msg; | |
3673 | ||
3674 | ret = msi_compose_msg(NULL, irq, &msg); | |
3675 | if (ret < 0) | |
3676 | return ret; | |
3677 | ||
3678 | hpet_msi_write(irq, &msg); | |
3679 | set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq, | |
3680 | "edge"); | |
c81bba49 | 3681 | |
58ac1e76 | 3682 | return 0; |
3683 | } | |
3684 | #endif | |
3685 | ||
54168ed7 | 3686 | #endif /* CONFIG_PCI_MSI */ |
8b955b0d EB |
3687 | /* |
3688 | * Hypertransport interrupt support | |
3689 | */ | |
3690 | #ifdef CONFIG_HT_IRQ | |
3691 | ||
3692 | #ifdef CONFIG_SMP | |
3693 | ||
497c9a19 | 3694 | static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) |
8b955b0d | 3695 | { |
ec68307c EB |
3696 | struct ht_irq_msg msg; |
3697 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 3698 | |
497c9a19 | 3699 | msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); |
ec68307c | 3700 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); |
8b955b0d | 3701 | |
497c9a19 | 3702 | msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); |
ec68307c | 3703 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3704 | |
ec68307c | 3705 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
3706 | } |
3707 | ||
22f65d31 | 3708 | static void set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask) |
8b955b0d | 3709 | { |
3145e941 | 3710 | struct irq_desc *desc = irq_to_desc(irq); |
497c9a19 | 3711 | struct irq_cfg *cfg; |
8b955b0d | 3712 | unsigned int dest; |
8b955b0d | 3713 | |
22f65d31 MT |
3714 | dest = set_desc_affinity(desc, mask); |
3715 | if (dest == BAD_APICID) | |
497c9a19 | 3716 | return; |
8b955b0d | 3717 | |
3145e941 | 3718 | cfg = desc->chip_data; |
8b955b0d | 3719 | |
497c9a19 | 3720 | target_ht_irq(irq, dest, cfg->vector); |
8b955b0d | 3721 | } |
3145e941 | 3722 | |
8b955b0d EB |
3723 | #endif |
3724 | ||
c37e108d | 3725 | static struct irq_chip ht_irq_chip = { |
8b955b0d EB |
3726 | .name = "PCI-HT", |
3727 | .mask = mask_ht_irq, | |
3728 | .unmask = unmask_ht_irq, | |
1d025192 | 3729 | .ack = ack_apic_edge, |
8b955b0d EB |
3730 | #ifdef CONFIG_SMP |
3731 | .set_affinity = set_ht_irq_affinity, | |
3732 | #endif | |
3733 | .retrigger = ioapic_retrigger_irq, | |
3734 | }; | |
3735 | ||
3736 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
3737 | { | |
497c9a19 YL |
3738 | struct irq_cfg *cfg; |
3739 | int err; | |
8b955b0d | 3740 | |
3145e941 | 3741 | cfg = irq_cfg(irq); |
e7986739 | 3742 | err = assign_irq_vector(irq, cfg, TARGET_CPUS); |
54168ed7 | 3743 | if (!err) { |
ec68307c | 3744 | struct ht_irq_msg msg; |
8b955b0d | 3745 | unsigned dest; |
8b955b0d | 3746 | |
22f65d31 | 3747 | dest = cpu_mask_to_apicid_and(cfg->domain, TARGET_CPUS); |
8b955b0d | 3748 | |
ec68307c | 3749 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3750 | |
ec68307c EB |
3751 | msg.address_lo = |
3752 | HT_IRQ_LOW_BASE | | |
8b955b0d | 3753 | HT_IRQ_LOW_DEST_ID(dest) | |
497c9a19 | 3754 | HT_IRQ_LOW_VECTOR(cfg->vector) | |
8b955b0d EB |
3755 | ((INT_DEST_MODE == 0) ? |
3756 | HT_IRQ_LOW_DM_PHYSICAL : | |
3757 | HT_IRQ_LOW_DM_LOGICAL) | | |
3758 | HT_IRQ_LOW_RQEOI_EDGE | | |
3759 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
3760 | HT_IRQ_LOW_MT_FIXED : | |
3761 | HT_IRQ_LOW_MT_ARBITRATED) | | |
3762 | HT_IRQ_LOW_IRQ_MASKED; | |
3763 | ||
ec68307c | 3764 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 3765 | |
a460e745 IM |
3766 | set_irq_chip_and_handler_name(irq, &ht_irq_chip, |
3767 | handle_edge_irq, "edge"); | |
c81bba49 YL |
3768 | |
3769 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq); | |
8b955b0d | 3770 | } |
497c9a19 | 3771 | return err; |
8b955b0d EB |
3772 | } |
3773 | #endif /* CONFIG_HT_IRQ */ | |
3774 | ||
4173a0e7 DN |
3775 | #ifdef CONFIG_X86_64 |
3776 | /* | |
3777 | * Re-target the irq to the specified CPU and enable the specified MMR located | |
3778 | * on the specified blade to allow the sending of MSIs to the specified CPU. | |
3779 | */ | |
3780 | int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade, | |
3781 | unsigned long mmr_offset) | |
3782 | { | |
22f65d31 | 3783 | const struct cpumask *eligible_cpu = cpumask_of(cpu); |
4173a0e7 DN |
3784 | struct irq_cfg *cfg; |
3785 | int mmr_pnode; | |
3786 | unsigned long mmr_value; | |
3787 | struct uv_IO_APIC_route_entry *entry; | |
3788 | unsigned long flags; | |
3789 | int err; | |
3790 | ||
3145e941 YL |
3791 | cfg = irq_cfg(irq); |
3792 | ||
e7986739 | 3793 | err = assign_irq_vector(irq, cfg, eligible_cpu); |
4173a0e7 DN |
3794 | if (err != 0) |
3795 | return err; | |
3796 | ||
3797 | spin_lock_irqsave(&vector_lock, flags); | |
3798 | set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq, | |
3799 | irq_name); | |
3800 | spin_unlock_irqrestore(&vector_lock, flags); | |
3801 | ||
4173a0e7 DN |
3802 | mmr_value = 0; |
3803 | entry = (struct uv_IO_APIC_route_entry *)&mmr_value; | |
3804 | BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long)); | |
3805 | ||
3806 | entry->vector = cfg->vector; | |
3807 | entry->delivery_mode = INT_DELIVERY_MODE; | |
3808 | entry->dest_mode = INT_DEST_MODE; | |
3809 | entry->polarity = 0; | |
3810 | entry->trigger = 0; | |
3811 | entry->mask = 0; | |
e7986739 | 3812 | entry->dest = cpu_mask_to_apicid(eligible_cpu); |
4173a0e7 DN |
3813 | |
3814 | mmr_pnode = uv_blade_to_pnode(mmr_blade); | |
3815 | uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value); | |
3816 | ||
3817 | return irq; | |
3818 | } | |
3819 | ||
3820 | /* | |
3821 | * Disable the specified MMR located on the specified blade so that MSIs are | |
3822 | * longer allowed to be sent. | |
3823 | */ | |
3824 | void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset) | |
3825 | { | |
3826 | unsigned long mmr_value; | |
3827 | struct uv_IO_APIC_route_entry *entry; | |
3828 | int mmr_pnode; | |
3829 | ||
3830 | mmr_value = 0; | |
3831 | entry = (struct uv_IO_APIC_route_entry *)&mmr_value; | |
3832 | BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long)); | |
3833 | ||
3834 | entry->mask = 1; | |
3835 | ||
3836 | mmr_pnode = uv_blade_to_pnode(mmr_blade); | |
3837 | uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value); | |
3838 | } | |
3839 | #endif /* CONFIG_X86_64 */ | |
3840 | ||
9d6a4d08 YL |
3841 | int __init io_apic_get_redir_entries (int ioapic) |
3842 | { | |
3843 | union IO_APIC_reg_01 reg_01; | |
3844 | unsigned long flags; | |
3845 | ||
3846 | spin_lock_irqsave(&ioapic_lock, flags); | |
3847 | reg_01.raw = io_apic_read(ioapic, 1); | |
3848 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3849 | ||
3850 | return reg_01.bits.entries; | |
3851 | } | |
3852 | ||
be5d5350 | 3853 | void __init probe_nr_irqs_gsi(void) |
9d6a4d08 | 3854 | { |
be5d5350 YL |
3855 | int idx; |
3856 | int nr = 0; | |
3857 | ||
3858 | for (idx = 0; idx < nr_ioapics; idx++) | |
3859 | nr += io_apic_get_redir_entries(idx) + 1; | |
3860 | ||
3861 | if (nr > nr_irqs_gsi) | |
3862 | nr_irqs_gsi = nr; | |
9d6a4d08 YL |
3863 | } |
3864 | ||
1da177e4 | 3865 | /* -------------------------------------------------------------------------- |
54168ed7 | 3866 | ACPI-based IOAPIC Configuration |
1da177e4 LT |
3867 | -------------------------------------------------------------------------- */ |
3868 | ||
888ba6c6 | 3869 | #ifdef CONFIG_ACPI |
1da177e4 | 3870 | |
54168ed7 | 3871 | #ifdef CONFIG_X86_32 |
36062448 | 3872 | int __init io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
3873 | { |
3874 | union IO_APIC_reg_00 reg_00; | |
3875 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
3876 | physid_mask_t tmp; | |
3877 | unsigned long flags; | |
3878 | int i = 0; | |
3879 | ||
3880 | /* | |
36062448 PC |
3881 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
3882 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 3883 | * supports up to 16 on one shared APIC bus. |
36062448 | 3884 | * |
1da177e4 LT |
3885 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
3886 | * advantage of new APIC bus architecture. | |
3887 | */ | |
3888 | ||
3889 | if (physids_empty(apic_id_map)) | |
3890 | apic_id_map = ioapic_phys_id_map(phys_cpu_present_map); | |
3891 | ||
3892 | spin_lock_irqsave(&ioapic_lock, flags); | |
3893 | reg_00.raw = io_apic_read(ioapic, 0); | |
3894 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3895 | ||
3896 | if (apic_id >= get_physical_broadcast()) { | |
3897 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
3898 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
3899 | apic_id = reg_00.bits.ID; | |
3900 | } | |
3901 | ||
3902 | /* | |
36062448 | 3903 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
3904 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
3905 | */ | |
3906 | if (check_apicid_used(apic_id_map, apic_id)) { | |
3907 | ||
3908 | for (i = 0; i < get_physical_broadcast(); i++) { | |
3909 | if (!check_apicid_used(apic_id_map, i)) | |
3910 | break; | |
3911 | } | |
3912 | ||
3913 | if (i == get_physical_broadcast()) | |
3914 | panic("Max apic_id exceeded!\n"); | |
3915 | ||
3916 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
3917 | "trying %d\n", ioapic, apic_id, i); | |
3918 | ||
3919 | apic_id = i; | |
36062448 | 3920 | } |
1da177e4 LT |
3921 | |
3922 | tmp = apicid_to_cpu_present(apic_id); | |
3923 | physids_or(apic_id_map, apic_id_map, tmp); | |
3924 | ||
3925 | if (reg_00.bits.ID != apic_id) { | |
3926 | reg_00.bits.ID = apic_id; | |
3927 | ||
3928 | spin_lock_irqsave(&ioapic_lock, flags); | |
3929 | io_apic_write(ioapic, 0, reg_00.raw); | |
3930 | reg_00.raw = io_apic_read(ioapic, 0); | |
3931 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3932 | ||
3933 | /* Sanity check */ | |
6070f9ec AD |
3934 | if (reg_00.bits.ID != apic_id) { |
3935 | printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); | |
3936 | return -1; | |
3937 | } | |
1da177e4 LT |
3938 | } |
3939 | ||
3940 | apic_printk(APIC_VERBOSE, KERN_INFO | |
3941 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
3942 | ||
3943 | return apic_id; | |
3944 | } | |
3945 | ||
36062448 | 3946 | int __init io_apic_get_version(int ioapic) |
1da177e4 LT |
3947 | { |
3948 | union IO_APIC_reg_01 reg_01; | |
3949 | unsigned long flags; | |
3950 | ||
3951 | spin_lock_irqsave(&ioapic_lock, flags); | |
3952 | reg_01.raw = io_apic_read(ioapic, 1); | |
3953 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3954 | ||
3955 | return reg_01.bits.version; | |
3956 | } | |
54168ed7 | 3957 | #endif |
1da177e4 | 3958 | |
54168ed7 | 3959 | int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity) |
1da177e4 | 3960 | { |
0b8f1efa YL |
3961 | struct irq_desc *desc; |
3962 | struct irq_cfg *cfg; | |
3963 | int cpu = boot_cpu_id; | |
3964 | ||
1da177e4 | 3965 | if (!IO_APIC_IRQ(irq)) { |
54168ed7 | 3966 | apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", |
1da177e4 LT |
3967 | ioapic); |
3968 | return -EINVAL; | |
3969 | } | |
3970 | ||
0b8f1efa YL |
3971 | desc = irq_to_desc_alloc_cpu(irq, cpu); |
3972 | if (!desc) { | |
3973 | printk(KERN_INFO "can not get irq_desc %d\n", irq); | |
3974 | return 0; | |
3975 | } | |
3976 | ||
1da177e4 LT |
3977 | /* |
3978 | * IRQs < 16 are already in the irq_2_pin[] map | |
3979 | */ | |
99d093d1 | 3980 | if (irq >= NR_IRQS_LEGACY) { |
0b8f1efa | 3981 | cfg = desc->chip_data; |
3145e941 | 3982 | add_pin_to_irq_cpu(cfg, cpu, ioapic, pin); |
0b8f1efa | 3983 | } |
1da177e4 | 3984 | |
3145e941 | 3985 | setup_IO_APIC_irq(ioapic, pin, irq, desc, triggering, polarity); |
1da177e4 LT |
3986 | |
3987 | return 0; | |
3988 | } | |
3989 | ||
54168ed7 | 3990 | |
61fd47e0 SL |
3991 | int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity) |
3992 | { | |
3993 | int i; | |
3994 | ||
3995 | if (skip_ioapic_setup) | |
3996 | return -1; | |
3997 | ||
3998 | for (i = 0; i < mp_irq_entries; i++) | |
2fddb6e2 AS |
3999 | if (mp_irqs[i].mp_irqtype == mp_INT && |
4000 | mp_irqs[i].mp_srcbusirq == bus_irq) | |
61fd47e0 SL |
4001 | break; |
4002 | if (i >= mp_irq_entries) | |
4003 | return -1; | |
4004 | ||
4005 | *trigger = irq_trigger(i); | |
4006 | *polarity = irq_polarity(i); | |
4007 | return 0; | |
4008 | } | |
4009 | ||
888ba6c6 | 4010 | #endif /* CONFIG_ACPI */ |
1a3f239d | 4011 | |
497c9a19 YL |
4012 | /* |
4013 | * This function currently is only a helper for the i386 smp boot process where | |
4014 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
4015 | * so mask in all cases should simply be TARGET_CPUS | |
4016 | */ | |
4017 | #ifdef CONFIG_SMP | |
4018 | void __init setup_ioapic_dest(void) | |
4019 | { | |
4020 | int pin, ioapic, irq, irq_entry; | |
6c2e9403 | 4021 | struct irq_desc *desc; |
497c9a19 | 4022 | struct irq_cfg *cfg; |
22f65d31 | 4023 | const struct cpumask *mask; |
497c9a19 YL |
4024 | |
4025 | if (skip_ioapic_setup == 1) | |
4026 | return; | |
4027 | ||
4028 | for (ioapic = 0; ioapic < nr_ioapics; ioapic++) { | |
4029 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { | |
4030 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); | |
4031 | if (irq_entry == -1) | |
4032 | continue; | |
4033 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
4034 | ||
4035 | /* setup_IO_APIC_irqs could fail to get vector for some device | |
4036 | * when you have too many devices, because at that time only boot | |
4037 | * cpu is online. | |
4038 | */ | |
0b8f1efa YL |
4039 | desc = irq_to_desc(irq); |
4040 | cfg = desc->chip_data; | |
6c2e9403 | 4041 | if (!cfg->vector) { |
3145e941 | 4042 | setup_IO_APIC_irq(ioapic, pin, irq, desc, |
497c9a19 YL |
4043 | irq_trigger(irq_entry), |
4044 | irq_polarity(irq_entry)); | |
6c2e9403 TG |
4045 | continue; |
4046 | ||
4047 | } | |
4048 | ||
4049 | /* | |
4050 | * Honour affinities which have been set in early boot | |
4051 | */ | |
6c2e9403 TG |
4052 | if (desc->status & |
4053 | (IRQ_NO_BALANCING | IRQ_AFFINITY_SET)) | |
e7986739 | 4054 | mask = &desc->affinity; |
6c2e9403 TG |
4055 | else |
4056 | mask = TARGET_CPUS; | |
4057 | ||
54168ed7 | 4058 | #ifdef CONFIG_INTR_REMAP |
6c2e9403 | 4059 | if (intr_remapping_enabled) |
e7986739 | 4060 | set_ir_ioapic_affinity_irq_desc(desc, mask); |
54168ed7 | 4061 | else |
6c2e9403 | 4062 | #endif |
e7986739 | 4063 | set_ioapic_affinity_irq_desc(desc, mask); |
497c9a19 YL |
4064 | } |
4065 | ||
4066 | } | |
4067 | } | |
4068 | #endif | |
4069 | ||
54168ed7 IM |
4070 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
4071 | ||
4072 | static struct resource *ioapic_resources; | |
4073 | ||
4074 | static struct resource * __init ioapic_setup_resources(void) | |
4075 | { | |
4076 | unsigned long n; | |
4077 | struct resource *res; | |
4078 | char *mem; | |
4079 | int i; | |
4080 | ||
4081 | if (nr_ioapics <= 0) | |
4082 | return NULL; | |
4083 | ||
4084 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); | |
4085 | n *= nr_ioapics; | |
4086 | ||
4087 | mem = alloc_bootmem(n); | |
4088 | res = (void *)mem; | |
4089 | ||
4090 | if (mem != NULL) { | |
4091 | mem += sizeof(struct resource) * nr_ioapics; | |
4092 | ||
4093 | for (i = 0; i < nr_ioapics; i++) { | |
4094 | res[i].name = mem; | |
4095 | res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
4096 | sprintf(mem, "IOAPIC %u", i); | |
4097 | mem += IOAPIC_RESOURCE_NAME_SIZE; | |
4098 | } | |
4099 | } | |
4100 | ||
4101 | ioapic_resources = res; | |
4102 | ||
4103 | return res; | |
4104 | } | |
54168ed7 | 4105 | |
f3294a33 YL |
4106 | void __init ioapic_init_mappings(void) |
4107 | { | |
4108 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
54168ed7 | 4109 | struct resource *ioapic_res; |
d6c88a50 | 4110 | int i; |
f3294a33 | 4111 | |
54168ed7 | 4112 | ioapic_res = ioapic_setup_resources(); |
f3294a33 YL |
4113 | for (i = 0; i < nr_ioapics; i++) { |
4114 | if (smp_found_config) { | |
4115 | ioapic_phys = mp_ioapics[i].mp_apicaddr; | |
54168ed7 | 4116 | #ifdef CONFIG_X86_32 |
d6c88a50 TG |
4117 | if (!ioapic_phys) { |
4118 | printk(KERN_ERR | |
4119 | "WARNING: bogus zero IO-APIC " | |
4120 | "address found in MPTABLE, " | |
4121 | "disabling IO/APIC support!\n"); | |
4122 | smp_found_config = 0; | |
4123 | skip_ioapic_setup = 1; | |
4124 | goto fake_ioapic_page; | |
4125 | } | |
54168ed7 | 4126 | #endif |
f3294a33 | 4127 | } else { |
54168ed7 | 4128 | #ifdef CONFIG_X86_32 |
f3294a33 | 4129 | fake_ioapic_page: |
54168ed7 | 4130 | #endif |
f3294a33 | 4131 | ioapic_phys = (unsigned long) |
54168ed7 | 4132 | alloc_bootmem_pages(PAGE_SIZE); |
f3294a33 YL |
4133 | ioapic_phys = __pa(ioapic_phys); |
4134 | } | |
4135 | set_fixmap_nocache(idx, ioapic_phys); | |
54168ed7 IM |
4136 | apic_printk(APIC_VERBOSE, |
4137 | "mapped IOAPIC to %08lx (%08lx)\n", | |
4138 | __fix_to_virt(idx), ioapic_phys); | |
f3294a33 | 4139 | idx++; |
54168ed7 | 4140 | |
54168ed7 IM |
4141 | if (ioapic_res != NULL) { |
4142 | ioapic_res->start = ioapic_phys; | |
4143 | ioapic_res->end = ioapic_phys + (4 * 1024) - 1; | |
4144 | ioapic_res++; | |
4145 | } | |
f3294a33 YL |
4146 | } |
4147 | } | |
4148 | ||
54168ed7 IM |
4149 | static int __init ioapic_insert_resources(void) |
4150 | { | |
4151 | int i; | |
4152 | struct resource *r = ioapic_resources; | |
4153 | ||
4154 | if (!r) { | |
4155 | printk(KERN_ERR | |
4156 | "IO APIC resources could be not be allocated.\n"); | |
4157 | return -1; | |
4158 | } | |
4159 | ||
4160 | for (i = 0; i < nr_ioapics; i++) { | |
4161 | insert_resource(&iomem_resource, r); | |
4162 | r++; | |
4163 | } | |
4164 | ||
4165 | return 0; | |
4166 | } | |
4167 | ||
4168 | /* Insert the IO APIC resources after PCI initialization has occured to handle | |
4169 | * IO APICS that are mapped in on a BAR in PCI space. */ | |
4170 | late_initcall(ioapic_insert_resources); |