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x86: make io_apic_64.c and io_apic_32.c the same
[deliverable/linux.git] / arch / x86 / kernel / io_apic_32.c
CommitLineData
1da177e4
LT		 1/*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23#include <linux/mm.h>
1da177e4
LT		 24#include <linux/interrupt.h>
25#include <linux/init.h>
26#include <linux/delay.h>
27#include <linux/sched.h>
d4057bdb 28#include <linux/pci.h>
1da177e4
LT		 29#include <linux/mc146818rtc.h>
30#include <linux/compiler.h>
31#include <linux/acpi.h>
129f6946 32#include <linux/module.h>
1da177e4 33#include <linux/sysdev.h>
3b7d1921 34#include <linux/msi.h>
95d77884 35#include <linux/htirq.h>
7dfb7103 36#include <linux/freezer.h>
f26d6a2b 37#include <linux/kthread.h>
d4057bdb
YL		 38#include <linux/jiffies.h> /* time_after() */
39#ifdef CONFIG_ACPI
40#include <acpi/acpi_bus.h>
41#endif
42#include <linux/bootmem.h>
43#include <linux/dmar.h>
54d5d424 44
d4057bdb 45#include <asm/idle.h>
1da177e4
LT		 46#include <asm/io.h>
47#include <asm/smp.h>
48#include <asm/desc.h>
d4057bdb
YL		 49#include <asm/proto.h>
50#include <asm/acpi.h>
51#include <asm/dma.h>
1da177e4 52#include <asm/timer.h>
306e440d 53#include <asm/i8259.h>
3e4ff115 54#include <asm/nmi.h>
2d3fcc1c 55#include <asm/msidef.h>
8b955b0d 56#include <asm/hypertransport.h>
a4dbc34d 57#include <asm/setup.h>
d4057bdb 58#include <asm/irq_remapping.h>
1da177e4 59
497c9a19 60#include <mach_ipi.h>
1da177e4 61#include <mach_apic.h>
874c4fe3 62#include <mach_apicdef.h>
1da177e4 63
32f71aff
MR		 64#define __apicdebuginit(type) static type __init
65
1da177e4
LT		 66/*
67 * Is the SiS APIC rmw bug present ?
68 * -1 = don't know, 0 = no, 1 = yes
69 */
70int sis_apic_bug = -1;
71
efa2559f
YL		 72static DEFINE_SPINLOCK(ioapic_lock);
73static DEFINE_SPINLOCK(vector_lock);
74
301e6190 75int first_free_entry;
efa2559f
YL		 76/*
77 * Rough estimation of how many shared IRQs there are, can
78 * be changed anytime.
79 */
80int pin_map_size;
81
1da177e4
LT		 82/*
83 * # of IRQ routing registers
84 */
85int nr_ioapic_registers[MAX_IO_APICS];
86
9f640ccb 87/* I/O APIC entries */
ec2cd0a2 88struct mp_config_ioapic mp_ioapics[MAX_IO_APICS];
9f640ccb
AS		 89int nr_ioapics;
90
584f734d 91/* MP IRQ source entries */
2fddb6e2 92struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
584f734d
AS		 93
94/* # of MP IRQ source entries */
95int mp_irq_entries;
96
8732fc4b
AS		 97#if defined (CONFIG_MCA) || defined (CONFIG_EISA)
98int mp_bus_id_to_type[MAX_MP_BUSSES];
99#endif
100
101DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
102
efa2559f
YL		 103int skip_ioapic_setup;
104
105static int __init parse_noapic(char *arg)
106{
107 /* disable IO-APIC */
108 disable_ioapic_setup();
109 return 0;
110}
111early_param("noapic", parse_noapic);
66759a01 112
da51a821 113struct irq_cfg;
0f978f45 114struct irq_pin_list;
a1420f39 115struct irq_cfg {
da51a821
YL		 116 unsigned int irq;
117 struct irq_cfg *next;
0f978f45 118 struct irq_pin_list *irq_2_pin;
497c9a19
YL		 119 cpumask_t domain;
120 cpumask_t old_domain;
121 unsigned move_cleanup_count;
a1420f39 122 u8 vector;
497c9a19 123 u8 move_in_progress : 1;
a1420f39
YL		 124};
125
a1420f39
YL		 126/* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
127static struct irq_cfg irq_cfg_legacy[] __initdata = {
497c9a19
YL		 128 [0] = { .irq = 0, .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
129 [1] = { .irq = 1, .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
130 [2] = { .irq = 2, .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
131 [3] = { .irq = 3, .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
132 [4] = { .irq = 4, .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
133 [5] = { .irq = 5, .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
134 [6] = { .irq = 6, .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
135 [7] = { .irq = 7, .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
136 [8] = { .irq = 8, .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
137 [9] = { .irq = 9, .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
138 [10] = { .irq = 10, .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
139 [11] = { .irq = 11, .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
140 [12] = { .irq = 12, .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
141 [13] = { .irq = 13, .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
142 [14] = { .irq = 14, .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
143 [15] = { .irq = 15, .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
a1420f39
YL		 144};
145
da51a821
YL		 146static struct irq_cfg irq_cfg_init = { .irq = -1U, };
147/* need to be biger than size of irq_cfg_legacy */
148static int nr_irq_cfg = 32;
149
150static int __init parse_nr_irq_cfg(char *arg)
151{
152 if (arg) {
153 nr_irq_cfg = simple_strtoul(arg, NULL, 0);
154 if (nr_irq_cfg < 32)
155 nr_irq_cfg = 32;
156 }
157 return 0;
158}
159
160early_param("nr_irq_cfg", parse_nr_irq_cfg);
161
162static void init_one_irq_cfg(struct irq_cfg *cfg)
163{
164 memcpy(cfg, &irq_cfg_init, sizeof(struct irq_cfg));
165}
166
167static struct irq_cfg *irq_cfgx;
168static struct irq_cfg *irq_cfgx_free;
a1420f39
YL		 169static void __init init_work(void *data)
170{
da51a821
YL		 171 struct dyn_array *da = data;
172 struct irq_cfg *cfg;
173 int legacy_count;
174 int i;
175
176 cfg = *da->name;
a1420f39 177
da51a821 178 memcpy(cfg, irq_cfg_legacy, sizeof(irq_cfg_legacy));
a1420f39 179
da51a821
YL		 180 legacy_count = sizeof(irq_cfg_legacy)/sizeof(irq_cfg_legacy[0]);
181 for (i = legacy_count; i < *da->nr; i++)
182 init_one_irq_cfg(&cfg[i]);
a1420f39 183
da51a821
YL		 184 for (i = 1; i < *da->nr; i++)
185 cfg[i-1].next = &cfg[i];
a1420f39 186
da51a821
YL		 187 irq_cfgx_free = &irq_cfgx[legacy_count];
188 irq_cfgx[legacy_count - 1].next = NULL;
a1420f39
YL		 189}
190
da51a821
YL		 191#define for_each_irq_cfg(cfg) \
192 for (cfg = irq_cfgx; cfg; cfg = cfg->next)
193
194DEFINE_DYN_ARRAY(irq_cfgx, sizeof(struct irq_cfg), nr_irq_cfg, PAGE_SIZE, init_work);
a1420f39
YL		 195
196static struct irq_cfg *irq_cfg(unsigned int irq)
197{
da51a821
YL		 198 struct irq_cfg *cfg;
199
200 cfg = irq_cfgx;
201 while (cfg) {
202 if (cfg->irq == irq)
203 return cfg;
204
205 cfg = cfg->next;
206 }
207
208 return NULL;
209}
210
211static struct irq_cfg *irq_cfg_alloc(unsigned int irq)
212{
213 struct irq_cfg *cfg, *cfg_pri;
214 int i;
215 int count = 0;
216
217 cfg_pri = cfg = irq_cfgx;
218 while (cfg) {
219 if (cfg->irq == irq)
220 return cfg;
221
222 cfg_pri = cfg;
223 cfg = cfg->next;
224 count++;
225 }
226
227 if (!irq_cfgx_free) {
228 unsigned long phys;
229 unsigned long total_bytes;
230 /*
231 * we run out of pre-allocate ones, allocate more
232 */
233 printk(KERN_DEBUG "try to get more irq_cfg %d\n", nr_irq_cfg);
234
235 total_bytes = sizeof(struct irq_cfg) * nr_irq_cfg;
236 if (after_bootmem)
237 cfg = kzalloc(total_bytes, GFP_ATOMIC);
238 else
239 cfg = __alloc_bootmem_nopanic(total_bytes, PAGE_SIZE, 0);
a1420f39 240
da51a821
YL		 241 if (!cfg)
242 panic("please boot with nr_irq_cfg= %d\n", count * 2);
243
244 phys = __pa(cfg);
245 printk(KERN_DEBUG "irq_irq ==> [%#lx - %#lx]\n", phys, phys + total_bytes);
246
247 for (i = 0; i < nr_irq_cfg; i++)
248 init_one_irq_cfg(&cfg[i]);
249
250 for (i = 1; i < nr_irq_cfg; i++)
251 cfg[i-1].next = &cfg[i];
252
253 irq_cfgx_free = cfg;
254 }
255
256 cfg = irq_cfgx_free;
257 irq_cfgx_free = irq_cfgx_free->next;
258 cfg->next = NULL;
259 if (cfg_pri)
260 cfg_pri->next = cfg;
261 else
262 irq_cfgx = cfg;
263 cfg->irq = irq;
264 printk(KERN_DEBUG "found new irq_cfg for irq %d\n", cfg->irq);
265
266#ifdef CONFIG_HAVE_SPARSE_IRQ_DEBUG
267 {
268 /* dump the results */
269 struct irq_cfg *cfg;
270 unsigned long phys;
271 unsigned long bytes = sizeof(struct irq_cfg);
272
273 printk(KERN_DEBUG "=========================== %d\n", irq);
274 printk(KERN_DEBUG "irq_cfg dump after get that for %d\n", irq);
275 for_each_irq_cfg(cfg) {
276 phys = __pa(cfg);
277 printk(KERN_DEBUG "irq_cfg %d ==> [%#lx - %#lx]\n", cfg->irq, phys, phys + bytes);
278 }
279 printk(KERN_DEBUG "===========================\n");
280 }
281#endif
282 return cfg;
a1420f39
YL		 283}
284
1da177e4
LT		 285/*
286 * This is performance-critical, we want to do it O(1)
287 *
288 * the indexing order of this array favors 1:1 mappings
289 * between pins and IRQs.
290 */
291
0f978f45
YL		 292struct irq_pin_list {
293 int apic, pin;
294 struct irq_pin_list *next;
295};
296
297static struct irq_pin_list *irq_2_pin_head;
298/* fill one page ? */
299static int nr_irq_2_pin = 0x100;
300static struct irq_pin_list *irq_2_pin_ptr;
301static void __init irq_2_pin_init_work(void *data)
302{
303 struct dyn_array *da = data;
304 struct irq_pin_list *pin;
305 int i;
306
307 pin = *da->name;
308
309 for (i = 1; i < *da->nr; i++)
310 pin[i-1].next = &pin[i];
311
312 irq_2_pin_ptr = &pin[0];
313}
314DEFINE_DYN_ARRAY(irq_2_pin_head, sizeof(struct irq_pin_list), nr_irq_2_pin, PAGE_SIZE, irq_2_pin_init_work);
315
316static struct irq_pin_list *get_one_free_irq_2_pin(void)
317{
318 struct irq_pin_list *pin;
319 int i;
320
321 pin = irq_2_pin_ptr;
322
323 if (pin) {
324 irq_2_pin_ptr = pin->next;
325 pin->next = NULL;
326 return pin;
327 }
328
329 /*
330 * we run out of pre-allocate ones, allocate more
331 */
332 printk(KERN_DEBUG "try to get more irq_2_pin %d\n", nr_irq_2_pin);
333
334 if (after_bootmem)
335 pin = kzalloc(sizeof(struct irq_pin_list)*nr_irq_2_pin,
336 GFP_ATOMIC);
337 else
338 pin = __alloc_bootmem_nopanic(sizeof(struct irq_pin_list) *
339 nr_irq_2_pin, PAGE_SIZE, 0);
340
341 if (!pin)
342 panic("can not get more irq_2_pin\n");
301e6190 343
0f978f45
YL		 344 for (i = 1; i < nr_irq_2_pin; i++)
345 pin[i-1].next = &pin[i];
346
347 irq_2_pin_ptr = pin->next;
348 pin->next = NULL;
349
350 return pin;
351}
1da177e4 352
130fe05d
LT		 353struct io_apic {
354 unsigned int index;
355 unsigned int unused[3];
356 unsigned int data;
357};
358
359static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
360{
361 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
ec2cd0a2 362 + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK);
130fe05d
LT		 363}
364
365static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
366{
367 struct io_apic __iomem *io_apic = io_apic_base(apic);
368 writel(reg, &io_apic->index);
369 return readl(&io_apic->data);
370}
371
372static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
373{
374 struct io_apic __iomem *io_apic = io_apic_base(apic);
375 writel(reg, &io_apic->index);
376 writel(value, &io_apic->data);
377}
378
379/*
380 * Re-write a value: to be used for read-modify-write
381 * cycles where the read already set up the index register.
382 *
383 * Older SiS APIC requires we rewrite the index register
384 */
385static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
386{
cb468984 387 volatile struct io_apic __iomem *io_apic = io_apic_base(apic);
130fe05d
LT		 388 if (sis_apic_bug)
389 writel(reg, &io_apic->index);
390 writel(value, &io_apic->data);
391}
392
047c8fdb
YL		 393#ifdef CONFIG_X86_64
394static bool io_apic_level_ack_pending(unsigned int irq)
395{
396 struct irq_pin_list *entry;
397 unsigned long flags;
398 struct irq_cfg *cfg = irq_cfg(irq);
399
400 spin_lock_irqsave(&ioapic_lock, flags);
401 entry = cfg->irq_2_pin;
402 for (;;) {
403 unsigned int reg;
404 int pin;
405
406 if (!entry)
407 break;
408 pin = entry->pin;
409 reg = io_apic_read(entry->apic, 0x10 + pin*2);
410 /* Is the remote IRR bit set? */
411 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
412 spin_unlock_irqrestore(&ioapic_lock, flags);
413 return true;
414 }
415 if (!entry->next)
416 break;
417 entry = entry->next;
418 }
419 spin_unlock_irqrestore(&ioapic_lock, flags);
420
421 return false;
422}
423#endif
424
cf4c6a2f
AK		 425union entry_union {
426 struct { u32 w1, w2; };
427 struct IO_APIC_route_entry entry;
428};
429
430static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
431{
432 union entry_union eu;
433 unsigned long flags;
434 spin_lock_irqsave(&ioapic_lock, flags);
435 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
436 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
437 spin_unlock_irqrestore(&ioapic_lock, flags);
438 return eu.entry;
439}
440
f9dadfa7
LT		 441/*
442 * When we write a new IO APIC routing entry, we need to write the high
443 * word first! If the mask bit in the low word is clear, we will enable
444 * the interrupt, and we need to make sure the entry is fully populated
445 * before that happens.
446 */
d15512f4
AK		 447static void
448__ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
cf4c6a2f 449{
cf4c6a2f
AK		 450 union entry_union eu;
451 eu.entry = e;
f9dadfa7
LT		 452 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
453 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
d15512f4
AK		 454}
455
456static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
457{
458 unsigned long flags;
459 spin_lock_irqsave(&ioapic_lock, flags);
460 __ioapic_write_entry(apic, pin, e);
f9dadfa7
LT		 461 spin_unlock_irqrestore(&ioapic_lock, flags);
462}
463
464/*
465 * When we mask an IO APIC routing entry, we need to write the low
466 * word first, in order to set the mask bit before we change the
467 * high bits!
468 */
469static void ioapic_mask_entry(int apic, int pin)
470{
471 unsigned long flags;
472 union entry_union eu = { .entry.mask = 1 };
473
cf4c6a2f
AK		 474 spin_lock_irqsave(&ioapic_lock, flags);
475 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
476 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
477 spin_unlock_irqrestore(&ioapic_lock, flags);
478}
479
497c9a19
YL		 480#ifdef CONFIG_SMP
481static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
482{
483 int apic, pin;
484 struct irq_cfg *cfg;
485 struct irq_pin_list *entry;
486
487 cfg = irq_cfg(irq);
488 entry = cfg->irq_2_pin;
489 for (;;) {
490 unsigned int reg;
491
492 if (!entry)
493 break;
494
495 apic = entry->apic;
496 pin = entry->pin;
497 io_apic_write(apic, 0x11 + pin*2, dest);
498 reg = io_apic_read(apic, 0x10 + pin*2);
499 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
500 reg |= vector;
501 io_apic_modify(apic, 0x10 + pin *2, reg);
502 if (!entry->next)
503 break;
504 entry = entry->next;
505 }
506}
efa2559f
YL		 507
508static int assign_irq_vector(int irq, cpumask_t mask);
509
497c9a19
YL		 510static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
511{
512 struct irq_cfg *cfg;
513 unsigned long flags;
514 unsigned int dest;
515 cpumask_t tmp;
516
497c9a19
YL		 517 cpus_and(tmp, mask, cpu_online_map);
518 if (cpus_empty(tmp))
519 return;
520
047c8fdb 521 cfg = irq_cfg(irq);
497c9a19
YL		 522 if (assign_irq_vector(irq, mask))
523 return;
524
525 cpus_and(tmp, cfg->domain, mask);
497c9a19
YL		 526 dest = cpu_mask_to_apicid(tmp);
527 /*
528 * Only the high 8 bits are valid.
529 */
530 dest = SET_APIC_LOGICAL_ID(dest);
531
532 spin_lock_irqsave(&ioapic_lock, flags);
533 __target_IO_APIC_irq(irq, dest, cfg->vector);
534 irq_to_desc(irq)->affinity = mask;
535 spin_unlock_irqrestore(&ioapic_lock, flags);
536}
537
538#endif /* CONFIG_SMP */
539
1da177e4
LT		 540/*
541 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
542 * shared ISA-space IRQs, so we have to support them. We are super
543 * fast in the common case, and fast for shared ISA-space IRQs.
544 */
545static void add_pin_to_irq(unsigned int irq, int apic, int pin)
546{
0f978f45
YL		 547 struct irq_cfg *cfg;
548 struct irq_pin_list *entry;
549
550 /* first time to refer irq_cfg, so with new */
551 cfg = irq_cfg_alloc(irq);
552 entry = cfg->irq_2_pin;
553 if (!entry) {
554 entry = get_one_free_irq_2_pin();
555 cfg->irq_2_pin = entry;
556 entry->apic = apic;
557 entry->pin = pin;
558 printk(KERN_DEBUG " 0 add_pin_to_irq: irq %d --> apic %d pin %d\n", irq, apic, pin);
559 return;
560 }
1da177e4 561
0f978f45
YL		 562 while (entry->next) {
563 /* not again, please */
564 if (entry->apic == apic && entry->pin == pin)
565 return;
1da177e4 566
0f978f45 567 entry = entry->next;
1da177e4 568 }
0f978f45
YL		 569
570 entry->next = get_one_free_irq_2_pin();
571 entry = entry->next;
1da177e4
LT		 572 entry->apic = apic;
573 entry->pin = pin;
0f978f45 574 printk(KERN_DEBUG " x add_pin_to_irq: irq %d --> apic %d pin %d\n", irq, apic, pin);
1da177e4
LT		 575}
576
577/*
578 * Reroute an IRQ to a different pin.
579 */
580static void __init replace_pin_at_irq(unsigned int irq,
581 int oldapic, int oldpin,
582 int newapic, int newpin)
583{
0f978f45
YL		 584 struct irq_cfg *cfg = irq_cfg(irq);
585 struct irq_pin_list *entry = cfg->irq_2_pin;
586 int replaced = 0;
1da177e4 587
0f978f45 588 while (entry) {
1da177e4
LT		 589 if (entry->apic == oldapic && entry->pin == oldpin) {
590 entry->apic = newapic;
591 entry->pin = newpin;
0f978f45
YL		 592 replaced = 1;
593 /* every one is different, right? */
1da177e4 594 break;
0f978f45
YL		 595 }
596 entry = entry->next;
1da177e4 597 }
0f978f45
YL		 598
599 /* why? call replace before add? */
600 if (!replaced)
601 add_pin_to_irq(irq, newapic, newpin);
1da177e4
LT		 602}
603
047c8fdb
YL		 604#ifdef CONFIG_X86_64
605/*
606 * Synchronize the IO-APIC and the CPU by doing
607 * a dummy read from the IO-APIC
608 */
609static inline void io_apic_sync(unsigned int apic)
610{
611 struct io_apic __iomem *io_apic = io_apic_base(apic);
612 readl(&io_apic->data);
613}
614
615#define __DO_ACTION(R, ACTION, FINAL) \
616 \
617{ \
618 int pin; \
619 struct irq_cfg *cfg; \
620 struct irq_pin_list *entry; \
621 \
622 cfg = irq_cfg(irq); \
623 entry = cfg->irq_2_pin; \
624 for (;;) { \
625 unsigned int reg; \
626 if (!entry) \
627 break; \
628 pin = entry->pin; \
629 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
630 reg ACTION; \
631 io_apic_modify(entry->apic, 0x10 + R + pin*2, reg); \
632 FINAL; \
633 if (!entry->next) \
634 break; \
635 entry = entry->next; \
636 } \
637}
638
639#define DO_ACTION(name,R,ACTION, FINAL) \
640 \
641 static void name##_IO_APIC_irq (unsigned int irq) \
642 __DO_ACTION(R, ACTION, FINAL)
643
644/* mask = 1 */
645DO_ACTION(__mask, 0, |= IO_APIC_REDIR_MASKED, io_apic_sync(entry->apic))
646
647/* mask = 0 */
648DO_ACTION(__unmask, 0, &= ~IO_APIC_REDIR_MASKED, )
649
650#else
651
36062448 652static void __modify_IO_APIC_irq(unsigned int irq, unsigned long enable, unsigned long disable)
1da177e4 653{
0f978f45
YL		 654 struct irq_cfg *cfg;
655 struct irq_pin_list *entry;
1da177e4
LT		 656 unsigned int pin, reg;
657
0f978f45
YL		 658 cfg = irq_cfg(irq);
659 entry = cfg->irq_2_pin;
1da177e4 660 for (;;) {
0f978f45 661 if (!entry)
1da177e4 662 break;
0f978f45 663 pin = entry->pin;
1da177e4
LT		 664 reg = io_apic_read(entry->apic, 0x10 + pin*2);
665 reg &= ~disable;
666 reg |= enable;
667 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
668 if (!entry->next)
669 break;
0f978f45 670 entry = entry->next;
1da177e4
LT		 671 }
672}
673
674/* mask = 1 */
36062448 675static void __mask_IO_APIC_irq(unsigned int irq)
1da177e4 676{
46b3b4ef 677 __modify_IO_APIC_irq(irq, IO_APIC_REDIR_MASKED, 0);
1da177e4
LT		 678}
679
680/* mask = 0 */
36062448 681static void __unmask_IO_APIC_irq(unsigned int irq)
1da177e4 682{
46b3b4ef 683 __modify_IO_APIC_irq(irq, 0, IO_APIC_REDIR_MASKED);
1da177e4
LT		 684}
685
686/* mask = 1, trigger = 0 */
36062448 687static void __mask_and_edge_IO_APIC_irq(unsigned int irq)
1da177e4 688{
46b3b4ef
CG		 689 __modify_IO_APIC_irq(irq, IO_APIC_REDIR_MASKED,
690 IO_APIC_REDIR_LEVEL_TRIGGER);
1da177e4
LT		 691}
692
693/* mask = 0, trigger = 1 */
36062448 694static void __unmask_and_level_IO_APIC_irq(unsigned int irq)
1da177e4 695{
46b3b4ef
CG		 696 __modify_IO_APIC_irq(irq, IO_APIC_REDIR_LEVEL_TRIGGER,
697 IO_APIC_REDIR_MASKED);
1da177e4
LT		 698}
699
047c8fdb
YL		 700#endif
701
36062448 702static void mask_IO_APIC_irq(unsigned int irq)
1da177e4
LT		 703{
704 unsigned long flags;
705
706 spin_lock_irqsave(&ioapic_lock, flags);
707 __mask_IO_APIC_irq(irq);
708 spin_unlock_irqrestore(&ioapic_lock, flags);
709}
710
36062448 711static void unmask_IO_APIC_irq(unsigned int irq)
1da177e4
LT		 712{
713 unsigned long flags;
714
715 spin_lock_irqsave(&ioapic_lock, flags);
716 __unmask_IO_APIC_irq(irq);
717 spin_unlock_irqrestore(&ioapic_lock, flags);
718}
719
720static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
721{
722 struct IO_APIC_route_entry entry;
36062448 723
1da177e4 724 /* Check delivery_mode to be sure we're not clearing an SMI pin */
cf4c6a2f 725 entry = ioapic_read_entry(apic, pin);
1da177e4
LT		 726 if (entry.delivery_mode == dest_SMI)
727 return;
728
729 /*
730 * Disable it in the IO-APIC irq-routing table:
731 */
f9dadfa7 732 ioapic_mask_entry(apic, pin);
1da177e4
LT		 733}
734
36062448 735static void clear_IO_APIC(void)
1da177e4
LT		 736{
737 int apic, pin;
738
739 for (apic = 0; apic < nr_ioapics; apic++)
740 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
741 clear_IO_APIC_pin(apic, pin);
742}
743
1da177e4 744#ifndef CONFIG_SMP
75604d7f 745void send_IPI_self(int vector)
1da177e4
LT		 746{
747 unsigned int cfg;
748
749 /*
750 * Wait for idle.
751 */
752 apic_wait_icr_idle();
753 cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
754 /*
755 * Send the IPI. The write to APIC_ICR fires this off.
756 */
593f4a78 757 apic_write(APIC_ICR, cfg);
1da177e4
LT		 758}
759#endif /* !CONFIG_SMP */
760
761
762/*
763 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
764 * specific CPU-side IRQs.
765 */
766
767#define MAX_PIRQS 8
768static int pirq_entries [MAX_PIRQS];
769static int pirqs_enabled;
1da177e4 770
1da177e4
LT		 771static int __init ioapic_pirq_setup(char *str)
772{
773 int i, max;
774 int ints[MAX_PIRQS+1];
775
776 get_options(str, ARRAY_SIZE(ints), ints);
777
778 for (i = 0; i < MAX_PIRQS; i++)
779 pirq_entries[i] = -1;
780
781 pirqs_enabled = 1;
782 apic_printk(APIC_VERBOSE, KERN_INFO
783 "PIRQ redirection, working around broken MP-BIOS.\n");
784 max = MAX_PIRQS;
785 if (ints[0] < MAX_PIRQS)
786 max = ints[0];
787
788 for (i = 0; i < max; i++) {
789 apic_printk(APIC_VERBOSE, KERN_DEBUG
790 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
791 /*
792 * PIRQs are mapped upside down, usually.
793 */
794 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
795 }
796 return 1;
797}
798
799__setup("pirq=", ioapic_pirq_setup);
800
801/*
802 * Find the IRQ entry number of a certain pin.
803 */
804static int find_irq_entry(int apic, int pin, int type)
805{
806 int i;
807
808 for (i = 0; i < mp_irq_entries; i++)
2fddb6e2
AS		 809 if (mp_irqs[i].mp_irqtype == type &&
810 (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid ||
811 mp_irqs[i].mp_dstapic == MP_APIC_ALL) &&
812 mp_irqs[i].mp_dstirq == pin)
1da177e4
LT		 813 return i;
814
815 return -1;
816}
817
818/*
819 * Find the pin to which IRQ[irq] (ISA) is connected
820 */
fcfd636a 821static int __init find_isa_irq_pin(int irq, int type)
1da177e4
LT		 822{
823 int i;
824
825 for (i = 0; i < mp_irq_entries; i++) {
2fddb6e2 826 int lbus = mp_irqs[i].mp_srcbus;
1da177e4 827
d27e2b8e 828 if (test_bit(lbus, mp_bus_not_pci) &&
2fddb6e2
AS		 829 (mp_irqs[i].mp_irqtype == type) &&
830 (mp_irqs[i].mp_srcbusirq == irq))
1da177e4 831
2fddb6e2 832 return mp_irqs[i].mp_dstirq;
1da177e4
LT		 833 }
834 return -1;
835}
836
fcfd636a
EB		 837static int __init find_isa_irq_apic(int irq, int type)
838{
839 int i;
840
841 for (i = 0; i < mp_irq_entries; i++) {
2fddb6e2 842 int lbus = mp_irqs[i].mp_srcbus;
fcfd636a 843
73b2961b 844 if (test_bit(lbus, mp_bus_not_pci) &&
2fddb6e2
AS		 845 (mp_irqs[i].mp_irqtype == type) &&
846 (mp_irqs[i].mp_srcbusirq == irq))
fcfd636a
EB		 847 break;
848 }
849 if (i < mp_irq_entries) {
850 int apic;
36062448 851 for (apic = 0; apic < nr_ioapics; apic++) {
2fddb6e2 852 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic)
fcfd636a
EB		 853 return apic;
854 }
855 }
856
857 return -1;
858}
859
1da177e4
LT		 860/*
861 * Find a specific PCI IRQ entry.
862 * Not an __init, possibly needed by modules
863 */
864static int pin_2_irq(int idx, int apic, int pin);
865
866int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
867{
868 int apic, i, best_guess = -1;
869
870 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
871 "slot:%d, pin:%d.\n", bus, slot, pin);
ce6444d3 872 if (test_bit(bus, mp_bus_not_pci)) {
1da177e4
LT		 873 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
874 return -1;
875 }
876 for (i = 0; i < mp_irq_entries; i++) {
2fddb6e2 877 int lbus = mp_irqs[i].mp_srcbus;
1da177e4
LT		 878
879 for (apic = 0; apic < nr_ioapics; apic++)
2fddb6e2
AS		 880 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic ||
881 mp_irqs[i].mp_dstapic == MP_APIC_ALL)
1da177e4
LT		 882 break;
883
47cab822 884 if (!test_bit(lbus, mp_bus_not_pci) &&
2fddb6e2 885 !mp_irqs[i].mp_irqtype &&
1da177e4 886 (bus == lbus) &&
2fddb6e2 887 (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) {
3de352bb 888 int irq = pin_2_irq(i, apic, mp_irqs[i].mp_dstirq);
1da177e4
LT		 889
890 if (!(apic || IO_APIC_IRQ(irq)))
891 continue;
892
2fddb6e2 893 if (pin == (mp_irqs[i].mp_srcbusirq & 3))
1da177e4
LT		 894 return irq;
895 /*
896 * Use the first all-but-pin matching entry as a
897 * best-guess fuzzy result for broken mptables.
898 */
899 if (best_guess < 0)
900 best_guess = irq;
901 }
902 }
903 return best_guess;
904}
129f6946 905EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1da177e4 906
c0a282c2 907#if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1da177e4
LT		 908/*
909 * EISA Edge/Level control register, ELCR
910 */
911static int EISA_ELCR(unsigned int irq)
912{
913 if (irq < 16) {
914 unsigned int port = 0x4d0 + (irq >> 3);
915 return (inb(port) >> (irq & 7)) & 1;
916 }
917 apic_printk(APIC_VERBOSE, KERN_INFO
918 "Broken MPtable reports ISA irq %d\n", irq);
919 return 0;
920}
c0a282c2 921#endif
1da177e4 922
6728801d
AS		 923/* ISA interrupts are always polarity zero edge triggered,
924 * when listed as conforming in the MP table. */
925
926#define default_ISA_trigger(idx) (0)
927#define default_ISA_polarity(idx) (0)
928
1da177e4
LT		 929/* EISA interrupts are always polarity zero and can be edge or level
930 * trigger depending on the ELCR value. If an interrupt is listed as
931 * EISA conforming in the MP table, that means its trigger type must
932 * be read in from the ELCR */
933
2fddb6e2 934#define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq))
6728801d 935#define default_EISA_polarity(idx) default_ISA_polarity(idx)
1da177e4
LT		 936
937/* PCI interrupts are always polarity one level triggered,
938 * when listed as conforming in the MP table. */
939
940#define default_PCI_trigger(idx) (1)
941#define default_PCI_polarity(idx) (1)
942
943/* MCA interrupts are always polarity zero level triggered,
944 * when listed as conforming in the MP table. */
945
946#define default_MCA_trigger(idx) (1)
6728801d 947#define default_MCA_polarity(idx) default_ISA_polarity(idx)
1da177e4 948
61fd47e0 949static int MPBIOS_polarity(int idx)
1da177e4 950{
2fddb6e2 951 int bus = mp_irqs[idx].mp_srcbus;
1da177e4
LT		 952 int polarity;
953
954 /*
955 * Determine IRQ line polarity (high active or low active):
956 */
3de352bb 957 switch (mp_irqs[idx].mp_irqflag & 3) {
36062448 958 case 0: /* conforms, ie. bus-type dependent polarity */
1da177e4 959 {
36062448
PC		 960 polarity = test_bit(bus, mp_bus_not_pci)?
961 default_ISA_polarity(idx):
962 default_PCI_polarity(idx);
963 break;
964 }
965 case 1: /* high active */
966 {
967 polarity = 0;
968 break;
969 }
970 case 2: /* reserved */
971 {
972 printk(KERN_WARNING "broken BIOS!!\n");
973 polarity = 1;
974 break;
975 }
976 case 3: /* low active */
977 {
978 polarity = 1;
979 break;
980 }
981 default: /* invalid */
982 {
983 printk(KERN_WARNING "broken BIOS!!\n");
984 polarity = 1;
985 break;
986 }
1da177e4
LT		 987 }
988 return polarity;
989}
990
991static int MPBIOS_trigger(int idx)
992{
2fddb6e2 993 int bus = mp_irqs[idx].mp_srcbus;
1da177e4
LT		 994 int trigger;
995
996 /*
997 * Determine IRQ trigger mode (edge or level sensitive):
998 */
3de352bb 999 switch ((mp_irqs[idx].mp_irqflag>>2) & 3) {
36062448 1000 case 0: /* conforms, ie. bus-type dependent */
1da177e4 1001 {
36062448
PC		 1002 trigger = test_bit(bus, mp_bus_not_pci)?
1003 default_ISA_trigger(idx):
1004 default_PCI_trigger(idx);
c0a282c2 1005#if defined(CONFIG_EISA) || defined(CONFIG_MCA)
36062448
PC		 1006 switch (mp_bus_id_to_type[bus]) {
1007 case MP_BUS_ISA: /* ISA pin */
1008 {
1009 /* set before the switch */
1da177e4
LT		 1010 break;
1011 }
36062448 1012 case MP_BUS_EISA: /* EISA pin */
1da177e4 1013 {
36062448 1014 trigger = default_EISA_trigger(idx);
1da177e4
LT		 1015 break;
1016 }
36062448 1017 case MP_BUS_PCI: /* PCI pin */
1da177e4 1018 {
36062448 1019 /* set before the switch */
1da177e4
LT		 1020 break;
1021 }
36062448 1022 case MP_BUS_MCA: /* MCA pin */
1da177e4 1023 {
36062448 1024 trigger = default_MCA_trigger(idx);
1da177e4
LT		 1025 break;
1026 }
36062448 1027 default:
1da177e4
LT		 1028 {
1029 printk(KERN_WARNING "broken BIOS!!\n");
36062448 1030 trigger = 1;
1da177e4
LT		 1031 break;
1032 }
1033 }
36062448
PC		 1034#endif
1035 break;
1036 }
1037 case 1: /* edge */
1038 {
1039 trigger = 0;
1040 break;
1041 }
1042 case 2: /* reserved */
1043 {
1044 printk(KERN_WARNING "broken BIOS!!\n");
1045 trigger = 1;
1046 break;
1047 }
1048 case 3: /* level */
1049 {
1050 trigger = 1;
1051 break;
1052 }
1053 default: /* invalid */
1054 {
1055 printk(KERN_WARNING "broken BIOS!!\n");
1056 trigger = 0;
1057 break;
1058 }
1059 }
1da177e4
LT		 1060 return trigger;
1061}
1062
1063static inline int irq_polarity(int idx)
1064{
1065 return MPBIOS_polarity(idx);
1066}
1067
1068static inline int irq_trigger(int idx)
1069{
1070 return MPBIOS_trigger(idx);
1071}
1072
efa2559f 1073int (*ioapic_renumber_irq)(int ioapic, int irq);
1da177e4
LT		 1074static int pin_2_irq(int idx, int apic, int pin)
1075{
1076 int irq, i;
2fddb6e2 1077 int bus = mp_irqs[idx].mp_srcbus;
1da177e4
LT		 1078
1079 /*
1080 * Debugging check, we are in big trouble if this message pops up!
1081 */
2fddb6e2 1082 if (mp_irqs[idx].mp_dstirq != pin)
1da177e4
LT		 1083 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1084
643befed 1085 if (test_bit(bus, mp_bus_not_pci))
2fddb6e2 1086 irq = mp_irqs[idx].mp_srcbusirq;
643befed
AS		 1087 else {
1088 /*
1089 * PCI IRQs are mapped in order
1090 */
1091 i = irq = 0;
1092 while (i < apic)
1093 irq += nr_ioapic_registers[i++];
1094 irq += pin;
1da177e4 1095
643befed
AS		 1096 /*
1097 * For MPS mode, so far only needed by ES7000 platform
1098 */
1099 if (ioapic_renumber_irq)
1100 irq = ioapic_renumber_irq(apic, irq);
1da177e4
LT		 1101 }
1102
1103 /*
1104 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1105 */
1106 if ((pin >= 16) && (pin <= 23)) {
1107 if (pirq_entries[pin-16] != -1) {
1108 if (!pirq_entries[pin-16]) {
1109 apic_printk(APIC_VERBOSE, KERN_DEBUG
1110 "disabling PIRQ%d\n", pin-16);
1111 } else {
1112 irq = pirq_entries[pin-16];
1113 apic_printk(APIC_VERBOSE, KERN_DEBUG
1114 "using PIRQ%d -> IRQ %d\n",
1115 pin-16, irq);
1116 }
1117 }
1118 }
1119 return irq;
1120}
1121
497c9a19
YL		 1122void lock_vector_lock(void)
1123{
1124 /* Used to the online set of cpus does not change
1125 * during assign_irq_vector.
1126 */
1127 spin_lock(&vector_lock);
1128}
1da177e4 1129
497c9a19 1130void unlock_vector_lock(void)
1da177e4 1131{
497c9a19
YL		 1132 spin_unlock(&vector_lock);
1133}
1da177e4 1134
497c9a19
YL		 1135static int __assign_irq_vector(int irq, cpumask_t mask)
1136{
047c8fdb
YL		 1137 /*
1138 * NOTE! The local APIC isn't very good at handling
1139 * multiple interrupts at the same interrupt level.
1140 * As the interrupt level is determined by taking the
1141 * vector number and shifting that right by 4, we
1142 * want to spread these out a bit so that they don't
1143 * all fall in the same interrupt level.
1144 *
1145 * Also, we've got to be careful not to trash gate
1146 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1147 */
497c9a19
YL		 1148 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1149 unsigned int old_vector;
1150 int cpu;
1151 struct irq_cfg *cfg;
ace80ab7 1152
497c9a19 1153 cfg = irq_cfg(irq);
8339f000 1154
497c9a19
YL		 1155 /* Only try and allocate irqs on cpus that are present */
1156 cpus_and(mask, mask, cpu_online_map);
ace80ab7 1157
497c9a19
YL		 1158 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1159 return -EBUSY;
0a1ad60d 1160
497c9a19
YL		 1161 old_vector = cfg->vector;
1162 if (old_vector) {
1163 cpumask_t tmp;
1164 cpus_and(tmp, cfg->domain, mask);
1165 if (!cpus_empty(tmp))
1166 return 0;
1167 }
1168
1169 for_each_cpu_mask_nr(cpu, mask) {
1170 cpumask_t domain, new_mask;
1171 int new_cpu;
1172 int vector, offset;
1173
1174 domain = vector_allocation_domain(cpu);
1175 cpus_and(new_mask, domain, cpu_online_map);
1176
1177 vector = current_vector;
1178 offset = current_offset;
1179next:
1180 vector += 8;
1181 if (vector >= first_system_vector) {
1182 /* If we run out of vectors on large boxen, must share them. */
1183 offset = (offset + 1) % 8;
1184 vector = FIRST_DEVICE_VECTOR + offset;
1185 }
1186 if (unlikely(current_vector == vector))
1187 continue;
047c8fdb
YL		 1188#ifdef CONFIG_X86_64
1189 if (vector == IA32_SYSCALL_VECTOR)
497c9a19 1190 goto next;
047c8fdb
YL		 1191#else
1192 if (vector == SYSCALL_VECTOR)
1193 goto next;
1194#endif
497c9a19
YL		 1195 for_each_cpu_mask_nr(new_cpu, new_mask)
1196 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1197 goto next;
1198 /* Found one! */
1199 current_vector = vector;
1200 current_offset = offset;
1201 if (old_vector) {
1202 cfg->move_in_progress = 1;
1203 cfg->old_domain = cfg->domain;
1204 }
7a959cff
YL		 1205 printk(KERN_DEBUG "assign_irq_vector: irq %d vector %#x cpu ", irq, vector);
1206 for_each_cpu_mask_nr(new_cpu, new_mask) {
1207 per_cpu(vector_irq, new_cpu)[vector] = irq;
1208 printk(KERN_CONT " %d ", new_cpu);
1209 }
1210 printk(KERN_CONT "\n");
497c9a19
YL		 1211 cfg->vector = vector;
1212 cfg->domain = domain;
1213 return 0;
1214 }
1215 return -ENOSPC;
1216}
1217
1218static int assign_irq_vector(int irq, cpumask_t mask)
1219{
1220 int err;
ace80ab7 1221 unsigned long flags;
ace80ab7
EB		 1222
1223 spin_lock_irqsave(&vector_lock, flags);
497c9a19 1224 err = __assign_irq_vector(irq, mask);
26a3c49c 1225 spin_unlock_irqrestore(&vector_lock, flags);
1da177e4 1226
497c9a19
YL		 1227 return err;
1228}
1229
1230static void __clear_irq_vector(int irq)
1231{
1232 struct irq_cfg *cfg;
1233 cpumask_t mask;
1234 int cpu, vector;
1235
1236 cfg = irq_cfg(irq);
1237 BUG_ON(!cfg->vector);
1238
1239 vector = cfg->vector;
1240 cpus_and(mask, cfg->domain, cpu_online_map);
1241 for_each_cpu_mask_nr(cpu, mask)
1242 per_cpu(vector_irq, cpu)[vector] = -1;
1243
1244 cfg->vector = 0;
1245 cpus_clear(cfg->domain);
1246}
1247
1248void __setup_vector_irq(int cpu)
1249{
1250 /* Initialize vector_irq on a new cpu */
1251 /* This function must be called with vector_lock held */
1252 int irq, vector;
1253 struct irq_cfg *cfg;
1254
1255 /* Mark the inuse vectors */
1256 for_each_irq_cfg(cfg) {
1257 if (!cpu_isset(cpu, cfg->domain))
1258 continue;
1259 vector = cfg->vector;
1260 irq = cfg->irq;
1261 per_cpu(vector_irq, cpu)[vector] = irq;
1262 }
1263 /* Mark the free vectors */
1264 for (vector = 0; vector < NR_VECTORS; ++vector) {
1265 irq = per_cpu(vector_irq, cpu)[vector];
1266 if (irq < 0)
1267 continue;
1268
1269 cfg = irq_cfg(irq);
1270 if (!cpu_isset(cpu, cfg->domain))
1271 per_cpu(vector_irq, cpu)[vector] = -1;
1272 }
1da177e4 1273}
3fde6900 1274
f5b9ed7a 1275static struct irq_chip ioapic_chip;
1da177e4
LT		 1276
1277#define IOAPIC_AUTO -1
1278#define IOAPIC_EDGE 0
1279#define IOAPIC_LEVEL 1
1280
047c8fdb 1281#ifdef CONFIG_X86_32
1d025192
YL		 1282static inline int IO_APIC_irq_trigger(int irq)
1283{
1284 int apic, idx, pin;
1285
1286 for (apic = 0; apic < nr_ioapics; apic++) {
1287 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1288 idx = find_irq_entry(apic, pin, mp_INT);
1289 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1290 return irq_trigger(idx);
1291 }
1292 }
1293 /*
1294 * nonexistent IRQs are edge default
1295 */
1296 return 0;
1297}
047c8fdb
YL		 1298#else
1299static inline int IO_APIC_irq_trigger(int irq)
1300{
1301 return 1;
1302}
1303#endif
1d025192 1304
497c9a19 1305static void ioapic_register_intr(int irq, unsigned long trigger)
1da177e4 1306{
08678b08
YL		 1307 struct irq_desc *desc;
1308
199751d7
YL		 1309 /* first time to use this irq_desc */
1310 if (irq < 16)
1311 desc = irq_to_desc(irq);
1312 else
1313 desc = irq_to_desc_alloc(irq);
1314
6ebcc00e 1315 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
047c8fdb 1316 trigger == IOAPIC_LEVEL)
08678b08 1317 desc->status |= IRQ_LEVEL;
047c8fdb
YL		 1318 else
1319 desc->status &= ~IRQ_LEVEL;
1320
1321 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1322 trigger == IOAPIC_LEVEL)
a460e745
IM		 1323 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1324 handle_fasteoi_irq, "fasteoi");
047c8fdb 1325 else
a460e745
IM		 1326 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1327 handle_edge_irq, "edge");
1da177e4
LT		 1328}
1329
497c9a19
YL		 1330static int setup_ioapic_entry(int apic, int irq,
1331 struct IO_APIC_route_entry *entry,
1332 unsigned int destination, int trigger,
1333 int polarity, int vector)
1da177e4 1334{
497c9a19
YL		 1335 /*
1336 * add it to the IO-APIC irq-routing table:
1337 */
1338 memset(entry,0,sizeof(*entry));
1339
1340 entry->delivery_mode = INT_DELIVERY_MODE;
1341 entry->dest_mode = INT_DEST_MODE;
d83e94ac 1342 entry->dest = destination;
497c9a19
YL		 1343
1344 entry->mask = 0; /* enable IRQ */
1345 entry->trigger = trigger;
1346 entry->polarity = polarity;
1347 entry->vector = vector;
1348
1349 /* Mask level triggered irqs.
1350 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1351 */
1352 if (trigger)
1353 entry->mask = 1;
1354
1355 return 0;
1356}
1357
1358static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
1359 int trigger, int polarity)
1360{
1361 struct irq_cfg *cfg;
1da177e4 1362 struct IO_APIC_route_entry entry;
497c9a19
YL		 1363 cpumask_t mask;
1364
1365 if (!IO_APIC_IRQ(irq))
1366 return;
1367
1368 cfg = irq_cfg(irq);
1369
1370 mask = TARGET_CPUS;
1371 if (assign_irq_vector(irq, mask))
1372 return;
1373
1374 cpus_and(mask, cfg->domain, mask);
1375
1376 apic_printk(APIC_VERBOSE,KERN_DEBUG
1377 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1378 "IRQ %d Mode:%i Active:%i)\n",
1379 apic, mp_ioapics[apic].mp_apicid, pin, cfg->vector,
1380 irq, trigger, polarity);
1381
1382
1383 if (setup_ioapic_entry(mp_ioapics[apic].mp_apicid, irq, &entry,
1384 cpu_mask_to_apicid(mask), trigger, polarity,
1385 cfg->vector)) {
1386 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1387 mp_ioapics[apic].mp_apicid, pin);
1388 __clear_irq_vector(irq);
1389 return;
1390 }
1391
1392 ioapic_register_intr(irq, trigger);
1393 if (irq < 16)
1394 disable_8259A_irq(irq);
1395
1396 ioapic_write_entry(apic, pin, entry);
1397}
1398
1399static void __init setup_IO_APIC_irqs(void)
1400{
1401 int apic, pin, idx, irq, first_notcon = 1;
1da177e4
LT		 1402
1403 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1404
1405 for (apic = 0; apic < nr_ioapics; apic++) {
1406 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1407
497c9a19 1408 idx = find_irq_entry(apic,pin,mp_INT);
1da177e4
LT		 1409 if (idx == -1) {
1410 if (first_notcon) {
497c9a19 1411 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mp_apicid, pin);
1da177e4
LT		 1412 first_notcon = 0;
1413 } else
497c9a19 1414 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mp_apicid, pin);
1da177e4
LT		 1415 continue;
1416 }
20d225b9
YL		 1417 if (!first_notcon) {
1418 apic_printk(APIC_VERBOSE, " not connected.\n");
1419 first_notcon = 1;
1420 }
1421
1da177e4 1422 irq = pin_2_irq(idx, apic, pin);
1da177e4 1423
497c9a19
YL		 1424 if (multi_timer_check(apic, irq))
1425 continue;
1da177e4 1426
497c9a19 1427 add_pin_to_irq(irq, apic, pin);
36062448 1428
497c9a19
YL		 1429 setup_IO_APIC_irq(apic, pin, irq,
1430 irq_trigger(idx), irq_polarity(idx));
1da177e4
LT		 1431 }
1432 }
1433
1434 if (!first_notcon)
1435 apic_printk(APIC_VERBOSE, " not connected.\n");
1436}
1437
1438/*
f7633ce5 1439 * Set up the timer pin, possibly with the 8259A-master behind.
1da177e4 1440 */
f7633ce5
MR		 1441static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
1442 int vector)
1da177e4
LT		 1443{
1444 struct IO_APIC_route_entry entry;
1da177e4 1445
36062448 1446 memset(&entry, 0, sizeof(entry));
1da177e4
LT		 1447
1448 /*
1449 * We use logical delivery to get the timer IRQ
1450 * to the first CPU.
1451 */
1452 entry.dest_mode = INT_DEST_MODE;
03be7505 1453 entry.mask = 1; /* mask IRQ now */
d83e94ac 1454 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
1da177e4
LT		 1455 entry.delivery_mode = INT_DELIVERY_MODE;
1456 entry.polarity = 0;
1457 entry.trigger = 0;
1458 entry.vector = vector;
1459
1460 /*
1461 * The timer IRQ doesn't have to know that behind the
f7633ce5 1462 * scene we may have a 8259A-master in AEOI mode ...
1da177e4 1463 */
497c9a19 1464 ioapic_register_intr(0, IOAPIC_EDGE);
1da177e4
LT		 1465
1466 /*
1467 * Add it to the IO-APIC irq-routing table:
1468 */
cf4c6a2f 1469 ioapic_write_entry(apic, pin, entry);
1da177e4
LT		 1470}
1471
32f71aff
MR		 1472
1473__apicdebuginit(void) print_IO_APIC(void)
1da177e4
LT		 1474{
1475 int apic, i;
1476 union IO_APIC_reg_00 reg_00;
1477 union IO_APIC_reg_01 reg_01;
1478 union IO_APIC_reg_02 reg_02;
1479 union IO_APIC_reg_03 reg_03;
1480 unsigned long flags;
0f978f45 1481 struct irq_cfg *cfg;
1da177e4
LT		 1482
1483 if (apic_verbosity == APIC_QUIET)
1484 return;
1485
36062448 1486 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1da177e4
LT		 1487 for (i = 0; i < nr_ioapics; i++)
1488 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
ec2cd0a2 1489 mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]);
1da177e4
LT		 1490
1491 /*
1492 * We are a bit conservative about what we expect. We have to
1493 * know about every hardware change ASAP.
1494 */
1495 printk(KERN_INFO "testing the IO APIC.......................\n");
1496
1497 for (apic = 0; apic < nr_ioapics; apic++) {
1498
1499 spin_lock_irqsave(&ioapic_lock, flags);
1500 reg_00.raw = io_apic_read(apic, 0);
1501 reg_01.raw = io_apic_read(apic, 1);
1502 if (reg_01.bits.version >= 0x10)
1503 reg_02.raw = io_apic_read(apic, 2);
1504 if (reg_01.bits.version >= 0x20)
1505 reg_03.raw = io_apic_read(apic, 3);
1506 spin_unlock_irqrestore(&ioapic_lock, flags);
1507
ec2cd0a2 1508 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid);
1da177e4
LT		 1509 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1510 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1511 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1512 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1da177e4
LT		 1513
1514 printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1515 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1da177e4
LT		 1516
1517 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1518 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1da177e4
LT		 1519
1520 /*
1521 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1522 * but the value of reg_02 is read as the previous read register
1523 * value, so ignore it if reg_02 == reg_01.
1524 */
1525 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1526 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1527 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1da177e4
LT		 1528 }
1529
1530 /*
1531 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1532 * or reg_03, but the value of reg_0[23] is read as the previous read
1533 * register value, so ignore it if reg_03 == reg_0[12].
1534 */
1535 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1536 reg_03.raw != reg_01.raw) {
1537 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1538 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1da177e4
LT		 1539 }
1540
1541 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1542
d83e94ac
YL		 1543 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1544 " Stat Dmod Deli Vect: \n");
1da177e4
LT		 1545
1546 for (i = 0; i <= reg_01.bits.entries; i++) {
1547 struct IO_APIC_route_entry entry;
1548
cf4c6a2f 1549 entry = ioapic_read_entry(apic, i);
1da177e4 1550
d83e94ac 1551 printk(KERN_DEBUG " %02x %02X ", i, entry.dest);
1da177e4
LT		 1552
1553 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1554 entry.mask,
1555 entry.trigger,
1556 entry.irr,
1557 entry.polarity,
1558 entry.delivery_status,
1559 entry.dest_mode,
1560 entry.delivery_mode,
1561 entry.vector
1562 );
1563 }
1564 }
1da177e4 1565 printk(KERN_DEBUG "IRQ to pin mappings:\n");
0f978f45
YL		 1566 for_each_irq_cfg(cfg) {
1567 struct irq_pin_list *entry = cfg->irq_2_pin;
1568 if (!entry)
1da177e4 1569 continue;
ace80ab7 1570 printk(KERN_DEBUG "IRQ%d ", i);
1da177e4
LT		 1571 for (;;) {
1572 printk("-> %d:%d", entry->apic, entry->pin);
1573 if (!entry->next)
1574 break;
0f978f45 1575 entry = entry->next;
1da177e4
LT		 1576 }
1577 printk("\n");
1578 }
1579
1580 printk(KERN_INFO ".................................... done.\n");
1581
1582 return;
1583}
1584
32f71aff 1585__apicdebuginit(void) print_APIC_bitfield(int base)
1da177e4
LT		 1586{
1587 unsigned int v;
1588 int i, j;
1589
1590 if (apic_verbosity == APIC_QUIET)
1591 return;
1592
1593 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1594 for (i = 0; i < 8; i++) {
1595 v = apic_read(base + i*0x10);
1596 for (j = 0; j < 32; j++) {
1597 if (v & (1<<j))
1598 printk("1");
1599 else
1600 printk("0");
1601 }
1602 printk("\n");
1603 }
1604}
1605
32f71aff 1606__apicdebuginit(void) print_local_APIC(void *dummy)
1da177e4
LT		 1607{
1608 unsigned int v, ver, maxlvt;
7ab6af7a 1609 u64 icr;
1da177e4
LT		 1610
1611 if (apic_verbosity == APIC_QUIET)
1612 return;
1613
1614 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1615 smp_processor_id(), hard_smp_processor_id());
66823114 1616 v = apic_read(APIC_ID);
05f2d12c 1617 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v,
4c9961d5 1618 GET_APIC_ID(v));
1da177e4
LT		 1619 v = apic_read(APIC_LVR);
1620 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1621 ver = GET_APIC_VERSION(v);
e05d723f 1622 maxlvt = lapic_get_maxlvt();
1da177e4
LT		 1623
1624 v = apic_read(APIC_TASKPRI);
1625 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1626
1627 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1628 v = apic_read(APIC_ARBPRI);
1629 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1630 v & APIC_ARBPRI_MASK);
1631 v = apic_read(APIC_PROCPRI);
1632 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1633 }
1634
1635 v = apic_read(APIC_EOI);
1636 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1637 v = apic_read(APIC_RRR);
1638 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1639 v = apic_read(APIC_LDR);
1640 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1641 v = apic_read(APIC_DFR);
1642 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1643 v = apic_read(APIC_SPIV);
1644 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1645
1646 printk(KERN_DEBUG "... APIC ISR field:\n");
1647 print_APIC_bitfield(APIC_ISR);
1648 printk(KERN_DEBUG "... APIC TMR field:\n");
1649 print_APIC_bitfield(APIC_TMR);
1650 printk(KERN_DEBUG "... APIC IRR field:\n");
1651 print_APIC_bitfield(APIC_IRR);
1652
1653 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1654 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1655 apic_write(APIC_ESR, 0);
1656 v = apic_read(APIC_ESR);
1657 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1658 }
1659
7ab6af7a
HS		 1660 icr = apic_icr_read();
1661 printk(KERN_DEBUG "... APIC ICR: %08x\n", icr);
1662 printk(KERN_DEBUG "... APIC ICR2: %08x\n", icr >> 32);
1da177e4
LT		 1663
1664 v = apic_read(APIC_LVTT);
1665 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1666
1667 if (maxlvt > 3) { /* PC is LVT#4. */
1668 v = apic_read(APIC_LVTPC);
1669 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1670 }
1671 v = apic_read(APIC_LVT0);
1672 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1673 v = apic_read(APIC_LVT1);
1674 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1675
1676 if (maxlvt > 2) { /* ERR is LVT#3. */
1677 v = apic_read(APIC_LVTERR);
1678 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1679 }
1680
1681 v = apic_read(APIC_TMICT);
1682 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1683 v = apic_read(APIC_TMCCT);
1684 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1685 v = apic_read(APIC_TDCR);
1686 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1687 printk("\n");
1688}
1689
32f71aff 1690__apicdebuginit(void) print_all_local_APICs(void)
1da177e4 1691{
15c8b6c1 1692 on_each_cpu(print_local_APIC, NULL, 1);
1da177e4
LT		 1693}
1694
32f71aff 1695__apicdebuginit(void) print_PIC(void)
1da177e4 1696{
1da177e4
LT		 1697 unsigned int v;
1698 unsigned long flags;
1699
1700 if (apic_verbosity == APIC_QUIET)
1701 return;
1702
1703 printk(KERN_DEBUG "\nprinting PIC contents\n");
1704
1705 spin_lock_irqsave(&i8259A_lock, flags);
1706
1707 v = inb(0xa1) << 8 | inb(0x21);
1708 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1709
1710 v = inb(0xa0) << 8 | inb(0x20);
1711 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1712
36062448
PC		 1713 outb(0x0b, 0xa0);
1714 outb(0x0b, 0x20);
1da177e4 1715 v = inb(0xa0) << 8 | inb(0x20);
36062448
PC		 1716 outb(0x0a, 0xa0);
1717 outb(0x0a, 0x20);
1da177e4
LT		 1718
1719 spin_unlock_irqrestore(&i8259A_lock, flags);
1720
1721 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1722
1723 v = inb(0x4d1) << 8 | inb(0x4d0);
1724 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1725}
1726
32f71aff
MR		 1727__apicdebuginit(int) print_all_ICs(void)
1728{
1729 print_PIC();
1730 print_all_local_APICs();
1731 print_IO_APIC();
1732
1733 return 0;
1734}
1735
1736fs_initcall(print_all_ICs);
1737
1da177e4 1738
efa2559f
YL		 1739/* Where if anywhere is the i8259 connect in external int mode */
1740static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1741
1da177e4
LT		 1742static void __init enable_IO_APIC(void)
1743{
1744 union IO_APIC_reg_01 reg_01;
fcfd636a
EB		 1745 int i8259_apic, i8259_pin;
1746 int i, apic;
1da177e4
LT		 1747 unsigned long flags;
1748
1da177e4
LT		 1749 if (!pirqs_enabled)
1750 for (i = 0; i < MAX_PIRQS; i++)
1751 pirq_entries[i] = -1;
1752
1753 /*
1754 * The number of IO-APIC IRQ registers (== #pins):
1755 */
fcfd636a 1756 for (apic = 0; apic < nr_ioapics; apic++) {
1da177e4 1757 spin_lock_irqsave(&ioapic_lock, flags);
fcfd636a 1758 reg_01.raw = io_apic_read(apic, 1);
1da177e4 1759 spin_unlock_irqrestore(&ioapic_lock, flags);
fcfd636a
EB		 1760 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1761 }
36062448 1762 for (apic = 0; apic < nr_ioapics; apic++) {
fcfd636a
EB		 1763 int pin;
1764 /* See if any of the pins is in ExtINT mode */
1008fddc 1765 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
fcfd636a 1766 struct IO_APIC_route_entry entry;
cf4c6a2f 1767 entry = ioapic_read_entry(apic, pin);
fcfd636a 1768
fcfd636a
EB		 1769 /* If the interrupt line is enabled and in ExtInt mode
1770 * I have found the pin where the i8259 is connected.
1771 */
1772 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1773 ioapic_i8259.apic = apic;
1774 ioapic_i8259.pin = pin;
1775 goto found_i8259;
1776 }
1777 }
1778 }
1779 found_i8259:
1780 /* Look to see what if the MP table has reported the ExtINT */
1781 /* If we could not find the appropriate pin by looking at the ioapic
1782 * the i8259 probably is not connected the ioapic but give the
1783 * mptable a chance anyway.
1784 */
1785 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1786 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1787 /* Trust the MP table if nothing is setup in the hardware */
1788 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1789 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1790 ioapic_i8259.pin = i8259_pin;
1791 ioapic_i8259.apic = i8259_apic;
1792 }
1793 /* Complain if the MP table and the hardware disagree */
1794 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1795 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1796 {
1797 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1da177e4
LT		 1798 }
1799
1800 /*
1801 * Do not trust the IO-APIC being empty at bootup
1802 */
1803 clear_IO_APIC();
1804}
1805
1806/*
1807 * Not an __init, needed by the reboot code
1808 */
1809void disable_IO_APIC(void)
1810{
1811 /*
1812 * Clear the IO-APIC before rebooting:
1813 */
1814 clear_IO_APIC();
1815
650927ef 1816 /*
0b968d23 1817 * If the i8259 is routed through an IOAPIC
650927ef 1818 * Put that IOAPIC in virtual wire mode
0b968d23 1819 * so legacy interrupts can be delivered.
650927ef 1820 */
fcfd636a 1821 if (ioapic_i8259.pin != -1) {
650927ef 1822 struct IO_APIC_route_entry entry;
650927ef
EB		 1823
1824 memset(&entry, 0, sizeof(entry));
1825 entry.mask = 0; /* Enabled */
1826 entry.trigger = 0; /* Edge */
1827 entry.irr = 0;
1828 entry.polarity = 0; /* High */
1829 entry.delivery_status = 0;
1830 entry.dest_mode = 0; /* Physical */
fcfd636a 1831 entry.delivery_mode = dest_ExtINT; /* ExtInt */
650927ef 1832 entry.vector = 0;
d83e94ac 1833 entry.dest = read_apic_id();
650927ef
EB		 1834
1835 /*
1836 * Add it to the IO-APIC irq-routing table:
1837 */
cf4c6a2f 1838 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
650927ef 1839 }
fcfd636a 1840 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1da177e4
LT		 1841}
1842
1843/*
1844 * function to set the IO-APIC physical IDs based on the
1845 * values stored in the MPC table.
1846 *
1847 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1848 */
1849
1da177e4
LT		 1850static void __init setup_ioapic_ids_from_mpc(void)
1851{
1852 union IO_APIC_reg_00 reg_00;
1853 physid_mask_t phys_id_present_map;
1854 int apic;
1855 int i;
1856 unsigned char old_id;
1857 unsigned long flags;
1858
a4dbc34d 1859 if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
d49c4288 1860 return;
d49c4288 1861
ca05fea6
NP		 1862 /*
1863 * Don't check I/O APIC IDs for xAPIC systems. They have
1864 * no meaning without the serial APIC bus.
1865 */
7c5c1e42
SL		 1866 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1867 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
ca05fea6 1868 return;
1da177e4
LT		 1869 /*
1870 * This is broken; anything with a real cpu count has to
1871 * circumvent this idiocy regardless.
1872 */
1873 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1874
1875 /*
1876 * Set the IOAPIC ID to the value stored in the MPC table.
1877 */
1878 for (apic = 0; apic < nr_ioapics; apic++) {
1879
1880 /* Read the register 0 value */
1881 spin_lock_irqsave(&ioapic_lock, flags);
1882 reg_00.raw = io_apic_read(apic, 0);
1883 spin_unlock_irqrestore(&ioapic_lock, flags);
36062448 1884
ec2cd0a2 1885 old_id = mp_ioapics[apic].mp_apicid;
1da177e4 1886
ec2cd0a2 1887 if (mp_ioapics[apic].mp_apicid >= get_physical_broadcast()) {
1da177e4 1888 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
ec2cd0a2 1889 apic, mp_ioapics[apic].mp_apicid);
1da177e4
LT		 1890 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1891 reg_00.bits.ID);
ec2cd0a2 1892 mp_ioapics[apic].mp_apicid = reg_00.bits.ID;
1da177e4
LT		 1893 }
1894
1da177e4
LT		 1895 /*
1896 * Sanity check, is the ID really free? Every APIC in a
1897 * system must have a unique ID or we get lots of nice
1898 * 'stuck on smp_invalidate_needed IPI wait' messages.
1899 */
1900 if (check_apicid_used(phys_id_present_map,
ec2cd0a2 1901 mp_ioapics[apic].mp_apicid)) {
1da177e4 1902 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
ec2cd0a2 1903 apic, mp_ioapics[apic].mp_apicid);
1da177e4
LT		 1904 for (i = 0; i < get_physical_broadcast(); i++)
1905 if (!physid_isset(i, phys_id_present_map))
1906 break;
1907 if (i >= get_physical_broadcast())
1908 panic("Max APIC ID exceeded!\n");
1909 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1910 i);
1911 physid_set(i, phys_id_present_map);
ec2cd0a2 1912 mp_ioapics[apic].mp_apicid = i;
1da177e4
LT		 1913 } else {
1914 physid_mask_t tmp;
ec2cd0a2 1915 tmp = apicid_to_cpu_present(mp_ioapics[apic].mp_apicid);
1da177e4
LT		 1916 apic_printk(APIC_VERBOSE, "Setting %d in the "
1917 "phys_id_present_map\n",
ec2cd0a2 1918 mp_ioapics[apic].mp_apicid);
1da177e4
LT		 1919 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1920 }
1921
1922
1923 /*
1924 * We need to adjust the IRQ routing table
1925 * if the ID changed.
1926 */
ec2cd0a2 1927 if (old_id != mp_ioapics[apic].mp_apicid)
1da177e4 1928 for (i = 0; i < mp_irq_entries; i++)
2fddb6e2
AS		 1929 if (mp_irqs[i].mp_dstapic == old_id)
1930 mp_irqs[i].mp_dstapic
ec2cd0a2 1931 = mp_ioapics[apic].mp_apicid;
1da177e4
LT		 1932
1933 /*
1934 * Read the right value from the MPC table and
1935 * write it into the ID register.
36062448 1936 */
1da177e4
LT		 1937 apic_printk(APIC_VERBOSE, KERN_INFO
1938 "...changing IO-APIC physical APIC ID to %d ...",
ec2cd0a2 1939 mp_ioapics[apic].mp_apicid);
1da177e4 1940
ec2cd0a2 1941 reg_00.bits.ID = mp_ioapics[apic].mp_apicid;
1da177e4
LT		 1942 spin_lock_irqsave(&ioapic_lock, flags);
1943 io_apic_write(apic, 0, reg_00.raw);
1944 spin_unlock_irqrestore(&ioapic_lock, flags);
1945
1946 /*
1947 * Sanity check
1948 */
1949 spin_lock_irqsave(&ioapic_lock, flags);
1950 reg_00.raw = io_apic_read(apic, 0);
1951 spin_unlock_irqrestore(&ioapic_lock, flags);
ec2cd0a2 1952 if (reg_00.bits.ID != mp_ioapics[apic].mp_apicid)
1da177e4
LT		 1953 printk("could not set ID!\n");
1954 else
1955 apic_printk(APIC_VERBOSE, " ok.\n");
1956 }
1957}
1da177e4 1958
7ce0bcfd 1959int no_timer_check __initdata;
8542b200
ZA		 1960
1961static int __init notimercheck(char *s)
1962{
1963 no_timer_check = 1;
1964 return 1;
1965}
1966__setup("no_timer_check", notimercheck);
1967
1da177e4
LT		 1968/*
1969 * There is a nasty bug in some older SMP boards, their mptable lies
1970 * about the timer IRQ. We do the following to work around the situation:
1971 *
1972 * - timer IRQ defaults to IO-APIC IRQ
1973 * - if this function detects that timer IRQs are defunct, then we fall
1974 * back to ISA timer IRQs
1975 */
f0a7a5c9 1976static int __init timer_irq_works(void)
1da177e4
LT		 1977{
1978 unsigned long t1 = jiffies;
4aae0702 1979 unsigned long flags;
1da177e4 1980
8542b200
ZA		 1981 if (no_timer_check)
1982 return 1;
1983
4aae0702 1984 local_save_flags(flags);
1da177e4
LT		 1985 local_irq_enable();
1986 /* Let ten ticks pass... */
1987 mdelay((10 * 1000) / HZ);
4aae0702 1988 local_irq_restore(flags);
1da177e4
LT		 1989
1990 /*
1991 * Expect a few ticks at least, to be sure some possible
1992 * glue logic does not lock up after one or two first
1993 * ticks in a non-ExtINT mode. Also the local APIC
1994 * might have cached one ExtINT interrupt. Finally, at
1995 * least one tick may be lost due to delays.
1996 */
1d16b53e 1997 if (time_after(jiffies, t1 + 4))
1da177e4
LT		 1998 return 1;
1999
2000 return 0;
2001}
2002
2003/*
2004 * In the SMP+IOAPIC case it might happen that there are an unspecified
2005 * number of pending IRQ events unhandled. These cases are very rare,
2006 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2007 * better to do it this way as thus we do not have to be aware of
2008 * 'pending' interrupts in the IRQ path, except at this point.
2009 */
2010/*
2011 * Edge triggered needs to resend any interrupt
2012 * that was delayed but this is now handled in the device
2013 * independent code.
2014 */
2015
2016/*
f5b9ed7a
IM		 2017 * Startup quirk:
2018 *
1da177e4
LT		 2019 * Starting up a edge-triggered IO-APIC interrupt is
2020 * nasty - we need to make sure that we get the edge.
2021 * If it is already asserted for some reason, we need
2022 * return 1 to indicate that is was pending.
2023 *
2024 * This is not complete - we should be able to fake
2025 * an edge even if it isn't on the 8259A...
f5b9ed7a
IM		 2026 *
2027 * (We do this for level-triggered IRQs too - it cannot hurt.)
1da177e4 2028 */
f5b9ed7a 2029static unsigned int startup_ioapic_irq(unsigned int irq)
1da177e4
LT		 2030{
2031 int was_pending = 0;
2032 unsigned long flags;
2033
2034 spin_lock_irqsave(&ioapic_lock, flags);
2035 if (irq < 16) {
2036 disable_8259A_irq(irq);
2037 if (i8259A_irq_pending(irq))
2038 was_pending = 1;
2039 }
2040 __unmask_IO_APIC_irq(irq);
2041 spin_unlock_irqrestore(&ioapic_lock, flags);
2042
2043 return was_pending;
2044}
2045
ace80ab7 2046static int ioapic_retrigger_irq(unsigned int irq)
1da177e4 2047{
a1420f39 2048 send_IPI_self(irq_cfg(irq)->vector);
c0ad90a3
IM		 2049
2050 return 1;
2051}
2052
497c9a19
YL		 2053#ifdef CONFIG_SMP
2054asmlinkage void smp_irq_move_cleanup_interrupt(void)
2055{
2056 unsigned vector, me;
2057 ack_APIC_irq();
2058 irq_enter();
2059
2060 me = smp_processor_id();
2061 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2062 unsigned int irq;
2063 struct irq_desc *desc;
2064 struct irq_cfg *cfg;
2065 irq = __get_cpu_var(vector_irq)[vector];
2066
2067 desc = irq_to_desc(irq);
2068 if (!desc)
2069 continue;
2070
2071 cfg = irq_cfg(irq);
2072 spin_lock(&desc->lock);
2073 if (!cfg->move_cleanup_count)
2074 goto unlock;
2075
2076 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
2077 goto unlock;
2078
2079 __get_cpu_var(vector_irq)[vector] = -1;
2080 cfg->move_cleanup_count--;
2081unlock:
2082 spin_unlock(&desc->lock);
2083 }
2084
2085 irq_exit();
2086}
2087
2088static void irq_complete_move(unsigned int irq)
2089{
2090 struct irq_cfg *cfg = irq_cfg(irq);
2091 unsigned vector, me;
2092
2093 if (likely(!cfg->move_in_progress))
2094 return;
2095
2096 vector = ~get_irq_regs()->orig_ax;
2097 me = smp_processor_id();
2098 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
2099 cpumask_t cleanup_mask;
2100
2101 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
2102 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
2103 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2104 cfg->move_in_progress = 0;
2105 }
2106}
2107#else
2108static inline void irq_complete_move(unsigned int irq) {}
2109#endif
2110
1d025192
YL		 2111static void ack_apic_edge(unsigned int irq)
2112{
2113 irq_complete_move(irq);
2114 move_native_irq(irq);
2115 ack_APIC_irq();
2116}
2117
047c8fdb
YL		 2118#ifdef CONFIG_X86_64
2119static void ack_apic_level(unsigned int irq)
2120{
2121 int do_unmask_irq = 0;
2122
2123 irq_complete_move(irq);
2124#ifdef CONFIG_GENERIC_PENDING_IRQ
2125 /* If we are moving the irq we need to mask it */
2126 if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
2127 do_unmask_irq = 1;
2128 mask_IO_APIC_irq(irq);
2129 }
2130#endif
2131
2132 /*
2133 * We must acknowledge the irq before we move it or the acknowledge will
2134 * not propagate properly.
2135 */
2136 ack_APIC_irq();
2137
2138 /* Now we can move and renable the irq */
2139 if (unlikely(do_unmask_irq)) {
2140 /* Only migrate the irq if the ack has been received.
2141 *
2142 * On rare occasions the broadcast level triggered ack gets
2143 * delayed going to ioapics, and if we reprogram the
2144 * vector while Remote IRR is still set the irq will never
2145 * fire again.
2146 *
2147 * To prevent this scenario we read the Remote IRR bit
2148 * of the ioapic. This has two effects.
2149 * - On any sane system the read of the ioapic will
2150 * flush writes (and acks) going to the ioapic from
2151 * this cpu.
2152 * - We get to see if the ACK has actually been delivered.
2153 *
2154 * Based on failed experiments of reprogramming the
2155 * ioapic entry from outside of irq context starting
2156 * with masking the ioapic entry and then polling until
2157 * Remote IRR was clear before reprogramming the
2158 * ioapic I don't trust the Remote IRR bit to be
2159 * completey accurate.
2160 *
2161 * However there appears to be no other way to plug
2162 * this race, so if the Remote IRR bit is not
2163 * accurate and is causing problems then it is a hardware bug
2164 * and you can go talk to the chipset vendor about it.
2165 */
2166 if (!io_apic_level_ack_pending(irq))
2167 move_masked_irq(irq, desc);
2168 unmask_IO_APIC_irq(irq);
2169 }
2170}
2171#else
efa2559f 2172atomic_t irq_mis_count;
1d025192
YL		 2173static void ack_apic_level(unsigned int irq)
2174{
2175 unsigned long v;
2176 int i;
2177
2178 irq_complete_move(irq);
2179 move_native_irq(irq);
2180/*
2181 * It appears there is an erratum which affects at least version 0x11
2182 * of I/O APIC (that's the 82093AA and cores integrated into various
2183 * chipsets). Under certain conditions a level-triggered interrupt is
2184 * erroneously delivered as edge-triggered one but the respective IRR
2185 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2186 * message but it will never arrive and further interrupts are blocked
2187 * from the source. The exact reason is so far unknown, but the
2188 * phenomenon was observed when two consecutive interrupt requests
2189 * from a given source get delivered to the same CPU and the source is
2190 * temporarily disabled in between.
2191 *
2192 * A workaround is to simulate an EOI message manually. We achieve it
2193 * by setting the trigger mode to edge and then to level when the edge
2194 * trigger mode gets detected in the TMR of a local APIC for a
2195 * level-triggered interrupt. We mask the source for the time of the
2196 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2197 * The idea is from Manfred Spraul. --macro
2198 */
2199 i = irq_cfg(irq)->vector;
2200
2201 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2202
2203 ack_APIC_irq();
2204
2205 if (!(v & (1 << (i & 0x1f)))) {
2206 atomic_inc(&irq_mis_count);
2207 spin_lock(&ioapic_lock);
2208 __mask_and_edge_IO_APIC_irq(irq);
2209 __unmask_and_level_IO_APIC_irq(irq);
2210 spin_unlock(&ioapic_lock);
2211 }
2212}
047c8fdb 2213#endif
1d025192 2214
f5b9ed7a
IM		 2215static struct irq_chip ioapic_chip __read_mostly = {
2216 .name = "IO-APIC",
ace80ab7
EB		 2217 .startup = startup_ioapic_irq,
2218 .mask = mask_IO_APIC_irq,
2219 .unmask = unmask_IO_APIC_irq,
1d025192
YL		 2220 .ack = ack_apic_edge,
2221 .eoi = ack_apic_level,
54d5d424 2222#ifdef CONFIG_SMP
ace80ab7 2223 .set_affinity = set_ioapic_affinity_irq,
54d5d424 2224#endif
ace80ab7 2225 .retrigger = ioapic_retrigger_irq,
1da177e4
LT		 2226};
2227
1da177e4
LT		 2228
2229static inline void init_IO_APIC_traps(void)
2230{
2231 int irq;
08678b08 2232 struct irq_desc *desc;
da51a821 2233 struct irq_cfg *cfg;
1da177e4
LT		 2234
2235 /*
2236 * NOTE! The local APIC isn't very good at handling
2237 * multiple interrupts at the same interrupt level.
2238 * As the interrupt level is determined by taking the
2239 * vector number and shifting that right by 4, we
2240 * want to spread these out a bit so that they don't
2241 * all fall in the same interrupt level.
2242 *
2243 * Also, we've got to be careful not to trash gate
2244 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2245 */
da51a821
YL		 2246 for_each_irq_cfg(cfg) {
2247 irq = cfg->irq;
2248 if (IO_APIC_IRQ(irq) && !cfg->vector) {
1da177e4
LT		 2249 /*
2250 * Hmm.. We don't have an entry for this,
2251 * so default to an old-fashioned 8259
2252 * interrupt if we can..
2253 */
2254 if (irq < 16)
2255 make_8259A_irq(irq);
08678b08
YL		 2256 else {
2257 desc = irq_to_desc(irq);
1da177e4 2258 /* Strange. Oh, well.. */
08678b08
YL		 2259 desc->chip = &no_irq_chip;
2260 }
1da177e4
LT		 2261 }
2262 }
2263}
2264
f5b9ed7a
IM		 2265/*
2266 * The local APIC irq-chip implementation:
2267 */
1da177e4 2268
36062448 2269static void mask_lapic_irq(unsigned int irq)
1da177e4
LT		 2270{
2271 unsigned long v;
2272
2273 v = apic_read(APIC_LVT0);
593f4a78 2274 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1da177e4
LT		 2275}
2276
36062448 2277static void unmask_lapic_irq(unsigned int irq)
1da177e4 2278{
f5b9ed7a 2279 unsigned long v;
1da177e4 2280
f5b9ed7a 2281 v = apic_read(APIC_LVT0);
593f4a78 2282 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
f5b9ed7a 2283}
1da177e4 2284
1d025192
YL		 2285static void ack_lapic_irq(unsigned int irq)
2286{
2287 ack_APIC_irq();
2288}
2289
f5b9ed7a 2290static struct irq_chip lapic_chip __read_mostly = {
9a1c6192 2291 .name = "local-APIC",
f5b9ed7a
IM		 2292 .mask = mask_lapic_irq,
2293 .unmask = unmask_lapic_irq,
c88ac1df 2294 .ack = ack_lapic_irq,
1da177e4
LT		 2295};
2296
497c9a19 2297static void lapic_register_intr(int irq)
c88ac1df 2298{
08678b08
YL		 2299 struct irq_desc *desc;
2300
2301 desc = irq_to_desc(irq);
2302 desc->status &= ~IRQ_LEVEL;
c88ac1df
MR		 2303 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2304 "edge");
c88ac1df
MR		 2305}
2306
e9427101 2307static void __init setup_nmi(void)
1da177e4
LT		 2308{
2309 /*
36062448 2310 * Dirty trick to enable the NMI watchdog ...
1da177e4
LT		 2311 * We put the 8259A master into AEOI mode and
2312 * unmask on all local APICs LVT0 as NMI.
2313 *
2314 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2315 * is from Maciej W. Rozycki - so we do not have to EOI from
2316 * the NMI handler or the timer interrupt.
36062448 2317 */
1da177e4
LT		 2318 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2319
e9427101 2320 enable_NMI_through_LVT0();
1da177e4
LT		 2321
2322 apic_printk(APIC_VERBOSE, " done.\n");
2323}
2324
2325/*
2326 * This looks a bit hackish but it's about the only one way of sending
2327 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2328 * not support the ExtINT mode, unfortunately. We need to send these
2329 * cycles as some i82489DX-based boards have glue logic that keeps the
2330 * 8259A interrupt line asserted until INTA. --macro
2331 */
28acf285 2332static inline void __init unlock_ExtINT_logic(void)
1da177e4 2333{
fcfd636a 2334 int apic, pin, i;
1da177e4
LT		 2335 struct IO_APIC_route_entry entry0, entry1;
2336 unsigned char save_control, save_freq_select;
1da177e4 2337
fcfd636a 2338 pin = find_isa_irq_pin(8, mp_INT);
956fb531
AB		 2339 if (pin == -1) {
2340 WARN_ON_ONCE(1);
2341 return;
2342 }
fcfd636a 2343 apic = find_isa_irq_apic(8, mp_INT);
956fb531
AB		 2344 if (apic == -1) {
2345 WARN_ON_ONCE(1);
1da177e4 2346 return;
956fb531 2347 }
1da177e4 2348
cf4c6a2f 2349 entry0 = ioapic_read_entry(apic, pin);
fcfd636a 2350 clear_IO_APIC_pin(apic, pin);
1da177e4
LT		 2351
2352 memset(&entry1, 0, sizeof(entry1));
2353
2354 entry1.dest_mode = 0; /* physical delivery */
2355 entry1.mask = 0; /* unmask IRQ now */
d83e94ac 2356 entry1.dest = hard_smp_processor_id();
1da177e4
LT		 2357 entry1.delivery_mode = dest_ExtINT;
2358 entry1.polarity = entry0.polarity;
2359 entry1.trigger = 0;
2360 entry1.vector = 0;
2361
cf4c6a2f 2362 ioapic_write_entry(apic, pin, entry1);
1da177e4
LT		 2363
2364 save_control = CMOS_READ(RTC_CONTROL);
2365 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2366 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2367 RTC_FREQ_SELECT);
2368 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2369
2370 i = 100;
2371 while (i-- > 0) {
2372 mdelay(10);
2373 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2374 i -= 10;
2375 }
2376
2377 CMOS_WRITE(save_control, RTC_CONTROL);
2378 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
fcfd636a 2379 clear_IO_APIC_pin(apic, pin);
1da177e4 2380
cf4c6a2f 2381 ioapic_write_entry(apic, pin, entry0);
1da177e4
LT		 2382}
2383
efa2559f 2384static int disable_timer_pin_1 __initdata;
047c8fdb 2385/* Actually the next is obsolete, but keep it for paranoid reasons -AK */
efa2559f
YL		 2386static int __init parse_disable_timer_pin_1(char *arg)
2387{
2388 disable_timer_pin_1 = 1;
2389 return 0;
2390}
2391early_param("disable_timer_pin_1", parse_disable_timer_pin_1);
2392
2393int timer_through_8259 __initdata;
2394
1da177e4
LT		 2395/*
2396 * This code may look a bit paranoid, but it's supposed to cooperate with
2397 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2398 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2399 * fanatically on his truly buggy board.
2400 */
8542b200 2401static inline void __init check_timer(void)
1da177e4 2402{
497c9a19 2403 struct irq_cfg *cfg = irq_cfg(0);
fcfd636a 2404 int apic1, pin1, apic2, pin2;
4aae0702 2405 unsigned long flags;
047c8fdb
YL		 2406 unsigned int ver;
2407 int no_pin1 = 0;
4aae0702
IM		 2408
2409 local_irq_save(flags);
d4d25dec 2410
6e908947
IM		 2411 ver = apic_read(APIC_LVR);
2412 ver = GET_APIC_VERSION(ver);
2413
1da177e4
LT		 2414 /*
2415 * get/set the timer IRQ vector:
2416 */
2417 disable_8259A_irq(0);
497c9a19 2418 assign_irq_vector(0, TARGET_CPUS);
1da177e4
LT		 2419
2420 /*
d11d5794
MR		 2421 * As IRQ0 is to be enabled in the 8259A, the virtual
2422 * wire has to be disabled in the local APIC. Also
2423 * timer interrupts need to be acknowledged manually in
2424 * the 8259A for the i82489DX when using the NMI
2425 * watchdog as that APIC treats NMIs as level-triggered.
2426 * The AEOI mode will finish them in the 8259A
2427 * automatically.
1da177e4 2428 */
593f4a78 2429 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1da177e4 2430 init_8259A(1);
d11d5794 2431 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
1da177e4 2432
fcfd636a
EB		 2433 pin1 = find_isa_irq_pin(0, mp_INT);
2434 apic1 = find_isa_irq_apic(0, mp_INT);
2435 pin2 = ioapic_i8259.pin;
2436 apic2 = ioapic_i8259.apic;
1da177e4 2437
49a66a0b
MR		 2438 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2439 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
497c9a19 2440 cfg->vector, apic1, pin1, apic2, pin2);
1da177e4 2441
691874fa
MR		 2442 /*
2443 * Some BIOS writers are clueless and report the ExtINTA
2444 * I/O APIC input from the cascaded 8259A as the timer
2445 * interrupt input. So just in case, if only one pin
2446 * was found above, try it both directly and through the
2447 * 8259A.
2448 */
2449 if (pin1 == -1) {
2450 pin1 = pin2;
2451 apic1 = apic2;
2452 no_pin1 = 1;
2453 } else if (pin2 == -1) {
2454 pin2 = pin1;
2455 apic2 = apic1;
2456 }
2457
1da177e4
LT		 2458 if (pin1 != -1) {
2459 /*
2460 * Ok, does IRQ0 through the IOAPIC work?
2461 */
691874fa
MR		 2462 if (no_pin1) {
2463 add_pin_to_irq(0, apic1, pin1);
497c9a19 2464 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
691874fa 2465 }
1da177e4
LT		 2466 unmask_IO_APIC_irq(0);
2467 if (timer_irq_works()) {
2468 if (nmi_watchdog == NMI_IO_APIC) {
1da177e4
LT		 2469 setup_nmi();
2470 enable_8259A_irq(0);
1da177e4 2471 }
66759a01
CE		 2472 if (disable_timer_pin_1 > 0)
2473 clear_IO_APIC_pin(0, pin1);
4aae0702 2474 goto out;
1da177e4 2475 }
fcfd636a 2476 clear_IO_APIC_pin(apic1, pin1);
691874fa 2477 if (!no_pin1)
49a66a0b
MR		 2478 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2479 "8254 timer not connected to IO-APIC\n");
1da177e4 2480
49a66a0b
MR		 2481 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2482 "(IRQ0) through the 8259A ...\n");
2483 apic_printk(APIC_QUIET, KERN_INFO
2484 "..... (found apic %d pin %d) ...\n", apic2, pin2);
1da177e4
LT		 2485 /*
2486 * legacy devices should be connected to IO APIC #0
2487 */
691874fa 2488 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
497c9a19 2489 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
24742ece 2490 unmask_IO_APIC_irq(0);
ecd29476 2491 enable_8259A_irq(0);
1da177e4 2492 if (timer_irq_works()) {
49a66a0b 2493 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
35542c5e 2494 timer_through_8259 = 1;
1da177e4 2495 if (nmi_watchdog == NMI_IO_APIC) {
60134ebe 2496 disable_8259A_irq(0);
1da177e4 2497 setup_nmi();
60134ebe 2498 enable_8259A_irq(0);
1da177e4 2499 }
4aae0702 2500 goto out;
1da177e4
LT		 2501 }
2502 /*
2503 * Cleanup, just in case ...
2504 */
ecd29476 2505 disable_8259A_irq(0);
fcfd636a 2506 clear_IO_APIC_pin(apic2, pin2);
49a66a0b 2507 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
1da177e4 2508 }
1da177e4
LT		 2509
2510 if (nmi_watchdog == NMI_IO_APIC) {
49a66a0b
MR		 2511 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2512 "through the IO-APIC - disabling NMI Watchdog!\n");
067fa0ff 2513 nmi_watchdog = NMI_NONE;
1da177e4 2514 }
d11d5794 2515 timer_ack = 0;
1da177e4 2516
49a66a0b
MR		 2517 apic_printk(APIC_QUIET, KERN_INFO
2518 "...trying to set up timer as Virtual Wire IRQ...\n");
1da177e4 2519
497c9a19
YL		 2520 lapic_register_intr(0);
2521 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
1da177e4
LT		 2522 enable_8259A_irq(0);
2523
2524 if (timer_irq_works()) {
49a66a0b 2525 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
4aae0702 2526 goto out;
1da177e4 2527 }
e67465f1 2528 disable_8259A_irq(0);
497c9a19 2529 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
49a66a0b 2530 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
1da177e4 2531
49a66a0b
MR		 2532 apic_printk(APIC_QUIET, KERN_INFO
2533 "...trying to set up timer as ExtINT IRQ...\n");
1da177e4 2534
1da177e4
LT		 2535 init_8259A(0);
2536 make_8259A_irq(0);
593f4a78 2537 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1da177e4
LT		 2538
2539 unlock_ExtINT_logic();
2540
2541 if (timer_irq_works()) {
49a66a0b 2542 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
4aae0702 2543 goto out;
1da177e4 2544 }
49a66a0b 2545 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
1da177e4 2546 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
49a66a0b 2547 "report. Then try booting with the 'noapic' option.\n");
4aae0702
IM		 2548out:
2549 local_irq_restore(flags);
1da177e4
LT		 2550}
2551
2552/*
af174783
MR		 2553 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2554 * to devices. However there may be an I/O APIC pin available for
2555 * this interrupt regardless. The pin may be left unconnected, but
2556 * typically it will be reused as an ExtINT cascade interrupt for
2557 * the master 8259A. In the MPS case such a pin will normally be
2558 * reported as an ExtINT interrupt in the MP table. With ACPI
2559 * there is no provision for ExtINT interrupts, and in the absence
2560 * of an override it would be treated as an ordinary ISA I/O APIC
2561 * interrupt, that is edge-triggered and unmasked by default. We
2562 * used to do this, but it caused problems on some systems because
2563 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2564 * the same ExtINT cascade interrupt to drive the local APIC of the
2565 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2566 * the I/O APIC in all cases now. No actual device should request
2567 * it anyway. --macro
1da177e4
LT		 2568 */
2569#define PIC_IRQS (1 << PIC_CASCADE_IR)
2570
2571void __init setup_IO_APIC(void)
2572{
2573 enable_IO_APIC();
2574
af174783 2575 io_apic_irqs = ~PIC_IRQS;
1da177e4
LT		 2576
2577 printk("ENABLING IO-APIC IRQs\n");
2578
2579 /*
2580 * Set up IO-APIC IRQ routing.
2581 */
2582 if (!acpi_ioapic)
2583 setup_ioapic_ids_from_mpc();
2584 sync_Arb_IDs();
2585 setup_IO_APIC_irqs();
2586 init_IO_APIC_traps();
1e4c85f9 2587 check_timer();
1da177e4
LT		 2588}
2589
2590/*
2591 * Called after all the initialization is done. If we didnt find any
2592 * APIC bugs then we can allow the modify fast path
2593 */
36062448 2594
1da177e4
LT		 2595static int __init io_apic_bug_finalize(void)
2596{
36062448 2597 if (sis_apic_bug == -1)
1da177e4
LT		 2598 sis_apic_bug = 0;
2599 return 0;
2600}
2601
2602late_initcall(io_apic_bug_finalize);
2603
2604struct sysfs_ioapic_data {
2605 struct sys_device dev;
2606 struct IO_APIC_route_entry entry[0];
2607};
36062448 2608static struct sysfs_ioapic_data *mp_ioapic_data[MAX_IO_APICS];
1da177e4 2609
438510f6 2610static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1da177e4
LT		 2611{
2612 struct IO_APIC_route_entry *entry;
2613 struct sysfs_ioapic_data *data;
1da177e4 2614 int i;
36062448 2615
1da177e4
LT		 2616 data = container_of(dev, struct sysfs_ioapic_data, dev);
2617 entry = data->entry;
36062448 2618 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
cf4c6a2f 2619 entry[i] = ioapic_read_entry(dev->id, i);
1da177e4
LT		 2620
2621 return 0;
2622}
2623
2624static int ioapic_resume(struct sys_device *dev)
2625{
2626 struct IO_APIC_route_entry *entry;
2627 struct sysfs_ioapic_data *data;
2628 unsigned long flags;
2629 union IO_APIC_reg_00 reg_00;
2630 int i;
36062448 2631
1da177e4
LT		 2632 data = container_of(dev, struct sysfs_ioapic_data, dev);
2633 entry = data->entry;
2634
2635 spin_lock_irqsave(&ioapic_lock, flags);
2636 reg_00.raw = io_apic_read(dev->id, 0);
ec2cd0a2
AS		 2637 if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) {
2638 reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid;
1da177e4
LT		 2639 io_apic_write(dev->id, 0, reg_00.raw);
2640 }
1da177e4 2641 spin_unlock_irqrestore(&ioapic_lock, flags);
36062448 2642 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
cf4c6a2f 2643 ioapic_write_entry(dev->id, i, entry[i]);
1da177e4
LT		 2644
2645 return 0;
2646}
2647
2648static struct sysdev_class ioapic_sysdev_class = {
af5ca3f4 2649 .name = "ioapic",
1da177e4
LT		 2650 .suspend = ioapic_suspend,
2651 .resume = ioapic_resume,
2652};
2653
2654static int __init ioapic_init_sysfs(void)
2655{
36062448 2656 struct sys_device *dev;
1da177e4
LT		 2657 int i, size, error = 0;
2658
2659 error = sysdev_class_register(&ioapic_sysdev_class);
2660 if (error)
2661 return error;
2662
36062448
PC		 2663 for (i = 0; i < nr_ioapics; i++) {
2664 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1da177e4 2665 * sizeof(struct IO_APIC_route_entry);
25556c16 2666 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
1da177e4
LT		 2667 if (!mp_ioapic_data[i]) {
2668 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2669 continue;
2670 }
1da177e4 2671 dev = &mp_ioapic_data[i]->dev;
36062448 2672 dev->id = i;
1da177e4
LT		 2673 dev->cls = &ioapic_sysdev_class;
2674 error = sysdev_register(dev);
2675 if (error) {
2676 kfree(mp_ioapic_data[i]);
2677 mp_ioapic_data[i] = NULL;
2678 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2679 continue;
2680 }
2681 }
2682
2683 return 0;
2684}
2685
2686device_initcall(ioapic_init_sysfs);
2687
3fc471ed 2688/*
95d77884 2689 * Dynamic irq allocate and deallocation
3fc471ed 2690 */
199751d7 2691unsigned int create_irq_nr(unsigned int irq_want)
3fc471ed 2692{
ace80ab7 2693 /* Allocate an unused irq */
497c9a19 2694 unsigned int irq, new;
3fc471ed 2695 unsigned long flags;
da51a821 2696 struct irq_cfg *cfg_new;
3fc471ed 2697
497c9a19 2698#ifndef CONFIG_HAVE_SPARSE_IRQ
199751d7
YL		 2699 /* only can use bus/dev/fn.. when per_cpu vector is used */
2700 irq_want = nr_irqs - 1;
497c9a19 2701#endif
199751d7
YL		 2702
2703 irq = 0;
ace80ab7 2704 spin_lock_irqsave(&vector_lock, flags);
199751d7 2705 for (new = (nr_irqs - 1); new > 0; new--) {
ace80ab7
EB		 2706 if (platform_legacy_irq(new))
2707 continue;
da51a821
YL		 2708 cfg_new = irq_cfg(new);
2709 if (cfg_new && cfg_new->vector != 0)
ace80ab7 2710 continue;
047c8fdb 2711 /* check if need to create one */
da51a821
YL		 2712 if (!cfg_new)
2713 cfg_new = irq_cfg_alloc(new);
497c9a19 2714 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
ace80ab7
EB		 2715 irq = new;
2716 break;
2717 }
2718 spin_unlock_irqrestore(&vector_lock, flags);
3fc471ed 2719
199751d7 2720 if (irq > 0) {
3fc471ed
EB		 2721 dynamic_irq_init(irq);
2722 }
2723 return irq;
2724}
2725
199751d7
YL		 2726int create_irq(void)
2727{
2728 return create_irq_nr(nr_irqs - 1);
2729}
2730
3fc471ed
EB		 2731void destroy_irq(unsigned int irq)
2732{
2733 unsigned long flags;
3fc471ed
EB		 2734
2735 dynamic_irq_cleanup(irq);
2736
2737 spin_lock_irqsave(&vector_lock, flags);
497c9a19 2738 __clear_irq_vector(irq);
3fc471ed
EB		 2739 spin_unlock_irqrestore(&vector_lock, flags);
2740}
3fc471ed 2741
2d3fcc1c 2742/*
27b46d76 2743 * MSI message composition
2d3fcc1c
EB		 2744 */
2745#ifdef CONFIG_PCI_MSI
3b7d1921 2746static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2d3fcc1c 2747{
497c9a19
YL		 2748 struct irq_cfg *cfg;
2749 int err;
2d3fcc1c 2750 unsigned dest;
497c9a19 2751 cpumask_t tmp;
2d3fcc1c 2752
497c9a19
YL		 2753 tmp = TARGET_CPUS;
2754 err = assign_irq_vector(irq, tmp);
2755 if (err)
2756 return err;
2d3fcc1c 2757
497c9a19
YL		 2758 cfg = irq_cfg(irq);
2759 cpus_and(tmp, cfg->domain, tmp);
2760 dest = cpu_mask_to_apicid(tmp);
2761
2762 msg->address_hi = MSI_ADDR_BASE_HI;
2763 msg->address_lo =
2764 MSI_ADDR_BASE_LO |
2765 ((INT_DEST_MODE == 0) ?
2766 MSI_ADDR_DEST_MODE_PHYSICAL:
2767 MSI_ADDR_DEST_MODE_LOGICAL) |
2768 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2769 MSI_ADDR_REDIRECTION_CPU:
2770 MSI_ADDR_REDIRECTION_LOWPRI) |
2771 MSI_ADDR_DEST_ID(dest);
2772
2773 msg->data =
2774 MSI_DATA_TRIGGER_EDGE |
2775 MSI_DATA_LEVEL_ASSERT |
2776 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2777 MSI_DATA_DELIVERY_FIXED:
2778 MSI_DATA_DELIVERY_LOWPRI) |
2779 MSI_DATA_VECTOR(cfg->vector);
2780
2781 return err;
2d3fcc1c
EB		 2782}
2783
3b7d1921
EB		 2784#ifdef CONFIG_SMP
2785static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2d3fcc1c 2786{
497c9a19 2787 struct irq_cfg *cfg;
3b7d1921
EB		 2788 struct msi_msg msg;
2789 unsigned int dest;
2790 cpumask_t tmp;
3b7d1921
EB		 2791
2792 cpus_and(tmp, mask, cpu_online_map);
2793 if (cpus_empty(tmp))
497c9a19 2794 return;
2d3fcc1c 2795
497c9a19 2796 if (assign_irq_vector(irq, mask))
3b7d1921 2797 return;
2d3fcc1c 2798
497c9a19
YL		 2799 cfg = irq_cfg(irq);
2800 cpus_and(tmp, cfg->domain, mask);
2801 dest = cpu_mask_to_apicid(tmp);
3b7d1921
EB		 2802
2803 read_msi_msg(irq, &msg);
2804
2805 msg.data &= ~MSI_DATA_VECTOR_MASK;
497c9a19 2806 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3b7d1921
EB		 2807 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2808 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2809
2810 write_msi_msg(irq, &msg);
199751d7 2811 irq_to_desc(irq)->affinity = mask;
2d3fcc1c 2812}
3b7d1921 2813#endif /* CONFIG_SMP */
2d3fcc1c 2814
3b7d1921
EB		 2815/*
2816 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2817 * which implement the MSI or MSI-X Capability Structure.
2818 */
2819static struct irq_chip msi_chip = {
2820 .name = "PCI-MSI",
2821 .unmask = unmask_msi_irq,
2822 .mask = mask_msi_irq,
1d025192 2823 .ack = ack_apic_edge,
3b7d1921
EB		 2824#ifdef CONFIG_SMP
2825 .set_affinity = set_msi_irq_affinity,
2826#endif
2827 .retrigger = ioapic_retrigger_irq,
2d3fcc1c
EB		 2828};
2829
1d025192
YL		 2830
2831static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc, int irq)
2832{
2833 int ret;
2834 struct msi_msg msg;
2835
2836 ret = msi_compose_msg(dev, irq, &msg);
2837 if (ret < 0)
2838 return ret;
2839
2840 set_irq_msi(irq, desc);
2841 write_msi_msg(irq, &msg);
2842
2843 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
2844
2845 return 0;
2846}
2847
199751d7
YL		 2848static unsigned int build_irq_for_pci_dev(struct pci_dev *dev)
2849{
2850 unsigned int irq;
2851
2852 irq = dev->bus->number;
2853 irq <<= 8;
2854 irq |= dev->devfn;
2855 irq <<= 12;
2856
2857 return irq;
2858}
2859
f7feaca7 2860int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
3b7d1921 2861{
f7feaca7 2862 int irq, ret;
199751d7
YL		 2863
2864 unsigned int irq_want;
2865
2866 irq_want = build_irq_for_pci_dev(dev) + 0x100;
2867
2868 irq = create_irq_nr(irq_want);
2869
2870 if (irq == 0)
2871 return -1;
f7feaca7 2872
1d025192 2873 ret = setup_msi_irq(dev, desc, irq);
f7feaca7
EB		 2874 if (ret < 0) {
2875 destroy_irq(irq);
3b7d1921 2876 return ret;
1d025192 2877 }
3b7d1921 2878
7fe3730d 2879 return 0;
3b7d1921
EB		 2880}
2881
047c8fdb
YL		 2882int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
2883{
2884 unsigned int irq;
2885 int ret, sub_handle;
2886 struct msi_desc *desc;
2887 unsigned int irq_want;
2888
2889 irq_want = build_irq_for_pci_dev(dev) + 0x100;
2890 sub_handle = 0;
2891 list_for_each_entry(desc, &dev->msi_list, list) {
2892 irq = create_irq_nr(irq_want--);
2893 if (irq == 0)
2894 return -1;
2895 ret = setup_msi_irq(dev, desc, irq);
2896 if (ret < 0)
2897 goto error;
2898 sub_handle++;
2899 }
2900 return 0;
2901
2902error:
2903 destroy_irq(irq);
2904 return ret;
2905}
2906
2907
3b7d1921
EB		 2908void arch_teardown_msi_irq(unsigned int irq)
2909{
f7feaca7 2910 destroy_irq(irq);
3b7d1921
EB		 2911}
2912
2d3fcc1c
EB		 2913#endif /* CONFIG_PCI_MSI */
2914
8b955b0d
EB		 2915/*
2916 * Hypertransport interrupt support
2917 */
2918#ifdef CONFIG_HT_IRQ
2919
2920#ifdef CONFIG_SMP
2921
497c9a19 2922static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
8b955b0d 2923{
ec68307c
EB		 2924 struct ht_irq_msg msg;
2925 fetch_ht_irq_msg(irq, &msg);
8b955b0d 2926
497c9a19 2927 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
ec68307c 2928 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
8b955b0d 2929
497c9a19 2930 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
ec68307c 2931 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
8b955b0d 2932
ec68307c 2933 write_ht_irq_msg(irq, &msg);
8b955b0d
EB		 2934}
2935
2936static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2937{
497c9a19 2938 struct irq_cfg *cfg;
8b955b0d
EB		 2939 unsigned int dest;
2940 cpumask_t tmp;
2941
2942 cpus_and(tmp, mask, cpu_online_map);
2943 if (cpus_empty(tmp))
497c9a19 2944 return;
8b955b0d 2945
497c9a19
YL		 2946 if (assign_irq_vector(irq, mask))
2947 return;
8b955b0d 2948
497c9a19
YL		 2949 cfg = irq_cfg(irq);
2950 cpus_and(tmp, cfg->domain, mask);
2951 dest = cpu_mask_to_apicid(tmp);
8b955b0d 2952
497c9a19 2953 target_ht_irq(irq, dest, cfg->vector);
199751d7 2954 irq_to_desc(irq)->affinity = mask;
8b955b0d
EB		 2955}
2956#endif
2957
c37e108d 2958static struct irq_chip ht_irq_chip = {
8b955b0d
EB		 2959 .name = "PCI-HT",
2960 .mask = mask_ht_irq,
2961 .unmask = unmask_ht_irq,
1d025192 2962 .ack = ack_apic_edge,
8b955b0d
EB		 2963#ifdef CONFIG_SMP
2964 .set_affinity = set_ht_irq_affinity,
2965#endif
2966 .retrigger = ioapic_retrigger_irq,
2967};
2968
2969int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2970{
497c9a19
YL		 2971 struct irq_cfg *cfg;
2972 int err;
2973 cpumask_t tmp;
8b955b0d 2974
497c9a19
YL		 2975 tmp = TARGET_CPUS;
2976 err = assign_irq_vector(irq, tmp);
2977 if ( !err) {
ec68307c 2978 struct ht_irq_msg msg;
8b955b0d 2979 unsigned dest;
8b955b0d 2980
497c9a19
YL		 2981 cfg = irq_cfg(irq);
2982 cpus_and(tmp, cfg->domain, tmp);
8b955b0d
EB		 2983 dest = cpu_mask_to_apicid(tmp);
2984
ec68307c 2985 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
8b955b0d 2986
ec68307c
EB		 2987 msg.address_lo =
2988 HT_IRQ_LOW_BASE |
8b955b0d 2989 HT_IRQ_LOW_DEST_ID(dest) |
497c9a19 2990 HT_IRQ_LOW_VECTOR(cfg->vector) |
8b955b0d
EB		 2991 ((INT_DEST_MODE == 0) ?
2992 HT_IRQ_LOW_DM_PHYSICAL :
2993 HT_IRQ_LOW_DM_LOGICAL) |
2994 HT_IRQ_LOW_RQEOI_EDGE |
2995 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2996 HT_IRQ_LOW_MT_FIXED :
2997 HT_IRQ_LOW_MT_ARBITRATED) |
2998 HT_IRQ_LOW_IRQ_MASKED;
2999
ec68307c 3000 write_ht_irq_msg(irq, &msg);
8b955b0d 3001
a460e745
IM		 3002 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3003 handle_edge_irq, "edge");
8b955b0d 3004 }
497c9a19 3005 return err;
8b955b0d
EB		 3006}
3007#endif /* CONFIG_HT_IRQ */
3008
1da177e4 3009/* --------------------------------------------------------------------------
36062448 3010 ACPI-based IOAPIC Configuration
1da177e4
LT		 3011 -------------------------------------------------------------------------- */
3012
888ba6c6 3013#ifdef CONFIG_ACPI
1da177e4 3014
36062448 3015int __init io_apic_get_unique_id(int ioapic, int apic_id)
1da177e4
LT		 3016{
3017 union IO_APIC_reg_00 reg_00;
3018 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3019 physid_mask_t tmp;
3020 unsigned long flags;
3021 int i = 0;
3022
3023 /*
36062448
PC		 3024 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3025 * buses (one for LAPICs, one for IOAPICs), where predecessors only
1da177e4 3026 * supports up to 16 on one shared APIC bus.
36062448 3027 *
1da177e4
LT		 3028 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3029 * advantage of new APIC bus architecture.
3030 */
3031
3032 if (physids_empty(apic_id_map))
3033 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
3034
3035 spin_lock_irqsave(&ioapic_lock, flags);
3036 reg_00.raw = io_apic_read(ioapic, 0);
3037 spin_unlock_irqrestore(&ioapic_lock, flags);
3038
3039 if (apic_id >= get_physical_broadcast()) {
3040 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3041 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3042 apic_id = reg_00.bits.ID;
3043 }
3044
3045 /*
36062448 3046 * Every APIC in a system must have a unique ID or we get lots of nice
1da177e4
LT		 3047 * 'stuck on smp_invalidate_needed IPI wait' messages.
3048 */
3049 if (check_apicid_used(apic_id_map, apic_id)) {
3050
3051 for (i = 0; i < get_physical_broadcast(); i++) {
3052 if (!check_apicid_used(apic_id_map, i))
3053 break;
3054 }
3055
3056 if (i == get_physical_broadcast())
3057 panic("Max apic_id exceeded!\n");
3058
3059 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3060 "trying %d\n", ioapic, apic_id, i);
3061
3062 apic_id = i;
36062448 3063 }
1da177e4
LT		 3064
3065 tmp = apicid_to_cpu_present(apic_id);
3066 physids_or(apic_id_map, apic_id_map, tmp);
3067
3068 if (reg_00.bits.ID != apic_id) {
3069 reg_00.bits.ID = apic_id;
3070
3071 spin_lock_irqsave(&ioapic_lock, flags);
3072 io_apic_write(ioapic, 0, reg_00.raw);
3073 reg_00.raw = io_apic_read(ioapic, 0);
3074 spin_unlock_irqrestore(&ioapic_lock, flags);
3075
3076 /* Sanity check */
6070f9ec
AD		 3077 if (reg_00.bits.ID != apic_id) {
3078 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3079 return -1;
3080 }
1da177e4
LT		 3081 }
3082
3083 apic_printk(APIC_VERBOSE, KERN_INFO
3084 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3085
3086 return apic_id;
3087}
3088
3089
36062448 3090int __init io_apic_get_version(int ioapic)
1da177e4
LT		 3091{
3092 union IO_APIC_reg_01 reg_01;
3093 unsigned long flags;
3094
3095 spin_lock_irqsave(&ioapic_lock, flags);
3096 reg_01.raw = io_apic_read(ioapic, 1);
3097 spin_unlock_irqrestore(&ioapic_lock, flags);
3098
3099 return reg_01.bits.version;
3100}
3101
3102
36062448 3103int __init io_apic_get_redir_entries(int ioapic)
1da177e4
LT		 3104{
3105 union IO_APIC_reg_01 reg_01;
3106 unsigned long flags;
3107
3108 spin_lock_irqsave(&ioapic_lock, flags);
3109 reg_01.raw = io_apic_read(ioapic, 1);
3110 spin_unlock_irqrestore(&ioapic_lock, flags);
3111
3112 return reg_01.bits.entries;
3113}
3114
3115
497c9a19 3116int io_apic_set_pci_routing(int ioapic, int pin, int irq, int triggering, int polarity)
1da177e4 3117{
1da177e4
LT		 3118 if (!IO_APIC_IRQ(irq)) {
3119 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3120 ioapic);
3121 return -EINVAL;
3122 }
3123
1da177e4
LT		 3124 /*
3125 * IRQs < 16 are already in the irq_2_pin[] map
3126 */
3127 if (irq >= 16)
3128 add_pin_to_irq(irq, ioapic, pin);
3129
497c9a19 3130 setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
1da177e4
LT		 3131
3132 return 0;
3133}
3134
61fd47e0
SL		 3135int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
3136{
3137 int i;
3138
3139 if (skip_ioapic_setup)
3140 return -1;
3141
3142 for (i = 0; i < mp_irq_entries; i++)
2fddb6e2
AS		 3143 if (mp_irqs[i].mp_irqtype == mp_INT &&
3144 mp_irqs[i].mp_srcbusirq == bus_irq)
61fd47e0
SL		 3145 break;
3146 if (i >= mp_irq_entries)
3147 return -1;
3148
3149 *trigger = irq_trigger(i);
3150 *polarity = irq_polarity(i);
3151 return 0;
3152}
3153
888ba6c6 3154#endif /* CONFIG_ACPI */
1a3f239d 3155
497c9a19
YL		 3156/*
3157 * This function currently is only a helper for the i386 smp boot process where
3158 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3159 * so mask in all cases should simply be TARGET_CPUS
3160 */
3161#ifdef CONFIG_SMP
3162void __init setup_ioapic_dest(void)
3163{
3164 int pin, ioapic, irq, irq_entry;
3165 struct irq_cfg *cfg;
3166 struct irq_desc *desc;
3167
3168 if (skip_ioapic_setup == 1)
3169 return;
3170
3171 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
3172 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
3173 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
3174 if (irq_entry == -1)
3175 continue;
3176 irq = pin_2_irq(irq_entry, ioapic, pin);
3177
3178 /* setup_IO_APIC_irqs could fail to get vector for some device
3179 * when you have too many devices, because at that time only boot
3180 * cpu is online.
3181 */
3182 cfg = irq_cfg(irq);
3183 if (!cfg->vector)
3184 setup_IO_APIC_irq(ioapic, pin, irq,
3185 irq_trigger(irq_entry),
3186 irq_polarity(irq_entry));
3187 else {
3188 desc = irq_to_desc(irq);
3189 set_ioapic_affinity_irq(irq, TARGET_CPUS);
3190 }
3191 }
3192
3193 }
3194}
3195#endif
3196
f3294a33
YL		 3197void __init ioapic_init_mappings(void)
3198{
3199 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
3200 int i;
3201
3202 for (i = 0; i < nr_ioapics; i++) {
3203 if (smp_found_config) {
3204 ioapic_phys = mp_ioapics[i].mp_apicaddr;
3205 if (!ioapic_phys) {
3206 printk(KERN_ERR
3207 "WARNING: bogus zero IO-APIC "
3208 "address found in MPTABLE, "
3209 "disabling IO/APIC support!\n");
3210 smp_found_config = 0;
3211 skip_ioapic_setup = 1;
3212 goto fake_ioapic_page;
3213 }
3214 } else {
3215fake_ioapic_page:
3216 ioapic_phys = (unsigned long)
3217 alloc_bootmem_pages(PAGE_SIZE);
3218 ioapic_phys = __pa(ioapic_phys);
3219 }
3220 set_fixmap_nocache(idx, ioapic_phys);
3221 printk(KERN_DEBUG "mapped IOAPIC to %08lx (%08lx)\n",
3222 __fix_to_virt(idx), ioapic_phys);
3223 idx++;
3224 }
3225}
3226
Linux kernel - Deliverables
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