Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
4 | * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo | |
5 | * | |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
f3294a33 | 28 | #include <linux/bootmem.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
1da177e4 | 33 | #include <linux/sysdev.h> |
2d3fcc1c | 34 | #include <linux/pci.h> |
3b7d1921 | 35 | #include <linux/msi.h> |
95d77884 | 36 | #include <linux/htirq.h> |
7dfb7103 | 37 | #include <linux/freezer.h> |
f26d6a2b | 38 | #include <linux/kthread.h> |
1d16b53e | 39 | #include <linux/jiffies.h> /* time_after() */ |
54d5d424 | 40 | |
1da177e4 LT |
41 | #include <asm/io.h> |
42 | #include <asm/smp.h> | |
43 | #include <asm/desc.h> | |
44 | #include <asm/timer.h> | |
306e440d | 45 | #include <asm/i8259.h> |
3e4ff115 | 46 | #include <asm/nmi.h> |
2d3fcc1c | 47 | #include <asm/msidef.h> |
8b955b0d | 48 | #include <asm/hypertransport.h> |
a4dbc34d | 49 | #include <asm/setup.h> |
1da177e4 LT |
50 | |
51 | #include <mach_apic.h> | |
874c4fe3 | 52 | #include <mach_apicdef.h> |
1da177e4 | 53 | |
32f71aff MR |
54 | #define __apicdebuginit(type) static type __init |
55 | ||
1da177e4 LT |
56 | int (*ioapic_renumber_irq)(int ioapic, int irq); |
57 | atomic_t irq_mis_count; | |
58 | ||
fcfd636a EB |
59 | /* Where if anywhere is the i8259 connect in external int mode */ |
60 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
61 | ||
1da177e4 | 62 | static DEFINE_SPINLOCK(ioapic_lock); |
d388e5fd | 63 | DEFINE_SPINLOCK(vector_lock); |
1da177e4 | 64 | |
35542c5e | 65 | int timer_through_8259 __initdata; |
f9262c12 | 66 | |
1da177e4 LT |
67 | /* |
68 | * Is the SiS APIC rmw bug present ? | |
69 | * -1 = don't know, 0 = no, 1 = yes | |
70 | */ | |
71 | int sis_apic_bug = -1; | |
72 | ||
301e6190 | 73 | int first_free_entry; |
1da177e4 LT |
74 | /* |
75 | * # of IRQ routing registers | |
76 | */ | |
77 | int nr_ioapic_registers[MAX_IO_APICS]; | |
78 | ||
9f640ccb | 79 | /* I/O APIC entries */ |
ec2cd0a2 | 80 | struct mp_config_ioapic mp_ioapics[MAX_IO_APICS]; |
9f640ccb AS |
81 | int nr_ioapics; |
82 | ||
584f734d | 83 | /* MP IRQ source entries */ |
2fddb6e2 | 84 | struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
85 | |
86 | /* # of MP IRQ source entries */ | |
87 | int mp_irq_entries; | |
88 | ||
8732fc4b AS |
89 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
90 | int mp_bus_id_to_type[MAX_MP_BUSSES]; | |
91 | #endif | |
92 | ||
93 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
94 | ||
1a3f239d | 95 | static int disable_timer_pin_1 __initdata; |
66759a01 | 96 | |
1da177e4 LT |
97 | /* |
98 | * Rough estimation of how many shared IRQs there are, can | |
99 | * be changed anytime. | |
100 | */ | |
301e6190 | 101 | int pin_map_size; |
0799e432 | 102 | |
1da177e4 LT |
103 | /* |
104 | * This is performance-critical, we want to do it O(1) | |
105 | * | |
106 | * the indexing order of this array favors 1:1 mappings | |
107 | * between pins and IRQs. | |
108 | */ | |
109 | ||
110 | static struct irq_pin_list { | |
111 | int apic, pin, next; | |
301e6190 YL |
112 | } *irq_2_pin; |
113 | ||
114 | DEFINE_DYN_ARRAY(irq_2_pin, sizeof(struct irq_pin_list), pin_map_size, 16, NULL); | |
1da177e4 | 115 | |
130fe05d LT |
116 | struct io_apic { |
117 | unsigned int index; | |
118 | unsigned int unused[3]; | |
119 | unsigned int data; | |
120 | }; | |
121 | ||
122 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
123 | { | |
124 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
ec2cd0a2 | 125 | + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK); |
130fe05d LT |
126 | } |
127 | ||
128 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) | |
129 | { | |
130 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
131 | writel(reg, &io_apic->index); | |
132 | return readl(&io_apic->data); | |
133 | } | |
134 | ||
135 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) | |
136 | { | |
137 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
138 | writel(reg, &io_apic->index); | |
139 | writel(value, &io_apic->data); | |
140 | } | |
141 | ||
142 | /* | |
143 | * Re-write a value: to be used for read-modify-write | |
144 | * cycles where the read already set up the index register. | |
145 | * | |
146 | * Older SiS APIC requires we rewrite the index register | |
147 | */ | |
148 | static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) | |
149 | { | |
cb468984 | 150 | volatile struct io_apic __iomem *io_apic = io_apic_base(apic); |
130fe05d LT |
151 | if (sis_apic_bug) |
152 | writel(reg, &io_apic->index); | |
153 | writel(value, &io_apic->data); | |
154 | } | |
155 | ||
cf4c6a2f AK |
156 | union entry_union { |
157 | struct { u32 w1, w2; }; | |
158 | struct IO_APIC_route_entry entry; | |
159 | }; | |
160 | ||
161 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) | |
162 | { | |
163 | union entry_union eu; | |
164 | unsigned long flags; | |
165 | spin_lock_irqsave(&ioapic_lock, flags); | |
166 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); | |
167 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
168 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
169 | return eu.entry; | |
170 | } | |
171 | ||
f9dadfa7 LT |
172 | /* |
173 | * When we write a new IO APIC routing entry, we need to write the high | |
174 | * word first! If the mask bit in the low word is clear, we will enable | |
175 | * the interrupt, and we need to make sure the entry is fully populated | |
176 | * before that happens. | |
177 | */ | |
d15512f4 AK |
178 | static void |
179 | __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
cf4c6a2f | 180 | { |
cf4c6a2f AK |
181 | union entry_union eu; |
182 | eu.entry = e; | |
f9dadfa7 LT |
183 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
184 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
185 | } |
186 | ||
187 | static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
188 | { | |
189 | unsigned long flags; | |
190 | spin_lock_irqsave(&ioapic_lock, flags); | |
191 | __ioapic_write_entry(apic, pin, e); | |
f9dadfa7 LT |
192 | spin_unlock_irqrestore(&ioapic_lock, flags); |
193 | } | |
194 | ||
195 | /* | |
196 | * When we mask an IO APIC routing entry, we need to write the low | |
197 | * word first, in order to set the mask bit before we change the | |
198 | * high bits! | |
199 | */ | |
200 | static void ioapic_mask_entry(int apic, int pin) | |
201 | { | |
202 | unsigned long flags; | |
203 | union entry_union eu = { .entry.mask = 1 }; | |
204 | ||
cf4c6a2f AK |
205 | spin_lock_irqsave(&ioapic_lock, flags); |
206 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
207 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
208 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
209 | } | |
210 | ||
1da177e4 LT |
211 | /* |
212 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
213 | * shared ISA-space IRQs, so we have to support them. We are super | |
214 | * fast in the common case, and fast for shared ISA-space IRQs. | |
215 | */ | |
216 | static void add_pin_to_irq(unsigned int irq, int apic, int pin) | |
217 | { | |
1da177e4 LT |
218 | struct irq_pin_list *entry = irq_2_pin + irq; |
219 | ||
220 | while (entry->next) | |
221 | entry = irq_2_pin + entry->next; | |
222 | ||
223 | if (entry->pin != -1) { | |
224 | entry->next = first_free_entry; | |
225 | entry = irq_2_pin + entry->next; | |
0799e432 | 226 | if (++first_free_entry >= pin_map_size) |
1da177e4 LT |
227 | panic("io_apic.c: whoops"); |
228 | } | |
229 | entry->apic = apic; | |
230 | entry->pin = pin; | |
231 | } | |
232 | ||
233 | /* | |
234 | * Reroute an IRQ to a different pin. | |
235 | */ | |
236 | static void __init replace_pin_at_irq(unsigned int irq, | |
237 | int oldapic, int oldpin, | |
238 | int newapic, int newpin) | |
239 | { | |
240 | struct irq_pin_list *entry = irq_2_pin + irq; | |
241 | ||
242 | while (1) { | |
243 | if (entry->apic == oldapic && entry->pin == oldpin) { | |
244 | entry->apic = newapic; | |
245 | entry->pin = newpin; | |
246 | } | |
247 | if (!entry->next) | |
248 | break; | |
249 | entry = irq_2_pin + entry->next; | |
250 | } | |
251 | } | |
252 | ||
36062448 | 253 | static void __modify_IO_APIC_irq(unsigned int irq, unsigned long enable, unsigned long disable) |
1da177e4 LT |
254 | { |
255 | struct irq_pin_list *entry = irq_2_pin + irq; | |
256 | unsigned int pin, reg; | |
257 | ||
258 | for (;;) { | |
259 | pin = entry->pin; | |
260 | if (pin == -1) | |
261 | break; | |
262 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
263 | reg &= ~disable; | |
264 | reg |= enable; | |
265 | io_apic_modify(entry->apic, 0x10 + pin*2, reg); | |
266 | if (!entry->next) | |
267 | break; | |
268 | entry = irq_2_pin + entry->next; | |
269 | } | |
270 | } | |
271 | ||
272 | /* mask = 1 */ | |
36062448 | 273 | static void __mask_IO_APIC_irq(unsigned int irq) |
1da177e4 | 274 | { |
46b3b4ef | 275 | __modify_IO_APIC_irq(irq, IO_APIC_REDIR_MASKED, 0); |
1da177e4 LT |
276 | } |
277 | ||
278 | /* mask = 0 */ | |
36062448 | 279 | static void __unmask_IO_APIC_irq(unsigned int irq) |
1da177e4 | 280 | { |
46b3b4ef | 281 | __modify_IO_APIC_irq(irq, 0, IO_APIC_REDIR_MASKED); |
1da177e4 LT |
282 | } |
283 | ||
284 | /* mask = 1, trigger = 0 */ | |
36062448 | 285 | static void __mask_and_edge_IO_APIC_irq(unsigned int irq) |
1da177e4 | 286 | { |
46b3b4ef CG |
287 | __modify_IO_APIC_irq(irq, IO_APIC_REDIR_MASKED, |
288 | IO_APIC_REDIR_LEVEL_TRIGGER); | |
1da177e4 LT |
289 | } |
290 | ||
291 | /* mask = 0, trigger = 1 */ | |
36062448 | 292 | static void __unmask_and_level_IO_APIC_irq(unsigned int irq) |
1da177e4 | 293 | { |
46b3b4ef CG |
294 | __modify_IO_APIC_irq(irq, IO_APIC_REDIR_LEVEL_TRIGGER, |
295 | IO_APIC_REDIR_MASKED); | |
1da177e4 LT |
296 | } |
297 | ||
36062448 | 298 | static void mask_IO_APIC_irq(unsigned int irq) |
1da177e4 LT |
299 | { |
300 | unsigned long flags; | |
301 | ||
302 | spin_lock_irqsave(&ioapic_lock, flags); | |
303 | __mask_IO_APIC_irq(irq); | |
304 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
305 | } | |
306 | ||
36062448 | 307 | static void unmask_IO_APIC_irq(unsigned int irq) |
1da177e4 LT |
308 | { |
309 | unsigned long flags; | |
310 | ||
311 | spin_lock_irqsave(&ioapic_lock, flags); | |
312 | __unmask_IO_APIC_irq(irq); | |
313 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
314 | } | |
315 | ||
316 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) | |
317 | { | |
318 | struct IO_APIC_route_entry entry; | |
36062448 | 319 | |
1da177e4 | 320 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 321 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
322 | if (entry.delivery_mode == dest_SMI) |
323 | return; | |
324 | ||
325 | /* | |
326 | * Disable it in the IO-APIC irq-routing table: | |
327 | */ | |
f9dadfa7 | 328 | ioapic_mask_entry(apic, pin); |
1da177e4 LT |
329 | } |
330 | ||
36062448 | 331 | static void clear_IO_APIC(void) |
1da177e4 LT |
332 | { |
333 | int apic, pin; | |
334 | ||
335 | for (apic = 0; apic < nr_ioapics; apic++) | |
336 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) | |
337 | clear_IO_APIC_pin(apic, pin); | |
338 | } | |
339 | ||
54d5d424 | 340 | #ifdef CONFIG_SMP |
1da177e4 LT |
341 | static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask) |
342 | { | |
343 | unsigned long flags; | |
344 | int pin; | |
345 | struct irq_pin_list *entry = irq_2_pin + irq; | |
346 | unsigned int apicid_value; | |
54d5d424 | 347 | cpumask_t tmp; |
36062448 | 348 | |
54d5d424 AR |
349 | cpus_and(tmp, cpumask, cpu_online_map); |
350 | if (cpus_empty(tmp)) | |
351 | tmp = TARGET_CPUS; | |
352 | ||
353 | cpus_and(cpumask, tmp, CPU_MASK_ALL); | |
354 | ||
1da177e4 LT |
355 | apicid_value = cpu_mask_to_apicid(cpumask); |
356 | /* Prepare to do the io_apic_write */ | |
357 | apicid_value = apicid_value << 24; | |
358 | spin_lock_irqsave(&ioapic_lock, flags); | |
359 | for (;;) { | |
360 | pin = entry->pin; | |
361 | if (pin == -1) | |
362 | break; | |
363 | io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value); | |
364 | if (!entry->next) | |
365 | break; | |
366 | entry = irq_2_pin + entry->next; | |
367 | } | |
9f0a5ba5 | 368 | irq_desc[irq].affinity = cpumask; |
1da177e4 LT |
369 | spin_unlock_irqrestore(&ioapic_lock, flags); |
370 | } | |
371 | ||
372 | #if defined(CONFIG_IRQBALANCE) | |
373 | # include <asm/processor.h> /* kernel_thread() */ | |
374 | # include <linux/kernel_stat.h> /* kstat */ | |
375 | # include <linux/slab.h> /* kmalloc() */ | |
1d16b53e | 376 | # include <linux/timer.h> |
36062448 | 377 | |
1da177e4 | 378 | #define IRQBALANCE_CHECK_ARCH -999 |
1b61b910 ZY |
379 | #define MAX_BALANCED_IRQ_INTERVAL (5*HZ) |
380 | #define MIN_BALANCED_IRQ_INTERVAL (HZ/2) | |
381 | #define BALANCED_IRQ_MORE_DELTA (HZ/10) | |
382 | #define BALANCED_IRQ_LESS_DELTA (HZ) | |
383 | ||
384 | static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH; | |
385 | static int physical_balance __read_mostly; | |
386 | static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL; | |
1da177e4 LT |
387 | |
388 | static struct irq_cpu_info { | |
36062448 PC |
389 | unsigned long *last_irq; |
390 | unsigned long *irq_delta; | |
1da177e4 LT |
391 | unsigned long irq; |
392 | } irq_cpu_data[NR_CPUS]; | |
393 | ||
394 | #define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq) | |
36062448 PC |
395 | #define LAST_CPU_IRQ(cpu, irq) (irq_cpu_data[cpu].last_irq[irq]) |
396 | #define IRQ_DELTA(cpu, irq) (irq_cpu_data[cpu].irq_delta[irq]) | |
1da177e4 LT |
397 | |
398 | #define IDLE_ENOUGH(cpu,now) \ | |
399 | (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1)) | |
400 | ||
401 | #define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask) | |
402 | ||
d5a7430d | 403 | #define CPU_TO_PACKAGEINDEX(i) (first_cpu(per_cpu(cpu_sibling_map, i))) |
1da177e4 | 404 | |
301e6190 YL |
405 | static cpumask_t balance_irq_affinity_init __initdata = CPU_MASK_ALL; |
406 | ||
407 | static cpumask_t *balance_irq_affinity; | |
408 | ||
409 | ||
410 | static void __init irq_affinity_init_work(void *data) | |
411 | { | |
412 | struct dyn_array *da = data; | |
413 | ||
414 | int i; | |
415 | struct balance_irq_affinity *affinity; | |
416 | ||
417 | affinity = *da->name; | |
418 | ||
419 | for (i = 0; i < *da->nr; i++) | |
420 | memcpy(&affinity[i], &balance_irq_affinity_init, | |
421 | sizeof(struct balance_irq_affinity)); | |
422 | ||
423 | } | |
424 | ||
425 | DEFINE_DYN_ARRAY(balance_irq_affinity, sizeof(struct balance_irq_affinity), nr_irqs, PAGE_SIZE, irq_affinity_init_work); | |
426 | ||
1da177e4 | 427 | |
1b61b910 ZY |
428 | void set_balance_irq_affinity(unsigned int irq, cpumask_t mask) |
429 | { | |
430 | balance_irq_affinity[irq] = mask; | |
431 | } | |
1da177e4 LT |
432 | |
433 | static unsigned long move(int curr_cpu, cpumask_t allowed_mask, | |
434 | unsigned long now, int direction) | |
435 | { | |
436 | int search_idle = 1; | |
437 | int cpu = curr_cpu; | |
438 | ||
439 | goto inside; | |
440 | ||
441 | do { | |
442 | if (unlikely(cpu == curr_cpu)) | |
443 | search_idle = 0; | |
444 | inside: | |
445 | if (direction == 1) { | |
446 | cpu++; | |
447 | if (cpu >= NR_CPUS) | |
448 | cpu = 0; | |
449 | } else { | |
450 | cpu--; | |
451 | if (cpu == -1) | |
452 | cpu = NR_CPUS-1; | |
453 | } | |
36062448 PC |
454 | } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu, allowed_mask) || |
455 | (search_idle && !IDLE_ENOUGH(cpu, now))); | |
1da177e4 LT |
456 | |
457 | return cpu; | |
458 | } | |
459 | ||
460 | static inline void balance_irq(int cpu, int irq) | |
461 | { | |
462 | unsigned long now = jiffies; | |
463 | cpumask_t allowed_mask; | |
464 | unsigned int new_cpu; | |
36062448 | 465 | |
1da177e4 | 466 | if (irqbalance_disabled) |
36062448 | 467 | return; |
1da177e4 | 468 | |
1b61b910 | 469 | cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]); |
1da177e4 | 470 | new_cpu = move(cpu, allowed_mask, now, 1); |
36062448 | 471 | if (cpu != new_cpu) |
54d5d424 | 472 | set_pending_irq(irq, cpumask_of_cpu(new_cpu)); |
1da177e4 LT |
473 | } |
474 | ||
475 | static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold) | |
476 | { | |
477 | int i, j; | |
edc2cbf4 | 478 | |
394e3902 | 479 | for_each_online_cpu(i) { |
0799e432 | 480 | for (j = 0; j < nr_irqs; j++) { |
1da177e4 LT |
481 | if (!irq_desc[j].action) |
482 | continue; | |
483 | /* Is it a significant load ? */ | |
36062448 | 484 | if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i), j) < |
1da177e4 LT |
485 | useful_load_threshold) |
486 | continue; | |
487 | balance_irq(i, j); | |
488 | } | |
489 | } | |
490 | balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL, | |
36062448 | 491 | balanced_irq_interval - BALANCED_IRQ_LESS_DELTA); |
1da177e4 LT |
492 | return; |
493 | } | |
494 | ||
495 | static void do_irq_balance(void) | |
496 | { | |
497 | int i, j; | |
498 | unsigned long max_cpu_irq = 0, min_cpu_irq = (~0); | |
499 | unsigned long move_this_load = 0; | |
500 | int max_loaded = 0, min_loaded = 0; | |
501 | int load; | |
502 | unsigned long useful_load_threshold = balanced_irq_interval + 10; | |
503 | int selected_irq; | |
504 | int tmp_loaded, first_attempt = 1; | |
505 | unsigned long tmp_cpu_irq; | |
506 | unsigned long imbalance = 0; | |
507 | cpumask_t allowed_mask, target_cpu_mask, tmp; | |
508 | ||
c8912599 | 509 | for_each_possible_cpu(i) { |
1da177e4 LT |
510 | int package_index; |
511 | CPU_IRQ(i) = 0; | |
512 | if (!cpu_online(i)) | |
513 | continue; | |
514 | package_index = CPU_TO_PACKAGEINDEX(i); | |
0799e432 | 515 | for (j = 0; j < nr_irqs; j++) { |
1da177e4 | 516 | unsigned long value_now, delta; |
950f4427 TG |
517 | /* Is this an active IRQ or balancing disabled ? */ |
518 | if (!irq_desc[j].action || irq_balancing_disabled(j)) | |
1da177e4 | 519 | continue; |
36062448 PC |
520 | if (package_index == i) |
521 | IRQ_DELTA(package_index, j) = 0; | |
1da177e4 LT |
522 | /* Determine the total count per processor per IRQ */ |
523 | value_now = (unsigned long) kstat_cpu(i).irqs[j]; | |
524 | ||
525 | /* Determine the activity per processor per IRQ */ | |
36062448 | 526 | delta = value_now - LAST_CPU_IRQ(i, j); |
1da177e4 LT |
527 | |
528 | /* Update last_cpu_irq[][] for the next time */ | |
36062448 | 529 | LAST_CPU_IRQ(i, j) = value_now; |
1da177e4 LT |
530 | |
531 | /* Ignore IRQs whose rate is less than the clock */ | |
532 | if (delta < useful_load_threshold) | |
533 | continue; | |
534 | /* update the load for the processor or package total */ | |
36062448 | 535 | IRQ_DELTA(package_index, j) += delta; |
1da177e4 LT |
536 | |
537 | /* Keep track of the higher numbered sibling as well */ | |
538 | if (i != package_index) | |
539 | CPU_IRQ(i) += delta; | |
540 | /* | |
541 | * We have sibling A and sibling B in the package | |
542 | * | |
543 | * cpu_irq[A] = load for cpu A + load for cpu B | |
544 | * cpu_irq[B] = load for cpu B | |
545 | */ | |
546 | CPU_IRQ(package_index) += delta; | |
547 | } | |
548 | } | |
549 | /* Find the least loaded processor package */ | |
394e3902 | 550 | for_each_online_cpu(i) { |
1da177e4 LT |
551 | if (i != CPU_TO_PACKAGEINDEX(i)) |
552 | continue; | |
553 | if (min_cpu_irq > CPU_IRQ(i)) { | |
554 | min_cpu_irq = CPU_IRQ(i); | |
555 | min_loaded = i; | |
556 | } | |
557 | } | |
558 | max_cpu_irq = ULONG_MAX; | |
559 | ||
560 | tryanothercpu: | |
36062448 PC |
561 | /* |
562 | * Look for heaviest loaded processor. | |
1da177e4 LT |
563 | * We may come back to get the next heaviest loaded processor. |
564 | * Skip processors with trivial loads. | |
565 | */ | |
566 | tmp_cpu_irq = 0; | |
567 | tmp_loaded = -1; | |
394e3902 | 568 | for_each_online_cpu(i) { |
1da177e4 LT |
569 | if (i != CPU_TO_PACKAGEINDEX(i)) |
570 | continue; | |
36062448 | 571 | if (max_cpu_irq <= CPU_IRQ(i)) |
1da177e4 LT |
572 | continue; |
573 | if (tmp_cpu_irq < CPU_IRQ(i)) { | |
574 | tmp_cpu_irq = CPU_IRQ(i); | |
575 | tmp_loaded = i; | |
576 | } | |
577 | } | |
578 | ||
579 | if (tmp_loaded == -1) { | |
36062448 PC |
580 | /* |
581 | * In the case of small number of heavy interrupt sources, | |
582 | * loading some of the cpus too much. We use Ingo's original | |
1da177e4 LT |
583 | * approach to rotate them around. |
584 | */ | |
585 | if (!first_attempt && imbalance >= useful_load_threshold) { | |
586 | rotate_irqs_among_cpus(useful_load_threshold); | |
587 | return; | |
588 | } | |
589 | goto not_worth_the_effort; | |
590 | } | |
36062448 | 591 | |
1da177e4 LT |
592 | first_attempt = 0; /* heaviest search */ |
593 | max_cpu_irq = tmp_cpu_irq; /* load */ | |
594 | max_loaded = tmp_loaded; /* processor */ | |
595 | imbalance = (max_cpu_irq - min_cpu_irq) / 2; | |
36062448 PC |
596 | |
597 | /* | |
598 | * if imbalance is less than approx 10% of max load, then | |
1da177e4 LT |
599 | * observe diminishing returns action. - quit |
600 | */ | |
edc2cbf4 | 601 | if (imbalance < (max_cpu_irq >> 3)) |
1da177e4 | 602 | goto not_worth_the_effort; |
1da177e4 LT |
603 | |
604 | tryanotherirq: | |
605 | /* if we select an IRQ to move that can't go where we want, then | |
606 | * see if there is another one to try. | |
607 | */ | |
608 | move_this_load = 0; | |
609 | selected_irq = -1; | |
0799e432 | 610 | for (j = 0; j < nr_irqs; j++) { |
1da177e4 LT |
611 | /* Is this an active IRQ? */ |
612 | if (!irq_desc[j].action) | |
613 | continue; | |
36062448 | 614 | if (imbalance <= IRQ_DELTA(max_loaded, j)) |
1da177e4 LT |
615 | continue; |
616 | /* Try to find the IRQ that is closest to the imbalance | |
617 | * without going over. | |
618 | */ | |
36062448 PC |
619 | if (move_this_load < IRQ_DELTA(max_loaded, j)) { |
620 | move_this_load = IRQ_DELTA(max_loaded, j); | |
1da177e4 LT |
621 | selected_irq = j; |
622 | } | |
623 | } | |
36062448 | 624 | if (selected_irq == -1) |
1da177e4 | 625 | goto tryanothercpu; |
1da177e4 LT |
626 | |
627 | imbalance = move_this_load; | |
36062448 | 628 | |
27b46d76 | 629 | /* For physical_balance case, we accumulated both load |
1da177e4 LT |
630 | * values in the one of the siblings cpu_irq[], |
631 | * to use the same code for physical and logical processors | |
36062448 | 632 | * as much as possible. |
1da177e4 LT |
633 | * |
634 | * NOTE: the cpu_irq[] array holds the sum of the load for | |
635 | * sibling A and sibling B in the slot for the lowest numbered | |
636 | * sibling (A), _AND_ the load for sibling B in the slot for | |
637 | * the higher numbered sibling. | |
638 | * | |
639 | * We seek the least loaded sibling by making the comparison | |
640 | * (A+B)/2 vs B | |
641 | */ | |
642 | load = CPU_IRQ(min_loaded) >> 1; | |
d5a7430d | 643 | for_each_cpu_mask(j, per_cpu(cpu_sibling_map, min_loaded)) { |
1da177e4 LT |
644 | if (load > CPU_IRQ(j)) { |
645 | /* This won't change cpu_sibling_map[min_loaded] */ | |
646 | load = CPU_IRQ(j); | |
647 | min_loaded = j; | |
648 | } | |
649 | } | |
650 | ||
1b61b910 ZY |
651 | cpus_and(allowed_mask, |
652 | cpu_online_map, | |
653 | balance_irq_affinity[selected_irq]); | |
1da177e4 LT |
654 | target_cpu_mask = cpumask_of_cpu(min_loaded); |
655 | cpus_and(tmp, target_cpu_mask, allowed_mask); | |
656 | ||
657 | if (!cpus_empty(tmp)) { | |
1da177e4 | 658 | /* mark for change destination */ |
54d5d424 AR |
659 | set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded)); |
660 | ||
36062448 | 661 | /* Since we made a change, come back sooner to |
1da177e4 LT |
662 | * check for more variation. |
663 | */ | |
664 | balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL, | |
36062448 | 665 | balanced_irq_interval - BALANCED_IRQ_LESS_DELTA); |
1da177e4 LT |
666 | return; |
667 | } | |
668 | goto tryanotherirq; | |
669 | ||
670 | not_worth_the_effort: | |
671 | /* | |
672 | * if we did not find an IRQ to move, then adjust the time interval | |
673 | * upward | |
674 | */ | |
675 | balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL, | |
36062448 | 676 | balanced_irq_interval + BALANCED_IRQ_MORE_DELTA); |
1da177e4 LT |
677 | return; |
678 | } | |
679 | ||
680 | static int balanced_irq(void *unused) | |
681 | { | |
682 | int i; | |
683 | unsigned long prev_balance_time = jiffies; | |
684 | long time_remaining = balanced_irq_interval; | |
685 | ||
1da177e4 | 686 | /* push everything to CPU 0 to give us a starting point. */ |
0799e432 | 687 | for (i = 0 ; i < nr_irqs ; i++) { |
cd916d31 | 688 | irq_desc[i].pending_mask = cpumask_of_cpu(0); |
54d5d424 | 689 | set_pending_irq(i, cpumask_of_cpu(0)); |
1da177e4 LT |
690 | } |
691 | ||
83144186 | 692 | set_freezable(); |
1da177e4 | 693 | for ( ; ; ) { |
52e6e630 | 694 | time_remaining = schedule_timeout_interruptible(time_remaining); |
3e1d1d28 | 695 | try_to_freeze(); |
1da177e4 LT |
696 | if (time_after(jiffies, |
697 | prev_balance_time+balanced_irq_interval)) { | |
f3705136 | 698 | preempt_disable(); |
1da177e4 LT |
699 | do_irq_balance(); |
700 | prev_balance_time = jiffies; | |
701 | time_remaining = balanced_irq_interval; | |
f3705136 | 702 | preempt_enable(); |
1da177e4 LT |
703 | } |
704 | } | |
705 | return 0; | |
706 | } | |
707 | ||
708 | static int __init balanced_irq_init(void) | |
709 | { | |
710 | int i; | |
711 | struct cpuinfo_x86 *c; | |
712 | cpumask_t tmp; | |
713 | ||
714 | cpus_shift_right(tmp, cpu_online_map, 2); | |
36062448 | 715 | c = &boot_cpu_data; |
1da177e4 LT |
716 | /* When not overwritten by the command line ask subarchitecture. */ |
717 | if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH) | |
718 | irqbalance_disabled = NO_BALANCE_IRQ; | |
719 | if (irqbalance_disabled) | |
720 | return 0; | |
36062448 | 721 | |
1da177e4 LT |
722 | /* disable irqbalance completely if there is only one processor online */ |
723 | if (num_online_cpus() < 2) { | |
724 | irqbalance_disabled = 1; | |
725 | return 0; | |
726 | } | |
727 | /* | |
728 | * Enable physical balance only if more than 1 physical processor | |
729 | * is present | |
730 | */ | |
731 | if (smp_num_siblings > 1 && !cpus_empty(tmp)) | |
732 | physical_balance = 1; | |
733 | ||
394e3902 | 734 | for_each_online_cpu(i) { |
0799e432 YL |
735 | irq_cpu_data[i].irq_delta = kzalloc(sizeof(unsigned long) * nr_irqs, GFP_KERNEL); |
736 | irq_cpu_data[i].last_irq = kzalloc(sizeof(unsigned long) * nr_irqs, GFP_KERNEL); | |
1da177e4 LT |
737 | if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) { |
738 | printk(KERN_ERR "balanced_irq_init: out of memory"); | |
739 | goto failed; | |
740 | } | |
1da177e4 | 741 | } |
36062448 | 742 | |
1da177e4 | 743 | printk(KERN_INFO "Starting balanced_irq\n"); |
f26d6a2b | 744 | if (!IS_ERR(kthread_run(balanced_irq, NULL, "kirqd"))) |
1da177e4 | 745 | return 0; |
f26d6a2b | 746 | printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq"); |
1da177e4 | 747 | failed: |
c8912599 | 748 | for_each_possible_cpu(i) { |
4ae6673e | 749 | kfree(irq_cpu_data[i].irq_delta); |
394e3902 | 750 | irq_cpu_data[i].irq_delta = NULL; |
4ae6673e | 751 | kfree(irq_cpu_data[i].last_irq); |
394e3902 | 752 | irq_cpu_data[i].last_irq = NULL; |
1da177e4 LT |
753 | } |
754 | return 0; | |
755 | } | |
756 | ||
c2481cc4 | 757 | int __devinit irqbalance_disable(char *str) |
1da177e4 LT |
758 | { |
759 | irqbalance_disabled = 1; | |
9b41046c | 760 | return 1; |
1da177e4 LT |
761 | } |
762 | ||
763 | __setup("noirqbalance", irqbalance_disable); | |
764 | ||
1da177e4 | 765 | late_initcall(balanced_irq_init); |
1da177e4 | 766 | #endif /* CONFIG_IRQBALANCE */ |
54d5d424 | 767 | #endif /* CONFIG_SMP */ |
1da177e4 LT |
768 | |
769 | #ifndef CONFIG_SMP | |
75604d7f | 770 | void send_IPI_self(int vector) |
1da177e4 LT |
771 | { |
772 | unsigned int cfg; | |
773 | ||
774 | /* | |
775 | * Wait for idle. | |
776 | */ | |
777 | apic_wait_icr_idle(); | |
778 | cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL; | |
779 | /* | |
780 | * Send the IPI. The write to APIC_ICR fires this off. | |
781 | */ | |
593f4a78 | 782 | apic_write(APIC_ICR, cfg); |
1da177e4 LT |
783 | } |
784 | #endif /* !CONFIG_SMP */ | |
785 | ||
786 | ||
787 | /* | |
788 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
789 | * specific CPU-side IRQs. | |
790 | */ | |
791 | ||
792 | #define MAX_PIRQS 8 | |
793 | static int pirq_entries [MAX_PIRQS]; | |
794 | static int pirqs_enabled; | |
795 | int skip_ioapic_setup; | |
796 | ||
1da177e4 LT |
797 | static int __init ioapic_pirq_setup(char *str) |
798 | { | |
799 | int i, max; | |
800 | int ints[MAX_PIRQS+1]; | |
801 | ||
802 | get_options(str, ARRAY_SIZE(ints), ints); | |
803 | ||
804 | for (i = 0; i < MAX_PIRQS; i++) | |
805 | pirq_entries[i] = -1; | |
806 | ||
807 | pirqs_enabled = 1; | |
808 | apic_printk(APIC_VERBOSE, KERN_INFO | |
809 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
810 | max = MAX_PIRQS; | |
811 | if (ints[0] < MAX_PIRQS) | |
812 | max = ints[0]; | |
813 | ||
814 | for (i = 0; i < max; i++) { | |
815 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
816 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
817 | /* | |
818 | * PIRQs are mapped upside down, usually. | |
819 | */ | |
820 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
821 | } | |
822 | return 1; | |
823 | } | |
824 | ||
825 | __setup("pirq=", ioapic_pirq_setup); | |
826 | ||
827 | /* | |
828 | * Find the IRQ entry number of a certain pin. | |
829 | */ | |
830 | static int find_irq_entry(int apic, int pin, int type) | |
831 | { | |
832 | int i; | |
833 | ||
834 | for (i = 0; i < mp_irq_entries; i++) | |
2fddb6e2 AS |
835 | if (mp_irqs[i].mp_irqtype == type && |
836 | (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid || | |
837 | mp_irqs[i].mp_dstapic == MP_APIC_ALL) && | |
838 | mp_irqs[i].mp_dstirq == pin) | |
1da177e4 LT |
839 | return i; |
840 | ||
841 | return -1; | |
842 | } | |
843 | ||
844 | /* | |
845 | * Find the pin to which IRQ[irq] (ISA) is connected | |
846 | */ | |
fcfd636a | 847 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
848 | { |
849 | int i; | |
850 | ||
851 | for (i = 0; i < mp_irq_entries; i++) { | |
2fddb6e2 | 852 | int lbus = mp_irqs[i].mp_srcbus; |
1da177e4 | 853 | |
d27e2b8e | 854 | if (test_bit(lbus, mp_bus_not_pci) && |
2fddb6e2 AS |
855 | (mp_irqs[i].mp_irqtype == type) && |
856 | (mp_irqs[i].mp_srcbusirq == irq)) | |
1da177e4 | 857 | |
2fddb6e2 | 858 | return mp_irqs[i].mp_dstirq; |
1da177e4 LT |
859 | } |
860 | return -1; | |
861 | } | |
862 | ||
fcfd636a EB |
863 | static int __init find_isa_irq_apic(int irq, int type) |
864 | { | |
865 | int i; | |
866 | ||
867 | for (i = 0; i < mp_irq_entries; i++) { | |
2fddb6e2 | 868 | int lbus = mp_irqs[i].mp_srcbus; |
fcfd636a | 869 | |
73b2961b | 870 | if (test_bit(lbus, mp_bus_not_pci) && |
2fddb6e2 AS |
871 | (mp_irqs[i].mp_irqtype == type) && |
872 | (mp_irqs[i].mp_srcbusirq == irq)) | |
fcfd636a EB |
873 | break; |
874 | } | |
875 | if (i < mp_irq_entries) { | |
876 | int apic; | |
36062448 | 877 | for (apic = 0; apic < nr_ioapics; apic++) { |
2fddb6e2 | 878 | if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic) |
fcfd636a EB |
879 | return apic; |
880 | } | |
881 | } | |
882 | ||
883 | return -1; | |
884 | } | |
885 | ||
1da177e4 LT |
886 | /* |
887 | * Find a specific PCI IRQ entry. | |
888 | * Not an __init, possibly needed by modules | |
889 | */ | |
890 | static int pin_2_irq(int idx, int apic, int pin); | |
891 | ||
892 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin) | |
893 | { | |
894 | int apic, i, best_guess = -1; | |
895 | ||
896 | apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, " | |
897 | "slot:%d, pin:%d.\n", bus, slot, pin); | |
ce6444d3 | 898 | if (test_bit(bus, mp_bus_not_pci)) { |
1da177e4 LT |
899 | printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus); |
900 | return -1; | |
901 | } | |
902 | for (i = 0; i < mp_irq_entries; i++) { | |
2fddb6e2 | 903 | int lbus = mp_irqs[i].mp_srcbus; |
1da177e4 LT |
904 | |
905 | for (apic = 0; apic < nr_ioapics; apic++) | |
2fddb6e2 AS |
906 | if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic || |
907 | mp_irqs[i].mp_dstapic == MP_APIC_ALL) | |
1da177e4 LT |
908 | break; |
909 | ||
47cab822 | 910 | if (!test_bit(lbus, mp_bus_not_pci) && |
2fddb6e2 | 911 | !mp_irqs[i].mp_irqtype && |
1da177e4 | 912 | (bus == lbus) && |
2fddb6e2 | 913 | (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) { |
3de352bb | 914 | int irq = pin_2_irq(i, apic, mp_irqs[i].mp_dstirq); |
1da177e4 LT |
915 | |
916 | if (!(apic || IO_APIC_IRQ(irq))) | |
917 | continue; | |
918 | ||
2fddb6e2 | 919 | if (pin == (mp_irqs[i].mp_srcbusirq & 3)) |
1da177e4 LT |
920 | return irq; |
921 | /* | |
922 | * Use the first all-but-pin matching entry as a | |
923 | * best-guess fuzzy result for broken mptables. | |
924 | */ | |
925 | if (best_guess < 0) | |
926 | best_guess = irq; | |
927 | } | |
928 | } | |
929 | return best_guess; | |
930 | } | |
129f6946 | 931 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); |
1da177e4 LT |
932 | |
933 | /* | |
36062448 | 934 | * This function currently is only a helper for the i386 smp boot process where |
1da177e4 LT |
935 | * we need to reprogram the ioredtbls to cater for the cpus which have come online |
936 | * so mask in all cases should simply be TARGET_CPUS | |
937 | */ | |
54d5d424 | 938 | #ifdef CONFIG_SMP |
1da177e4 LT |
939 | void __init setup_ioapic_dest(void) |
940 | { | |
941 | int pin, ioapic, irq, irq_entry; | |
942 | ||
943 | if (skip_ioapic_setup == 1) | |
944 | return; | |
945 | ||
946 | for (ioapic = 0; ioapic < nr_ioapics; ioapic++) { | |
947 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { | |
948 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); | |
949 | if (irq_entry == -1) | |
950 | continue; | |
951 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
952 | set_ioapic_affinity_irq(irq, TARGET_CPUS); | |
953 | } | |
954 | ||
955 | } | |
956 | } | |
54d5d424 | 957 | #endif |
1da177e4 | 958 | |
c0a282c2 | 959 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
1da177e4 LT |
960 | /* |
961 | * EISA Edge/Level control register, ELCR | |
962 | */ | |
963 | static int EISA_ELCR(unsigned int irq) | |
964 | { | |
965 | if (irq < 16) { | |
966 | unsigned int port = 0x4d0 + (irq >> 3); | |
967 | return (inb(port) >> (irq & 7)) & 1; | |
968 | } | |
969 | apic_printk(APIC_VERBOSE, KERN_INFO | |
970 | "Broken MPtable reports ISA irq %d\n", irq); | |
971 | return 0; | |
972 | } | |
c0a282c2 | 973 | #endif |
1da177e4 | 974 | |
6728801d AS |
975 | /* ISA interrupts are always polarity zero edge triggered, |
976 | * when listed as conforming in the MP table. */ | |
977 | ||
978 | #define default_ISA_trigger(idx) (0) | |
979 | #define default_ISA_polarity(idx) (0) | |
980 | ||
1da177e4 LT |
981 | /* EISA interrupts are always polarity zero and can be edge or level |
982 | * trigger depending on the ELCR value. If an interrupt is listed as | |
983 | * EISA conforming in the MP table, that means its trigger type must | |
984 | * be read in from the ELCR */ | |
985 | ||
2fddb6e2 | 986 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq)) |
6728801d | 987 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
988 | |
989 | /* PCI interrupts are always polarity one level triggered, | |
990 | * when listed as conforming in the MP table. */ | |
991 | ||
992 | #define default_PCI_trigger(idx) (1) | |
993 | #define default_PCI_polarity(idx) (1) | |
994 | ||
995 | /* MCA interrupts are always polarity zero level triggered, | |
996 | * when listed as conforming in the MP table. */ | |
997 | ||
998 | #define default_MCA_trigger(idx) (1) | |
6728801d | 999 | #define default_MCA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 | 1000 | |
61fd47e0 | 1001 | static int MPBIOS_polarity(int idx) |
1da177e4 | 1002 | { |
2fddb6e2 | 1003 | int bus = mp_irqs[idx].mp_srcbus; |
1da177e4 LT |
1004 | int polarity; |
1005 | ||
1006 | /* | |
1007 | * Determine IRQ line polarity (high active or low active): | |
1008 | */ | |
3de352bb | 1009 | switch (mp_irqs[idx].mp_irqflag & 3) { |
36062448 | 1010 | case 0: /* conforms, ie. bus-type dependent polarity */ |
1da177e4 | 1011 | { |
36062448 PC |
1012 | polarity = test_bit(bus, mp_bus_not_pci)? |
1013 | default_ISA_polarity(idx): | |
1014 | default_PCI_polarity(idx); | |
1015 | break; | |
1016 | } | |
1017 | case 1: /* high active */ | |
1018 | { | |
1019 | polarity = 0; | |
1020 | break; | |
1021 | } | |
1022 | case 2: /* reserved */ | |
1023 | { | |
1024 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1025 | polarity = 1; | |
1026 | break; | |
1027 | } | |
1028 | case 3: /* low active */ | |
1029 | { | |
1030 | polarity = 1; | |
1031 | break; | |
1032 | } | |
1033 | default: /* invalid */ | |
1034 | { | |
1035 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1036 | polarity = 1; | |
1037 | break; | |
1038 | } | |
1da177e4 LT |
1039 | } |
1040 | return polarity; | |
1041 | } | |
1042 | ||
1043 | static int MPBIOS_trigger(int idx) | |
1044 | { | |
2fddb6e2 | 1045 | int bus = mp_irqs[idx].mp_srcbus; |
1da177e4 LT |
1046 | int trigger; |
1047 | ||
1048 | /* | |
1049 | * Determine IRQ trigger mode (edge or level sensitive): | |
1050 | */ | |
3de352bb | 1051 | switch ((mp_irqs[idx].mp_irqflag>>2) & 3) { |
36062448 | 1052 | case 0: /* conforms, ie. bus-type dependent */ |
1da177e4 | 1053 | { |
36062448 PC |
1054 | trigger = test_bit(bus, mp_bus_not_pci)? |
1055 | default_ISA_trigger(idx): | |
1056 | default_PCI_trigger(idx); | |
c0a282c2 | 1057 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
36062448 PC |
1058 | switch (mp_bus_id_to_type[bus]) { |
1059 | case MP_BUS_ISA: /* ISA pin */ | |
1060 | { | |
1061 | /* set before the switch */ | |
1da177e4 LT |
1062 | break; |
1063 | } | |
36062448 | 1064 | case MP_BUS_EISA: /* EISA pin */ |
1da177e4 | 1065 | { |
36062448 | 1066 | trigger = default_EISA_trigger(idx); |
1da177e4 LT |
1067 | break; |
1068 | } | |
36062448 | 1069 | case MP_BUS_PCI: /* PCI pin */ |
1da177e4 | 1070 | { |
36062448 | 1071 | /* set before the switch */ |
1da177e4 LT |
1072 | break; |
1073 | } | |
36062448 | 1074 | case MP_BUS_MCA: /* MCA pin */ |
1da177e4 | 1075 | { |
36062448 | 1076 | trigger = default_MCA_trigger(idx); |
1da177e4 LT |
1077 | break; |
1078 | } | |
36062448 | 1079 | default: |
1da177e4 LT |
1080 | { |
1081 | printk(KERN_WARNING "broken BIOS!!\n"); | |
36062448 | 1082 | trigger = 1; |
1da177e4 LT |
1083 | break; |
1084 | } | |
1085 | } | |
36062448 PC |
1086 | #endif |
1087 | break; | |
1088 | } | |
1089 | case 1: /* edge */ | |
1090 | { | |
1091 | trigger = 0; | |
1092 | break; | |
1093 | } | |
1094 | case 2: /* reserved */ | |
1095 | { | |
1096 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1097 | trigger = 1; | |
1098 | break; | |
1099 | } | |
1100 | case 3: /* level */ | |
1101 | { | |
1102 | trigger = 1; | |
1103 | break; | |
1104 | } | |
1105 | default: /* invalid */ | |
1106 | { | |
1107 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1108 | trigger = 0; | |
1109 | break; | |
1110 | } | |
1111 | } | |
1da177e4 LT |
1112 | return trigger; |
1113 | } | |
1114 | ||
1115 | static inline int irq_polarity(int idx) | |
1116 | { | |
1117 | return MPBIOS_polarity(idx); | |
1118 | } | |
1119 | ||
1120 | static inline int irq_trigger(int idx) | |
1121 | { | |
1122 | return MPBIOS_trigger(idx); | |
1123 | } | |
1124 | ||
1125 | static int pin_2_irq(int idx, int apic, int pin) | |
1126 | { | |
1127 | int irq, i; | |
2fddb6e2 | 1128 | int bus = mp_irqs[idx].mp_srcbus; |
1da177e4 LT |
1129 | |
1130 | /* | |
1131 | * Debugging check, we are in big trouble if this message pops up! | |
1132 | */ | |
2fddb6e2 | 1133 | if (mp_irqs[idx].mp_dstirq != pin) |
1da177e4 LT |
1134 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); |
1135 | ||
643befed | 1136 | if (test_bit(bus, mp_bus_not_pci)) |
2fddb6e2 | 1137 | irq = mp_irqs[idx].mp_srcbusirq; |
643befed AS |
1138 | else { |
1139 | /* | |
1140 | * PCI IRQs are mapped in order | |
1141 | */ | |
1142 | i = irq = 0; | |
1143 | while (i < apic) | |
1144 | irq += nr_ioapic_registers[i++]; | |
1145 | irq += pin; | |
1da177e4 | 1146 | |
643befed AS |
1147 | /* |
1148 | * For MPS mode, so far only needed by ES7000 platform | |
1149 | */ | |
1150 | if (ioapic_renumber_irq) | |
1151 | irq = ioapic_renumber_irq(apic, irq); | |
1da177e4 LT |
1152 | } |
1153 | ||
1154 | /* | |
1155 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
1156 | */ | |
1157 | if ((pin >= 16) && (pin <= 23)) { | |
1158 | if (pirq_entries[pin-16] != -1) { | |
1159 | if (!pirq_entries[pin-16]) { | |
1160 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1161 | "disabling PIRQ%d\n", pin-16); | |
1162 | } else { | |
1163 | irq = pirq_entries[pin-16]; | |
1164 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1165 | "using PIRQ%d -> IRQ %d\n", | |
1166 | pin-16, irq); | |
1167 | } | |
1168 | } | |
1169 | } | |
1170 | return irq; | |
1171 | } | |
1172 | ||
1173 | static inline int IO_APIC_irq_trigger(int irq) | |
1174 | { | |
1175 | int apic, idx, pin; | |
1176 | ||
1177 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1178 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
36062448 PC |
1179 | idx = find_irq_entry(apic, pin, mp_INT); |
1180 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin))) | |
1da177e4 LT |
1181 | return irq_trigger(idx); |
1182 | } | |
1183 | } | |
1184 | /* | |
1185 | * nonexistent IRQs are edge default | |
1186 | */ | |
1187 | return 0; | |
1188 | } | |
1189 | ||
1190 | /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */ | |
301e6190 YL |
1191 | static u8 irq_vector_init_first __initdata = FIRST_DEVICE_VECTOR; |
1192 | static u8 *irq_vector; | |
1193 | ||
1194 | static void __init irq_vector_init_work(void *data) | |
1195 | { | |
1196 | struct dyn_array *da = data; | |
1197 | ||
1198 | u8 *irq_vec; | |
1199 | ||
1200 | irq_vec = *da->name; | |
1201 | ||
1202 | irq_vec[0] = irq_vector_init_first; | |
1203 | } | |
1204 | ||
1205 | DEFINE_DYN_ARRAY(irq_vector, sizeof(u8), nr_irqs, PAGE_SIZE, irq_vector_init_work); | |
1da177e4 | 1206 | |
ace80ab7 | 1207 | static int __assign_irq_vector(int irq) |
1da177e4 | 1208 | { |
36062448 | 1209 | static int current_vector = FIRST_DEVICE_VECTOR, current_offset; |
dbeb2be2 | 1210 | int vector, offset; |
1da177e4 | 1211 | |
301e6190 | 1212 | BUG_ON((unsigned)irq >= nr_irqs); |
0a1ad60d | 1213 | |
b940d22d EB |
1214 | if (irq_vector[irq] > 0) |
1215 | return irq_vector[irq]; | |
ace80ab7 | 1216 | |
0a1ad60d | 1217 | vector = current_vector; |
8339f000 EB |
1218 | offset = current_offset; |
1219 | next: | |
1220 | vector += 8; | |
305b92a2 | 1221 | if (vector >= first_system_vector) { |
8339f000 EB |
1222 | offset = (offset + 1) % 8; |
1223 | vector = FIRST_DEVICE_VECTOR + offset; | |
1224 | } | |
1225 | if (vector == current_vector) | |
1226 | return -ENOSPC; | |
dbeb2be2 | 1227 | if (test_and_set_bit(vector, used_vectors)) |
8339f000 | 1228 | goto next; |
8339f000 EB |
1229 | |
1230 | current_vector = vector; | |
1231 | current_offset = offset; | |
b940d22d | 1232 | irq_vector[irq] = vector; |
ace80ab7 EB |
1233 | |
1234 | return vector; | |
1235 | } | |
0a1ad60d | 1236 | |
ace80ab7 EB |
1237 | static int assign_irq_vector(int irq) |
1238 | { | |
1239 | unsigned long flags; | |
1240 | int vector; | |
1241 | ||
1242 | spin_lock_irqsave(&vector_lock, flags); | |
1243 | vector = __assign_irq_vector(irq); | |
26a3c49c | 1244 | spin_unlock_irqrestore(&vector_lock, flags); |
1da177e4 | 1245 | |
0a1ad60d | 1246 | return vector; |
1da177e4 | 1247 | } |
3fde6900 | 1248 | |
f5b9ed7a | 1249 | static struct irq_chip ioapic_chip; |
1da177e4 LT |
1250 | |
1251 | #define IOAPIC_AUTO -1 | |
1252 | #define IOAPIC_EDGE 0 | |
1253 | #define IOAPIC_LEVEL 1 | |
1254 | ||
d1bef4ed | 1255 | static void ioapic_register_intr(int irq, int vector, unsigned long trigger) |
1da177e4 | 1256 | { |
6ebcc00e | 1257 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
cc75b92d TG |
1258 | trigger == IOAPIC_LEVEL) { |
1259 | irq_desc[irq].status |= IRQ_LEVEL; | |
a460e745 IM |
1260 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
1261 | handle_fasteoi_irq, "fasteoi"); | |
cc75b92d TG |
1262 | } else { |
1263 | irq_desc[irq].status &= ~IRQ_LEVEL; | |
a460e745 IM |
1264 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
1265 | handle_edge_irq, "edge"); | |
cc75b92d | 1266 | } |
ace80ab7 | 1267 | set_intr_gate(vector, interrupt[irq]); |
1da177e4 LT |
1268 | } |
1269 | ||
1270 | static void __init setup_IO_APIC_irqs(void) | |
1271 | { | |
1272 | struct IO_APIC_route_entry entry; | |
1273 | int apic, pin, idx, irq, first_notcon = 1, vector; | |
1da177e4 LT |
1274 | |
1275 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1276 | ||
1277 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1278 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1279 | ||
1280 | /* | |
1281 | * add it to the IO-APIC irq-routing table: | |
1282 | */ | |
36062448 | 1283 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
1284 | |
1285 | entry.delivery_mode = INT_DELIVERY_MODE; | |
1286 | entry.dest_mode = INT_DEST_MODE; | |
1287 | entry.mask = 0; /* enable IRQ */ | |
36062448 | 1288 | entry.dest.logical.logical_dest = |
1da177e4 LT |
1289 | cpu_mask_to_apicid(TARGET_CPUS); |
1290 | ||
36062448 | 1291 | idx = find_irq_entry(apic, pin, mp_INT); |
1da177e4 LT |
1292 | if (idx == -1) { |
1293 | if (first_notcon) { | |
1294 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1295 | " IO-APIC (apicid-pin) %d-%d", | |
ec2cd0a2 | 1296 | mp_ioapics[apic].mp_apicid, |
1da177e4 LT |
1297 | pin); |
1298 | first_notcon = 0; | |
1299 | } else | |
1300 | apic_printk(APIC_VERBOSE, ", %d-%d", | |
ec2cd0a2 | 1301 | mp_ioapics[apic].mp_apicid, pin); |
1da177e4 LT |
1302 | continue; |
1303 | } | |
1304 | ||
20d225b9 YL |
1305 | if (!first_notcon) { |
1306 | apic_printk(APIC_VERBOSE, " not connected.\n"); | |
1307 | first_notcon = 1; | |
1308 | } | |
1309 | ||
1da177e4 LT |
1310 | entry.trigger = irq_trigger(idx); |
1311 | entry.polarity = irq_polarity(idx); | |
1312 | ||
1313 | if (irq_trigger(idx)) { | |
1314 | entry.trigger = 1; | |
1315 | entry.mask = 1; | |
1316 | } | |
1317 | ||
1318 | irq = pin_2_irq(idx, apic, pin); | |
1319 | /* | |
1320 | * skip adding the timer int on secondary nodes, which causes | |
1321 | * a small but painful rift in the time-space continuum | |
1322 | */ | |
1323 | if (multi_timer_check(apic, irq)) | |
1324 | continue; | |
1325 | else | |
1326 | add_pin_to_irq(irq, apic, pin); | |
1327 | ||
1328 | if (!apic && !IO_APIC_IRQ(irq)) | |
1329 | continue; | |
1330 | ||
1331 | if (IO_APIC_IRQ(irq)) { | |
1332 | vector = assign_irq_vector(irq); | |
1333 | entry.vector = vector; | |
1334 | ioapic_register_intr(irq, vector, IOAPIC_AUTO); | |
36062448 | 1335 | |
1da177e4 LT |
1336 | if (!apic && (irq < 16)) |
1337 | disable_8259A_irq(irq); | |
1338 | } | |
a2249cba | 1339 | ioapic_write_entry(apic, pin, entry); |
1da177e4 LT |
1340 | } |
1341 | } | |
1342 | ||
1343 | if (!first_notcon) | |
1344 | apic_printk(APIC_VERBOSE, " not connected.\n"); | |
1345 | } | |
1346 | ||
1347 | /* | |
f7633ce5 | 1348 | * Set up the timer pin, possibly with the 8259A-master behind. |
1da177e4 | 1349 | */ |
f7633ce5 MR |
1350 | static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin, |
1351 | int vector) | |
1da177e4 LT |
1352 | { |
1353 | struct IO_APIC_route_entry entry; | |
1da177e4 | 1354 | |
36062448 | 1355 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
1356 | |
1357 | /* | |
1358 | * We use logical delivery to get the timer IRQ | |
1359 | * to the first CPU. | |
1360 | */ | |
1361 | entry.dest_mode = INT_DEST_MODE; | |
03be7505 | 1362 | entry.mask = 1; /* mask IRQ now */ |
1da177e4 LT |
1363 | entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS); |
1364 | entry.delivery_mode = INT_DELIVERY_MODE; | |
1365 | entry.polarity = 0; | |
1366 | entry.trigger = 0; | |
1367 | entry.vector = vector; | |
1368 | ||
1369 | /* | |
1370 | * The timer IRQ doesn't have to know that behind the | |
f7633ce5 | 1371 | * scene we may have a 8259A-master in AEOI mode ... |
1da177e4 | 1372 | */ |
f0825262 | 1373 | ioapic_register_intr(0, vector, IOAPIC_EDGE); |
1da177e4 LT |
1374 | |
1375 | /* | |
1376 | * Add it to the IO-APIC irq-routing table: | |
1377 | */ | |
cf4c6a2f | 1378 | ioapic_write_entry(apic, pin, entry); |
1da177e4 LT |
1379 | } |
1380 | ||
32f71aff MR |
1381 | |
1382 | __apicdebuginit(void) print_IO_APIC(void) | |
1da177e4 LT |
1383 | { |
1384 | int apic, i; | |
1385 | union IO_APIC_reg_00 reg_00; | |
1386 | union IO_APIC_reg_01 reg_01; | |
1387 | union IO_APIC_reg_02 reg_02; | |
1388 | union IO_APIC_reg_03 reg_03; | |
1389 | unsigned long flags; | |
1390 | ||
1391 | if (apic_verbosity == APIC_QUIET) | |
1392 | return; | |
1393 | ||
36062448 | 1394 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); |
1da177e4 LT |
1395 | for (i = 0; i < nr_ioapics; i++) |
1396 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", | |
ec2cd0a2 | 1397 | mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]); |
1da177e4 LT |
1398 | |
1399 | /* | |
1400 | * We are a bit conservative about what we expect. We have to | |
1401 | * know about every hardware change ASAP. | |
1402 | */ | |
1403 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1404 | ||
1405 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1406 | ||
1407 | spin_lock_irqsave(&ioapic_lock, flags); | |
1408 | reg_00.raw = io_apic_read(apic, 0); | |
1409 | reg_01.raw = io_apic_read(apic, 1); | |
1410 | if (reg_01.bits.version >= 0x10) | |
1411 | reg_02.raw = io_apic_read(apic, 2); | |
1412 | if (reg_01.bits.version >= 0x20) | |
1413 | reg_03.raw = io_apic_read(apic, 3); | |
1414 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1415 | ||
ec2cd0a2 | 1416 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
1417 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1418 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1419 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1420 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 LT |
1421 | |
1422 | printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw); | |
1423 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); | |
1da177e4 LT |
1424 | |
1425 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
1426 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); | |
1da177e4 LT |
1427 | |
1428 | /* | |
1429 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1430 | * but the value of reg_02 is read as the previous read register | |
1431 | * value, so ignore it if reg_02 == reg_01. | |
1432 | */ | |
1433 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1434 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1435 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1436 | } |
1437 | ||
1438 | /* | |
1439 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1440 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1441 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1442 | */ | |
1443 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1444 | reg_03.raw != reg_01.raw) { | |
1445 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1446 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1447 | } |
1448 | ||
1449 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1450 | ||
1451 | printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol" | |
1452 | " Stat Dest Deli Vect: \n"); | |
1453 | ||
1454 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
1455 | struct IO_APIC_route_entry entry; | |
1456 | ||
cf4c6a2f | 1457 | entry = ioapic_read_entry(apic, i); |
1da177e4 LT |
1458 | |
1459 | printk(KERN_DEBUG " %02x %03X %02X ", | |
1460 | i, | |
1461 | entry.dest.logical.logical_dest, | |
1462 | entry.dest.physical.physical_dest | |
1463 | ); | |
1464 | ||
1465 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", | |
1466 | entry.mask, | |
1467 | entry.trigger, | |
1468 | entry.irr, | |
1469 | entry.polarity, | |
1470 | entry.delivery_status, | |
1471 | entry.dest_mode, | |
1472 | entry.delivery_mode, | |
1473 | entry.vector | |
1474 | ); | |
1475 | } | |
1476 | } | |
1da177e4 | 1477 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
0799e432 | 1478 | for (i = 0; i < nr_irqs; i++) { |
1da177e4 LT |
1479 | struct irq_pin_list *entry = irq_2_pin + i; |
1480 | if (entry->pin < 0) | |
1481 | continue; | |
ace80ab7 | 1482 | printk(KERN_DEBUG "IRQ%d ", i); |
1da177e4 LT |
1483 | for (;;) { |
1484 | printk("-> %d:%d", entry->apic, entry->pin); | |
1485 | if (!entry->next) | |
1486 | break; | |
1487 | entry = irq_2_pin + entry->next; | |
1488 | } | |
1489 | printk("\n"); | |
1490 | } | |
1491 | ||
1492 | printk(KERN_INFO ".................................... done.\n"); | |
1493 | ||
1494 | return; | |
1495 | } | |
1496 | ||
32f71aff | 1497 | __apicdebuginit(void) print_APIC_bitfield(int base) |
1da177e4 LT |
1498 | { |
1499 | unsigned int v; | |
1500 | int i, j; | |
1501 | ||
1502 | if (apic_verbosity == APIC_QUIET) | |
1503 | return; | |
1504 | ||
1505 | printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG); | |
1506 | for (i = 0; i < 8; i++) { | |
1507 | v = apic_read(base + i*0x10); | |
1508 | for (j = 0; j < 32; j++) { | |
1509 | if (v & (1<<j)) | |
1510 | printk("1"); | |
1511 | else | |
1512 | printk("0"); | |
1513 | } | |
1514 | printk("\n"); | |
1515 | } | |
1516 | } | |
1517 | ||
32f71aff | 1518 | __apicdebuginit(void) print_local_APIC(void *dummy) |
1da177e4 LT |
1519 | { |
1520 | unsigned int v, ver, maxlvt; | |
7ab6af7a | 1521 | u64 icr; |
1da177e4 LT |
1522 | |
1523 | if (apic_verbosity == APIC_QUIET) | |
1524 | return; | |
1525 | ||
1526 | printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", | |
1527 | smp_processor_id(), hard_smp_processor_id()); | |
66823114 | 1528 | v = apic_read(APIC_ID); |
05f2d12c | 1529 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, |
4c9961d5 | 1530 | GET_APIC_ID(v)); |
1da177e4 LT |
1531 | v = apic_read(APIC_LVR); |
1532 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1533 | ver = GET_APIC_VERSION(v); | |
e05d723f | 1534 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1535 | |
1536 | v = apic_read(APIC_TASKPRI); | |
1537 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1538 | ||
1539 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ | |
1540 | v = apic_read(APIC_ARBPRI); | |
1541 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1542 | v & APIC_ARBPRI_MASK); | |
1543 | v = apic_read(APIC_PROCPRI); | |
1544 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1545 | } | |
1546 | ||
1547 | v = apic_read(APIC_EOI); | |
1548 | printk(KERN_DEBUG "... APIC EOI: %08x\n", v); | |
1549 | v = apic_read(APIC_RRR); | |
1550 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1551 | v = apic_read(APIC_LDR); | |
1552 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
1553 | v = apic_read(APIC_DFR); | |
1554 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1555 | v = apic_read(APIC_SPIV); | |
1556 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1557 | ||
1558 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
1559 | print_APIC_bitfield(APIC_ISR); | |
1560 | printk(KERN_DEBUG "... APIC TMR field:\n"); | |
1561 | print_APIC_bitfield(APIC_TMR); | |
1562 | printk(KERN_DEBUG "... APIC IRR field:\n"); | |
1563 | print_APIC_bitfield(APIC_IRR); | |
1564 | ||
1565 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ | |
1566 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1567 | apic_write(APIC_ESR, 0); | |
1568 | v = apic_read(APIC_ESR); | |
1569 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1570 | } | |
1571 | ||
7ab6af7a HS |
1572 | icr = apic_icr_read(); |
1573 | printk(KERN_DEBUG "... APIC ICR: %08x\n", icr); | |
1574 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", icr >> 32); | |
1da177e4 LT |
1575 | |
1576 | v = apic_read(APIC_LVTT); | |
1577 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1578 | ||
1579 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1580 | v = apic_read(APIC_LVTPC); | |
1581 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1582 | } | |
1583 | v = apic_read(APIC_LVT0); | |
1584 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1585 | v = apic_read(APIC_LVT1); | |
1586 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1587 | ||
1588 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1589 | v = apic_read(APIC_LVTERR); | |
1590 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1591 | } | |
1592 | ||
1593 | v = apic_read(APIC_TMICT); | |
1594 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1595 | v = apic_read(APIC_TMCCT); | |
1596 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1597 | v = apic_read(APIC_TDCR); | |
1598 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
1599 | printk("\n"); | |
1600 | } | |
1601 | ||
32f71aff | 1602 | __apicdebuginit(void) print_all_local_APICs(void) |
1da177e4 | 1603 | { |
15c8b6c1 | 1604 | on_each_cpu(print_local_APIC, NULL, 1); |
1da177e4 LT |
1605 | } |
1606 | ||
32f71aff | 1607 | __apicdebuginit(void) print_PIC(void) |
1da177e4 | 1608 | { |
1da177e4 LT |
1609 | unsigned int v; |
1610 | unsigned long flags; | |
1611 | ||
1612 | if (apic_verbosity == APIC_QUIET) | |
1613 | return; | |
1614 | ||
1615 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1616 | ||
1617 | spin_lock_irqsave(&i8259A_lock, flags); | |
1618 | ||
1619 | v = inb(0xa1) << 8 | inb(0x21); | |
1620 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1621 | ||
1622 | v = inb(0xa0) << 8 | inb(0x20); | |
1623 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1624 | ||
36062448 PC |
1625 | outb(0x0b, 0xa0); |
1626 | outb(0x0b, 0x20); | |
1da177e4 | 1627 | v = inb(0xa0) << 8 | inb(0x20); |
36062448 PC |
1628 | outb(0x0a, 0xa0); |
1629 | outb(0x0a, 0x20); | |
1da177e4 LT |
1630 | |
1631 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
1632 | ||
1633 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1634 | ||
1635 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1636 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1637 | } | |
1638 | ||
32f71aff MR |
1639 | __apicdebuginit(int) print_all_ICs(void) |
1640 | { | |
1641 | print_PIC(); | |
1642 | print_all_local_APICs(); | |
1643 | print_IO_APIC(); | |
1644 | ||
1645 | return 0; | |
1646 | } | |
1647 | ||
1648 | fs_initcall(print_all_ICs); | |
1649 | ||
1da177e4 LT |
1650 | |
1651 | static void __init enable_IO_APIC(void) | |
1652 | { | |
1653 | union IO_APIC_reg_01 reg_01; | |
fcfd636a EB |
1654 | int i8259_apic, i8259_pin; |
1655 | int i, apic; | |
1da177e4 LT |
1656 | unsigned long flags; |
1657 | ||
0799e432 | 1658 | for (i = 0; i < pin_map_size; i++) { |
1da177e4 LT |
1659 | irq_2_pin[i].pin = -1; |
1660 | irq_2_pin[i].next = 0; | |
1661 | } | |
1662 | if (!pirqs_enabled) | |
1663 | for (i = 0; i < MAX_PIRQS; i++) | |
1664 | pirq_entries[i] = -1; | |
1665 | ||
1666 | /* | |
1667 | * The number of IO-APIC IRQ registers (== #pins): | |
1668 | */ | |
fcfd636a | 1669 | for (apic = 0; apic < nr_ioapics; apic++) { |
1da177e4 | 1670 | spin_lock_irqsave(&ioapic_lock, flags); |
fcfd636a | 1671 | reg_01.raw = io_apic_read(apic, 1); |
1da177e4 | 1672 | spin_unlock_irqrestore(&ioapic_lock, flags); |
fcfd636a EB |
1673 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; |
1674 | } | |
36062448 | 1675 | for (apic = 0; apic < nr_ioapics; apic++) { |
fcfd636a EB |
1676 | int pin; |
1677 | /* See if any of the pins is in ExtINT mode */ | |
1008fddc | 1678 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
fcfd636a | 1679 | struct IO_APIC_route_entry entry; |
cf4c6a2f | 1680 | entry = ioapic_read_entry(apic, pin); |
fcfd636a EB |
1681 | |
1682 | ||
1683 | /* If the interrupt line is enabled and in ExtInt mode | |
1684 | * I have found the pin where the i8259 is connected. | |
1685 | */ | |
1686 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1687 | ioapic_i8259.apic = apic; | |
1688 | ioapic_i8259.pin = pin; | |
1689 | goto found_i8259; | |
1690 | } | |
1691 | } | |
1692 | } | |
1693 | found_i8259: | |
1694 | /* Look to see what if the MP table has reported the ExtINT */ | |
1695 | /* If we could not find the appropriate pin by looking at the ioapic | |
1696 | * the i8259 probably is not connected the ioapic but give the | |
1697 | * mptable a chance anyway. | |
1698 | */ | |
1699 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1700 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1701 | /* Trust the MP table if nothing is setup in the hardware */ | |
1702 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1703 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1704 | ioapic_i8259.pin = i8259_pin; | |
1705 | ioapic_i8259.apic = i8259_apic; | |
1706 | } | |
1707 | /* Complain if the MP table and the hardware disagree */ | |
1708 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1709 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1710 | { | |
1711 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1712 | } |
1713 | ||
1714 | /* | |
1715 | * Do not trust the IO-APIC being empty at bootup | |
1716 | */ | |
1717 | clear_IO_APIC(); | |
1718 | } | |
1719 | ||
1720 | /* | |
1721 | * Not an __init, needed by the reboot code | |
1722 | */ | |
1723 | void disable_IO_APIC(void) | |
1724 | { | |
1725 | /* | |
1726 | * Clear the IO-APIC before rebooting: | |
1727 | */ | |
1728 | clear_IO_APIC(); | |
1729 | ||
650927ef | 1730 | /* |
0b968d23 | 1731 | * If the i8259 is routed through an IOAPIC |
650927ef | 1732 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 1733 | * so legacy interrupts can be delivered. |
650927ef | 1734 | */ |
fcfd636a | 1735 | if (ioapic_i8259.pin != -1) { |
650927ef | 1736 | struct IO_APIC_route_entry entry; |
650927ef EB |
1737 | |
1738 | memset(&entry, 0, sizeof(entry)); | |
1739 | entry.mask = 0; /* Enabled */ | |
1740 | entry.trigger = 0; /* Edge */ | |
1741 | entry.irr = 0; | |
1742 | entry.polarity = 0; /* High */ | |
1743 | entry.delivery_status = 0; | |
1744 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 1745 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 1746 | entry.vector = 0; |
4c9961d5 | 1747 | entry.dest.physical.physical_dest = read_apic_id(); |
650927ef EB |
1748 | |
1749 | /* | |
1750 | * Add it to the IO-APIC irq-routing table: | |
1751 | */ | |
cf4c6a2f | 1752 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 1753 | } |
fcfd636a | 1754 | disconnect_bsp_APIC(ioapic_i8259.pin != -1); |
1da177e4 LT |
1755 | } |
1756 | ||
1757 | /* | |
1758 | * function to set the IO-APIC physical IDs based on the | |
1759 | * values stored in the MPC table. | |
1760 | * | |
1761 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
1762 | */ | |
1763 | ||
1da177e4 LT |
1764 | static void __init setup_ioapic_ids_from_mpc(void) |
1765 | { | |
1766 | union IO_APIC_reg_00 reg_00; | |
1767 | physid_mask_t phys_id_present_map; | |
1768 | int apic; | |
1769 | int i; | |
1770 | unsigned char old_id; | |
1771 | unsigned long flags; | |
1772 | ||
a4dbc34d | 1773 | if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids()) |
d49c4288 | 1774 | return; |
d49c4288 | 1775 | |
ca05fea6 NP |
1776 | /* |
1777 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
1778 | * no meaning without the serial APIC bus. | |
1779 | */ | |
7c5c1e42 SL |
1780 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
1781 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
ca05fea6 | 1782 | return; |
1da177e4 LT |
1783 | /* |
1784 | * This is broken; anything with a real cpu count has to | |
1785 | * circumvent this idiocy regardless. | |
1786 | */ | |
1787 | phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map); | |
1788 | ||
1789 | /* | |
1790 | * Set the IOAPIC ID to the value stored in the MPC table. | |
1791 | */ | |
1792 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1793 | ||
1794 | /* Read the register 0 value */ | |
1795 | spin_lock_irqsave(&ioapic_lock, flags); | |
1796 | reg_00.raw = io_apic_read(apic, 0); | |
1797 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
36062448 | 1798 | |
ec2cd0a2 | 1799 | old_id = mp_ioapics[apic].mp_apicid; |
1da177e4 | 1800 | |
ec2cd0a2 | 1801 | if (mp_ioapics[apic].mp_apicid >= get_physical_broadcast()) { |
1da177e4 | 1802 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
ec2cd0a2 | 1803 | apic, mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
1804 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
1805 | reg_00.bits.ID); | |
ec2cd0a2 | 1806 | mp_ioapics[apic].mp_apicid = reg_00.bits.ID; |
1da177e4 LT |
1807 | } |
1808 | ||
1da177e4 LT |
1809 | /* |
1810 | * Sanity check, is the ID really free? Every APIC in a | |
1811 | * system must have a unique ID or we get lots of nice | |
1812 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
1813 | */ | |
1814 | if (check_apicid_used(phys_id_present_map, | |
ec2cd0a2 | 1815 | mp_ioapics[apic].mp_apicid)) { |
1da177e4 | 1816 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
ec2cd0a2 | 1817 | apic, mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
1818 | for (i = 0; i < get_physical_broadcast(); i++) |
1819 | if (!physid_isset(i, phys_id_present_map)) | |
1820 | break; | |
1821 | if (i >= get_physical_broadcast()) | |
1822 | panic("Max APIC ID exceeded!\n"); | |
1823 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
1824 | i); | |
1825 | physid_set(i, phys_id_present_map); | |
ec2cd0a2 | 1826 | mp_ioapics[apic].mp_apicid = i; |
1da177e4 LT |
1827 | } else { |
1828 | physid_mask_t tmp; | |
ec2cd0a2 | 1829 | tmp = apicid_to_cpu_present(mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
1830 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
1831 | "phys_id_present_map\n", | |
ec2cd0a2 | 1832 | mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
1833 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
1834 | } | |
1835 | ||
1836 | ||
1837 | /* | |
1838 | * We need to adjust the IRQ routing table | |
1839 | * if the ID changed. | |
1840 | */ | |
ec2cd0a2 | 1841 | if (old_id != mp_ioapics[apic].mp_apicid) |
1da177e4 | 1842 | for (i = 0; i < mp_irq_entries; i++) |
2fddb6e2 AS |
1843 | if (mp_irqs[i].mp_dstapic == old_id) |
1844 | mp_irqs[i].mp_dstapic | |
ec2cd0a2 | 1845 | = mp_ioapics[apic].mp_apicid; |
1da177e4 LT |
1846 | |
1847 | /* | |
1848 | * Read the right value from the MPC table and | |
1849 | * write it into the ID register. | |
36062448 | 1850 | */ |
1da177e4 LT |
1851 | apic_printk(APIC_VERBOSE, KERN_INFO |
1852 | "...changing IO-APIC physical APIC ID to %d ...", | |
ec2cd0a2 | 1853 | mp_ioapics[apic].mp_apicid); |
1da177e4 | 1854 | |
ec2cd0a2 | 1855 | reg_00.bits.ID = mp_ioapics[apic].mp_apicid; |
1da177e4 LT |
1856 | spin_lock_irqsave(&ioapic_lock, flags); |
1857 | io_apic_write(apic, 0, reg_00.raw); | |
1858 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1859 | ||
1860 | /* | |
1861 | * Sanity check | |
1862 | */ | |
1863 | spin_lock_irqsave(&ioapic_lock, flags); | |
1864 | reg_00.raw = io_apic_read(apic, 0); | |
1865 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
ec2cd0a2 | 1866 | if (reg_00.bits.ID != mp_ioapics[apic].mp_apicid) |
1da177e4 LT |
1867 | printk("could not set ID!\n"); |
1868 | else | |
1869 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
1870 | } | |
1871 | } | |
1da177e4 | 1872 | |
7ce0bcfd | 1873 | int no_timer_check __initdata; |
8542b200 ZA |
1874 | |
1875 | static int __init notimercheck(char *s) | |
1876 | { | |
1877 | no_timer_check = 1; | |
1878 | return 1; | |
1879 | } | |
1880 | __setup("no_timer_check", notimercheck); | |
1881 | ||
1da177e4 LT |
1882 | /* |
1883 | * There is a nasty bug in some older SMP boards, their mptable lies | |
1884 | * about the timer IRQ. We do the following to work around the situation: | |
1885 | * | |
1886 | * - timer IRQ defaults to IO-APIC IRQ | |
1887 | * - if this function detects that timer IRQs are defunct, then we fall | |
1888 | * back to ISA timer IRQs | |
1889 | */ | |
f0a7a5c9 | 1890 | static int __init timer_irq_works(void) |
1da177e4 LT |
1891 | { |
1892 | unsigned long t1 = jiffies; | |
4aae0702 | 1893 | unsigned long flags; |
1da177e4 | 1894 | |
8542b200 ZA |
1895 | if (no_timer_check) |
1896 | return 1; | |
1897 | ||
4aae0702 | 1898 | local_save_flags(flags); |
1da177e4 LT |
1899 | local_irq_enable(); |
1900 | /* Let ten ticks pass... */ | |
1901 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 1902 | local_irq_restore(flags); |
1da177e4 LT |
1903 | |
1904 | /* | |
1905 | * Expect a few ticks at least, to be sure some possible | |
1906 | * glue logic does not lock up after one or two first | |
1907 | * ticks in a non-ExtINT mode. Also the local APIC | |
1908 | * might have cached one ExtINT interrupt. Finally, at | |
1909 | * least one tick may be lost due to delays. | |
1910 | */ | |
1d16b53e | 1911 | if (time_after(jiffies, t1 + 4)) |
1da177e4 LT |
1912 | return 1; |
1913 | ||
1914 | return 0; | |
1915 | } | |
1916 | ||
1917 | /* | |
1918 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
1919 | * number of pending IRQ events unhandled. These cases are very rare, | |
1920 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
1921 | * better to do it this way as thus we do not have to be aware of | |
1922 | * 'pending' interrupts in the IRQ path, except at this point. | |
1923 | */ | |
1924 | /* | |
1925 | * Edge triggered needs to resend any interrupt | |
1926 | * that was delayed but this is now handled in the device | |
1927 | * independent code. | |
1928 | */ | |
1929 | ||
1930 | /* | |
f5b9ed7a IM |
1931 | * Startup quirk: |
1932 | * | |
1da177e4 LT |
1933 | * Starting up a edge-triggered IO-APIC interrupt is |
1934 | * nasty - we need to make sure that we get the edge. | |
1935 | * If it is already asserted for some reason, we need | |
1936 | * return 1 to indicate that is was pending. | |
1937 | * | |
1938 | * This is not complete - we should be able to fake | |
1939 | * an edge even if it isn't on the 8259A... | |
f5b9ed7a IM |
1940 | * |
1941 | * (We do this for level-triggered IRQs too - it cannot hurt.) | |
1da177e4 | 1942 | */ |
f5b9ed7a | 1943 | static unsigned int startup_ioapic_irq(unsigned int irq) |
1da177e4 LT |
1944 | { |
1945 | int was_pending = 0; | |
1946 | unsigned long flags; | |
1947 | ||
1948 | spin_lock_irqsave(&ioapic_lock, flags); | |
1949 | if (irq < 16) { | |
1950 | disable_8259A_irq(irq); | |
1951 | if (i8259A_irq_pending(irq)) | |
1952 | was_pending = 1; | |
1953 | } | |
1954 | __unmask_IO_APIC_irq(irq); | |
1955 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1956 | ||
1957 | return was_pending; | |
1958 | } | |
1959 | ||
f5b9ed7a | 1960 | static void ack_ioapic_irq(unsigned int irq) |
1da177e4 | 1961 | { |
ace80ab7 | 1962 | move_native_irq(irq); |
1da177e4 LT |
1963 | ack_APIC_irq(); |
1964 | } | |
1965 | ||
f5b9ed7a | 1966 | static void ack_ioapic_quirk_irq(unsigned int irq) |
1da177e4 LT |
1967 | { |
1968 | unsigned long v; | |
1969 | int i; | |
1970 | ||
ace80ab7 | 1971 | move_native_irq(irq); |
1da177e4 LT |
1972 | /* |
1973 | * It appears there is an erratum which affects at least version 0x11 | |
1974 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
1975 | * chipsets). Under certain conditions a level-triggered interrupt is | |
1976 | * erroneously delivered as edge-triggered one but the respective IRR | |
1977 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
1978 | * message but it will never arrive and further interrupts are blocked | |
1979 | * from the source. The exact reason is so far unknown, but the | |
1980 | * phenomenon was observed when two consecutive interrupt requests | |
1981 | * from a given source get delivered to the same CPU and the source is | |
1982 | * temporarily disabled in between. | |
1983 | * | |
1984 | * A workaround is to simulate an EOI message manually. We achieve it | |
1985 | * by setting the trigger mode to edge and then to level when the edge | |
1986 | * trigger mode gets detected in the TMR of a local APIC for a | |
1987 | * level-triggered interrupt. We mask the source for the time of the | |
1988 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
1989 | * The idea is from Manfred Spraul. --macro | |
1990 | */ | |
b940d22d | 1991 | i = irq_vector[irq]; |
1da177e4 LT |
1992 | |
1993 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); | |
1994 | ||
1995 | ack_APIC_irq(); | |
1996 | ||
1997 | if (!(v & (1 << (i & 0x1f)))) { | |
1998 | atomic_inc(&irq_mis_count); | |
1999 | spin_lock(&ioapic_lock); | |
2000 | __mask_and_edge_IO_APIC_irq(irq); | |
2001 | __unmask_and_level_IO_APIC_irq(irq); | |
2002 | spin_unlock(&ioapic_lock); | |
2003 | } | |
2004 | } | |
2005 | ||
ace80ab7 | 2006 | static int ioapic_retrigger_irq(unsigned int irq) |
1da177e4 | 2007 | { |
b940d22d | 2008 | send_IPI_self(irq_vector[irq]); |
c0ad90a3 IM |
2009 | |
2010 | return 1; | |
2011 | } | |
2012 | ||
f5b9ed7a IM |
2013 | static struct irq_chip ioapic_chip __read_mostly = { |
2014 | .name = "IO-APIC", | |
ace80ab7 EB |
2015 | .startup = startup_ioapic_irq, |
2016 | .mask = mask_IO_APIC_irq, | |
2017 | .unmask = unmask_IO_APIC_irq, | |
2018 | .ack = ack_ioapic_irq, | |
2019 | .eoi = ack_ioapic_quirk_irq, | |
54d5d424 | 2020 | #ifdef CONFIG_SMP |
ace80ab7 | 2021 | .set_affinity = set_ioapic_affinity_irq, |
54d5d424 | 2022 | #endif |
ace80ab7 | 2023 | .retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
2024 | }; |
2025 | ||
1da177e4 LT |
2026 | |
2027 | static inline void init_IO_APIC_traps(void) | |
2028 | { | |
2029 | int irq; | |
2030 | ||
2031 | /* | |
2032 | * NOTE! The local APIC isn't very good at handling | |
2033 | * multiple interrupts at the same interrupt level. | |
2034 | * As the interrupt level is determined by taking the | |
2035 | * vector number and shifting that right by 4, we | |
2036 | * want to spread these out a bit so that they don't | |
2037 | * all fall in the same interrupt level. | |
2038 | * | |
2039 | * Also, we've got to be careful not to trash gate | |
2040 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
2041 | */ | |
0799e432 | 2042 | for (irq = 0; irq < nr_irqs ; irq++) { |
addfc66b | 2043 | if (IO_APIC_IRQ(irq) && !irq_vector[irq]) { |
1da177e4 LT |
2044 | /* |
2045 | * Hmm.. We don't have an entry for this, | |
2046 | * so default to an old-fashioned 8259 | |
2047 | * interrupt if we can.. | |
2048 | */ | |
2049 | if (irq < 16) | |
2050 | make_8259A_irq(irq); | |
2051 | else | |
2052 | /* Strange. Oh, well.. */ | |
f5b9ed7a | 2053 | irq_desc[irq].chip = &no_irq_chip; |
1da177e4 LT |
2054 | } |
2055 | } | |
2056 | } | |
2057 | ||
f5b9ed7a IM |
2058 | /* |
2059 | * The local APIC irq-chip implementation: | |
2060 | */ | |
1da177e4 | 2061 | |
c88ac1df | 2062 | static void ack_lapic_irq(unsigned int irq) |
f5b9ed7a IM |
2063 | { |
2064 | ack_APIC_irq(); | |
1da177e4 LT |
2065 | } |
2066 | ||
36062448 | 2067 | static void mask_lapic_irq(unsigned int irq) |
1da177e4 LT |
2068 | { |
2069 | unsigned long v; | |
2070 | ||
2071 | v = apic_read(APIC_LVT0); | |
593f4a78 | 2072 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
2073 | } |
2074 | ||
36062448 | 2075 | static void unmask_lapic_irq(unsigned int irq) |
1da177e4 | 2076 | { |
f5b9ed7a | 2077 | unsigned long v; |
1da177e4 | 2078 | |
f5b9ed7a | 2079 | v = apic_read(APIC_LVT0); |
593f4a78 | 2080 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
f5b9ed7a | 2081 | } |
1da177e4 | 2082 | |
f5b9ed7a | 2083 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 2084 | .name = "local-APIC", |
f5b9ed7a IM |
2085 | .mask = mask_lapic_irq, |
2086 | .unmask = unmask_lapic_irq, | |
c88ac1df | 2087 | .ack = ack_lapic_irq, |
1da177e4 LT |
2088 | }; |
2089 | ||
c88ac1df MR |
2090 | static void lapic_register_intr(int irq, int vector) |
2091 | { | |
2092 | irq_desc[irq].status &= ~IRQ_LEVEL; | |
2093 | set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, | |
2094 | "edge"); | |
2095 | set_intr_gate(vector, interrupt[irq]); | |
2096 | } | |
2097 | ||
e9427101 | 2098 | static void __init setup_nmi(void) |
1da177e4 LT |
2099 | { |
2100 | /* | |
36062448 | 2101 | * Dirty trick to enable the NMI watchdog ... |
1da177e4 LT |
2102 | * We put the 8259A master into AEOI mode and |
2103 | * unmask on all local APICs LVT0 as NMI. | |
2104 | * | |
2105 | * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') | |
2106 | * is from Maciej W. Rozycki - so we do not have to EOI from | |
2107 | * the NMI handler or the timer interrupt. | |
36062448 | 2108 | */ |
1da177e4 LT |
2109 | apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ..."); |
2110 | ||
e9427101 | 2111 | enable_NMI_through_LVT0(); |
1da177e4 LT |
2112 | |
2113 | apic_printk(APIC_VERBOSE, " done.\n"); | |
2114 | } | |
2115 | ||
2116 | /* | |
2117 | * This looks a bit hackish but it's about the only one way of sending | |
2118 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2119 | * not support the ExtINT mode, unfortunately. We need to send these | |
2120 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2121 | * 8259A interrupt line asserted until INTA. --macro | |
2122 | */ | |
28acf285 | 2123 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2124 | { |
fcfd636a | 2125 | int apic, pin, i; |
1da177e4 LT |
2126 | struct IO_APIC_route_entry entry0, entry1; |
2127 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2128 | |
fcfd636a | 2129 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2130 | if (pin == -1) { |
2131 | WARN_ON_ONCE(1); | |
2132 | return; | |
2133 | } | |
fcfd636a | 2134 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2135 | if (apic == -1) { |
2136 | WARN_ON_ONCE(1); | |
1da177e4 | 2137 | return; |
956fb531 | 2138 | } |
1da177e4 | 2139 | |
cf4c6a2f | 2140 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2141 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2142 | |
2143 | memset(&entry1, 0, sizeof(entry1)); | |
2144 | ||
2145 | entry1.dest_mode = 0; /* physical delivery */ | |
2146 | entry1.mask = 0; /* unmask IRQ now */ | |
2147 | entry1.dest.physical.physical_dest = hard_smp_processor_id(); | |
2148 | entry1.delivery_mode = dest_ExtINT; | |
2149 | entry1.polarity = entry0.polarity; | |
2150 | entry1.trigger = 0; | |
2151 | entry1.vector = 0; | |
2152 | ||
cf4c6a2f | 2153 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2154 | |
2155 | save_control = CMOS_READ(RTC_CONTROL); | |
2156 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2157 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2158 | RTC_FREQ_SELECT); | |
2159 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2160 | ||
2161 | i = 100; | |
2162 | while (i-- > 0) { | |
2163 | mdelay(10); | |
2164 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2165 | i -= 10; | |
2166 | } | |
2167 | ||
2168 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2169 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2170 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2171 | |
cf4c6a2f | 2172 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2173 | } |
2174 | ||
2175 | /* | |
2176 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2177 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2178 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2179 | * fanatically on his truly buggy board. | |
2180 | */ | |
8542b200 | 2181 | static inline void __init check_timer(void) |
1da177e4 | 2182 | { |
fcfd636a | 2183 | int apic1, pin1, apic2, pin2; |
691874fa | 2184 | int no_pin1 = 0; |
1da177e4 | 2185 | int vector; |
6e908947 | 2186 | unsigned int ver; |
4aae0702 IM |
2187 | unsigned long flags; |
2188 | ||
2189 | local_irq_save(flags); | |
d4d25dec | 2190 | |
6e908947 IM |
2191 | ver = apic_read(APIC_LVR); |
2192 | ver = GET_APIC_VERSION(ver); | |
2193 | ||
1da177e4 LT |
2194 | /* |
2195 | * get/set the timer IRQ vector: | |
2196 | */ | |
2197 | disable_8259A_irq(0); | |
2198 | vector = assign_irq_vector(0); | |
2199 | set_intr_gate(vector, interrupt[0]); | |
2200 | ||
2201 | /* | |
d11d5794 MR |
2202 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2203 | * wire has to be disabled in the local APIC. Also | |
2204 | * timer interrupts need to be acknowledged manually in | |
2205 | * the 8259A for the i82489DX when using the NMI | |
2206 | * watchdog as that APIC treats NMIs as level-triggered. | |
2207 | * The AEOI mode will finish them in the 8259A | |
2208 | * automatically. | |
1da177e4 | 2209 | */ |
593f4a78 | 2210 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
1da177e4 | 2211 | init_8259A(1); |
d11d5794 | 2212 | timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver)); |
1da177e4 | 2213 | |
fcfd636a EB |
2214 | pin1 = find_isa_irq_pin(0, mp_INT); |
2215 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2216 | pin2 = ioapic_i8259.pin; | |
2217 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2218 | |
49a66a0b MR |
2219 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
2220 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", | |
2221 | vector, apic1, pin1, apic2, pin2); | |
1da177e4 | 2222 | |
691874fa MR |
2223 | /* |
2224 | * Some BIOS writers are clueless and report the ExtINTA | |
2225 | * I/O APIC input from the cascaded 8259A as the timer | |
2226 | * interrupt input. So just in case, if only one pin | |
2227 | * was found above, try it both directly and through the | |
2228 | * 8259A. | |
2229 | */ | |
2230 | if (pin1 == -1) { | |
2231 | pin1 = pin2; | |
2232 | apic1 = apic2; | |
2233 | no_pin1 = 1; | |
2234 | } else if (pin2 == -1) { | |
2235 | pin2 = pin1; | |
2236 | apic2 = apic1; | |
2237 | } | |
2238 | ||
1da177e4 LT |
2239 | if (pin1 != -1) { |
2240 | /* | |
2241 | * Ok, does IRQ0 through the IOAPIC work? | |
2242 | */ | |
691874fa MR |
2243 | if (no_pin1) { |
2244 | add_pin_to_irq(0, apic1, pin1); | |
2245 | setup_timer_IRQ0_pin(apic1, pin1, vector); | |
2246 | } | |
1da177e4 LT |
2247 | unmask_IO_APIC_irq(0); |
2248 | if (timer_irq_works()) { | |
2249 | if (nmi_watchdog == NMI_IO_APIC) { | |
1da177e4 LT |
2250 | setup_nmi(); |
2251 | enable_8259A_irq(0); | |
1da177e4 | 2252 | } |
66759a01 CE |
2253 | if (disable_timer_pin_1 > 0) |
2254 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 2255 | goto out; |
1da177e4 | 2256 | } |
fcfd636a | 2257 | clear_IO_APIC_pin(apic1, pin1); |
691874fa | 2258 | if (!no_pin1) |
49a66a0b MR |
2259 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
2260 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 2261 | |
49a66a0b MR |
2262 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
2263 | "(IRQ0) through the 8259A ...\n"); | |
2264 | apic_printk(APIC_QUIET, KERN_INFO | |
2265 | "..... (found apic %d pin %d) ...\n", apic2, pin2); | |
1da177e4 LT |
2266 | /* |
2267 | * legacy devices should be connected to IO APIC #0 | |
2268 | */ | |
691874fa | 2269 | replace_pin_at_irq(0, apic1, pin1, apic2, pin2); |
f7633ce5 | 2270 | setup_timer_IRQ0_pin(apic2, pin2, vector); |
24742ece | 2271 | unmask_IO_APIC_irq(0); |
ecd29476 | 2272 | enable_8259A_irq(0); |
1da177e4 | 2273 | if (timer_irq_works()) { |
49a66a0b | 2274 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
35542c5e | 2275 | timer_through_8259 = 1; |
1da177e4 | 2276 | if (nmi_watchdog == NMI_IO_APIC) { |
60134ebe | 2277 | disable_8259A_irq(0); |
1da177e4 | 2278 | setup_nmi(); |
60134ebe | 2279 | enable_8259A_irq(0); |
1da177e4 | 2280 | } |
4aae0702 | 2281 | goto out; |
1da177e4 LT |
2282 | } |
2283 | /* | |
2284 | * Cleanup, just in case ... | |
2285 | */ | |
ecd29476 | 2286 | disable_8259A_irq(0); |
fcfd636a | 2287 | clear_IO_APIC_pin(apic2, pin2); |
49a66a0b | 2288 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
1da177e4 | 2289 | } |
1da177e4 LT |
2290 | |
2291 | if (nmi_watchdog == NMI_IO_APIC) { | |
49a66a0b MR |
2292 | apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work " |
2293 | "through the IO-APIC - disabling NMI Watchdog!\n"); | |
067fa0ff | 2294 | nmi_watchdog = NMI_NONE; |
1da177e4 | 2295 | } |
d11d5794 | 2296 | timer_ack = 0; |
1da177e4 | 2297 | |
49a66a0b MR |
2298 | apic_printk(APIC_QUIET, KERN_INFO |
2299 | "...trying to set up timer as Virtual Wire IRQ...\n"); | |
1da177e4 | 2300 | |
c88ac1df | 2301 | lapic_register_intr(0, vector); |
593f4a78 | 2302 | apic_write(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */ |
1da177e4 LT |
2303 | enable_8259A_irq(0); |
2304 | ||
2305 | if (timer_irq_works()) { | |
49a66a0b | 2306 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2307 | goto out; |
1da177e4 | 2308 | } |
e67465f1 | 2309 | disable_8259A_irq(0); |
593f4a78 | 2310 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector); |
49a66a0b | 2311 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
1da177e4 | 2312 | |
49a66a0b MR |
2313 | apic_printk(APIC_QUIET, KERN_INFO |
2314 | "...trying to set up timer as ExtINT IRQ...\n"); | |
1da177e4 | 2315 | |
1da177e4 LT |
2316 | init_8259A(0); |
2317 | make_8259A_irq(0); | |
593f4a78 | 2318 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
2319 | |
2320 | unlock_ExtINT_logic(); | |
2321 | ||
2322 | if (timer_irq_works()) { | |
49a66a0b | 2323 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2324 | goto out; |
1da177e4 | 2325 | } |
49a66a0b | 2326 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
1da177e4 | 2327 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
49a66a0b | 2328 | "report. Then try booting with the 'noapic' option.\n"); |
4aae0702 IM |
2329 | out: |
2330 | local_irq_restore(flags); | |
1da177e4 LT |
2331 | } |
2332 | ||
2333 | /* | |
af174783 MR |
2334 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
2335 | * to devices. However there may be an I/O APIC pin available for | |
2336 | * this interrupt regardless. The pin may be left unconnected, but | |
2337 | * typically it will be reused as an ExtINT cascade interrupt for | |
2338 | * the master 8259A. In the MPS case such a pin will normally be | |
2339 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
2340 | * there is no provision for ExtINT interrupts, and in the absence | |
2341 | * of an override it would be treated as an ordinary ISA I/O APIC | |
2342 | * interrupt, that is edge-triggered and unmasked by default. We | |
2343 | * used to do this, but it caused problems on some systems because | |
2344 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
2345 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
2346 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
2347 | * the I/O APIC in all cases now. No actual device should request | |
2348 | * it anyway. --macro | |
1da177e4 LT |
2349 | */ |
2350 | #define PIC_IRQS (1 << PIC_CASCADE_IR) | |
2351 | ||
2352 | void __init setup_IO_APIC(void) | |
2353 | { | |
dbeb2be2 RR |
2354 | int i; |
2355 | ||
2356 | /* Reserve all the system vectors. */ | |
305b92a2 | 2357 | for (i = first_system_vector; i < NR_VECTORS; i++) |
dbeb2be2 RR |
2358 | set_bit(i, used_vectors); |
2359 | ||
1da177e4 LT |
2360 | enable_IO_APIC(); |
2361 | ||
af174783 | 2362 | io_apic_irqs = ~PIC_IRQS; |
1da177e4 LT |
2363 | |
2364 | printk("ENABLING IO-APIC IRQs\n"); | |
2365 | ||
2366 | /* | |
2367 | * Set up IO-APIC IRQ routing. | |
2368 | */ | |
2369 | if (!acpi_ioapic) | |
2370 | setup_ioapic_ids_from_mpc(); | |
2371 | sync_Arb_IDs(); | |
2372 | setup_IO_APIC_irqs(); | |
2373 | init_IO_APIC_traps(); | |
1e4c85f9 | 2374 | check_timer(); |
1da177e4 LT |
2375 | } |
2376 | ||
2377 | /* | |
2378 | * Called after all the initialization is done. If we didnt find any | |
2379 | * APIC bugs then we can allow the modify fast path | |
2380 | */ | |
36062448 | 2381 | |
1da177e4 LT |
2382 | static int __init io_apic_bug_finalize(void) |
2383 | { | |
36062448 | 2384 | if (sis_apic_bug == -1) |
1da177e4 LT |
2385 | sis_apic_bug = 0; |
2386 | return 0; | |
2387 | } | |
2388 | ||
2389 | late_initcall(io_apic_bug_finalize); | |
2390 | ||
2391 | struct sysfs_ioapic_data { | |
2392 | struct sys_device dev; | |
2393 | struct IO_APIC_route_entry entry[0]; | |
2394 | }; | |
36062448 | 2395 | static struct sysfs_ioapic_data *mp_ioapic_data[MAX_IO_APICS]; |
1da177e4 | 2396 | |
438510f6 | 2397 | static int ioapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
2398 | { |
2399 | struct IO_APIC_route_entry *entry; | |
2400 | struct sysfs_ioapic_data *data; | |
1da177e4 | 2401 | int i; |
36062448 | 2402 | |
1da177e4 LT |
2403 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
2404 | entry = data->entry; | |
36062448 | 2405 | for (i = 0; i < nr_ioapic_registers[dev->id]; i++) |
cf4c6a2f | 2406 | entry[i] = ioapic_read_entry(dev->id, i); |
1da177e4 LT |
2407 | |
2408 | return 0; | |
2409 | } | |
2410 | ||
2411 | static int ioapic_resume(struct sys_device *dev) | |
2412 | { | |
2413 | struct IO_APIC_route_entry *entry; | |
2414 | struct sysfs_ioapic_data *data; | |
2415 | unsigned long flags; | |
2416 | union IO_APIC_reg_00 reg_00; | |
2417 | int i; | |
36062448 | 2418 | |
1da177e4 LT |
2419 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
2420 | entry = data->entry; | |
2421 | ||
2422 | spin_lock_irqsave(&ioapic_lock, flags); | |
2423 | reg_00.raw = io_apic_read(dev->id, 0); | |
ec2cd0a2 AS |
2424 | if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) { |
2425 | reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid; | |
1da177e4 LT |
2426 | io_apic_write(dev->id, 0, reg_00.raw); |
2427 | } | |
1da177e4 | 2428 | spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 2429 | for (i = 0; i < nr_ioapic_registers[dev->id]; i++) |
cf4c6a2f | 2430 | ioapic_write_entry(dev->id, i, entry[i]); |
1da177e4 LT |
2431 | |
2432 | return 0; | |
2433 | } | |
2434 | ||
2435 | static struct sysdev_class ioapic_sysdev_class = { | |
af5ca3f4 | 2436 | .name = "ioapic", |
1da177e4 LT |
2437 | .suspend = ioapic_suspend, |
2438 | .resume = ioapic_resume, | |
2439 | }; | |
2440 | ||
2441 | static int __init ioapic_init_sysfs(void) | |
2442 | { | |
36062448 | 2443 | struct sys_device *dev; |
1da177e4 LT |
2444 | int i, size, error = 0; |
2445 | ||
2446 | error = sysdev_class_register(&ioapic_sysdev_class); | |
2447 | if (error) | |
2448 | return error; | |
2449 | ||
36062448 PC |
2450 | for (i = 0; i < nr_ioapics; i++) { |
2451 | size = sizeof(struct sys_device) + nr_ioapic_registers[i] | |
1da177e4 | 2452 | * sizeof(struct IO_APIC_route_entry); |
25556c16 | 2453 | mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL); |
1da177e4 LT |
2454 | if (!mp_ioapic_data[i]) { |
2455 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
2456 | continue; | |
2457 | } | |
1da177e4 | 2458 | dev = &mp_ioapic_data[i]->dev; |
36062448 | 2459 | dev->id = i; |
1da177e4 LT |
2460 | dev->cls = &ioapic_sysdev_class; |
2461 | error = sysdev_register(dev); | |
2462 | if (error) { | |
2463 | kfree(mp_ioapic_data[i]); | |
2464 | mp_ioapic_data[i] = NULL; | |
2465 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
2466 | continue; | |
2467 | } | |
2468 | } | |
2469 | ||
2470 | return 0; | |
2471 | } | |
2472 | ||
2473 | device_initcall(ioapic_init_sysfs); | |
2474 | ||
3fc471ed | 2475 | /* |
95d77884 | 2476 | * Dynamic irq allocate and deallocation |
3fc471ed EB |
2477 | */ |
2478 | int create_irq(void) | |
2479 | { | |
ace80ab7 | 2480 | /* Allocate an unused irq */ |
306a22c2 | 2481 | int irq, new, vector = 0; |
3fc471ed | 2482 | unsigned long flags; |
3fc471ed | 2483 | |
ace80ab7 EB |
2484 | irq = -ENOSPC; |
2485 | spin_lock_irqsave(&vector_lock, flags); | |
0799e432 | 2486 | for (new = (nr_irqs - 1); new >= 0; new--) { |
ace80ab7 EB |
2487 | if (platform_legacy_irq(new)) |
2488 | continue; | |
2489 | if (irq_vector[new] != 0) | |
2490 | continue; | |
2491 | vector = __assign_irq_vector(new); | |
2492 | if (likely(vector > 0)) | |
2493 | irq = new; | |
2494 | break; | |
2495 | } | |
2496 | spin_unlock_irqrestore(&vector_lock, flags); | |
3fc471ed | 2497 | |
ace80ab7 | 2498 | if (irq >= 0) { |
3fc471ed | 2499 | set_intr_gate(vector, interrupt[irq]); |
3fc471ed EB |
2500 | dynamic_irq_init(irq); |
2501 | } | |
2502 | return irq; | |
2503 | } | |
2504 | ||
2505 | void destroy_irq(unsigned int irq) | |
2506 | { | |
2507 | unsigned long flags; | |
3fc471ed EB |
2508 | |
2509 | dynamic_irq_cleanup(irq); | |
2510 | ||
2511 | spin_lock_irqsave(&vector_lock, flags); | |
9d9ad4b5 | 2512 | clear_bit(irq_vector[irq], used_vectors); |
3fc471ed EB |
2513 | irq_vector[irq] = 0; |
2514 | spin_unlock_irqrestore(&vector_lock, flags); | |
2515 | } | |
3fc471ed | 2516 | |
2d3fcc1c | 2517 | /* |
27b46d76 | 2518 | * MSI message composition |
2d3fcc1c EB |
2519 | */ |
2520 | #ifdef CONFIG_PCI_MSI | |
3b7d1921 | 2521 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg) |
2d3fcc1c | 2522 | { |
2d3fcc1c EB |
2523 | int vector; |
2524 | unsigned dest; | |
2525 | ||
2526 | vector = assign_irq_vector(irq); | |
2527 | if (vector >= 0) { | |
2528 | dest = cpu_mask_to_apicid(TARGET_CPUS); | |
2529 | ||
2530 | msg->address_hi = MSI_ADDR_BASE_HI; | |
2531 | msg->address_lo = | |
2532 | MSI_ADDR_BASE_LO | | |
2533 | ((INT_DEST_MODE == 0) ? | |
36062448 | 2534 | MSI_ADDR_DEST_MODE_PHYSICAL: |
2d3fcc1c EB |
2535 | MSI_ADDR_DEST_MODE_LOGICAL) | |
2536 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
2537 | MSI_ADDR_REDIRECTION_CPU: | |
2538 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
2539 | MSI_ADDR_DEST_ID(dest); | |
2540 | ||
2541 | msg->data = | |
2542 | MSI_DATA_TRIGGER_EDGE | | |
2543 | MSI_DATA_LEVEL_ASSERT | | |
2544 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
36062448 | 2545 | MSI_DATA_DELIVERY_FIXED: |
2d3fcc1c EB |
2546 | MSI_DATA_DELIVERY_LOWPRI) | |
2547 | MSI_DATA_VECTOR(vector); | |
2548 | } | |
2549 | return vector; | |
2550 | } | |
2551 | ||
3b7d1921 EB |
2552 | #ifdef CONFIG_SMP |
2553 | static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask) | |
2d3fcc1c | 2554 | { |
3b7d1921 EB |
2555 | struct msi_msg msg; |
2556 | unsigned int dest; | |
2557 | cpumask_t tmp; | |
2d3fcc1c | 2558 | int vector; |
3b7d1921 EB |
2559 | |
2560 | cpus_and(tmp, mask, cpu_online_map); | |
2561 | if (cpus_empty(tmp)) | |
2562 | tmp = TARGET_CPUS; | |
2d3fcc1c EB |
2563 | |
2564 | vector = assign_irq_vector(irq); | |
3b7d1921 EB |
2565 | if (vector < 0) |
2566 | return; | |
2d3fcc1c | 2567 | |
3b7d1921 EB |
2568 | dest = cpu_mask_to_apicid(mask); |
2569 | ||
2570 | read_msi_msg(irq, &msg); | |
2571 | ||
2572 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
2573 | msg.data |= MSI_DATA_VECTOR(vector); | |
2574 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
2575 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
2576 | ||
2577 | write_msi_msg(irq, &msg); | |
9f0a5ba5 | 2578 | irq_desc[irq].affinity = mask; |
2d3fcc1c | 2579 | } |
3b7d1921 | 2580 | #endif /* CONFIG_SMP */ |
2d3fcc1c | 2581 | |
3b7d1921 EB |
2582 | /* |
2583 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
2584 | * which implement the MSI or MSI-X Capability Structure. | |
2585 | */ | |
2586 | static struct irq_chip msi_chip = { | |
2587 | .name = "PCI-MSI", | |
2588 | .unmask = unmask_msi_irq, | |
2589 | .mask = mask_msi_irq, | |
2590 | .ack = ack_ioapic_irq, | |
2591 | #ifdef CONFIG_SMP | |
2592 | .set_affinity = set_msi_irq_affinity, | |
2593 | #endif | |
2594 | .retrigger = ioapic_retrigger_irq, | |
2d3fcc1c EB |
2595 | }; |
2596 | ||
f7feaca7 | 2597 | int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) |
3b7d1921 EB |
2598 | { |
2599 | struct msi_msg msg; | |
f7feaca7 EB |
2600 | int irq, ret; |
2601 | irq = create_irq(); | |
2602 | if (irq < 0) | |
2603 | return irq; | |
2604 | ||
3b7d1921 | 2605 | ret = msi_compose_msg(dev, irq, &msg); |
f7feaca7 EB |
2606 | if (ret < 0) { |
2607 | destroy_irq(irq); | |
3b7d1921 | 2608 | return ret; |
f7feaca7 | 2609 | } |
3b7d1921 | 2610 | |
7fe3730d | 2611 | set_irq_msi(irq, desc); |
3b7d1921 EB |
2612 | write_msi_msg(irq, &msg); |
2613 | ||
a460e745 IM |
2614 | set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, |
2615 | "edge"); | |
3b7d1921 | 2616 | |
7fe3730d | 2617 | return 0; |
3b7d1921 EB |
2618 | } |
2619 | ||
2620 | void arch_teardown_msi_irq(unsigned int irq) | |
2621 | { | |
f7feaca7 | 2622 | destroy_irq(irq); |
3b7d1921 EB |
2623 | } |
2624 | ||
2d3fcc1c EB |
2625 | #endif /* CONFIG_PCI_MSI */ |
2626 | ||
8b955b0d EB |
2627 | /* |
2628 | * Hypertransport interrupt support | |
2629 | */ | |
2630 | #ifdef CONFIG_HT_IRQ | |
2631 | ||
2632 | #ifdef CONFIG_SMP | |
2633 | ||
2634 | static void target_ht_irq(unsigned int irq, unsigned int dest) | |
2635 | { | |
ec68307c EB |
2636 | struct ht_irq_msg msg; |
2637 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 2638 | |
ec68307c EB |
2639 | msg.address_lo &= ~(HT_IRQ_LOW_DEST_ID_MASK); |
2640 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); | |
8b955b0d | 2641 | |
ec68307c EB |
2642 | msg.address_lo |= HT_IRQ_LOW_DEST_ID(dest); |
2643 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); | |
8b955b0d | 2644 | |
ec68307c | 2645 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
2646 | } |
2647 | ||
2648 | static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask) | |
2649 | { | |
2650 | unsigned int dest; | |
2651 | cpumask_t tmp; | |
2652 | ||
2653 | cpus_and(tmp, mask, cpu_online_map); | |
2654 | if (cpus_empty(tmp)) | |
2655 | tmp = TARGET_CPUS; | |
2656 | ||
2657 | cpus_and(mask, tmp, CPU_MASK_ALL); | |
2658 | ||
2659 | dest = cpu_mask_to_apicid(mask); | |
2660 | ||
2661 | target_ht_irq(irq, dest); | |
9f0a5ba5 | 2662 | irq_desc[irq].affinity = mask; |
8b955b0d EB |
2663 | } |
2664 | #endif | |
2665 | ||
c37e108d | 2666 | static struct irq_chip ht_irq_chip = { |
8b955b0d EB |
2667 | .name = "PCI-HT", |
2668 | .mask = mask_ht_irq, | |
2669 | .unmask = unmask_ht_irq, | |
2670 | .ack = ack_ioapic_irq, | |
2671 | #ifdef CONFIG_SMP | |
2672 | .set_affinity = set_ht_irq_affinity, | |
2673 | #endif | |
2674 | .retrigger = ioapic_retrigger_irq, | |
2675 | }; | |
2676 | ||
2677 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
2678 | { | |
2679 | int vector; | |
2680 | ||
2681 | vector = assign_irq_vector(irq); | |
2682 | if (vector >= 0) { | |
ec68307c | 2683 | struct ht_irq_msg msg; |
8b955b0d EB |
2684 | unsigned dest; |
2685 | cpumask_t tmp; | |
2686 | ||
2687 | cpus_clear(tmp); | |
2688 | cpu_set(vector >> 8, tmp); | |
2689 | dest = cpu_mask_to_apicid(tmp); | |
2690 | ||
ec68307c | 2691 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 2692 | |
ec68307c EB |
2693 | msg.address_lo = |
2694 | HT_IRQ_LOW_BASE | | |
8b955b0d EB |
2695 | HT_IRQ_LOW_DEST_ID(dest) | |
2696 | HT_IRQ_LOW_VECTOR(vector) | | |
2697 | ((INT_DEST_MODE == 0) ? | |
2698 | HT_IRQ_LOW_DM_PHYSICAL : | |
2699 | HT_IRQ_LOW_DM_LOGICAL) | | |
2700 | HT_IRQ_LOW_RQEOI_EDGE | | |
2701 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
2702 | HT_IRQ_LOW_MT_FIXED : | |
2703 | HT_IRQ_LOW_MT_ARBITRATED) | | |
2704 | HT_IRQ_LOW_IRQ_MASKED; | |
2705 | ||
ec68307c | 2706 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 2707 | |
a460e745 IM |
2708 | set_irq_chip_and_handler_name(irq, &ht_irq_chip, |
2709 | handle_edge_irq, "edge"); | |
8b955b0d EB |
2710 | } |
2711 | return vector; | |
2712 | } | |
2713 | #endif /* CONFIG_HT_IRQ */ | |
2714 | ||
1da177e4 | 2715 | /* -------------------------------------------------------------------------- |
36062448 | 2716 | ACPI-based IOAPIC Configuration |
1da177e4 LT |
2717 | -------------------------------------------------------------------------- */ |
2718 | ||
888ba6c6 | 2719 | #ifdef CONFIG_ACPI |
1da177e4 | 2720 | |
36062448 | 2721 | int __init io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
2722 | { |
2723 | union IO_APIC_reg_00 reg_00; | |
2724 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
2725 | physid_mask_t tmp; | |
2726 | unsigned long flags; | |
2727 | int i = 0; | |
2728 | ||
2729 | /* | |
36062448 PC |
2730 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
2731 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 2732 | * supports up to 16 on one shared APIC bus. |
36062448 | 2733 | * |
1da177e4 LT |
2734 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
2735 | * advantage of new APIC bus architecture. | |
2736 | */ | |
2737 | ||
2738 | if (physids_empty(apic_id_map)) | |
2739 | apic_id_map = ioapic_phys_id_map(phys_cpu_present_map); | |
2740 | ||
2741 | spin_lock_irqsave(&ioapic_lock, flags); | |
2742 | reg_00.raw = io_apic_read(ioapic, 0); | |
2743 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2744 | ||
2745 | if (apic_id >= get_physical_broadcast()) { | |
2746 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
2747 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
2748 | apic_id = reg_00.bits.ID; | |
2749 | } | |
2750 | ||
2751 | /* | |
36062448 | 2752 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
2753 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
2754 | */ | |
2755 | if (check_apicid_used(apic_id_map, apic_id)) { | |
2756 | ||
2757 | for (i = 0; i < get_physical_broadcast(); i++) { | |
2758 | if (!check_apicid_used(apic_id_map, i)) | |
2759 | break; | |
2760 | } | |
2761 | ||
2762 | if (i == get_physical_broadcast()) | |
2763 | panic("Max apic_id exceeded!\n"); | |
2764 | ||
2765 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
2766 | "trying %d\n", ioapic, apic_id, i); | |
2767 | ||
2768 | apic_id = i; | |
36062448 | 2769 | } |
1da177e4 LT |
2770 | |
2771 | tmp = apicid_to_cpu_present(apic_id); | |
2772 | physids_or(apic_id_map, apic_id_map, tmp); | |
2773 | ||
2774 | if (reg_00.bits.ID != apic_id) { | |
2775 | reg_00.bits.ID = apic_id; | |
2776 | ||
2777 | spin_lock_irqsave(&ioapic_lock, flags); | |
2778 | io_apic_write(ioapic, 0, reg_00.raw); | |
2779 | reg_00.raw = io_apic_read(ioapic, 0); | |
2780 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2781 | ||
2782 | /* Sanity check */ | |
6070f9ec AD |
2783 | if (reg_00.bits.ID != apic_id) { |
2784 | printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); | |
2785 | return -1; | |
2786 | } | |
1da177e4 LT |
2787 | } |
2788 | ||
2789 | apic_printk(APIC_VERBOSE, KERN_INFO | |
2790 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
2791 | ||
2792 | return apic_id; | |
2793 | } | |
2794 | ||
2795 | ||
36062448 | 2796 | int __init io_apic_get_version(int ioapic) |
1da177e4 LT |
2797 | { |
2798 | union IO_APIC_reg_01 reg_01; | |
2799 | unsigned long flags; | |
2800 | ||
2801 | spin_lock_irqsave(&ioapic_lock, flags); | |
2802 | reg_01.raw = io_apic_read(ioapic, 1); | |
2803 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2804 | ||
2805 | return reg_01.bits.version; | |
2806 | } | |
2807 | ||
2808 | ||
36062448 | 2809 | int __init io_apic_get_redir_entries(int ioapic) |
1da177e4 LT |
2810 | { |
2811 | union IO_APIC_reg_01 reg_01; | |
2812 | unsigned long flags; | |
2813 | ||
2814 | spin_lock_irqsave(&ioapic_lock, flags); | |
2815 | reg_01.raw = io_apic_read(ioapic, 1); | |
2816 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2817 | ||
2818 | return reg_01.bits.entries; | |
2819 | } | |
2820 | ||
2821 | ||
36062448 | 2822 | int io_apic_set_pci_routing(int ioapic, int pin, int irq, int edge_level, int active_high_low) |
1da177e4 LT |
2823 | { |
2824 | struct IO_APIC_route_entry entry; | |
1da177e4 LT |
2825 | |
2826 | if (!IO_APIC_IRQ(irq)) { | |
2827 | printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", | |
2828 | ioapic); | |
2829 | return -EINVAL; | |
2830 | } | |
2831 | ||
2832 | /* | |
2833 | * Generate a PCI IRQ routing entry and program the IOAPIC accordingly. | |
2834 | * Note that we mask (disable) IRQs now -- these get enabled when the | |
2835 | * corresponding device driver registers for this IRQ. | |
2836 | */ | |
2837 | ||
36062448 | 2838 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
2839 | |
2840 | entry.delivery_mode = INT_DELIVERY_MODE; | |
2841 | entry.dest_mode = INT_DEST_MODE; | |
2842 | entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS); | |
2843 | entry.trigger = edge_level; | |
2844 | entry.polarity = active_high_low; | |
2845 | entry.mask = 1; | |
2846 | ||
2847 | /* | |
2848 | * IRQs < 16 are already in the irq_2_pin[] map | |
2849 | */ | |
2850 | if (irq >= 16) | |
2851 | add_pin_to_irq(irq, ioapic, pin); | |
2852 | ||
2853 | entry.vector = assign_irq_vector(irq); | |
2854 | ||
2855 | apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry " | |
2856 | "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic, | |
ec2cd0a2 | 2857 | mp_ioapics[ioapic].mp_apicid, pin, entry.vector, irq, |
1da177e4 LT |
2858 | edge_level, active_high_low); |
2859 | ||
2860 | ioapic_register_intr(irq, entry.vector, edge_level); | |
2861 | ||
2862 | if (!ioapic && (irq < 16)) | |
2863 | disable_8259A_irq(irq); | |
2864 | ||
a2249cba | 2865 | ioapic_write_entry(ioapic, pin, entry); |
1da177e4 LT |
2866 | |
2867 | return 0; | |
2868 | } | |
2869 | ||
61fd47e0 SL |
2870 | int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity) |
2871 | { | |
2872 | int i; | |
2873 | ||
2874 | if (skip_ioapic_setup) | |
2875 | return -1; | |
2876 | ||
2877 | for (i = 0; i < mp_irq_entries; i++) | |
2fddb6e2 AS |
2878 | if (mp_irqs[i].mp_irqtype == mp_INT && |
2879 | mp_irqs[i].mp_srcbusirq == bus_irq) | |
61fd47e0 SL |
2880 | break; |
2881 | if (i >= mp_irq_entries) | |
2882 | return -1; | |
2883 | ||
2884 | *trigger = irq_trigger(i); | |
2885 | *polarity = irq_polarity(i); | |
2886 | return 0; | |
2887 | } | |
2888 | ||
888ba6c6 | 2889 | #endif /* CONFIG_ACPI */ |
1a3f239d RR |
2890 | |
2891 | static int __init parse_disable_timer_pin_1(char *arg) | |
2892 | { | |
2893 | disable_timer_pin_1 = 1; | |
2894 | return 0; | |
2895 | } | |
2896 | early_param("disable_timer_pin_1", parse_disable_timer_pin_1); | |
2897 | ||
2898 | static int __init parse_enable_timer_pin_1(char *arg) | |
2899 | { | |
2900 | disable_timer_pin_1 = -1; | |
2901 | return 0; | |
2902 | } | |
2903 | early_param("enable_timer_pin_1", parse_enable_timer_pin_1); | |
2904 | ||
2905 | static int __init parse_noapic(char *arg) | |
2906 | { | |
2907 | /* disable IO-APIC */ | |
2908 | disable_ioapic_setup(); | |
2909 | return 0; | |
2910 | } | |
2911 | early_param("noapic", parse_noapic); | |
f3294a33 YL |
2912 | |
2913 | void __init ioapic_init_mappings(void) | |
2914 | { | |
2915 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
2916 | int i; | |
2917 | ||
2918 | for (i = 0; i < nr_ioapics; i++) { | |
2919 | if (smp_found_config) { | |
2920 | ioapic_phys = mp_ioapics[i].mp_apicaddr; | |
2921 | if (!ioapic_phys) { | |
2922 | printk(KERN_ERR | |
2923 | "WARNING: bogus zero IO-APIC " | |
2924 | "address found in MPTABLE, " | |
2925 | "disabling IO/APIC support!\n"); | |
2926 | smp_found_config = 0; | |
2927 | skip_ioapic_setup = 1; | |
2928 | goto fake_ioapic_page; | |
2929 | } | |
2930 | } else { | |
2931 | fake_ioapic_page: | |
2932 | ioapic_phys = (unsigned long) | |
2933 | alloc_bootmem_pages(PAGE_SIZE); | |
2934 | ioapic_phys = __pa(ioapic_phys); | |
2935 | } | |
2936 | set_fixmap_nocache(idx, ioapic_phys); | |
2937 | printk(KERN_DEBUG "mapped IOAPIC to %08lx (%08lx)\n", | |
2938 | __fix_to_virt(idx), ioapic_phys); | |
2939 | idx++; | |
2940 | } | |
2941 | } | |
2942 |