Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
4 | * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo | |
5 | * | |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
f3294a33 | 28 | #include <linux/bootmem.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
1da177e4 | 33 | #include <linux/sysdev.h> |
2d3fcc1c | 34 | #include <linux/pci.h> |
3b7d1921 | 35 | #include <linux/msi.h> |
95d77884 | 36 | #include <linux/htirq.h> |
7dfb7103 | 37 | #include <linux/freezer.h> |
f26d6a2b | 38 | #include <linux/kthread.h> |
1d16b53e | 39 | #include <linux/jiffies.h> /* time_after() */ |
54d5d424 | 40 | |
1da177e4 LT |
41 | #include <asm/io.h> |
42 | #include <asm/smp.h> | |
43 | #include <asm/desc.h> | |
44 | #include <asm/timer.h> | |
306e440d | 45 | #include <asm/i8259.h> |
3e4ff115 | 46 | #include <asm/nmi.h> |
2d3fcc1c | 47 | #include <asm/msidef.h> |
8b955b0d | 48 | #include <asm/hypertransport.h> |
a4dbc34d | 49 | #include <asm/setup.h> |
1da177e4 LT |
50 | |
51 | #include <mach_apic.h> | |
874c4fe3 | 52 | #include <mach_apicdef.h> |
1da177e4 | 53 | |
32f71aff MR |
54 | #define __apicdebuginit(type) static type __init |
55 | ||
1da177e4 LT |
56 | int (*ioapic_renumber_irq)(int ioapic, int irq); |
57 | atomic_t irq_mis_count; | |
58 | ||
fcfd636a EB |
59 | /* Where if anywhere is the i8259 connect in external int mode */ |
60 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
61 | ||
1da177e4 | 62 | static DEFINE_SPINLOCK(ioapic_lock); |
d388e5fd | 63 | DEFINE_SPINLOCK(vector_lock); |
1da177e4 | 64 | |
35542c5e | 65 | int timer_through_8259 __initdata; |
f9262c12 | 66 | |
1da177e4 LT |
67 | /* |
68 | * Is the SiS APIC rmw bug present ? | |
69 | * -1 = don't know, 0 = no, 1 = yes | |
70 | */ | |
71 | int sis_apic_bug = -1; | |
72 | ||
301e6190 | 73 | int first_free_entry; |
1da177e4 LT |
74 | /* |
75 | * # of IRQ routing registers | |
76 | */ | |
77 | int nr_ioapic_registers[MAX_IO_APICS]; | |
78 | ||
9f640ccb | 79 | /* I/O APIC entries */ |
ec2cd0a2 | 80 | struct mp_config_ioapic mp_ioapics[MAX_IO_APICS]; |
9f640ccb AS |
81 | int nr_ioapics; |
82 | ||
584f734d | 83 | /* MP IRQ source entries */ |
2fddb6e2 | 84 | struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
85 | |
86 | /* # of MP IRQ source entries */ | |
87 | int mp_irq_entries; | |
88 | ||
8732fc4b AS |
89 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
90 | int mp_bus_id_to_type[MAX_MP_BUSSES]; | |
91 | #endif | |
92 | ||
93 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
94 | ||
1a3f239d | 95 | static int disable_timer_pin_1 __initdata; |
66759a01 | 96 | |
1da177e4 LT |
97 | /* |
98 | * Rough estimation of how many shared IRQs there are, can | |
99 | * be changed anytime. | |
100 | */ | |
301e6190 | 101 | int pin_map_size; |
0799e432 | 102 | |
1da177e4 LT |
103 | /* |
104 | * This is performance-critical, we want to do it O(1) | |
105 | * | |
106 | * the indexing order of this array favors 1:1 mappings | |
107 | * between pins and IRQs. | |
108 | */ | |
109 | ||
110 | static struct irq_pin_list { | |
111 | int apic, pin, next; | |
301e6190 YL |
112 | } *irq_2_pin; |
113 | ||
114 | DEFINE_DYN_ARRAY(irq_2_pin, sizeof(struct irq_pin_list), pin_map_size, 16, NULL); | |
1da177e4 | 115 | |
130fe05d LT |
116 | struct io_apic { |
117 | unsigned int index; | |
118 | unsigned int unused[3]; | |
119 | unsigned int data; | |
120 | }; | |
121 | ||
122 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
123 | { | |
124 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
ec2cd0a2 | 125 | + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK); |
130fe05d LT |
126 | } |
127 | ||
128 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) | |
129 | { | |
130 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
131 | writel(reg, &io_apic->index); | |
132 | return readl(&io_apic->data); | |
133 | } | |
134 | ||
135 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) | |
136 | { | |
137 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
138 | writel(reg, &io_apic->index); | |
139 | writel(value, &io_apic->data); | |
140 | } | |
141 | ||
142 | /* | |
143 | * Re-write a value: to be used for read-modify-write | |
144 | * cycles where the read already set up the index register. | |
145 | * | |
146 | * Older SiS APIC requires we rewrite the index register | |
147 | */ | |
148 | static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) | |
149 | { | |
cb468984 | 150 | volatile struct io_apic __iomem *io_apic = io_apic_base(apic); |
130fe05d LT |
151 | if (sis_apic_bug) |
152 | writel(reg, &io_apic->index); | |
153 | writel(value, &io_apic->data); | |
154 | } | |
155 | ||
cf4c6a2f AK |
156 | union entry_union { |
157 | struct { u32 w1, w2; }; | |
158 | struct IO_APIC_route_entry entry; | |
159 | }; | |
160 | ||
161 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) | |
162 | { | |
163 | union entry_union eu; | |
164 | unsigned long flags; | |
165 | spin_lock_irqsave(&ioapic_lock, flags); | |
166 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); | |
167 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
168 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
169 | return eu.entry; | |
170 | } | |
171 | ||
f9dadfa7 LT |
172 | /* |
173 | * When we write a new IO APIC routing entry, we need to write the high | |
174 | * word first! If the mask bit in the low word is clear, we will enable | |
175 | * the interrupt, and we need to make sure the entry is fully populated | |
176 | * before that happens. | |
177 | */ | |
d15512f4 AK |
178 | static void |
179 | __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
cf4c6a2f | 180 | { |
cf4c6a2f AK |
181 | union entry_union eu; |
182 | eu.entry = e; | |
f9dadfa7 LT |
183 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
184 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
185 | } |
186 | ||
187 | static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
188 | { | |
189 | unsigned long flags; | |
190 | spin_lock_irqsave(&ioapic_lock, flags); | |
191 | __ioapic_write_entry(apic, pin, e); | |
f9dadfa7 LT |
192 | spin_unlock_irqrestore(&ioapic_lock, flags); |
193 | } | |
194 | ||
195 | /* | |
196 | * When we mask an IO APIC routing entry, we need to write the low | |
197 | * word first, in order to set the mask bit before we change the | |
198 | * high bits! | |
199 | */ | |
200 | static void ioapic_mask_entry(int apic, int pin) | |
201 | { | |
202 | unsigned long flags; | |
203 | union entry_union eu = { .entry.mask = 1 }; | |
204 | ||
cf4c6a2f AK |
205 | spin_lock_irqsave(&ioapic_lock, flags); |
206 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
207 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
208 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
209 | } | |
210 | ||
1da177e4 LT |
211 | /* |
212 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
213 | * shared ISA-space IRQs, so we have to support them. We are super | |
214 | * fast in the common case, and fast for shared ISA-space IRQs. | |
215 | */ | |
216 | static void add_pin_to_irq(unsigned int irq, int apic, int pin) | |
217 | { | |
1da177e4 LT |
218 | struct irq_pin_list *entry = irq_2_pin + irq; |
219 | ||
220 | while (entry->next) | |
221 | entry = irq_2_pin + entry->next; | |
222 | ||
223 | if (entry->pin != -1) { | |
224 | entry->next = first_free_entry; | |
225 | entry = irq_2_pin + entry->next; | |
0799e432 | 226 | if (++first_free_entry >= pin_map_size) |
1da177e4 LT |
227 | panic("io_apic.c: whoops"); |
228 | } | |
229 | entry->apic = apic; | |
230 | entry->pin = pin; | |
231 | } | |
232 | ||
233 | /* | |
234 | * Reroute an IRQ to a different pin. | |
235 | */ | |
236 | static void __init replace_pin_at_irq(unsigned int irq, | |
237 | int oldapic, int oldpin, | |
238 | int newapic, int newpin) | |
239 | { | |
240 | struct irq_pin_list *entry = irq_2_pin + irq; | |
241 | ||
242 | while (1) { | |
243 | if (entry->apic == oldapic && entry->pin == oldpin) { | |
244 | entry->apic = newapic; | |
245 | entry->pin = newpin; | |
246 | } | |
247 | if (!entry->next) | |
248 | break; | |
249 | entry = irq_2_pin + entry->next; | |
250 | } | |
251 | } | |
252 | ||
36062448 | 253 | static void __modify_IO_APIC_irq(unsigned int irq, unsigned long enable, unsigned long disable) |
1da177e4 LT |
254 | { |
255 | struct irq_pin_list *entry = irq_2_pin + irq; | |
256 | unsigned int pin, reg; | |
257 | ||
258 | for (;;) { | |
259 | pin = entry->pin; | |
260 | if (pin == -1) | |
261 | break; | |
262 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
263 | reg &= ~disable; | |
264 | reg |= enable; | |
265 | io_apic_modify(entry->apic, 0x10 + pin*2, reg); | |
266 | if (!entry->next) | |
267 | break; | |
268 | entry = irq_2_pin + entry->next; | |
269 | } | |
270 | } | |
271 | ||
272 | /* mask = 1 */ | |
36062448 | 273 | static void __mask_IO_APIC_irq(unsigned int irq) |
1da177e4 | 274 | { |
46b3b4ef | 275 | __modify_IO_APIC_irq(irq, IO_APIC_REDIR_MASKED, 0); |
1da177e4 LT |
276 | } |
277 | ||
278 | /* mask = 0 */ | |
36062448 | 279 | static void __unmask_IO_APIC_irq(unsigned int irq) |
1da177e4 | 280 | { |
46b3b4ef | 281 | __modify_IO_APIC_irq(irq, 0, IO_APIC_REDIR_MASKED); |
1da177e4 LT |
282 | } |
283 | ||
284 | /* mask = 1, trigger = 0 */ | |
36062448 | 285 | static void __mask_and_edge_IO_APIC_irq(unsigned int irq) |
1da177e4 | 286 | { |
46b3b4ef CG |
287 | __modify_IO_APIC_irq(irq, IO_APIC_REDIR_MASKED, |
288 | IO_APIC_REDIR_LEVEL_TRIGGER); | |
1da177e4 LT |
289 | } |
290 | ||
291 | /* mask = 0, trigger = 1 */ | |
36062448 | 292 | static void __unmask_and_level_IO_APIC_irq(unsigned int irq) |
1da177e4 | 293 | { |
46b3b4ef CG |
294 | __modify_IO_APIC_irq(irq, IO_APIC_REDIR_LEVEL_TRIGGER, |
295 | IO_APIC_REDIR_MASKED); | |
1da177e4 LT |
296 | } |
297 | ||
36062448 | 298 | static void mask_IO_APIC_irq(unsigned int irq) |
1da177e4 LT |
299 | { |
300 | unsigned long flags; | |
301 | ||
302 | spin_lock_irqsave(&ioapic_lock, flags); | |
303 | __mask_IO_APIC_irq(irq); | |
304 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
305 | } | |
306 | ||
36062448 | 307 | static void unmask_IO_APIC_irq(unsigned int irq) |
1da177e4 LT |
308 | { |
309 | unsigned long flags; | |
310 | ||
311 | spin_lock_irqsave(&ioapic_lock, flags); | |
312 | __unmask_IO_APIC_irq(irq); | |
313 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
314 | } | |
315 | ||
316 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) | |
317 | { | |
318 | struct IO_APIC_route_entry entry; | |
36062448 | 319 | |
1da177e4 | 320 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 321 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
322 | if (entry.delivery_mode == dest_SMI) |
323 | return; | |
324 | ||
325 | /* | |
326 | * Disable it in the IO-APIC irq-routing table: | |
327 | */ | |
f9dadfa7 | 328 | ioapic_mask_entry(apic, pin); |
1da177e4 LT |
329 | } |
330 | ||
36062448 | 331 | static void clear_IO_APIC(void) |
1da177e4 LT |
332 | { |
333 | int apic, pin; | |
334 | ||
335 | for (apic = 0; apic < nr_ioapics; apic++) | |
336 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) | |
337 | clear_IO_APIC_pin(apic, pin); | |
338 | } | |
339 | ||
54d5d424 | 340 | #ifdef CONFIG_SMP |
1da177e4 LT |
341 | static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask) |
342 | { | |
343 | unsigned long flags; | |
344 | int pin; | |
345 | struct irq_pin_list *entry = irq_2_pin + irq; | |
346 | unsigned int apicid_value; | |
54d5d424 | 347 | cpumask_t tmp; |
08678b08 | 348 | struct irq_desc *desc; |
36062448 | 349 | |
54d5d424 AR |
350 | cpus_and(tmp, cpumask, cpu_online_map); |
351 | if (cpus_empty(tmp)) | |
352 | tmp = TARGET_CPUS; | |
353 | ||
354 | cpus_and(cpumask, tmp, CPU_MASK_ALL); | |
355 | ||
1da177e4 LT |
356 | apicid_value = cpu_mask_to_apicid(cpumask); |
357 | /* Prepare to do the io_apic_write */ | |
358 | apicid_value = apicid_value << 24; | |
359 | spin_lock_irqsave(&ioapic_lock, flags); | |
360 | for (;;) { | |
361 | pin = entry->pin; | |
362 | if (pin == -1) | |
363 | break; | |
364 | io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value); | |
365 | if (!entry->next) | |
366 | break; | |
367 | entry = irq_2_pin + entry->next; | |
368 | } | |
08678b08 YL |
369 | desc = irq_to_desc(irq); |
370 | desc->affinity = cpumask; | |
1da177e4 LT |
371 | spin_unlock_irqrestore(&ioapic_lock, flags); |
372 | } | |
373 | ||
54d5d424 | 374 | #endif /* CONFIG_SMP */ |
1da177e4 LT |
375 | |
376 | #ifndef CONFIG_SMP | |
75604d7f | 377 | void send_IPI_self(int vector) |
1da177e4 LT |
378 | { |
379 | unsigned int cfg; | |
380 | ||
381 | /* | |
382 | * Wait for idle. | |
383 | */ | |
384 | apic_wait_icr_idle(); | |
385 | cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL; | |
386 | /* | |
387 | * Send the IPI. The write to APIC_ICR fires this off. | |
388 | */ | |
593f4a78 | 389 | apic_write(APIC_ICR, cfg); |
1da177e4 LT |
390 | } |
391 | #endif /* !CONFIG_SMP */ | |
392 | ||
393 | ||
394 | /* | |
395 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
396 | * specific CPU-side IRQs. | |
397 | */ | |
398 | ||
399 | #define MAX_PIRQS 8 | |
400 | static int pirq_entries [MAX_PIRQS]; | |
401 | static int pirqs_enabled; | |
402 | int skip_ioapic_setup; | |
403 | ||
1da177e4 LT |
404 | static int __init ioapic_pirq_setup(char *str) |
405 | { | |
406 | int i, max; | |
407 | int ints[MAX_PIRQS+1]; | |
408 | ||
409 | get_options(str, ARRAY_SIZE(ints), ints); | |
410 | ||
411 | for (i = 0; i < MAX_PIRQS; i++) | |
412 | pirq_entries[i] = -1; | |
413 | ||
414 | pirqs_enabled = 1; | |
415 | apic_printk(APIC_VERBOSE, KERN_INFO | |
416 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
417 | max = MAX_PIRQS; | |
418 | if (ints[0] < MAX_PIRQS) | |
419 | max = ints[0]; | |
420 | ||
421 | for (i = 0; i < max; i++) { | |
422 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
423 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
424 | /* | |
425 | * PIRQs are mapped upside down, usually. | |
426 | */ | |
427 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
428 | } | |
429 | return 1; | |
430 | } | |
431 | ||
432 | __setup("pirq=", ioapic_pirq_setup); | |
433 | ||
434 | /* | |
435 | * Find the IRQ entry number of a certain pin. | |
436 | */ | |
437 | static int find_irq_entry(int apic, int pin, int type) | |
438 | { | |
439 | int i; | |
440 | ||
441 | for (i = 0; i < mp_irq_entries; i++) | |
2fddb6e2 AS |
442 | if (mp_irqs[i].mp_irqtype == type && |
443 | (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid || | |
444 | mp_irqs[i].mp_dstapic == MP_APIC_ALL) && | |
445 | mp_irqs[i].mp_dstirq == pin) | |
1da177e4 LT |
446 | return i; |
447 | ||
448 | return -1; | |
449 | } | |
450 | ||
451 | /* | |
452 | * Find the pin to which IRQ[irq] (ISA) is connected | |
453 | */ | |
fcfd636a | 454 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
455 | { |
456 | int i; | |
457 | ||
458 | for (i = 0; i < mp_irq_entries; i++) { | |
2fddb6e2 | 459 | int lbus = mp_irqs[i].mp_srcbus; |
1da177e4 | 460 | |
d27e2b8e | 461 | if (test_bit(lbus, mp_bus_not_pci) && |
2fddb6e2 AS |
462 | (mp_irqs[i].mp_irqtype == type) && |
463 | (mp_irqs[i].mp_srcbusirq == irq)) | |
1da177e4 | 464 | |
2fddb6e2 | 465 | return mp_irqs[i].mp_dstirq; |
1da177e4 LT |
466 | } |
467 | return -1; | |
468 | } | |
469 | ||
fcfd636a EB |
470 | static int __init find_isa_irq_apic(int irq, int type) |
471 | { | |
472 | int i; | |
473 | ||
474 | for (i = 0; i < mp_irq_entries; i++) { | |
2fddb6e2 | 475 | int lbus = mp_irqs[i].mp_srcbus; |
fcfd636a | 476 | |
73b2961b | 477 | if (test_bit(lbus, mp_bus_not_pci) && |
2fddb6e2 AS |
478 | (mp_irqs[i].mp_irqtype == type) && |
479 | (mp_irqs[i].mp_srcbusirq == irq)) | |
fcfd636a EB |
480 | break; |
481 | } | |
482 | if (i < mp_irq_entries) { | |
483 | int apic; | |
36062448 | 484 | for (apic = 0; apic < nr_ioapics; apic++) { |
2fddb6e2 | 485 | if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic) |
fcfd636a EB |
486 | return apic; |
487 | } | |
488 | } | |
489 | ||
490 | return -1; | |
491 | } | |
492 | ||
1da177e4 LT |
493 | /* |
494 | * Find a specific PCI IRQ entry. | |
495 | * Not an __init, possibly needed by modules | |
496 | */ | |
497 | static int pin_2_irq(int idx, int apic, int pin); | |
498 | ||
499 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin) | |
500 | { | |
501 | int apic, i, best_guess = -1; | |
502 | ||
503 | apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, " | |
504 | "slot:%d, pin:%d.\n", bus, slot, pin); | |
ce6444d3 | 505 | if (test_bit(bus, mp_bus_not_pci)) { |
1da177e4 LT |
506 | printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus); |
507 | return -1; | |
508 | } | |
509 | for (i = 0; i < mp_irq_entries; i++) { | |
2fddb6e2 | 510 | int lbus = mp_irqs[i].mp_srcbus; |
1da177e4 LT |
511 | |
512 | for (apic = 0; apic < nr_ioapics; apic++) | |
2fddb6e2 AS |
513 | if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic || |
514 | mp_irqs[i].mp_dstapic == MP_APIC_ALL) | |
1da177e4 LT |
515 | break; |
516 | ||
47cab822 | 517 | if (!test_bit(lbus, mp_bus_not_pci) && |
2fddb6e2 | 518 | !mp_irqs[i].mp_irqtype && |
1da177e4 | 519 | (bus == lbus) && |
2fddb6e2 | 520 | (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) { |
3de352bb | 521 | int irq = pin_2_irq(i, apic, mp_irqs[i].mp_dstirq); |
1da177e4 LT |
522 | |
523 | if (!(apic || IO_APIC_IRQ(irq))) | |
524 | continue; | |
525 | ||
2fddb6e2 | 526 | if (pin == (mp_irqs[i].mp_srcbusirq & 3)) |
1da177e4 LT |
527 | return irq; |
528 | /* | |
529 | * Use the first all-but-pin matching entry as a | |
530 | * best-guess fuzzy result for broken mptables. | |
531 | */ | |
532 | if (best_guess < 0) | |
533 | best_guess = irq; | |
534 | } | |
535 | } | |
536 | return best_guess; | |
537 | } | |
129f6946 | 538 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); |
1da177e4 LT |
539 | |
540 | /* | |
36062448 | 541 | * This function currently is only a helper for the i386 smp boot process where |
1da177e4 LT |
542 | * we need to reprogram the ioredtbls to cater for the cpus which have come online |
543 | * so mask in all cases should simply be TARGET_CPUS | |
544 | */ | |
54d5d424 | 545 | #ifdef CONFIG_SMP |
1da177e4 LT |
546 | void __init setup_ioapic_dest(void) |
547 | { | |
548 | int pin, ioapic, irq, irq_entry; | |
549 | ||
550 | if (skip_ioapic_setup == 1) | |
551 | return; | |
552 | ||
553 | for (ioapic = 0; ioapic < nr_ioapics; ioapic++) { | |
554 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { | |
555 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); | |
556 | if (irq_entry == -1) | |
557 | continue; | |
558 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
559 | set_ioapic_affinity_irq(irq, TARGET_CPUS); | |
560 | } | |
561 | ||
562 | } | |
563 | } | |
54d5d424 | 564 | #endif |
1da177e4 | 565 | |
c0a282c2 | 566 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
1da177e4 LT |
567 | /* |
568 | * EISA Edge/Level control register, ELCR | |
569 | */ | |
570 | static int EISA_ELCR(unsigned int irq) | |
571 | { | |
572 | if (irq < 16) { | |
573 | unsigned int port = 0x4d0 + (irq >> 3); | |
574 | return (inb(port) >> (irq & 7)) & 1; | |
575 | } | |
576 | apic_printk(APIC_VERBOSE, KERN_INFO | |
577 | "Broken MPtable reports ISA irq %d\n", irq); | |
578 | return 0; | |
579 | } | |
c0a282c2 | 580 | #endif |
1da177e4 | 581 | |
6728801d AS |
582 | /* ISA interrupts are always polarity zero edge triggered, |
583 | * when listed as conforming in the MP table. */ | |
584 | ||
585 | #define default_ISA_trigger(idx) (0) | |
586 | #define default_ISA_polarity(idx) (0) | |
587 | ||
1da177e4 LT |
588 | /* EISA interrupts are always polarity zero and can be edge or level |
589 | * trigger depending on the ELCR value. If an interrupt is listed as | |
590 | * EISA conforming in the MP table, that means its trigger type must | |
591 | * be read in from the ELCR */ | |
592 | ||
2fddb6e2 | 593 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq)) |
6728801d | 594 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
595 | |
596 | /* PCI interrupts are always polarity one level triggered, | |
597 | * when listed as conforming in the MP table. */ | |
598 | ||
599 | #define default_PCI_trigger(idx) (1) | |
600 | #define default_PCI_polarity(idx) (1) | |
601 | ||
602 | /* MCA interrupts are always polarity zero level triggered, | |
603 | * when listed as conforming in the MP table. */ | |
604 | ||
605 | #define default_MCA_trigger(idx) (1) | |
6728801d | 606 | #define default_MCA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 | 607 | |
61fd47e0 | 608 | static int MPBIOS_polarity(int idx) |
1da177e4 | 609 | { |
2fddb6e2 | 610 | int bus = mp_irqs[idx].mp_srcbus; |
1da177e4 LT |
611 | int polarity; |
612 | ||
613 | /* | |
614 | * Determine IRQ line polarity (high active or low active): | |
615 | */ | |
3de352bb | 616 | switch (mp_irqs[idx].mp_irqflag & 3) { |
36062448 | 617 | case 0: /* conforms, ie. bus-type dependent polarity */ |
1da177e4 | 618 | { |
36062448 PC |
619 | polarity = test_bit(bus, mp_bus_not_pci)? |
620 | default_ISA_polarity(idx): | |
621 | default_PCI_polarity(idx); | |
622 | break; | |
623 | } | |
624 | case 1: /* high active */ | |
625 | { | |
626 | polarity = 0; | |
627 | break; | |
628 | } | |
629 | case 2: /* reserved */ | |
630 | { | |
631 | printk(KERN_WARNING "broken BIOS!!\n"); | |
632 | polarity = 1; | |
633 | break; | |
634 | } | |
635 | case 3: /* low active */ | |
636 | { | |
637 | polarity = 1; | |
638 | break; | |
639 | } | |
640 | default: /* invalid */ | |
641 | { | |
642 | printk(KERN_WARNING "broken BIOS!!\n"); | |
643 | polarity = 1; | |
644 | break; | |
645 | } | |
1da177e4 LT |
646 | } |
647 | return polarity; | |
648 | } | |
649 | ||
650 | static int MPBIOS_trigger(int idx) | |
651 | { | |
2fddb6e2 | 652 | int bus = mp_irqs[idx].mp_srcbus; |
1da177e4 LT |
653 | int trigger; |
654 | ||
655 | /* | |
656 | * Determine IRQ trigger mode (edge or level sensitive): | |
657 | */ | |
3de352bb | 658 | switch ((mp_irqs[idx].mp_irqflag>>2) & 3) { |
36062448 | 659 | case 0: /* conforms, ie. bus-type dependent */ |
1da177e4 | 660 | { |
36062448 PC |
661 | trigger = test_bit(bus, mp_bus_not_pci)? |
662 | default_ISA_trigger(idx): | |
663 | default_PCI_trigger(idx); | |
c0a282c2 | 664 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
36062448 PC |
665 | switch (mp_bus_id_to_type[bus]) { |
666 | case MP_BUS_ISA: /* ISA pin */ | |
667 | { | |
668 | /* set before the switch */ | |
1da177e4 LT |
669 | break; |
670 | } | |
36062448 | 671 | case MP_BUS_EISA: /* EISA pin */ |
1da177e4 | 672 | { |
36062448 | 673 | trigger = default_EISA_trigger(idx); |
1da177e4 LT |
674 | break; |
675 | } | |
36062448 | 676 | case MP_BUS_PCI: /* PCI pin */ |
1da177e4 | 677 | { |
36062448 | 678 | /* set before the switch */ |
1da177e4 LT |
679 | break; |
680 | } | |
36062448 | 681 | case MP_BUS_MCA: /* MCA pin */ |
1da177e4 | 682 | { |
36062448 | 683 | trigger = default_MCA_trigger(idx); |
1da177e4 LT |
684 | break; |
685 | } | |
36062448 | 686 | default: |
1da177e4 LT |
687 | { |
688 | printk(KERN_WARNING "broken BIOS!!\n"); | |
36062448 | 689 | trigger = 1; |
1da177e4 LT |
690 | break; |
691 | } | |
692 | } | |
36062448 PC |
693 | #endif |
694 | break; | |
695 | } | |
696 | case 1: /* edge */ | |
697 | { | |
698 | trigger = 0; | |
699 | break; | |
700 | } | |
701 | case 2: /* reserved */ | |
702 | { | |
703 | printk(KERN_WARNING "broken BIOS!!\n"); | |
704 | trigger = 1; | |
705 | break; | |
706 | } | |
707 | case 3: /* level */ | |
708 | { | |
709 | trigger = 1; | |
710 | break; | |
711 | } | |
712 | default: /* invalid */ | |
713 | { | |
714 | printk(KERN_WARNING "broken BIOS!!\n"); | |
715 | trigger = 0; | |
716 | break; | |
717 | } | |
718 | } | |
1da177e4 LT |
719 | return trigger; |
720 | } | |
721 | ||
722 | static inline int irq_polarity(int idx) | |
723 | { | |
724 | return MPBIOS_polarity(idx); | |
725 | } | |
726 | ||
727 | static inline int irq_trigger(int idx) | |
728 | { | |
729 | return MPBIOS_trigger(idx); | |
730 | } | |
731 | ||
732 | static int pin_2_irq(int idx, int apic, int pin) | |
733 | { | |
734 | int irq, i; | |
2fddb6e2 | 735 | int bus = mp_irqs[idx].mp_srcbus; |
1da177e4 LT |
736 | |
737 | /* | |
738 | * Debugging check, we are in big trouble if this message pops up! | |
739 | */ | |
2fddb6e2 | 740 | if (mp_irqs[idx].mp_dstirq != pin) |
1da177e4 LT |
741 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); |
742 | ||
643befed | 743 | if (test_bit(bus, mp_bus_not_pci)) |
2fddb6e2 | 744 | irq = mp_irqs[idx].mp_srcbusirq; |
643befed AS |
745 | else { |
746 | /* | |
747 | * PCI IRQs are mapped in order | |
748 | */ | |
749 | i = irq = 0; | |
750 | while (i < apic) | |
751 | irq += nr_ioapic_registers[i++]; | |
752 | irq += pin; | |
1da177e4 | 753 | |
643befed AS |
754 | /* |
755 | * For MPS mode, so far only needed by ES7000 platform | |
756 | */ | |
757 | if (ioapic_renumber_irq) | |
758 | irq = ioapic_renumber_irq(apic, irq); | |
1da177e4 LT |
759 | } |
760 | ||
761 | /* | |
762 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
763 | */ | |
764 | if ((pin >= 16) && (pin <= 23)) { | |
765 | if (pirq_entries[pin-16] != -1) { | |
766 | if (!pirq_entries[pin-16]) { | |
767 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
768 | "disabling PIRQ%d\n", pin-16); | |
769 | } else { | |
770 | irq = pirq_entries[pin-16]; | |
771 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
772 | "using PIRQ%d -> IRQ %d\n", | |
773 | pin-16, irq); | |
774 | } | |
775 | } | |
776 | } | |
777 | return irq; | |
778 | } | |
779 | ||
780 | static inline int IO_APIC_irq_trigger(int irq) | |
781 | { | |
782 | int apic, idx, pin; | |
783 | ||
784 | for (apic = 0; apic < nr_ioapics; apic++) { | |
785 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
36062448 PC |
786 | idx = find_irq_entry(apic, pin, mp_INT); |
787 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin))) | |
1da177e4 LT |
788 | return irq_trigger(idx); |
789 | } | |
790 | } | |
791 | /* | |
792 | * nonexistent IRQs are edge default | |
793 | */ | |
794 | return 0; | |
795 | } | |
796 | ||
797 | /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */ | |
301e6190 YL |
798 | static u8 irq_vector_init_first __initdata = FIRST_DEVICE_VECTOR; |
799 | static u8 *irq_vector; | |
800 | ||
801 | static void __init irq_vector_init_work(void *data) | |
802 | { | |
803 | struct dyn_array *da = data; | |
804 | ||
805 | u8 *irq_vec; | |
806 | ||
807 | irq_vec = *da->name; | |
808 | ||
809 | irq_vec[0] = irq_vector_init_first; | |
810 | } | |
811 | ||
812 | DEFINE_DYN_ARRAY(irq_vector, sizeof(u8), nr_irqs, PAGE_SIZE, irq_vector_init_work); | |
1da177e4 | 813 | |
ace80ab7 | 814 | static int __assign_irq_vector(int irq) |
1da177e4 | 815 | { |
36062448 | 816 | static int current_vector = FIRST_DEVICE_VECTOR, current_offset; |
dbeb2be2 | 817 | int vector, offset; |
1da177e4 | 818 | |
301e6190 | 819 | BUG_ON((unsigned)irq >= nr_irqs); |
0a1ad60d | 820 | |
b940d22d EB |
821 | if (irq_vector[irq] > 0) |
822 | return irq_vector[irq]; | |
ace80ab7 | 823 | |
0a1ad60d | 824 | vector = current_vector; |
8339f000 EB |
825 | offset = current_offset; |
826 | next: | |
827 | vector += 8; | |
305b92a2 | 828 | if (vector >= first_system_vector) { |
8339f000 EB |
829 | offset = (offset + 1) % 8; |
830 | vector = FIRST_DEVICE_VECTOR + offset; | |
831 | } | |
832 | if (vector == current_vector) | |
833 | return -ENOSPC; | |
dbeb2be2 | 834 | if (test_and_set_bit(vector, used_vectors)) |
8339f000 | 835 | goto next; |
8339f000 EB |
836 | |
837 | current_vector = vector; | |
838 | current_offset = offset; | |
b940d22d | 839 | irq_vector[irq] = vector; |
ace80ab7 EB |
840 | |
841 | return vector; | |
842 | } | |
0a1ad60d | 843 | |
ace80ab7 EB |
844 | static int assign_irq_vector(int irq) |
845 | { | |
846 | unsigned long flags; | |
847 | int vector; | |
848 | ||
849 | spin_lock_irqsave(&vector_lock, flags); | |
850 | vector = __assign_irq_vector(irq); | |
26a3c49c | 851 | spin_unlock_irqrestore(&vector_lock, flags); |
1da177e4 | 852 | |
0a1ad60d | 853 | return vector; |
1da177e4 | 854 | } |
3fde6900 | 855 | |
f5b9ed7a | 856 | static struct irq_chip ioapic_chip; |
1da177e4 LT |
857 | |
858 | #define IOAPIC_AUTO -1 | |
859 | #define IOAPIC_EDGE 0 | |
860 | #define IOAPIC_LEVEL 1 | |
861 | ||
d1bef4ed | 862 | static void ioapic_register_intr(int irq, int vector, unsigned long trigger) |
1da177e4 | 863 | { |
08678b08 YL |
864 | struct irq_desc *desc; |
865 | ||
866 | desc = irq_to_desc(irq); | |
6ebcc00e | 867 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
cc75b92d | 868 | trigger == IOAPIC_LEVEL) { |
08678b08 | 869 | desc->status |= IRQ_LEVEL; |
a460e745 IM |
870 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
871 | handle_fasteoi_irq, "fasteoi"); | |
cc75b92d | 872 | } else { |
08678b08 | 873 | desc->status &= ~IRQ_LEVEL; |
a460e745 IM |
874 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
875 | handle_edge_irq, "edge"); | |
cc75b92d | 876 | } |
ace80ab7 | 877 | set_intr_gate(vector, interrupt[irq]); |
1da177e4 LT |
878 | } |
879 | ||
880 | static void __init setup_IO_APIC_irqs(void) | |
881 | { | |
882 | struct IO_APIC_route_entry entry; | |
883 | int apic, pin, idx, irq, first_notcon = 1, vector; | |
1da177e4 LT |
884 | |
885 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
886 | ||
887 | for (apic = 0; apic < nr_ioapics; apic++) { | |
888 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
889 | ||
890 | /* | |
891 | * add it to the IO-APIC irq-routing table: | |
892 | */ | |
36062448 | 893 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
894 | |
895 | entry.delivery_mode = INT_DELIVERY_MODE; | |
896 | entry.dest_mode = INT_DEST_MODE; | |
897 | entry.mask = 0; /* enable IRQ */ | |
36062448 | 898 | entry.dest.logical.logical_dest = |
1da177e4 LT |
899 | cpu_mask_to_apicid(TARGET_CPUS); |
900 | ||
36062448 | 901 | idx = find_irq_entry(apic, pin, mp_INT); |
1da177e4 LT |
902 | if (idx == -1) { |
903 | if (first_notcon) { | |
904 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
905 | " IO-APIC (apicid-pin) %d-%d", | |
ec2cd0a2 | 906 | mp_ioapics[apic].mp_apicid, |
1da177e4 LT |
907 | pin); |
908 | first_notcon = 0; | |
909 | } else | |
910 | apic_printk(APIC_VERBOSE, ", %d-%d", | |
ec2cd0a2 | 911 | mp_ioapics[apic].mp_apicid, pin); |
1da177e4 LT |
912 | continue; |
913 | } | |
914 | ||
20d225b9 YL |
915 | if (!first_notcon) { |
916 | apic_printk(APIC_VERBOSE, " not connected.\n"); | |
917 | first_notcon = 1; | |
918 | } | |
919 | ||
1da177e4 LT |
920 | entry.trigger = irq_trigger(idx); |
921 | entry.polarity = irq_polarity(idx); | |
922 | ||
923 | if (irq_trigger(idx)) { | |
924 | entry.trigger = 1; | |
925 | entry.mask = 1; | |
926 | } | |
927 | ||
928 | irq = pin_2_irq(idx, apic, pin); | |
929 | /* | |
930 | * skip adding the timer int on secondary nodes, which causes | |
931 | * a small but painful rift in the time-space continuum | |
932 | */ | |
933 | if (multi_timer_check(apic, irq)) | |
934 | continue; | |
935 | else | |
936 | add_pin_to_irq(irq, apic, pin); | |
937 | ||
938 | if (!apic && !IO_APIC_IRQ(irq)) | |
939 | continue; | |
940 | ||
941 | if (IO_APIC_IRQ(irq)) { | |
942 | vector = assign_irq_vector(irq); | |
943 | entry.vector = vector; | |
944 | ioapic_register_intr(irq, vector, IOAPIC_AUTO); | |
36062448 | 945 | |
1da177e4 LT |
946 | if (!apic && (irq < 16)) |
947 | disable_8259A_irq(irq); | |
948 | } | |
a2249cba | 949 | ioapic_write_entry(apic, pin, entry); |
1da177e4 LT |
950 | } |
951 | } | |
952 | ||
953 | if (!first_notcon) | |
954 | apic_printk(APIC_VERBOSE, " not connected.\n"); | |
955 | } | |
956 | ||
957 | /* | |
f7633ce5 | 958 | * Set up the timer pin, possibly with the 8259A-master behind. |
1da177e4 | 959 | */ |
f7633ce5 MR |
960 | static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin, |
961 | int vector) | |
1da177e4 LT |
962 | { |
963 | struct IO_APIC_route_entry entry; | |
1da177e4 | 964 | |
36062448 | 965 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
966 | |
967 | /* | |
968 | * We use logical delivery to get the timer IRQ | |
969 | * to the first CPU. | |
970 | */ | |
971 | entry.dest_mode = INT_DEST_MODE; | |
03be7505 | 972 | entry.mask = 1; /* mask IRQ now */ |
1da177e4 LT |
973 | entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS); |
974 | entry.delivery_mode = INT_DELIVERY_MODE; | |
975 | entry.polarity = 0; | |
976 | entry.trigger = 0; | |
977 | entry.vector = vector; | |
978 | ||
979 | /* | |
980 | * The timer IRQ doesn't have to know that behind the | |
f7633ce5 | 981 | * scene we may have a 8259A-master in AEOI mode ... |
1da177e4 | 982 | */ |
f0825262 | 983 | ioapic_register_intr(0, vector, IOAPIC_EDGE); |
1da177e4 LT |
984 | |
985 | /* | |
986 | * Add it to the IO-APIC irq-routing table: | |
987 | */ | |
cf4c6a2f | 988 | ioapic_write_entry(apic, pin, entry); |
1da177e4 LT |
989 | } |
990 | ||
32f71aff MR |
991 | |
992 | __apicdebuginit(void) print_IO_APIC(void) | |
1da177e4 LT |
993 | { |
994 | int apic, i; | |
995 | union IO_APIC_reg_00 reg_00; | |
996 | union IO_APIC_reg_01 reg_01; | |
997 | union IO_APIC_reg_02 reg_02; | |
998 | union IO_APIC_reg_03 reg_03; | |
999 | unsigned long flags; | |
1000 | ||
1001 | if (apic_verbosity == APIC_QUIET) | |
1002 | return; | |
1003 | ||
36062448 | 1004 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); |
1da177e4 LT |
1005 | for (i = 0; i < nr_ioapics; i++) |
1006 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", | |
ec2cd0a2 | 1007 | mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]); |
1da177e4 LT |
1008 | |
1009 | /* | |
1010 | * We are a bit conservative about what we expect. We have to | |
1011 | * know about every hardware change ASAP. | |
1012 | */ | |
1013 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1014 | ||
1015 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1016 | ||
1017 | spin_lock_irqsave(&ioapic_lock, flags); | |
1018 | reg_00.raw = io_apic_read(apic, 0); | |
1019 | reg_01.raw = io_apic_read(apic, 1); | |
1020 | if (reg_01.bits.version >= 0x10) | |
1021 | reg_02.raw = io_apic_read(apic, 2); | |
1022 | if (reg_01.bits.version >= 0x20) | |
1023 | reg_03.raw = io_apic_read(apic, 3); | |
1024 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1025 | ||
ec2cd0a2 | 1026 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
1027 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1028 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1029 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1030 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 LT |
1031 | |
1032 | printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw); | |
1033 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); | |
1da177e4 LT |
1034 | |
1035 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
1036 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); | |
1da177e4 LT |
1037 | |
1038 | /* | |
1039 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1040 | * but the value of reg_02 is read as the previous read register | |
1041 | * value, so ignore it if reg_02 == reg_01. | |
1042 | */ | |
1043 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1044 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1045 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1046 | } |
1047 | ||
1048 | /* | |
1049 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1050 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1051 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1052 | */ | |
1053 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1054 | reg_03.raw != reg_01.raw) { | |
1055 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1056 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1057 | } |
1058 | ||
1059 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1060 | ||
1061 | printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol" | |
1062 | " Stat Dest Deli Vect: \n"); | |
1063 | ||
1064 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
1065 | struct IO_APIC_route_entry entry; | |
1066 | ||
cf4c6a2f | 1067 | entry = ioapic_read_entry(apic, i); |
1da177e4 LT |
1068 | |
1069 | printk(KERN_DEBUG " %02x %03X %02X ", | |
1070 | i, | |
1071 | entry.dest.logical.logical_dest, | |
1072 | entry.dest.physical.physical_dest | |
1073 | ); | |
1074 | ||
1075 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", | |
1076 | entry.mask, | |
1077 | entry.trigger, | |
1078 | entry.irr, | |
1079 | entry.polarity, | |
1080 | entry.delivery_status, | |
1081 | entry.dest_mode, | |
1082 | entry.delivery_mode, | |
1083 | entry.vector | |
1084 | ); | |
1085 | } | |
1086 | } | |
1da177e4 | 1087 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
0799e432 | 1088 | for (i = 0; i < nr_irqs; i++) { |
1da177e4 LT |
1089 | struct irq_pin_list *entry = irq_2_pin + i; |
1090 | if (entry->pin < 0) | |
1091 | continue; | |
ace80ab7 | 1092 | printk(KERN_DEBUG "IRQ%d ", i); |
1da177e4 LT |
1093 | for (;;) { |
1094 | printk("-> %d:%d", entry->apic, entry->pin); | |
1095 | if (!entry->next) | |
1096 | break; | |
1097 | entry = irq_2_pin + entry->next; | |
1098 | } | |
1099 | printk("\n"); | |
1100 | } | |
1101 | ||
1102 | printk(KERN_INFO ".................................... done.\n"); | |
1103 | ||
1104 | return; | |
1105 | } | |
1106 | ||
32f71aff | 1107 | __apicdebuginit(void) print_APIC_bitfield(int base) |
1da177e4 LT |
1108 | { |
1109 | unsigned int v; | |
1110 | int i, j; | |
1111 | ||
1112 | if (apic_verbosity == APIC_QUIET) | |
1113 | return; | |
1114 | ||
1115 | printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG); | |
1116 | for (i = 0; i < 8; i++) { | |
1117 | v = apic_read(base + i*0x10); | |
1118 | for (j = 0; j < 32; j++) { | |
1119 | if (v & (1<<j)) | |
1120 | printk("1"); | |
1121 | else | |
1122 | printk("0"); | |
1123 | } | |
1124 | printk("\n"); | |
1125 | } | |
1126 | } | |
1127 | ||
32f71aff | 1128 | __apicdebuginit(void) print_local_APIC(void *dummy) |
1da177e4 LT |
1129 | { |
1130 | unsigned int v, ver, maxlvt; | |
7ab6af7a | 1131 | u64 icr; |
1da177e4 LT |
1132 | |
1133 | if (apic_verbosity == APIC_QUIET) | |
1134 | return; | |
1135 | ||
1136 | printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", | |
1137 | smp_processor_id(), hard_smp_processor_id()); | |
66823114 | 1138 | v = apic_read(APIC_ID); |
05f2d12c | 1139 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, |
4c9961d5 | 1140 | GET_APIC_ID(v)); |
1da177e4 LT |
1141 | v = apic_read(APIC_LVR); |
1142 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1143 | ver = GET_APIC_VERSION(v); | |
e05d723f | 1144 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1145 | |
1146 | v = apic_read(APIC_TASKPRI); | |
1147 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1148 | ||
1149 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ | |
1150 | v = apic_read(APIC_ARBPRI); | |
1151 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1152 | v & APIC_ARBPRI_MASK); | |
1153 | v = apic_read(APIC_PROCPRI); | |
1154 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1155 | } | |
1156 | ||
1157 | v = apic_read(APIC_EOI); | |
1158 | printk(KERN_DEBUG "... APIC EOI: %08x\n", v); | |
1159 | v = apic_read(APIC_RRR); | |
1160 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1161 | v = apic_read(APIC_LDR); | |
1162 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
1163 | v = apic_read(APIC_DFR); | |
1164 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1165 | v = apic_read(APIC_SPIV); | |
1166 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1167 | ||
1168 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
1169 | print_APIC_bitfield(APIC_ISR); | |
1170 | printk(KERN_DEBUG "... APIC TMR field:\n"); | |
1171 | print_APIC_bitfield(APIC_TMR); | |
1172 | printk(KERN_DEBUG "... APIC IRR field:\n"); | |
1173 | print_APIC_bitfield(APIC_IRR); | |
1174 | ||
1175 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ | |
1176 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1177 | apic_write(APIC_ESR, 0); | |
1178 | v = apic_read(APIC_ESR); | |
1179 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1180 | } | |
1181 | ||
7ab6af7a HS |
1182 | icr = apic_icr_read(); |
1183 | printk(KERN_DEBUG "... APIC ICR: %08x\n", icr); | |
1184 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", icr >> 32); | |
1da177e4 LT |
1185 | |
1186 | v = apic_read(APIC_LVTT); | |
1187 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1188 | ||
1189 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1190 | v = apic_read(APIC_LVTPC); | |
1191 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1192 | } | |
1193 | v = apic_read(APIC_LVT0); | |
1194 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1195 | v = apic_read(APIC_LVT1); | |
1196 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1197 | ||
1198 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1199 | v = apic_read(APIC_LVTERR); | |
1200 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1201 | } | |
1202 | ||
1203 | v = apic_read(APIC_TMICT); | |
1204 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1205 | v = apic_read(APIC_TMCCT); | |
1206 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1207 | v = apic_read(APIC_TDCR); | |
1208 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
1209 | printk("\n"); | |
1210 | } | |
1211 | ||
32f71aff | 1212 | __apicdebuginit(void) print_all_local_APICs(void) |
1da177e4 | 1213 | { |
15c8b6c1 | 1214 | on_each_cpu(print_local_APIC, NULL, 1); |
1da177e4 LT |
1215 | } |
1216 | ||
32f71aff | 1217 | __apicdebuginit(void) print_PIC(void) |
1da177e4 | 1218 | { |
1da177e4 LT |
1219 | unsigned int v; |
1220 | unsigned long flags; | |
1221 | ||
1222 | if (apic_verbosity == APIC_QUIET) | |
1223 | return; | |
1224 | ||
1225 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1226 | ||
1227 | spin_lock_irqsave(&i8259A_lock, flags); | |
1228 | ||
1229 | v = inb(0xa1) << 8 | inb(0x21); | |
1230 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1231 | ||
1232 | v = inb(0xa0) << 8 | inb(0x20); | |
1233 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1234 | ||
36062448 PC |
1235 | outb(0x0b, 0xa0); |
1236 | outb(0x0b, 0x20); | |
1da177e4 | 1237 | v = inb(0xa0) << 8 | inb(0x20); |
36062448 PC |
1238 | outb(0x0a, 0xa0); |
1239 | outb(0x0a, 0x20); | |
1da177e4 LT |
1240 | |
1241 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
1242 | ||
1243 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1244 | ||
1245 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1246 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1247 | } | |
1248 | ||
32f71aff MR |
1249 | __apicdebuginit(int) print_all_ICs(void) |
1250 | { | |
1251 | print_PIC(); | |
1252 | print_all_local_APICs(); | |
1253 | print_IO_APIC(); | |
1254 | ||
1255 | return 0; | |
1256 | } | |
1257 | ||
1258 | fs_initcall(print_all_ICs); | |
1259 | ||
1da177e4 LT |
1260 | |
1261 | static void __init enable_IO_APIC(void) | |
1262 | { | |
1263 | union IO_APIC_reg_01 reg_01; | |
fcfd636a EB |
1264 | int i8259_apic, i8259_pin; |
1265 | int i, apic; | |
1da177e4 LT |
1266 | unsigned long flags; |
1267 | ||
0799e432 | 1268 | for (i = 0; i < pin_map_size; i++) { |
1da177e4 LT |
1269 | irq_2_pin[i].pin = -1; |
1270 | irq_2_pin[i].next = 0; | |
1271 | } | |
1272 | if (!pirqs_enabled) | |
1273 | for (i = 0; i < MAX_PIRQS; i++) | |
1274 | pirq_entries[i] = -1; | |
1275 | ||
1276 | /* | |
1277 | * The number of IO-APIC IRQ registers (== #pins): | |
1278 | */ | |
fcfd636a | 1279 | for (apic = 0; apic < nr_ioapics; apic++) { |
1da177e4 | 1280 | spin_lock_irqsave(&ioapic_lock, flags); |
fcfd636a | 1281 | reg_01.raw = io_apic_read(apic, 1); |
1da177e4 | 1282 | spin_unlock_irqrestore(&ioapic_lock, flags); |
fcfd636a EB |
1283 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; |
1284 | } | |
36062448 | 1285 | for (apic = 0; apic < nr_ioapics; apic++) { |
fcfd636a EB |
1286 | int pin; |
1287 | /* See if any of the pins is in ExtINT mode */ | |
1008fddc | 1288 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
fcfd636a | 1289 | struct IO_APIC_route_entry entry; |
cf4c6a2f | 1290 | entry = ioapic_read_entry(apic, pin); |
fcfd636a EB |
1291 | |
1292 | ||
1293 | /* If the interrupt line is enabled and in ExtInt mode | |
1294 | * I have found the pin where the i8259 is connected. | |
1295 | */ | |
1296 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1297 | ioapic_i8259.apic = apic; | |
1298 | ioapic_i8259.pin = pin; | |
1299 | goto found_i8259; | |
1300 | } | |
1301 | } | |
1302 | } | |
1303 | found_i8259: | |
1304 | /* Look to see what if the MP table has reported the ExtINT */ | |
1305 | /* If we could not find the appropriate pin by looking at the ioapic | |
1306 | * the i8259 probably is not connected the ioapic but give the | |
1307 | * mptable a chance anyway. | |
1308 | */ | |
1309 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1310 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1311 | /* Trust the MP table if nothing is setup in the hardware */ | |
1312 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1313 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1314 | ioapic_i8259.pin = i8259_pin; | |
1315 | ioapic_i8259.apic = i8259_apic; | |
1316 | } | |
1317 | /* Complain if the MP table and the hardware disagree */ | |
1318 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1319 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1320 | { | |
1321 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1322 | } |
1323 | ||
1324 | /* | |
1325 | * Do not trust the IO-APIC being empty at bootup | |
1326 | */ | |
1327 | clear_IO_APIC(); | |
1328 | } | |
1329 | ||
1330 | /* | |
1331 | * Not an __init, needed by the reboot code | |
1332 | */ | |
1333 | void disable_IO_APIC(void) | |
1334 | { | |
1335 | /* | |
1336 | * Clear the IO-APIC before rebooting: | |
1337 | */ | |
1338 | clear_IO_APIC(); | |
1339 | ||
650927ef | 1340 | /* |
0b968d23 | 1341 | * If the i8259 is routed through an IOAPIC |
650927ef | 1342 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 1343 | * so legacy interrupts can be delivered. |
650927ef | 1344 | */ |
fcfd636a | 1345 | if (ioapic_i8259.pin != -1) { |
650927ef | 1346 | struct IO_APIC_route_entry entry; |
650927ef EB |
1347 | |
1348 | memset(&entry, 0, sizeof(entry)); | |
1349 | entry.mask = 0; /* Enabled */ | |
1350 | entry.trigger = 0; /* Edge */ | |
1351 | entry.irr = 0; | |
1352 | entry.polarity = 0; /* High */ | |
1353 | entry.delivery_status = 0; | |
1354 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 1355 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 1356 | entry.vector = 0; |
4c9961d5 | 1357 | entry.dest.physical.physical_dest = read_apic_id(); |
650927ef EB |
1358 | |
1359 | /* | |
1360 | * Add it to the IO-APIC irq-routing table: | |
1361 | */ | |
cf4c6a2f | 1362 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 1363 | } |
fcfd636a | 1364 | disconnect_bsp_APIC(ioapic_i8259.pin != -1); |
1da177e4 LT |
1365 | } |
1366 | ||
1367 | /* | |
1368 | * function to set the IO-APIC physical IDs based on the | |
1369 | * values stored in the MPC table. | |
1370 | * | |
1371 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
1372 | */ | |
1373 | ||
1da177e4 LT |
1374 | static void __init setup_ioapic_ids_from_mpc(void) |
1375 | { | |
1376 | union IO_APIC_reg_00 reg_00; | |
1377 | physid_mask_t phys_id_present_map; | |
1378 | int apic; | |
1379 | int i; | |
1380 | unsigned char old_id; | |
1381 | unsigned long flags; | |
1382 | ||
a4dbc34d | 1383 | if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids()) |
d49c4288 | 1384 | return; |
d49c4288 | 1385 | |
ca05fea6 NP |
1386 | /* |
1387 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
1388 | * no meaning without the serial APIC bus. | |
1389 | */ | |
7c5c1e42 SL |
1390 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
1391 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
ca05fea6 | 1392 | return; |
1da177e4 LT |
1393 | /* |
1394 | * This is broken; anything with a real cpu count has to | |
1395 | * circumvent this idiocy regardless. | |
1396 | */ | |
1397 | phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map); | |
1398 | ||
1399 | /* | |
1400 | * Set the IOAPIC ID to the value stored in the MPC table. | |
1401 | */ | |
1402 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1403 | ||
1404 | /* Read the register 0 value */ | |
1405 | spin_lock_irqsave(&ioapic_lock, flags); | |
1406 | reg_00.raw = io_apic_read(apic, 0); | |
1407 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
36062448 | 1408 | |
ec2cd0a2 | 1409 | old_id = mp_ioapics[apic].mp_apicid; |
1da177e4 | 1410 | |
ec2cd0a2 | 1411 | if (mp_ioapics[apic].mp_apicid >= get_physical_broadcast()) { |
1da177e4 | 1412 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
ec2cd0a2 | 1413 | apic, mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
1414 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
1415 | reg_00.bits.ID); | |
ec2cd0a2 | 1416 | mp_ioapics[apic].mp_apicid = reg_00.bits.ID; |
1da177e4 LT |
1417 | } |
1418 | ||
1da177e4 LT |
1419 | /* |
1420 | * Sanity check, is the ID really free? Every APIC in a | |
1421 | * system must have a unique ID or we get lots of nice | |
1422 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
1423 | */ | |
1424 | if (check_apicid_used(phys_id_present_map, | |
ec2cd0a2 | 1425 | mp_ioapics[apic].mp_apicid)) { |
1da177e4 | 1426 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
ec2cd0a2 | 1427 | apic, mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
1428 | for (i = 0; i < get_physical_broadcast(); i++) |
1429 | if (!physid_isset(i, phys_id_present_map)) | |
1430 | break; | |
1431 | if (i >= get_physical_broadcast()) | |
1432 | panic("Max APIC ID exceeded!\n"); | |
1433 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
1434 | i); | |
1435 | physid_set(i, phys_id_present_map); | |
ec2cd0a2 | 1436 | mp_ioapics[apic].mp_apicid = i; |
1da177e4 LT |
1437 | } else { |
1438 | physid_mask_t tmp; | |
ec2cd0a2 | 1439 | tmp = apicid_to_cpu_present(mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
1440 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
1441 | "phys_id_present_map\n", | |
ec2cd0a2 | 1442 | mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
1443 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
1444 | } | |
1445 | ||
1446 | ||
1447 | /* | |
1448 | * We need to adjust the IRQ routing table | |
1449 | * if the ID changed. | |
1450 | */ | |
ec2cd0a2 | 1451 | if (old_id != mp_ioapics[apic].mp_apicid) |
1da177e4 | 1452 | for (i = 0; i < mp_irq_entries; i++) |
2fddb6e2 AS |
1453 | if (mp_irqs[i].mp_dstapic == old_id) |
1454 | mp_irqs[i].mp_dstapic | |
ec2cd0a2 | 1455 | = mp_ioapics[apic].mp_apicid; |
1da177e4 LT |
1456 | |
1457 | /* | |
1458 | * Read the right value from the MPC table and | |
1459 | * write it into the ID register. | |
36062448 | 1460 | */ |
1da177e4 LT |
1461 | apic_printk(APIC_VERBOSE, KERN_INFO |
1462 | "...changing IO-APIC physical APIC ID to %d ...", | |
ec2cd0a2 | 1463 | mp_ioapics[apic].mp_apicid); |
1da177e4 | 1464 | |
ec2cd0a2 | 1465 | reg_00.bits.ID = mp_ioapics[apic].mp_apicid; |
1da177e4 LT |
1466 | spin_lock_irqsave(&ioapic_lock, flags); |
1467 | io_apic_write(apic, 0, reg_00.raw); | |
1468 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1469 | ||
1470 | /* | |
1471 | * Sanity check | |
1472 | */ | |
1473 | spin_lock_irqsave(&ioapic_lock, flags); | |
1474 | reg_00.raw = io_apic_read(apic, 0); | |
1475 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
ec2cd0a2 | 1476 | if (reg_00.bits.ID != mp_ioapics[apic].mp_apicid) |
1da177e4 LT |
1477 | printk("could not set ID!\n"); |
1478 | else | |
1479 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
1480 | } | |
1481 | } | |
1da177e4 | 1482 | |
7ce0bcfd | 1483 | int no_timer_check __initdata; |
8542b200 ZA |
1484 | |
1485 | static int __init notimercheck(char *s) | |
1486 | { | |
1487 | no_timer_check = 1; | |
1488 | return 1; | |
1489 | } | |
1490 | __setup("no_timer_check", notimercheck); | |
1491 | ||
1da177e4 LT |
1492 | /* |
1493 | * There is a nasty bug in some older SMP boards, their mptable lies | |
1494 | * about the timer IRQ. We do the following to work around the situation: | |
1495 | * | |
1496 | * - timer IRQ defaults to IO-APIC IRQ | |
1497 | * - if this function detects that timer IRQs are defunct, then we fall | |
1498 | * back to ISA timer IRQs | |
1499 | */ | |
f0a7a5c9 | 1500 | static int __init timer_irq_works(void) |
1da177e4 LT |
1501 | { |
1502 | unsigned long t1 = jiffies; | |
4aae0702 | 1503 | unsigned long flags; |
1da177e4 | 1504 | |
8542b200 ZA |
1505 | if (no_timer_check) |
1506 | return 1; | |
1507 | ||
4aae0702 | 1508 | local_save_flags(flags); |
1da177e4 LT |
1509 | local_irq_enable(); |
1510 | /* Let ten ticks pass... */ | |
1511 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 1512 | local_irq_restore(flags); |
1da177e4 LT |
1513 | |
1514 | /* | |
1515 | * Expect a few ticks at least, to be sure some possible | |
1516 | * glue logic does not lock up after one or two first | |
1517 | * ticks in a non-ExtINT mode. Also the local APIC | |
1518 | * might have cached one ExtINT interrupt. Finally, at | |
1519 | * least one tick may be lost due to delays. | |
1520 | */ | |
1d16b53e | 1521 | if (time_after(jiffies, t1 + 4)) |
1da177e4 LT |
1522 | return 1; |
1523 | ||
1524 | return 0; | |
1525 | } | |
1526 | ||
1527 | /* | |
1528 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
1529 | * number of pending IRQ events unhandled. These cases are very rare, | |
1530 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
1531 | * better to do it this way as thus we do not have to be aware of | |
1532 | * 'pending' interrupts in the IRQ path, except at this point. | |
1533 | */ | |
1534 | /* | |
1535 | * Edge triggered needs to resend any interrupt | |
1536 | * that was delayed but this is now handled in the device | |
1537 | * independent code. | |
1538 | */ | |
1539 | ||
1540 | /* | |
f5b9ed7a IM |
1541 | * Startup quirk: |
1542 | * | |
1da177e4 LT |
1543 | * Starting up a edge-triggered IO-APIC interrupt is |
1544 | * nasty - we need to make sure that we get the edge. | |
1545 | * If it is already asserted for some reason, we need | |
1546 | * return 1 to indicate that is was pending. | |
1547 | * | |
1548 | * This is not complete - we should be able to fake | |
1549 | * an edge even if it isn't on the 8259A... | |
f5b9ed7a IM |
1550 | * |
1551 | * (We do this for level-triggered IRQs too - it cannot hurt.) | |
1da177e4 | 1552 | */ |
f5b9ed7a | 1553 | static unsigned int startup_ioapic_irq(unsigned int irq) |
1da177e4 LT |
1554 | { |
1555 | int was_pending = 0; | |
1556 | unsigned long flags; | |
1557 | ||
1558 | spin_lock_irqsave(&ioapic_lock, flags); | |
1559 | if (irq < 16) { | |
1560 | disable_8259A_irq(irq); | |
1561 | if (i8259A_irq_pending(irq)) | |
1562 | was_pending = 1; | |
1563 | } | |
1564 | __unmask_IO_APIC_irq(irq); | |
1565 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1566 | ||
1567 | return was_pending; | |
1568 | } | |
1569 | ||
f5b9ed7a | 1570 | static void ack_ioapic_irq(unsigned int irq) |
1da177e4 | 1571 | { |
ace80ab7 | 1572 | move_native_irq(irq); |
1da177e4 LT |
1573 | ack_APIC_irq(); |
1574 | } | |
1575 | ||
f5b9ed7a | 1576 | static void ack_ioapic_quirk_irq(unsigned int irq) |
1da177e4 LT |
1577 | { |
1578 | unsigned long v; | |
1579 | int i; | |
1580 | ||
ace80ab7 | 1581 | move_native_irq(irq); |
1da177e4 LT |
1582 | /* |
1583 | * It appears there is an erratum which affects at least version 0x11 | |
1584 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
1585 | * chipsets). Under certain conditions a level-triggered interrupt is | |
1586 | * erroneously delivered as edge-triggered one but the respective IRR | |
1587 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
1588 | * message but it will never arrive and further interrupts are blocked | |
1589 | * from the source. The exact reason is so far unknown, but the | |
1590 | * phenomenon was observed when two consecutive interrupt requests | |
1591 | * from a given source get delivered to the same CPU and the source is | |
1592 | * temporarily disabled in between. | |
1593 | * | |
1594 | * A workaround is to simulate an EOI message manually. We achieve it | |
1595 | * by setting the trigger mode to edge and then to level when the edge | |
1596 | * trigger mode gets detected in the TMR of a local APIC for a | |
1597 | * level-triggered interrupt. We mask the source for the time of the | |
1598 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
1599 | * The idea is from Manfred Spraul. --macro | |
1600 | */ | |
b940d22d | 1601 | i = irq_vector[irq]; |
1da177e4 LT |
1602 | |
1603 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); | |
1604 | ||
1605 | ack_APIC_irq(); | |
1606 | ||
1607 | if (!(v & (1 << (i & 0x1f)))) { | |
1608 | atomic_inc(&irq_mis_count); | |
1609 | spin_lock(&ioapic_lock); | |
1610 | __mask_and_edge_IO_APIC_irq(irq); | |
1611 | __unmask_and_level_IO_APIC_irq(irq); | |
1612 | spin_unlock(&ioapic_lock); | |
1613 | } | |
1614 | } | |
1615 | ||
ace80ab7 | 1616 | static int ioapic_retrigger_irq(unsigned int irq) |
1da177e4 | 1617 | { |
b940d22d | 1618 | send_IPI_self(irq_vector[irq]); |
c0ad90a3 IM |
1619 | |
1620 | return 1; | |
1621 | } | |
1622 | ||
f5b9ed7a IM |
1623 | static struct irq_chip ioapic_chip __read_mostly = { |
1624 | .name = "IO-APIC", | |
ace80ab7 EB |
1625 | .startup = startup_ioapic_irq, |
1626 | .mask = mask_IO_APIC_irq, | |
1627 | .unmask = unmask_IO_APIC_irq, | |
1628 | .ack = ack_ioapic_irq, | |
1629 | .eoi = ack_ioapic_quirk_irq, | |
54d5d424 | 1630 | #ifdef CONFIG_SMP |
ace80ab7 | 1631 | .set_affinity = set_ioapic_affinity_irq, |
54d5d424 | 1632 | #endif |
ace80ab7 | 1633 | .retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
1634 | }; |
1635 | ||
1da177e4 LT |
1636 | |
1637 | static inline void init_IO_APIC_traps(void) | |
1638 | { | |
1639 | int irq; | |
08678b08 | 1640 | struct irq_desc *desc; |
1da177e4 LT |
1641 | |
1642 | /* | |
1643 | * NOTE! The local APIC isn't very good at handling | |
1644 | * multiple interrupts at the same interrupt level. | |
1645 | * As the interrupt level is determined by taking the | |
1646 | * vector number and shifting that right by 4, we | |
1647 | * want to spread these out a bit so that they don't | |
1648 | * all fall in the same interrupt level. | |
1649 | * | |
1650 | * Also, we've got to be careful not to trash gate | |
1651 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
1652 | */ | |
0799e432 | 1653 | for (irq = 0; irq < nr_irqs ; irq++) { |
addfc66b | 1654 | if (IO_APIC_IRQ(irq) && !irq_vector[irq]) { |
1da177e4 LT |
1655 | /* |
1656 | * Hmm.. We don't have an entry for this, | |
1657 | * so default to an old-fashioned 8259 | |
1658 | * interrupt if we can.. | |
1659 | */ | |
1660 | if (irq < 16) | |
1661 | make_8259A_irq(irq); | |
08678b08 YL |
1662 | else { |
1663 | desc = irq_to_desc(irq); | |
1da177e4 | 1664 | /* Strange. Oh, well.. */ |
08678b08 YL |
1665 | desc->chip = &no_irq_chip; |
1666 | } | |
1da177e4 LT |
1667 | } |
1668 | } | |
1669 | } | |
1670 | ||
f5b9ed7a IM |
1671 | /* |
1672 | * The local APIC irq-chip implementation: | |
1673 | */ | |
1da177e4 | 1674 | |
c88ac1df | 1675 | static void ack_lapic_irq(unsigned int irq) |
f5b9ed7a IM |
1676 | { |
1677 | ack_APIC_irq(); | |
1da177e4 LT |
1678 | } |
1679 | ||
36062448 | 1680 | static void mask_lapic_irq(unsigned int irq) |
1da177e4 LT |
1681 | { |
1682 | unsigned long v; | |
1683 | ||
1684 | v = apic_read(APIC_LVT0); | |
593f4a78 | 1685 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
1686 | } |
1687 | ||
36062448 | 1688 | static void unmask_lapic_irq(unsigned int irq) |
1da177e4 | 1689 | { |
f5b9ed7a | 1690 | unsigned long v; |
1da177e4 | 1691 | |
f5b9ed7a | 1692 | v = apic_read(APIC_LVT0); |
593f4a78 | 1693 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
f5b9ed7a | 1694 | } |
1da177e4 | 1695 | |
f5b9ed7a | 1696 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 1697 | .name = "local-APIC", |
f5b9ed7a IM |
1698 | .mask = mask_lapic_irq, |
1699 | .unmask = unmask_lapic_irq, | |
c88ac1df | 1700 | .ack = ack_lapic_irq, |
1da177e4 LT |
1701 | }; |
1702 | ||
c88ac1df MR |
1703 | static void lapic_register_intr(int irq, int vector) |
1704 | { | |
08678b08 YL |
1705 | struct irq_desc *desc; |
1706 | ||
1707 | desc = irq_to_desc(irq); | |
1708 | desc->status &= ~IRQ_LEVEL; | |
c88ac1df MR |
1709 | set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
1710 | "edge"); | |
1711 | set_intr_gate(vector, interrupt[irq]); | |
1712 | } | |
1713 | ||
e9427101 | 1714 | static void __init setup_nmi(void) |
1da177e4 LT |
1715 | { |
1716 | /* | |
36062448 | 1717 | * Dirty trick to enable the NMI watchdog ... |
1da177e4 LT |
1718 | * We put the 8259A master into AEOI mode and |
1719 | * unmask on all local APICs LVT0 as NMI. | |
1720 | * | |
1721 | * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') | |
1722 | * is from Maciej W. Rozycki - so we do not have to EOI from | |
1723 | * the NMI handler or the timer interrupt. | |
36062448 | 1724 | */ |
1da177e4 LT |
1725 | apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ..."); |
1726 | ||
e9427101 | 1727 | enable_NMI_through_LVT0(); |
1da177e4 LT |
1728 | |
1729 | apic_printk(APIC_VERBOSE, " done.\n"); | |
1730 | } | |
1731 | ||
1732 | /* | |
1733 | * This looks a bit hackish but it's about the only one way of sending | |
1734 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
1735 | * not support the ExtINT mode, unfortunately. We need to send these | |
1736 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
1737 | * 8259A interrupt line asserted until INTA. --macro | |
1738 | */ | |
28acf285 | 1739 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 1740 | { |
fcfd636a | 1741 | int apic, pin, i; |
1da177e4 LT |
1742 | struct IO_APIC_route_entry entry0, entry1; |
1743 | unsigned char save_control, save_freq_select; | |
1da177e4 | 1744 | |
fcfd636a | 1745 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
1746 | if (pin == -1) { |
1747 | WARN_ON_ONCE(1); | |
1748 | return; | |
1749 | } | |
fcfd636a | 1750 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
1751 | if (apic == -1) { |
1752 | WARN_ON_ONCE(1); | |
1da177e4 | 1753 | return; |
956fb531 | 1754 | } |
1da177e4 | 1755 | |
cf4c6a2f | 1756 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 1757 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
1758 | |
1759 | memset(&entry1, 0, sizeof(entry1)); | |
1760 | ||
1761 | entry1.dest_mode = 0; /* physical delivery */ | |
1762 | entry1.mask = 0; /* unmask IRQ now */ | |
1763 | entry1.dest.physical.physical_dest = hard_smp_processor_id(); | |
1764 | entry1.delivery_mode = dest_ExtINT; | |
1765 | entry1.polarity = entry0.polarity; | |
1766 | entry1.trigger = 0; | |
1767 | entry1.vector = 0; | |
1768 | ||
cf4c6a2f | 1769 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
1770 | |
1771 | save_control = CMOS_READ(RTC_CONTROL); | |
1772 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
1773 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
1774 | RTC_FREQ_SELECT); | |
1775 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
1776 | ||
1777 | i = 100; | |
1778 | while (i-- > 0) { | |
1779 | mdelay(10); | |
1780 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
1781 | i -= 10; | |
1782 | } | |
1783 | ||
1784 | CMOS_WRITE(save_control, RTC_CONTROL); | |
1785 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 1786 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 1787 | |
cf4c6a2f | 1788 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
1789 | } |
1790 | ||
1791 | /* | |
1792 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
1793 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
1794 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
1795 | * fanatically on his truly buggy board. | |
1796 | */ | |
8542b200 | 1797 | static inline void __init check_timer(void) |
1da177e4 | 1798 | { |
fcfd636a | 1799 | int apic1, pin1, apic2, pin2; |
691874fa | 1800 | int no_pin1 = 0; |
1da177e4 | 1801 | int vector; |
6e908947 | 1802 | unsigned int ver; |
4aae0702 IM |
1803 | unsigned long flags; |
1804 | ||
1805 | local_irq_save(flags); | |
d4d25dec | 1806 | |
6e908947 IM |
1807 | ver = apic_read(APIC_LVR); |
1808 | ver = GET_APIC_VERSION(ver); | |
1809 | ||
1da177e4 LT |
1810 | /* |
1811 | * get/set the timer IRQ vector: | |
1812 | */ | |
1813 | disable_8259A_irq(0); | |
1814 | vector = assign_irq_vector(0); | |
1815 | set_intr_gate(vector, interrupt[0]); | |
1816 | ||
1817 | /* | |
d11d5794 MR |
1818 | * As IRQ0 is to be enabled in the 8259A, the virtual |
1819 | * wire has to be disabled in the local APIC. Also | |
1820 | * timer interrupts need to be acknowledged manually in | |
1821 | * the 8259A for the i82489DX when using the NMI | |
1822 | * watchdog as that APIC treats NMIs as level-triggered. | |
1823 | * The AEOI mode will finish them in the 8259A | |
1824 | * automatically. | |
1da177e4 | 1825 | */ |
593f4a78 | 1826 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
1da177e4 | 1827 | init_8259A(1); |
d11d5794 | 1828 | timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver)); |
1da177e4 | 1829 | |
fcfd636a EB |
1830 | pin1 = find_isa_irq_pin(0, mp_INT); |
1831 | apic1 = find_isa_irq_apic(0, mp_INT); | |
1832 | pin2 = ioapic_i8259.pin; | |
1833 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 1834 | |
49a66a0b MR |
1835 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
1836 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", | |
1837 | vector, apic1, pin1, apic2, pin2); | |
1da177e4 | 1838 | |
691874fa MR |
1839 | /* |
1840 | * Some BIOS writers are clueless and report the ExtINTA | |
1841 | * I/O APIC input from the cascaded 8259A as the timer | |
1842 | * interrupt input. So just in case, if only one pin | |
1843 | * was found above, try it both directly and through the | |
1844 | * 8259A. | |
1845 | */ | |
1846 | if (pin1 == -1) { | |
1847 | pin1 = pin2; | |
1848 | apic1 = apic2; | |
1849 | no_pin1 = 1; | |
1850 | } else if (pin2 == -1) { | |
1851 | pin2 = pin1; | |
1852 | apic2 = apic1; | |
1853 | } | |
1854 | ||
1da177e4 LT |
1855 | if (pin1 != -1) { |
1856 | /* | |
1857 | * Ok, does IRQ0 through the IOAPIC work? | |
1858 | */ | |
691874fa MR |
1859 | if (no_pin1) { |
1860 | add_pin_to_irq(0, apic1, pin1); | |
1861 | setup_timer_IRQ0_pin(apic1, pin1, vector); | |
1862 | } | |
1da177e4 LT |
1863 | unmask_IO_APIC_irq(0); |
1864 | if (timer_irq_works()) { | |
1865 | if (nmi_watchdog == NMI_IO_APIC) { | |
1da177e4 LT |
1866 | setup_nmi(); |
1867 | enable_8259A_irq(0); | |
1da177e4 | 1868 | } |
66759a01 CE |
1869 | if (disable_timer_pin_1 > 0) |
1870 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 1871 | goto out; |
1da177e4 | 1872 | } |
fcfd636a | 1873 | clear_IO_APIC_pin(apic1, pin1); |
691874fa | 1874 | if (!no_pin1) |
49a66a0b MR |
1875 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
1876 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 1877 | |
49a66a0b MR |
1878 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
1879 | "(IRQ0) through the 8259A ...\n"); | |
1880 | apic_printk(APIC_QUIET, KERN_INFO | |
1881 | "..... (found apic %d pin %d) ...\n", apic2, pin2); | |
1da177e4 LT |
1882 | /* |
1883 | * legacy devices should be connected to IO APIC #0 | |
1884 | */ | |
691874fa | 1885 | replace_pin_at_irq(0, apic1, pin1, apic2, pin2); |
f7633ce5 | 1886 | setup_timer_IRQ0_pin(apic2, pin2, vector); |
24742ece | 1887 | unmask_IO_APIC_irq(0); |
ecd29476 | 1888 | enable_8259A_irq(0); |
1da177e4 | 1889 | if (timer_irq_works()) { |
49a66a0b | 1890 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
35542c5e | 1891 | timer_through_8259 = 1; |
1da177e4 | 1892 | if (nmi_watchdog == NMI_IO_APIC) { |
60134ebe | 1893 | disable_8259A_irq(0); |
1da177e4 | 1894 | setup_nmi(); |
60134ebe | 1895 | enable_8259A_irq(0); |
1da177e4 | 1896 | } |
4aae0702 | 1897 | goto out; |
1da177e4 LT |
1898 | } |
1899 | /* | |
1900 | * Cleanup, just in case ... | |
1901 | */ | |
ecd29476 | 1902 | disable_8259A_irq(0); |
fcfd636a | 1903 | clear_IO_APIC_pin(apic2, pin2); |
49a66a0b | 1904 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
1da177e4 | 1905 | } |
1da177e4 LT |
1906 | |
1907 | if (nmi_watchdog == NMI_IO_APIC) { | |
49a66a0b MR |
1908 | apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work " |
1909 | "through the IO-APIC - disabling NMI Watchdog!\n"); | |
067fa0ff | 1910 | nmi_watchdog = NMI_NONE; |
1da177e4 | 1911 | } |
d11d5794 | 1912 | timer_ack = 0; |
1da177e4 | 1913 | |
49a66a0b MR |
1914 | apic_printk(APIC_QUIET, KERN_INFO |
1915 | "...trying to set up timer as Virtual Wire IRQ...\n"); | |
1da177e4 | 1916 | |
c88ac1df | 1917 | lapic_register_intr(0, vector); |
593f4a78 | 1918 | apic_write(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */ |
1da177e4 LT |
1919 | enable_8259A_irq(0); |
1920 | ||
1921 | if (timer_irq_works()) { | |
49a66a0b | 1922 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 1923 | goto out; |
1da177e4 | 1924 | } |
e67465f1 | 1925 | disable_8259A_irq(0); |
593f4a78 | 1926 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector); |
49a66a0b | 1927 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
1da177e4 | 1928 | |
49a66a0b MR |
1929 | apic_printk(APIC_QUIET, KERN_INFO |
1930 | "...trying to set up timer as ExtINT IRQ...\n"); | |
1da177e4 | 1931 | |
1da177e4 LT |
1932 | init_8259A(0); |
1933 | make_8259A_irq(0); | |
593f4a78 | 1934 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
1935 | |
1936 | unlock_ExtINT_logic(); | |
1937 | ||
1938 | if (timer_irq_works()) { | |
49a66a0b | 1939 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 1940 | goto out; |
1da177e4 | 1941 | } |
49a66a0b | 1942 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
1da177e4 | 1943 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
49a66a0b | 1944 | "report. Then try booting with the 'noapic' option.\n"); |
4aae0702 IM |
1945 | out: |
1946 | local_irq_restore(flags); | |
1da177e4 LT |
1947 | } |
1948 | ||
1949 | /* | |
af174783 MR |
1950 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
1951 | * to devices. However there may be an I/O APIC pin available for | |
1952 | * this interrupt regardless. The pin may be left unconnected, but | |
1953 | * typically it will be reused as an ExtINT cascade interrupt for | |
1954 | * the master 8259A. In the MPS case such a pin will normally be | |
1955 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
1956 | * there is no provision for ExtINT interrupts, and in the absence | |
1957 | * of an override it would be treated as an ordinary ISA I/O APIC | |
1958 | * interrupt, that is edge-triggered and unmasked by default. We | |
1959 | * used to do this, but it caused problems on some systems because | |
1960 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
1961 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
1962 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
1963 | * the I/O APIC in all cases now. No actual device should request | |
1964 | * it anyway. --macro | |
1da177e4 LT |
1965 | */ |
1966 | #define PIC_IRQS (1 << PIC_CASCADE_IR) | |
1967 | ||
1968 | void __init setup_IO_APIC(void) | |
1969 | { | |
dbeb2be2 RR |
1970 | int i; |
1971 | ||
1972 | /* Reserve all the system vectors. */ | |
305b92a2 | 1973 | for (i = first_system_vector; i < NR_VECTORS; i++) |
dbeb2be2 RR |
1974 | set_bit(i, used_vectors); |
1975 | ||
1da177e4 LT |
1976 | enable_IO_APIC(); |
1977 | ||
af174783 | 1978 | io_apic_irqs = ~PIC_IRQS; |
1da177e4 LT |
1979 | |
1980 | printk("ENABLING IO-APIC IRQs\n"); | |
1981 | ||
1982 | /* | |
1983 | * Set up IO-APIC IRQ routing. | |
1984 | */ | |
1985 | if (!acpi_ioapic) | |
1986 | setup_ioapic_ids_from_mpc(); | |
1987 | sync_Arb_IDs(); | |
1988 | setup_IO_APIC_irqs(); | |
1989 | init_IO_APIC_traps(); | |
1e4c85f9 | 1990 | check_timer(); |
1da177e4 LT |
1991 | } |
1992 | ||
1993 | /* | |
1994 | * Called after all the initialization is done. If we didnt find any | |
1995 | * APIC bugs then we can allow the modify fast path | |
1996 | */ | |
36062448 | 1997 | |
1da177e4 LT |
1998 | static int __init io_apic_bug_finalize(void) |
1999 | { | |
36062448 | 2000 | if (sis_apic_bug == -1) |
1da177e4 LT |
2001 | sis_apic_bug = 0; |
2002 | return 0; | |
2003 | } | |
2004 | ||
2005 | late_initcall(io_apic_bug_finalize); | |
2006 | ||
2007 | struct sysfs_ioapic_data { | |
2008 | struct sys_device dev; | |
2009 | struct IO_APIC_route_entry entry[0]; | |
2010 | }; | |
36062448 | 2011 | static struct sysfs_ioapic_data *mp_ioapic_data[MAX_IO_APICS]; |
1da177e4 | 2012 | |
438510f6 | 2013 | static int ioapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
2014 | { |
2015 | struct IO_APIC_route_entry *entry; | |
2016 | struct sysfs_ioapic_data *data; | |
1da177e4 | 2017 | int i; |
36062448 | 2018 | |
1da177e4 LT |
2019 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
2020 | entry = data->entry; | |
36062448 | 2021 | for (i = 0; i < nr_ioapic_registers[dev->id]; i++) |
cf4c6a2f | 2022 | entry[i] = ioapic_read_entry(dev->id, i); |
1da177e4 LT |
2023 | |
2024 | return 0; | |
2025 | } | |
2026 | ||
2027 | static int ioapic_resume(struct sys_device *dev) | |
2028 | { | |
2029 | struct IO_APIC_route_entry *entry; | |
2030 | struct sysfs_ioapic_data *data; | |
2031 | unsigned long flags; | |
2032 | union IO_APIC_reg_00 reg_00; | |
2033 | int i; | |
36062448 | 2034 | |
1da177e4 LT |
2035 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
2036 | entry = data->entry; | |
2037 | ||
2038 | spin_lock_irqsave(&ioapic_lock, flags); | |
2039 | reg_00.raw = io_apic_read(dev->id, 0); | |
ec2cd0a2 AS |
2040 | if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) { |
2041 | reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid; | |
1da177e4 LT |
2042 | io_apic_write(dev->id, 0, reg_00.raw); |
2043 | } | |
1da177e4 | 2044 | spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 2045 | for (i = 0; i < nr_ioapic_registers[dev->id]; i++) |
cf4c6a2f | 2046 | ioapic_write_entry(dev->id, i, entry[i]); |
1da177e4 LT |
2047 | |
2048 | return 0; | |
2049 | } | |
2050 | ||
2051 | static struct sysdev_class ioapic_sysdev_class = { | |
af5ca3f4 | 2052 | .name = "ioapic", |
1da177e4 LT |
2053 | .suspend = ioapic_suspend, |
2054 | .resume = ioapic_resume, | |
2055 | }; | |
2056 | ||
2057 | static int __init ioapic_init_sysfs(void) | |
2058 | { | |
36062448 | 2059 | struct sys_device *dev; |
1da177e4 LT |
2060 | int i, size, error = 0; |
2061 | ||
2062 | error = sysdev_class_register(&ioapic_sysdev_class); | |
2063 | if (error) | |
2064 | return error; | |
2065 | ||
36062448 PC |
2066 | for (i = 0; i < nr_ioapics; i++) { |
2067 | size = sizeof(struct sys_device) + nr_ioapic_registers[i] | |
1da177e4 | 2068 | * sizeof(struct IO_APIC_route_entry); |
25556c16 | 2069 | mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL); |
1da177e4 LT |
2070 | if (!mp_ioapic_data[i]) { |
2071 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
2072 | continue; | |
2073 | } | |
1da177e4 | 2074 | dev = &mp_ioapic_data[i]->dev; |
36062448 | 2075 | dev->id = i; |
1da177e4 LT |
2076 | dev->cls = &ioapic_sysdev_class; |
2077 | error = sysdev_register(dev); | |
2078 | if (error) { | |
2079 | kfree(mp_ioapic_data[i]); | |
2080 | mp_ioapic_data[i] = NULL; | |
2081 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
2082 | continue; | |
2083 | } | |
2084 | } | |
2085 | ||
2086 | return 0; | |
2087 | } | |
2088 | ||
2089 | device_initcall(ioapic_init_sysfs); | |
2090 | ||
3fc471ed | 2091 | /* |
95d77884 | 2092 | * Dynamic irq allocate and deallocation |
3fc471ed EB |
2093 | */ |
2094 | int create_irq(void) | |
2095 | { | |
ace80ab7 | 2096 | /* Allocate an unused irq */ |
306a22c2 | 2097 | int irq, new, vector = 0; |
3fc471ed | 2098 | unsigned long flags; |
3fc471ed | 2099 | |
ace80ab7 EB |
2100 | irq = -ENOSPC; |
2101 | spin_lock_irqsave(&vector_lock, flags); | |
0799e432 | 2102 | for (new = (nr_irqs - 1); new >= 0; new--) { |
ace80ab7 EB |
2103 | if (platform_legacy_irq(new)) |
2104 | continue; | |
2105 | if (irq_vector[new] != 0) | |
2106 | continue; | |
2107 | vector = __assign_irq_vector(new); | |
2108 | if (likely(vector > 0)) | |
2109 | irq = new; | |
2110 | break; | |
2111 | } | |
2112 | spin_unlock_irqrestore(&vector_lock, flags); | |
3fc471ed | 2113 | |
ace80ab7 | 2114 | if (irq >= 0) { |
3fc471ed | 2115 | set_intr_gate(vector, interrupt[irq]); |
3fc471ed EB |
2116 | dynamic_irq_init(irq); |
2117 | } | |
2118 | return irq; | |
2119 | } | |
2120 | ||
2121 | void destroy_irq(unsigned int irq) | |
2122 | { | |
2123 | unsigned long flags; | |
3fc471ed EB |
2124 | |
2125 | dynamic_irq_cleanup(irq); | |
2126 | ||
2127 | spin_lock_irqsave(&vector_lock, flags); | |
9d9ad4b5 | 2128 | clear_bit(irq_vector[irq], used_vectors); |
3fc471ed EB |
2129 | irq_vector[irq] = 0; |
2130 | spin_unlock_irqrestore(&vector_lock, flags); | |
2131 | } | |
3fc471ed | 2132 | |
2d3fcc1c | 2133 | /* |
27b46d76 | 2134 | * MSI message composition |
2d3fcc1c EB |
2135 | */ |
2136 | #ifdef CONFIG_PCI_MSI | |
3b7d1921 | 2137 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg) |
2d3fcc1c | 2138 | { |
2d3fcc1c EB |
2139 | int vector; |
2140 | unsigned dest; | |
2141 | ||
2142 | vector = assign_irq_vector(irq); | |
2143 | if (vector >= 0) { | |
2144 | dest = cpu_mask_to_apicid(TARGET_CPUS); | |
2145 | ||
2146 | msg->address_hi = MSI_ADDR_BASE_HI; | |
2147 | msg->address_lo = | |
2148 | MSI_ADDR_BASE_LO | | |
2149 | ((INT_DEST_MODE == 0) ? | |
36062448 | 2150 | MSI_ADDR_DEST_MODE_PHYSICAL: |
2d3fcc1c EB |
2151 | MSI_ADDR_DEST_MODE_LOGICAL) | |
2152 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
2153 | MSI_ADDR_REDIRECTION_CPU: | |
2154 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
2155 | MSI_ADDR_DEST_ID(dest); | |
2156 | ||
2157 | msg->data = | |
2158 | MSI_DATA_TRIGGER_EDGE | | |
2159 | MSI_DATA_LEVEL_ASSERT | | |
2160 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
36062448 | 2161 | MSI_DATA_DELIVERY_FIXED: |
2d3fcc1c EB |
2162 | MSI_DATA_DELIVERY_LOWPRI) | |
2163 | MSI_DATA_VECTOR(vector); | |
2164 | } | |
2165 | return vector; | |
2166 | } | |
2167 | ||
3b7d1921 EB |
2168 | #ifdef CONFIG_SMP |
2169 | static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask) | |
2d3fcc1c | 2170 | { |
3b7d1921 EB |
2171 | struct msi_msg msg; |
2172 | unsigned int dest; | |
2173 | cpumask_t tmp; | |
2d3fcc1c | 2174 | int vector; |
08678b08 | 2175 | struct irq_desc *desc; |
3b7d1921 EB |
2176 | |
2177 | cpus_and(tmp, mask, cpu_online_map); | |
2178 | if (cpus_empty(tmp)) | |
2179 | tmp = TARGET_CPUS; | |
2d3fcc1c EB |
2180 | |
2181 | vector = assign_irq_vector(irq); | |
3b7d1921 EB |
2182 | if (vector < 0) |
2183 | return; | |
2d3fcc1c | 2184 | |
3b7d1921 EB |
2185 | dest = cpu_mask_to_apicid(mask); |
2186 | ||
2187 | read_msi_msg(irq, &msg); | |
2188 | ||
2189 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
2190 | msg.data |= MSI_DATA_VECTOR(vector); | |
2191 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
2192 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
2193 | ||
2194 | write_msi_msg(irq, &msg); | |
08678b08 YL |
2195 | desc = irq_to_desc(irq); |
2196 | desc->affinity = mask; | |
2d3fcc1c | 2197 | } |
3b7d1921 | 2198 | #endif /* CONFIG_SMP */ |
2d3fcc1c | 2199 | |
3b7d1921 EB |
2200 | /* |
2201 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
2202 | * which implement the MSI or MSI-X Capability Structure. | |
2203 | */ | |
2204 | static struct irq_chip msi_chip = { | |
2205 | .name = "PCI-MSI", | |
2206 | .unmask = unmask_msi_irq, | |
2207 | .mask = mask_msi_irq, | |
2208 | .ack = ack_ioapic_irq, | |
2209 | #ifdef CONFIG_SMP | |
2210 | .set_affinity = set_msi_irq_affinity, | |
2211 | #endif | |
2212 | .retrigger = ioapic_retrigger_irq, | |
2d3fcc1c EB |
2213 | }; |
2214 | ||
f7feaca7 | 2215 | int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) |
3b7d1921 EB |
2216 | { |
2217 | struct msi_msg msg; | |
f7feaca7 EB |
2218 | int irq, ret; |
2219 | irq = create_irq(); | |
2220 | if (irq < 0) | |
2221 | return irq; | |
2222 | ||
3b7d1921 | 2223 | ret = msi_compose_msg(dev, irq, &msg); |
f7feaca7 EB |
2224 | if (ret < 0) { |
2225 | destroy_irq(irq); | |
3b7d1921 | 2226 | return ret; |
f7feaca7 | 2227 | } |
3b7d1921 | 2228 | |
7fe3730d | 2229 | set_irq_msi(irq, desc); |
3b7d1921 EB |
2230 | write_msi_msg(irq, &msg); |
2231 | ||
a460e745 IM |
2232 | set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, |
2233 | "edge"); | |
3b7d1921 | 2234 | |
7fe3730d | 2235 | return 0; |
3b7d1921 EB |
2236 | } |
2237 | ||
2238 | void arch_teardown_msi_irq(unsigned int irq) | |
2239 | { | |
f7feaca7 | 2240 | destroy_irq(irq); |
3b7d1921 EB |
2241 | } |
2242 | ||
2d3fcc1c EB |
2243 | #endif /* CONFIG_PCI_MSI */ |
2244 | ||
8b955b0d EB |
2245 | /* |
2246 | * Hypertransport interrupt support | |
2247 | */ | |
2248 | #ifdef CONFIG_HT_IRQ | |
2249 | ||
2250 | #ifdef CONFIG_SMP | |
2251 | ||
2252 | static void target_ht_irq(unsigned int irq, unsigned int dest) | |
2253 | { | |
ec68307c EB |
2254 | struct ht_irq_msg msg; |
2255 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 2256 | |
ec68307c EB |
2257 | msg.address_lo &= ~(HT_IRQ_LOW_DEST_ID_MASK); |
2258 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); | |
8b955b0d | 2259 | |
ec68307c EB |
2260 | msg.address_lo |= HT_IRQ_LOW_DEST_ID(dest); |
2261 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); | |
8b955b0d | 2262 | |
ec68307c | 2263 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
2264 | } |
2265 | ||
2266 | static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask) | |
2267 | { | |
2268 | unsigned int dest; | |
2269 | cpumask_t tmp; | |
08678b08 | 2270 | struct irq_desc *desc; |
8b955b0d EB |
2271 | |
2272 | cpus_and(tmp, mask, cpu_online_map); | |
2273 | if (cpus_empty(tmp)) | |
2274 | tmp = TARGET_CPUS; | |
2275 | ||
2276 | cpus_and(mask, tmp, CPU_MASK_ALL); | |
2277 | ||
2278 | dest = cpu_mask_to_apicid(mask); | |
2279 | ||
2280 | target_ht_irq(irq, dest); | |
08678b08 YL |
2281 | desc = irq_to_desc(irq); |
2282 | desc->affinity = mask; | |
8b955b0d EB |
2283 | } |
2284 | #endif | |
2285 | ||
c37e108d | 2286 | static struct irq_chip ht_irq_chip = { |
8b955b0d EB |
2287 | .name = "PCI-HT", |
2288 | .mask = mask_ht_irq, | |
2289 | .unmask = unmask_ht_irq, | |
2290 | .ack = ack_ioapic_irq, | |
2291 | #ifdef CONFIG_SMP | |
2292 | .set_affinity = set_ht_irq_affinity, | |
2293 | #endif | |
2294 | .retrigger = ioapic_retrigger_irq, | |
2295 | }; | |
2296 | ||
2297 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
2298 | { | |
2299 | int vector; | |
2300 | ||
2301 | vector = assign_irq_vector(irq); | |
2302 | if (vector >= 0) { | |
ec68307c | 2303 | struct ht_irq_msg msg; |
8b955b0d EB |
2304 | unsigned dest; |
2305 | cpumask_t tmp; | |
2306 | ||
2307 | cpus_clear(tmp); | |
2308 | cpu_set(vector >> 8, tmp); | |
2309 | dest = cpu_mask_to_apicid(tmp); | |
2310 | ||
ec68307c | 2311 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 2312 | |
ec68307c EB |
2313 | msg.address_lo = |
2314 | HT_IRQ_LOW_BASE | | |
8b955b0d EB |
2315 | HT_IRQ_LOW_DEST_ID(dest) | |
2316 | HT_IRQ_LOW_VECTOR(vector) | | |
2317 | ((INT_DEST_MODE == 0) ? | |
2318 | HT_IRQ_LOW_DM_PHYSICAL : | |
2319 | HT_IRQ_LOW_DM_LOGICAL) | | |
2320 | HT_IRQ_LOW_RQEOI_EDGE | | |
2321 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
2322 | HT_IRQ_LOW_MT_FIXED : | |
2323 | HT_IRQ_LOW_MT_ARBITRATED) | | |
2324 | HT_IRQ_LOW_IRQ_MASKED; | |
2325 | ||
ec68307c | 2326 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 2327 | |
a460e745 IM |
2328 | set_irq_chip_and_handler_name(irq, &ht_irq_chip, |
2329 | handle_edge_irq, "edge"); | |
8b955b0d EB |
2330 | } |
2331 | return vector; | |
2332 | } | |
2333 | #endif /* CONFIG_HT_IRQ */ | |
2334 | ||
1da177e4 | 2335 | /* -------------------------------------------------------------------------- |
36062448 | 2336 | ACPI-based IOAPIC Configuration |
1da177e4 LT |
2337 | -------------------------------------------------------------------------- */ |
2338 | ||
888ba6c6 | 2339 | #ifdef CONFIG_ACPI |
1da177e4 | 2340 | |
36062448 | 2341 | int __init io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
2342 | { |
2343 | union IO_APIC_reg_00 reg_00; | |
2344 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
2345 | physid_mask_t tmp; | |
2346 | unsigned long flags; | |
2347 | int i = 0; | |
2348 | ||
2349 | /* | |
36062448 PC |
2350 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
2351 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 2352 | * supports up to 16 on one shared APIC bus. |
36062448 | 2353 | * |
1da177e4 LT |
2354 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
2355 | * advantage of new APIC bus architecture. | |
2356 | */ | |
2357 | ||
2358 | if (physids_empty(apic_id_map)) | |
2359 | apic_id_map = ioapic_phys_id_map(phys_cpu_present_map); | |
2360 | ||
2361 | spin_lock_irqsave(&ioapic_lock, flags); | |
2362 | reg_00.raw = io_apic_read(ioapic, 0); | |
2363 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2364 | ||
2365 | if (apic_id >= get_physical_broadcast()) { | |
2366 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
2367 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
2368 | apic_id = reg_00.bits.ID; | |
2369 | } | |
2370 | ||
2371 | /* | |
36062448 | 2372 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
2373 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
2374 | */ | |
2375 | if (check_apicid_used(apic_id_map, apic_id)) { | |
2376 | ||
2377 | for (i = 0; i < get_physical_broadcast(); i++) { | |
2378 | if (!check_apicid_used(apic_id_map, i)) | |
2379 | break; | |
2380 | } | |
2381 | ||
2382 | if (i == get_physical_broadcast()) | |
2383 | panic("Max apic_id exceeded!\n"); | |
2384 | ||
2385 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
2386 | "trying %d\n", ioapic, apic_id, i); | |
2387 | ||
2388 | apic_id = i; | |
36062448 | 2389 | } |
1da177e4 LT |
2390 | |
2391 | tmp = apicid_to_cpu_present(apic_id); | |
2392 | physids_or(apic_id_map, apic_id_map, tmp); | |
2393 | ||
2394 | if (reg_00.bits.ID != apic_id) { | |
2395 | reg_00.bits.ID = apic_id; | |
2396 | ||
2397 | spin_lock_irqsave(&ioapic_lock, flags); | |
2398 | io_apic_write(ioapic, 0, reg_00.raw); | |
2399 | reg_00.raw = io_apic_read(ioapic, 0); | |
2400 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2401 | ||
2402 | /* Sanity check */ | |
6070f9ec AD |
2403 | if (reg_00.bits.ID != apic_id) { |
2404 | printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); | |
2405 | return -1; | |
2406 | } | |
1da177e4 LT |
2407 | } |
2408 | ||
2409 | apic_printk(APIC_VERBOSE, KERN_INFO | |
2410 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
2411 | ||
2412 | return apic_id; | |
2413 | } | |
2414 | ||
2415 | ||
36062448 | 2416 | int __init io_apic_get_version(int ioapic) |
1da177e4 LT |
2417 | { |
2418 | union IO_APIC_reg_01 reg_01; | |
2419 | unsigned long flags; | |
2420 | ||
2421 | spin_lock_irqsave(&ioapic_lock, flags); | |
2422 | reg_01.raw = io_apic_read(ioapic, 1); | |
2423 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2424 | ||
2425 | return reg_01.bits.version; | |
2426 | } | |
2427 | ||
2428 | ||
36062448 | 2429 | int __init io_apic_get_redir_entries(int ioapic) |
1da177e4 LT |
2430 | { |
2431 | union IO_APIC_reg_01 reg_01; | |
2432 | unsigned long flags; | |
2433 | ||
2434 | spin_lock_irqsave(&ioapic_lock, flags); | |
2435 | reg_01.raw = io_apic_read(ioapic, 1); | |
2436 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2437 | ||
2438 | return reg_01.bits.entries; | |
2439 | } | |
2440 | ||
2441 | ||
36062448 | 2442 | int io_apic_set_pci_routing(int ioapic, int pin, int irq, int edge_level, int active_high_low) |
1da177e4 LT |
2443 | { |
2444 | struct IO_APIC_route_entry entry; | |
1da177e4 LT |
2445 | |
2446 | if (!IO_APIC_IRQ(irq)) { | |
2447 | printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", | |
2448 | ioapic); | |
2449 | return -EINVAL; | |
2450 | } | |
2451 | ||
2452 | /* | |
2453 | * Generate a PCI IRQ routing entry and program the IOAPIC accordingly. | |
2454 | * Note that we mask (disable) IRQs now -- these get enabled when the | |
2455 | * corresponding device driver registers for this IRQ. | |
2456 | */ | |
2457 | ||
36062448 | 2458 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
2459 | |
2460 | entry.delivery_mode = INT_DELIVERY_MODE; | |
2461 | entry.dest_mode = INT_DEST_MODE; | |
2462 | entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS); | |
2463 | entry.trigger = edge_level; | |
2464 | entry.polarity = active_high_low; | |
2465 | entry.mask = 1; | |
2466 | ||
2467 | /* | |
2468 | * IRQs < 16 are already in the irq_2_pin[] map | |
2469 | */ | |
2470 | if (irq >= 16) | |
2471 | add_pin_to_irq(irq, ioapic, pin); | |
2472 | ||
2473 | entry.vector = assign_irq_vector(irq); | |
2474 | ||
2475 | apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry " | |
2476 | "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic, | |
ec2cd0a2 | 2477 | mp_ioapics[ioapic].mp_apicid, pin, entry.vector, irq, |
1da177e4 LT |
2478 | edge_level, active_high_low); |
2479 | ||
2480 | ioapic_register_intr(irq, entry.vector, edge_level); | |
2481 | ||
2482 | if (!ioapic && (irq < 16)) | |
2483 | disable_8259A_irq(irq); | |
2484 | ||
a2249cba | 2485 | ioapic_write_entry(ioapic, pin, entry); |
1da177e4 LT |
2486 | |
2487 | return 0; | |
2488 | } | |
2489 | ||
61fd47e0 SL |
2490 | int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity) |
2491 | { | |
2492 | int i; | |
2493 | ||
2494 | if (skip_ioapic_setup) | |
2495 | return -1; | |
2496 | ||
2497 | for (i = 0; i < mp_irq_entries; i++) | |
2fddb6e2 AS |
2498 | if (mp_irqs[i].mp_irqtype == mp_INT && |
2499 | mp_irqs[i].mp_srcbusirq == bus_irq) | |
61fd47e0 SL |
2500 | break; |
2501 | if (i >= mp_irq_entries) | |
2502 | return -1; | |
2503 | ||
2504 | *trigger = irq_trigger(i); | |
2505 | *polarity = irq_polarity(i); | |
2506 | return 0; | |
2507 | } | |
2508 | ||
888ba6c6 | 2509 | #endif /* CONFIG_ACPI */ |
1a3f239d RR |
2510 | |
2511 | static int __init parse_disable_timer_pin_1(char *arg) | |
2512 | { | |
2513 | disable_timer_pin_1 = 1; | |
2514 | return 0; | |
2515 | } | |
2516 | early_param("disable_timer_pin_1", parse_disable_timer_pin_1); | |
2517 | ||
2518 | static int __init parse_enable_timer_pin_1(char *arg) | |
2519 | { | |
2520 | disable_timer_pin_1 = -1; | |
2521 | return 0; | |
2522 | } | |
2523 | early_param("enable_timer_pin_1", parse_enable_timer_pin_1); | |
2524 | ||
2525 | static int __init parse_noapic(char *arg) | |
2526 | { | |
2527 | /* disable IO-APIC */ | |
2528 | disable_ioapic_setup(); | |
2529 | return 0; | |
2530 | } | |
2531 | early_param("noapic", parse_noapic); | |
f3294a33 YL |
2532 | |
2533 | void __init ioapic_init_mappings(void) | |
2534 | { | |
2535 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
2536 | int i; | |
2537 | ||
2538 | for (i = 0; i < nr_ioapics; i++) { | |
2539 | if (smp_found_config) { | |
2540 | ioapic_phys = mp_ioapics[i].mp_apicaddr; | |
2541 | if (!ioapic_phys) { | |
2542 | printk(KERN_ERR | |
2543 | "WARNING: bogus zero IO-APIC " | |
2544 | "address found in MPTABLE, " | |
2545 | "disabling IO/APIC support!\n"); | |
2546 | smp_found_config = 0; | |
2547 | skip_ioapic_setup = 1; | |
2548 | goto fake_ioapic_page; | |
2549 | } | |
2550 | } else { | |
2551 | fake_ioapic_page: | |
2552 | ioapic_phys = (unsigned long) | |
2553 | alloc_bootmem_pages(PAGE_SIZE); | |
2554 | ioapic_phys = __pa(ioapic_phys); | |
2555 | } | |
2556 | set_fixmap_nocache(idx, ioapic_phys); | |
2557 | printk(KERN_DEBUG "mapped IOAPIC to %08lx (%08lx)\n", | |
2558 | __fix_to_virt(idx), ioapic_phys); | |
2559 | idx++; | |
2560 | } | |
2561 | } | |
2562 |