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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
4 | * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo | |
5 | * | |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
1da177e4 LT |
28 | #include <linux/mc146818rtc.h> |
29 | #include <linux/compiler.h> | |
30 | #include <linux/acpi.h> | |
129f6946 | 31 | #include <linux/module.h> |
1da177e4 | 32 | #include <linux/sysdev.h> |
2d3fcc1c | 33 | #include <linux/pci.h> |
3b7d1921 | 34 | #include <linux/msi.h> |
95d77884 | 35 | #include <linux/htirq.h> |
7dfb7103 | 36 | #include <linux/freezer.h> |
f26d6a2b | 37 | #include <linux/kthread.h> |
54d5d424 | 38 | |
1da177e4 LT |
39 | #include <asm/io.h> |
40 | #include <asm/smp.h> | |
41 | #include <asm/desc.h> | |
42 | #include <asm/timer.h> | |
306e440d | 43 | #include <asm/i8259.h> |
3e4ff115 | 44 | #include <asm/nmi.h> |
2d3fcc1c | 45 | #include <asm/msidef.h> |
8b955b0d | 46 | #include <asm/hypertransport.h> |
1da177e4 LT |
47 | |
48 | #include <mach_apic.h> | |
874c4fe3 | 49 | #include <mach_apicdef.h> |
1da177e4 LT |
50 | |
51 | #include "io_ports.h" | |
52 | ||
53 | int (*ioapic_renumber_irq)(int ioapic, int irq); | |
54 | atomic_t irq_mis_count; | |
55 | ||
fcfd636a EB |
56 | /* Where if anywhere is the i8259 connect in external int mode */ |
57 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
58 | ||
1da177e4 | 59 | static DEFINE_SPINLOCK(ioapic_lock); |
0a1ad60d | 60 | static DEFINE_SPINLOCK(vector_lock); |
1da177e4 | 61 | |
f9262c12 AK |
62 | int timer_over_8254 __initdata = 1; |
63 | ||
1da177e4 LT |
64 | /* |
65 | * Is the SiS APIC rmw bug present ? | |
66 | * -1 = don't know, 0 = no, 1 = yes | |
67 | */ | |
68 | int sis_apic_bug = -1; | |
69 | ||
70 | /* | |
71 | * # of IRQ routing registers | |
72 | */ | |
73 | int nr_ioapic_registers[MAX_IO_APICS]; | |
74 | ||
1a3f239d | 75 | static int disable_timer_pin_1 __initdata; |
66759a01 | 76 | |
1da177e4 LT |
77 | /* |
78 | * Rough estimation of how many shared IRQs there are, can | |
79 | * be changed anytime. | |
80 | */ | |
81 | #define MAX_PLUS_SHARED_IRQS NR_IRQS | |
82 | #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS) | |
83 | ||
84 | /* | |
85 | * This is performance-critical, we want to do it O(1) | |
86 | * | |
87 | * the indexing order of this array favors 1:1 mappings | |
88 | * between pins and IRQs. | |
89 | */ | |
90 | ||
91 | static struct irq_pin_list { | |
92 | int apic, pin, next; | |
93 | } irq_2_pin[PIN_MAP_SIZE]; | |
94 | ||
130fe05d LT |
95 | struct io_apic { |
96 | unsigned int index; | |
97 | unsigned int unused[3]; | |
98 | unsigned int data; | |
99 | }; | |
100 | ||
101 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
102 | { | |
103 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
104 | + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK); | |
105 | } | |
106 | ||
107 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) | |
108 | { | |
109 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
110 | writel(reg, &io_apic->index); | |
111 | return readl(&io_apic->data); | |
112 | } | |
113 | ||
114 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) | |
115 | { | |
116 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
117 | writel(reg, &io_apic->index); | |
118 | writel(value, &io_apic->data); | |
119 | } | |
120 | ||
121 | /* | |
122 | * Re-write a value: to be used for read-modify-write | |
123 | * cycles where the read already set up the index register. | |
124 | * | |
125 | * Older SiS APIC requires we rewrite the index register | |
126 | */ | |
127 | static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) | |
128 | { | |
cb468984 | 129 | volatile struct io_apic __iomem *io_apic = io_apic_base(apic); |
130fe05d LT |
130 | if (sis_apic_bug) |
131 | writel(reg, &io_apic->index); | |
132 | writel(value, &io_apic->data); | |
133 | } | |
134 | ||
cf4c6a2f AK |
135 | union entry_union { |
136 | struct { u32 w1, w2; }; | |
137 | struct IO_APIC_route_entry entry; | |
138 | }; | |
139 | ||
140 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) | |
141 | { | |
142 | union entry_union eu; | |
143 | unsigned long flags; | |
144 | spin_lock_irqsave(&ioapic_lock, flags); | |
145 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); | |
146 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
147 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
148 | return eu.entry; | |
149 | } | |
150 | ||
f9dadfa7 LT |
151 | /* |
152 | * When we write a new IO APIC routing entry, we need to write the high | |
153 | * word first! If the mask bit in the low word is clear, we will enable | |
154 | * the interrupt, and we need to make sure the entry is fully populated | |
155 | * before that happens. | |
156 | */ | |
d15512f4 AK |
157 | static void |
158 | __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
cf4c6a2f | 159 | { |
cf4c6a2f AK |
160 | union entry_union eu; |
161 | eu.entry = e; | |
f9dadfa7 LT |
162 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
163 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
164 | } |
165 | ||
166 | static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
167 | { | |
168 | unsigned long flags; | |
169 | spin_lock_irqsave(&ioapic_lock, flags); | |
170 | __ioapic_write_entry(apic, pin, e); | |
f9dadfa7 LT |
171 | spin_unlock_irqrestore(&ioapic_lock, flags); |
172 | } | |
173 | ||
174 | /* | |
175 | * When we mask an IO APIC routing entry, we need to write the low | |
176 | * word first, in order to set the mask bit before we change the | |
177 | * high bits! | |
178 | */ | |
179 | static void ioapic_mask_entry(int apic, int pin) | |
180 | { | |
181 | unsigned long flags; | |
182 | union entry_union eu = { .entry.mask = 1 }; | |
183 | ||
cf4c6a2f AK |
184 | spin_lock_irqsave(&ioapic_lock, flags); |
185 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
186 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
187 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
188 | } | |
189 | ||
1da177e4 LT |
190 | /* |
191 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
192 | * shared ISA-space IRQs, so we have to support them. We are super | |
193 | * fast in the common case, and fast for shared ISA-space IRQs. | |
194 | */ | |
195 | static void add_pin_to_irq(unsigned int irq, int apic, int pin) | |
196 | { | |
197 | static int first_free_entry = NR_IRQS; | |
198 | struct irq_pin_list *entry = irq_2_pin + irq; | |
199 | ||
200 | while (entry->next) | |
201 | entry = irq_2_pin + entry->next; | |
202 | ||
203 | if (entry->pin != -1) { | |
204 | entry->next = first_free_entry; | |
205 | entry = irq_2_pin + entry->next; | |
206 | if (++first_free_entry >= PIN_MAP_SIZE) | |
207 | panic("io_apic.c: whoops"); | |
208 | } | |
209 | entry->apic = apic; | |
210 | entry->pin = pin; | |
211 | } | |
212 | ||
213 | /* | |
214 | * Reroute an IRQ to a different pin. | |
215 | */ | |
216 | static void __init replace_pin_at_irq(unsigned int irq, | |
217 | int oldapic, int oldpin, | |
218 | int newapic, int newpin) | |
219 | { | |
220 | struct irq_pin_list *entry = irq_2_pin + irq; | |
221 | ||
222 | while (1) { | |
223 | if (entry->apic == oldapic && entry->pin == oldpin) { | |
224 | entry->apic = newapic; | |
225 | entry->pin = newpin; | |
226 | } | |
227 | if (!entry->next) | |
228 | break; | |
229 | entry = irq_2_pin + entry->next; | |
230 | } | |
231 | } | |
232 | ||
233 | static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable) | |
234 | { | |
235 | struct irq_pin_list *entry = irq_2_pin + irq; | |
236 | unsigned int pin, reg; | |
237 | ||
238 | for (;;) { | |
239 | pin = entry->pin; | |
240 | if (pin == -1) | |
241 | break; | |
242 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
243 | reg &= ~disable; | |
244 | reg |= enable; | |
245 | io_apic_modify(entry->apic, 0x10 + pin*2, reg); | |
246 | if (!entry->next) | |
247 | break; | |
248 | entry = irq_2_pin + entry->next; | |
249 | } | |
250 | } | |
251 | ||
252 | /* mask = 1 */ | |
253 | static void __mask_IO_APIC_irq (unsigned int irq) | |
254 | { | |
255 | __modify_IO_APIC_irq(irq, 0x00010000, 0); | |
256 | } | |
257 | ||
258 | /* mask = 0 */ | |
259 | static void __unmask_IO_APIC_irq (unsigned int irq) | |
260 | { | |
261 | __modify_IO_APIC_irq(irq, 0, 0x00010000); | |
262 | } | |
263 | ||
264 | /* mask = 1, trigger = 0 */ | |
265 | static void __mask_and_edge_IO_APIC_irq (unsigned int irq) | |
266 | { | |
267 | __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000); | |
268 | } | |
269 | ||
270 | /* mask = 0, trigger = 1 */ | |
271 | static void __unmask_and_level_IO_APIC_irq (unsigned int irq) | |
272 | { | |
273 | __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000); | |
274 | } | |
275 | ||
276 | static void mask_IO_APIC_irq (unsigned int irq) | |
277 | { | |
278 | unsigned long flags; | |
279 | ||
280 | spin_lock_irqsave(&ioapic_lock, flags); | |
281 | __mask_IO_APIC_irq(irq); | |
282 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
283 | } | |
284 | ||
285 | static void unmask_IO_APIC_irq (unsigned int irq) | |
286 | { | |
287 | unsigned long flags; | |
288 | ||
289 | spin_lock_irqsave(&ioapic_lock, flags); | |
290 | __unmask_IO_APIC_irq(irq); | |
291 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
292 | } | |
293 | ||
294 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) | |
295 | { | |
296 | struct IO_APIC_route_entry entry; | |
1da177e4 LT |
297 | |
298 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ | |
cf4c6a2f | 299 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
300 | if (entry.delivery_mode == dest_SMI) |
301 | return; | |
302 | ||
303 | /* | |
304 | * Disable it in the IO-APIC irq-routing table: | |
305 | */ | |
f9dadfa7 | 306 | ioapic_mask_entry(apic, pin); |
1da177e4 LT |
307 | } |
308 | ||
309 | static void clear_IO_APIC (void) | |
310 | { | |
311 | int apic, pin; | |
312 | ||
313 | for (apic = 0; apic < nr_ioapics; apic++) | |
314 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) | |
315 | clear_IO_APIC_pin(apic, pin); | |
316 | } | |
317 | ||
54d5d424 | 318 | #ifdef CONFIG_SMP |
1da177e4 LT |
319 | static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask) |
320 | { | |
321 | unsigned long flags; | |
322 | int pin; | |
323 | struct irq_pin_list *entry = irq_2_pin + irq; | |
324 | unsigned int apicid_value; | |
54d5d424 | 325 | cpumask_t tmp; |
1da177e4 | 326 | |
54d5d424 AR |
327 | cpus_and(tmp, cpumask, cpu_online_map); |
328 | if (cpus_empty(tmp)) | |
329 | tmp = TARGET_CPUS; | |
330 | ||
331 | cpus_and(cpumask, tmp, CPU_MASK_ALL); | |
332 | ||
1da177e4 LT |
333 | apicid_value = cpu_mask_to_apicid(cpumask); |
334 | /* Prepare to do the io_apic_write */ | |
335 | apicid_value = apicid_value << 24; | |
336 | spin_lock_irqsave(&ioapic_lock, flags); | |
337 | for (;;) { | |
338 | pin = entry->pin; | |
339 | if (pin == -1) | |
340 | break; | |
341 | io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value); | |
342 | if (!entry->next) | |
343 | break; | |
344 | entry = irq_2_pin + entry->next; | |
345 | } | |
9f0a5ba5 | 346 | irq_desc[irq].affinity = cpumask; |
1da177e4 LT |
347 | spin_unlock_irqrestore(&ioapic_lock, flags); |
348 | } | |
349 | ||
350 | #if defined(CONFIG_IRQBALANCE) | |
351 | # include <asm/processor.h> /* kernel_thread() */ | |
352 | # include <linux/kernel_stat.h> /* kstat */ | |
353 | # include <linux/slab.h> /* kmalloc() */ | |
354 | # include <linux/timer.h> /* time_after() */ | |
355 | ||
1da177e4 | 356 | #define IRQBALANCE_CHECK_ARCH -999 |
1b61b910 ZY |
357 | #define MAX_BALANCED_IRQ_INTERVAL (5*HZ) |
358 | #define MIN_BALANCED_IRQ_INTERVAL (HZ/2) | |
359 | #define BALANCED_IRQ_MORE_DELTA (HZ/10) | |
360 | #define BALANCED_IRQ_LESS_DELTA (HZ) | |
361 | ||
362 | static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH; | |
363 | static int physical_balance __read_mostly; | |
364 | static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL; | |
1da177e4 LT |
365 | |
366 | static struct irq_cpu_info { | |
367 | unsigned long * last_irq; | |
368 | unsigned long * irq_delta; | |
369 | unsigned long irq; | |
370 | } irq_cpu_data[NR_CPUS]; | |
371 | ||
372 | #define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq) | |
373 | #define LAST_CPU_IRQ(cpu,irq) (irq_cpu_data[cpu].last_irq[irq]) | |
374 | #define IRQ_DELTA(cpu,irq) (irq_cpu_data[cpu].irq_delta[irq]) | |
375 | ||
376 | #define IDLE_ENOUGH(cpu,now) \ | |
377 | (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1)) | |
378 | ||
379 | #define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask) | |
380 | ||
d5a7430d | 381 | #define CPU_TO_PACKAGEINDEX(i) (first_cpu(per_cpu(cpu_sibling_map, i))) |
1da177e4 | 382 | |
1b61b910 ZY |
383 | static cpumask_t balance_irq_affinity[NR_IRQS] = { |
384 | [0 ... NR_IRQS-1] = CPU_MASK_ALL | |
385 | }; | |
1da177e4 | 386 | |
1b61b910 ZY |
387 | void set_balance_irq_affinity(unsigned int irq, cpumask_t mask) |
388 | { | |
389 | balance_irq_affinity[irq] = mask; | |
390 | } | |
1da177e4 LT |
391 | |
392 | static unsigned long move(int curr_cpu, cpumask_t allowed_mask, | |
393 | unsigned long now, int direction) | |
394 | { | |
395 | int search_idle = 1; | |
396 | int cpu = curr_cpu; | |
397 | ||
398 | goto inside; | |
399 | ||
400 | do { | |
401 | if (unlikely(cpu == curr_cpu)) | |
402 | search_idle = 0; | |
403 | inside: | |
404 | if (direction == 1) { | |
405 | cpu++; | |
406 | if (cpu >= NR_CPUS) | |
407 | cpu = 0; | |
408 | } else { | |
409 | cpu--; | |
410 | if (cpu == -1) | |
411 | cpu = NR_CPUS-1; | |
412 | } | |
413 | } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) || | |
414 | (search_idle && !IDLE_ENOUGH(cpu,now))); | |
415 | ||
416 | return cpu; | |
417 | } | |
418 | ||
419 | static inline void balance_irq(int cpu, int irq) | |
420 | { | |
421 | unsigned long now = jiffies; | |
422 | cpumask_t allowed_mask; | |
423 | unsigned int new_cpu; | |
424 | ||
425 | if (irqbalance_disabled) | |
426 | return; | |
427 | ||
1b61b910 | 428 | cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]); |
1da177e4 LT |
429 | new_cpu = move(cpu, allowed_mask, now, 1); |
430 | if (cpu != new_cpu) { | |
54d5d424 | 431 | set_pending_irq(irq, cpumask_of_cpu(new_cpu)); |
1da177e4 LT |
432 | } |
433 | } | |
434 | ||
435 | static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold) | |
436 | { | |
437 | int i, j; | |
edc2cbf4 | 438 | |
394e3902 AM |
439 | for_each_online_cpu(i) { |
440 | for (j = 0; j < NR_IRQS; j++) { | |
1da177e4 LT |
441 | if (!irq_desc[j].action) |
442 | continue; | |
443 | /* Is it a significant load ? */ | |
444 | if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) < | |
445 | useful_load_threshold) | |
446 | continue; | |
447 | balance_irq(i, j); | |
448 | } | |
449 | } | |
450 | balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL, | |
451 | balanced_irq_interval - BALANCED_IRQ_LESS_DELTA); | |
452 | return; | |
453 | } | |
454 | ||
455 | static void do_irq_balance(void) | |
456 | { | |
457 | int i, j; | |
458 | unsigned long max_cpu_irq = 0, min_cpu_irq = (~0); | |
459 | unsigned long move_this_load = 0; | |
460 | int max_loaded = 0, min_loaded = 0; | |
461 | int load; | |
462 | unsigned long useful_load_threshold = balanced_irq_interval + 10; | |
463 | int selected_irq; | |
464 | int tmp_loaded, first_attempt = 1; | |
465 | unsigned long tmp_cpu_irq; | |
466 | unsigned long imbalance = 0; | |
467 | cpumask_t allowed_mask, target_cpu_mask, tmp; | |
468 | ||
c8912599 | 469 | for_each_possible_cpu(i) { |
1da177e4 LT |
470 | int package_index; |
471 | CPU_IRQ(i) = 0; | |
472 | if (!cpu_online(i)) | |
473 | continue; | |
474 | package_index = CPU_TO_PACKAGEINDEX(i); | |
475 | for (j = 0; j < NR_IRQS; j++) { | |
476 | unsigned long value_now, delta; | |
950f4427 TG |
477 | /* Is this an active IRQ or balancing disabled ? */ |
478 | if (!irq_desc[j].action || irq_balancing_disabled(j)) | |
1da177e4 LT |
479 | continue; |
480 | if ( package_index == i ) | |
481 | IRQ_DELTA(package_index,j) = 0; | |
482 | /* Determine the total count per processor per IRQ */ | |
483 | value_now = (unsigned long) kstat_cpu(i).irqs[j]; | |
484 | ||
485 | /* Determine the activity per processor per IRQ */ | |
486 | delta = value_now - LAST_CPU_IRQ(i,j); | |
487 | ||
488 | /* Update last_cpu_irq[][] for the next time */ | |
489 | LAST_CPU_IRQ(i,j) = value_now; | |
490 | ||
491 | /* Ignore IRQs whose rate is less than the clock */ | |
492 | if (delta < useful_load_threshold) | |
493 | continue; | |
494 | /* update the load for the processor or package total */ | |
495 | IRQ_DELTA(package_index,j) += delta; | |
496 | ||
497 | /* Keep track of the higher numbered sibling as well */ | |
498 | if (i != package_index) | |
499 | CPU_IRQ(i) += delta; | |
500 | /* | |
501 | * We have sibling A and sibling B in the package | |
502 | * | |
503 | * cpu_irq[A] = load for cpu A + load for cpu B | |
504 | * cpu_irq[B] = load for cpu B | |
505 | */ | |
506 | CPU_IRQ(package_index) += delta; | |
507 | } | |
508 | } | |
509 | /* Find the least loaded processor package */ | |
394e3902 | 510 | for_each_online_cpu(i) { |
1da177e4 LT |
511 | if (i != CPU_TO_PACKAGEINDEX(i)) |
512 | continue; | |
513 | if (min_cpu_irq > CPU_IRQ(i)) { | |
514 | min_cpu_irq = CPU_IRQ(i); | |
515 | min_loaded = i; | |
516 | } | |
517 | } | |
518 | max_cpu_irq = ULONG_MAX; | |
519 | ||
520 | tryanothercpu: | |
521 | /* Look for heaviest loaded processor. | |
522 | * We may come back to get the next heaviest loaded processor. | |
523 | * Skip processors with trivial loads. | |
524 | */ | |
525 | tmp_cpu_irq = 0; | |
526 | tmp_loaded = -1; | |
394e3902 | 527 | for_each_online_cpu(i) { |
1da177e4 LT |
528 | if (i != CPU_TO_PACKAGEINDEX(i)) |
529 | continue; | |
530 | if (max_cpu_irq <= CPU_IRQ(i)) | |
531 | continue; | |
532 | if (tmp_cpu_irq < CPU_IRQ(i)) { | |
533 | tmp_cpu_irq = CPU_IRQ(i); | |
534 | tmp_loaded = i; | |
535 | } | |
536 | } | |
537 | ||
538 | if (tmp_loaded == -1) { | |
539 | /* In the case of small number of heavy interrupt sources, | |
540 | * loading some of the cpus too much. We use Ingo's original | |
541 | * approach to rotate them around. | |
542 | */ | |
543 | if (!first_attempt && imbalance >= useful_load_threshold) { | |
544 | rotate_irqs_among_cpus(useful_load_threshold); | |
545 | return; | |
546 | } | |
547 | goto not_worth_the_effort; | |
548 | } | |
549 | ||
550 | first_attempt = 0; /* heaviest search */ | |
551 | max_cpu_irq = tmp_cpu_irq; /* load */ | |
552 | max_loaded = tmp_loaded; /* processor */ | |
553 | imbalance = (max_cpu_irq - min_cpu_irq) / 2; | |
554 | ||
1da177e4 LT |
555 | /* if imbalance is less than approx 10% of max load, then |
556 | * observe diminishing returns action. - quit | |
557 | */ | |
edc2cbf4 | 558 | if (imbalance < (max_cpu_irq >> 3)) |
1da177e4 | 559 | goto not_worth_the_effort; |
1da177e4 LT |
560 | |
561 | tryanotherirq: | |
562 | /* if we select an IRQ to move that can't go where we want, then | |
563 | * see if there is another one to try. | |
564 | */ | |
565 | move_this_load = 0; | |
566 | selected_irq = -1; | |
567 | for (j = 0; j < NR_IRQS; j++) { | |
568 | /* Is this an active IRQ? */ | |
569 | if (!irq_desc[j].action) | |
570 | continue; | |
571 | if (imbalance <= IRQ_DELTA(max_loaded,j)) | |
572 | continue; | |
573 | /* Try to find the IRQ that is closest to the imbalance | |
574 | * without going over. | |
575 | */ | |
576 | if (move_this_load < IRQ_DELTA(max_loaded,j)) { | |
577 | move_this_load = IRQ_DELTA(max_loaded,j); | |
578 | selected_irq = j; | |
579 | } | |
580 | } | |
581 | if (selected_irq == -1) { | |
582 | goto tryanothercpu; | |
583 | } | |
584 | ||
585 | imbalance = move_this_load; | |
586 | ||
27b46d76 | 587 | /* For physical_balance case, we accumulated both load |
1da177e4 LT |
588 | * values in the one of the siblings cpu_irq[], |
589 | * to use the same code for physical and logical processors | |
590 | * as much as possible. | |
591 | * | |
592 | * NOTE: the cpu_irq[] array holds the sum of the load for | |
593 | * sibling A and sibling B in the slot for the lowest numbered | |
594 | * sibling (A), _AND_ the load for sibling B in the slot for | |
595 | * the higher numbered sibling. | |
596 | * | |
597 | * We seek the least loaded sibling by making the comparison | |
598 | * (A+B)/2 vs B | |
599 | */ | |
600 | load = CPU_IRQ(min_loaded) >> 1; | |
d5a7430d | 601 | for_each_cpu_mask(j, per_cpu(cpu_sibling_map, min_loaded)) { |
1da177e4 LT |
602 | if (load > CPU_IRQ(j)) { |
603 | /* This won't change cpu_sibling_map[min_loaded] */ | |
604 | load = CPU_IRQ(j); | |
605 | min_loaded = j; | |
606 | } | |
607 | } | |
608 | ||
1b61b910 ZY |
609 | cpus_and(allowed_mask, |
610 | cpu_online_map, | |
611 | balance_irq_affinity[selected_irq]); | |
1da177e4 LT |
612 | target_cpu_mask = cpumask_of_cpu(min_loaded); |
613 | cpus_and(tmp, target_cpu_mask, allowed_mask); | |
614 | ||
615 | if (!cpus_empty(tmp)) { | |
1da177e4 | 616 | /* mark for change destination */ |
54d5d424 AR |
617 | set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded)); |
618 | ||
1da177e4 LT |
619 | /* Since we made a change, come back sooner to |
620 | * check for more variation. | |
621 | */ | |
622 | balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL, | |
623 | balanced_irq_interval - BALANCED_IRQ_LESS_DELTA); | |
624 | return; | |
625 | } | |
626 | goto tryanotherirq; | |
627 | ||
628 | not_worth_the_effort: | |
629 | /* | |
630 | * if we did not find an IRQ to move, then adjust the time interval | |
631 | * upward | |
632 | */ | |
633 | balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL, | |
634 | balanced_irq_interval + BALANCED_IRQ_MORE_DELTA); | |
1da177e4 LT |
635 | return; |
636 | } | |
637 | ||
638 | static int balanced_irq(void *unused) | |
639 | { | |
640 | int i; | |
641 | unsigned long prev_balance_time = jiffies; | |
642 | long time_remaining = balanced_irq_interval; | |
643 | ||
1da177e4 LT |
644 | /* push everything to CPU 0 to give us a starting point. */ |
645 | for (i = 0 ; i < NR_IRQS ; i++) { | |
cd916d31 | 646 | irq_desc[i].pending_mask = cpumask_of_cpu(0); |
54d5d424 | 647 | set_pending_irq(i, cpumask_of_cpu(0)); |
1da177e4 LT |
648 | } |
649 | ||
83144186 | 650 | set_freezable(); |
1da177e4 | 651 | for ( ; ; ) { |
52e6e630 | 652 | time_remaining = schedule_timeout_interruptible(time_remaining); |
3e1d1d28 | 653 | try_to_freeze(); |
1da177e4 LT |
654 | if (time_after(jiffies, |
655 | prev_balance_time+balanced_irq_interval)) { | |
f3705136 | 656 | preempt_disable(); |
1da177e4 LT |
657 | do_irq_balance(); |
658 | prev_balance_time = jiffies; | |
659 | time_remaining = balanced_irq_interval; | |
f3705136 | 660 | preempt_enable(); |
1da177e4 LT |
661 | } |
662 | } | |
663 | return 0; | |
664 | } | |
665 | ||
666 | static int __init balanced_irq_init(void) | |
667 | { | |
668 | int i; | |
669 | struct cpuinfo_x86 *c; | |
670 | cpumask_t tmp; | |
671 | ||
672 | cpus_shift_right(tmp, cpu_online_map, 2); | |
673 | c = &boot_cpu_data; | |
674 | /* When not overwritten by the command line ask subarchitecture. */ | |
675 | if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH) | |
676 | irqbalance_disabled = NO_BALANCE_IRQ; | |
677 | if (irqbalance_disabled) | |
678 | return 0; | |
679 | ||
680 | /* disable irqbalance completely if there is only one processor online */ | |
681 | if (num_online_cpus() < 2) { | |
682 | irqbalance_disabled = 1; | |
683 | return 0; | |
684 | } | |
685 | /* | |
686 | * Enable physical balance only if more than 1 physical processor | |
687 | * is present | |
688 | */ | |
689 | if (smp_num_siblings > 1 && !cpus_empty(tmp)) | |
690 | physical_balance = 1; | |
691 | ||
394e3902 | 692 | for_each_online_cpu(i) { |
1da177e4 LT |
693 | irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL); |
694 | irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL); | |
695 | if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) { | |
696 | printk(KERN_ERR "balanced_irq_init: out of memory"); | |
697 | goto failed; | |
698 | } | |
699 | memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS); | |
700 | memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS); | |
701 | } | |
702 | ||
703 | printk(KERN_INFO "Starting balanced_irq\n"); | |
f26d6a2b | 704 | if (!IS_ERR(kthread_run(balanced_irq, NULL, "kirqd"))) |
1da177e4 | 705 | return 0; |
f26d6a2b | 706 | printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq"); |
1da177e4 | 707 | failed: |
c8912599 | 708 | for_each_possible_cpu(i) { |
4ae6673e | 709 | kfree(irq_cpu_data[i].irq_delta); |
394e3902 | 710 | irq_cpu_data[i].irq_delta = NULL; |
4ae6673e | 711 | kfree(irq_cpu_data[i].last_irq); |
394e3902 | 712 | irq_cpu_data[i].last_irq = NULL; |
1da177e4 LT |
713 | } |
714 | return 0; | |
715 | } | |
716 | ||
c2481cc4 | 717 | int __devinit irqbalance_disable(char *str) |
1da177e4 LT |
718 | { |
719 | irqbalance_disabled = 1; | |
9b41046c | 720 | return 1; |
1da177e4 LT |
721 | } |
722 | ||
723 | __setup("noirqbalance", irqbalance_disable); | |
724 | ||
1da177e4 | 725 | late_initcall(balanced_irq_init); |
1da177e4 | 726 | #endif /* CONFIG_IRQBALANCE */ |
54d5d424 | 727 | #endif /* CONFIG_SMP */ |
1da177e4 LT |
728 | |
729 | #ifndef CONFIG_SMP | |
730 | void fastcall send_IPI_self(int vector) | |
731 | { | |
732 | unsigned int cfg; | |
733 | ||
734 | /* | |
735 | * Wait for idle. | |
736 | */ | |
737 | apic_wait_icr_idle(); | |
738 | cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL; | |
739 | /* | |
740 | * Send the IPI. The write to APIC_ICR fires this off. | |
741 | */ | |
742 | apic_write_around(APIC_ICR, cfg); | |
743 | } | |
744 | #endif /* !CONFIG_SMP */ | |
745 | ||
746 | ||
747 | /* | |
748 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
749 | * specific CPU-side IRQs. | |
750 | */ | |
751 | ||
752 | #define MAX_PIRQS 8 | |
753 | static int pirq_entries [MAX_PIRQS]; | |
754 | static int pirqs_enabled; | |
755 | int skip_ioapic_setup; | |
756 | ||
1da177e4 LT |
757 | static int __init ioapic_pirq_setup(char *str) |
758 | { | |
759 | int i, max; | |
760 | int ints[MAX_PIRQS+1]; | |
761 | ||
762 | get_options(str, ARRAY_SIZE(ints), ints); | |
763 | ||
764 | for (i = 0; i < MAX_PIRQS; i++) | |
765 | pirq_entries[i] = -1; | |
766 | ||
767 | pirqs_enabled = 1; | |
768 | apic_printk(APIC_VERBOSE, KERN_INFO | |
769 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
770 | max = MAX_PIRQS; | |
771 | if (ints[0] < MAX_PIRQS) | |
772 | max = ints[0]; | |
773 | ||
774 | for (i = 0; i < max; i++) { | |
775 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
776 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
777 | /* | |
778 | * PIRQs are mapped upside down, usually. | |
779 | */ | |
780 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
781 | } | |
782 | return 1; | |
783 | } | |
784 | ||
785 | __setup("pirq=", ioapic_pirq_setup); | |
786 | ||
787 | /* | |
788 | * Find the IRQ entry number of a certain pin. | |
789 | */ | |
790 | static int find_irq_entry(int apic, int pin, int type) | |
791 | { | |
792 | int i; | |
793 | ||
794 | for (i = 0; i < mp_irq_entries; i++) | |
795 | if (mp_irqs[i].mpc_irqtype == type && | |
796 | (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid || | |
797 | mp_irqs[i].mpc_dstapic == MP_APIC_ALL) && | |
798 | mp_irqs[i].mpc_dstirq == pin) | |
799 | return i; | |
800 | ||
801 | return -1; | |
802 | } | |
803 | ||
804 | /* | |
805 | * Find the pin to which IRQ[irq] (ISA) is connected | |
806 | */ | |
fcfd636a | 807 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
808 | { |
809 | int i; | |
810 | ||
811 | for (i = 0; i < mp_irq_entries; i++) { | |
812 | int lbus = mp_irqs[i].mpc_srcbus; | |
813 | ||
814 | if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA || | |
815 | mp_bus_id_to_type[lbus] == MP_BUS_EISA || | |
d7fb0271 | 816 | mp_bus_id_to_type[lbus] == MP_BUS_MCA |
1da177e4 LT |
817 | ) && |
818 | (mp_irqs[i].mpc_irqtype == type) && | |
819 | (mp_irqs[i].mpc_srcbusirq == irq)) | |
820 | ||
821 | return mp_irqs[i].mpc_dstirq; | |
822 | } | |
823 | return -1; | |
824 | } | |
825 | ||
fcfd636a EB |
826 | static int __init find_isa_irq_apic(int irq, int type) |
827 | { | |
828 | int i; | |
829 | ||
830 | for (i = 0; i < mp_irq_entries; i++) { | |
831 | int lbus = mp_irqs[i].mpc_srcbus; | |
832 | ||
833 | if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA || | |
834 | mp_bus_id_to_type[lbus] == MP_BUS_EISA || | |
d7fb0271 | 835 | mp_bus_id_to_type[lbus] == MP_BUS_MCA |
fcfd636a EB |
836 | ) && |
837 | (mp_irqs[i].mpc_irqtype == type) && | |
838 | (mp_irqs[i].mpc_srcbusirq == irq)) | |
839 | break; | |
840 | } | |
841 | if (i < mp_irq_entries) { | |
842 | int apic; | |
843 | for(apic = 0; apic < nr_ioapics; apic++) { | |
844 | if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic) | |
845 | return apic; | |
846 | } | |
847 | } | |
848 | ||
849 | return -1; | |
850 | } | |
851 | ||
1da177e4 LT |
852 | /* |
853 | * Find a specific PCI IRQ entry. | |
854 | * Not an __init, possibly needed by modules | |
855 | */ | |
856 | static int pin_2_irq(int idx, int apic, int pin); | |
857 | ||
858 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin) | |
859 | { | |
860 | int apic, i, best_guess = -1; | |
861 | ||
862 | apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, " | |
863 | "slot:%d, pin:%d.\n", bus, slot, pin); | |
864 | if (mp_bus_id_to_pci_bus[bus] == -1) { | |
865 | printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus); | |
866 | return -1; | |
867 | } | |
868 | for (i = 0; i < mp_irq_entries; i++) { | |
869 | int lbus = mp_irqs[i].mpc_srcbus; | |
870 | ||
871 | for (apic = 0; apic < nr_ioapics; apic++) | |
872 | if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic || | |
873 | mp_irqs[i].mpc_dstapic == MP_APIC_ALL) | |
874 | break; | |
875 | ||
876 | if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) && | |
877 | !mp_irqs[i].mpc_irqtype && | |
878 | (bus == lbus) && | |
879 | (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) { | |
880 | int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq); | |
881 | ||
882 | if (!(apic || IO_APIC_IRQ(irq))) | |
883 | continue; | |
884 | ||
885 | if (pin == (mp_irqs[i].mpc_srcbusirq & 3)) | |
886 | return irq; | |
887 | /* | |
888 | * Use the first all-but-pin matching entry as a | |
889 | * best-guess fuzzy result for broken mptables. | |
890 | */ | |
891 | if (best_guess < 0) | |
892 | best_guess = irq; | |
893 | } | |
894 | } | |
895 | return best_guess; | |
896 | } | |
129f6946 | 897 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); |
1da177e4 LT |
898 | |
899 | /* | |
900 | * This function currently is only a helper for the i386 smp boot process where | |
901 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
902 | * so mask in all cases should simply be TARGET_CPUS | |
903 | */ | |
54d5d424 | 904 | #ifdef CONFIG_SMP |
1da177e4 LT |
905 | void __init setup_ioapic_dest(void) |
906 | { | |
907 | int pin, ioapic, irq, irq_entry; | |
908 | ||
909 | if (skip_ioapic_setup == 1) | |
910 | return; | |
911 | ||
912 | for (ioapic = 0; ioapic < nr_ioapics; ioapic++) { | |
913 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { | |
914 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); | |
915 | if (irq_entry == -1) | |
916 | continue; | |
917 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
918 | set_ioapic_affinity_irq(irq, TARGET_CPUS); | |
919 | } | |
920 | ||
921 | } | |
922 | } | |
54d5d424 | 923 | #endif |
1da177e4 LT |
924 | |
925 | /* | |
926 | * EISA Edge/Level control register, ELCR | |
927 | */ | |
928 | static int EISA_ELCR(unsigned int irq) | |
929 | { | |
930 | if (irq < 16) { | |
931 | unsigned int port = 0x4d0 + (irq >> 3); | |
932 | return (inb(port) >> (irq & 7)) & 1; | |
933 | } | |
934 | apic_printk(APIC_VERBOSE, KERN_INFO | |
935 | "Broken MPtable reports ISA irq %d\n", irq); | |
936 | return 0; | |
937 | } | |
938 | ||
939 | /* EISA interrupts are always polarity zero and can be edge or level | |
940 | * trigger depending on the ELCR value. If an interrupt is listed as | |
941 | * EISA conforming in the MP table, that means its trigger type must | |
942 | * be read in from the ELCR */ | |
943 | ||
944 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq)) | |
945 | #define default_EISA_polarity(idx) (0) | |
946 | ||
947 | /* ISA interrupts are always polarity zero edge triggered, | |
948 | * when listed as conforming in the MP table. */ | |
949 | ||
950 | #define default_ISA_trigger(idx) (0) | |
951 | #define default_ISA_polarity(idx) (0) | |
952 | ||
953 | /* PCI interrupts are always polarity one level triggered, | |
954 | * when listed as conforming in the MP table. */ | |
955 | ||
956 | #define default_PCI_trigger(idx) (1) | |
957 | #define default_PCI_polarity(idx) (1) | |
958 | ||
959 | /* MCA interrupts are always polarity zero level triggered, | |
960 | * when listed as conforming in the MP table. */ | |
961 | ||
962 | #define default_MCA_trigger(idx) (1) | |
963 | #define default_MCA_polarity(idx) (0) | |
964 | ||
61fd47e0 | 965 | static int MPBIOS_polarity(int idx) |
1da177e4 LT |
966 | { |
967 | int bus = mp_irqs[idx].mpc_srcbus; | |
968 | int polarity; | |
969 | ||
970 | /* | |
971 | * Determine IRQ line polarity (high active or low active): | |
972 | */ | |
973 | switch (mp_irqs[idx].mpc_irqflag & 3) | |
974 | { | |
975 | case 0: /* conforms, ie. bus-type dependent polarity */ | |
976 | { | |
977 | switch (mp_bus_id_to_type[bus]) | |
978 | { | |
979 | case MP_BUS_ISA: /* ISA pin */ | |
980 | { | |
981 | polarity = default_ISA_polarity(idx); | |
982 | break; | |
983 | } | |
984 | case MP_BUS_EISA: /* EISA pin */ | |
985 | { | |
986 | polarity = default_EISA_polarity(idx); | |
987 | break; | |
988 | } | |
989 | case MP_BUS_PCI: /* PCI pin */ | |
990 | { | |
991 | polarity = default_PCI_polarity(idx); | |
992 | break; | |
993 | } | |
994 | case MP_BUS_MCA: /* MCA pin */ | |
995 | { | |
996 | polarity = default_MCA_polarity(idx); | |
997 | break; | |
998 | } | |
1da177e4 LT |
999 | default: |
1000 | { | |
1001 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1002 | polarity = 1; | |
1003 | break; | |
1004 | } | |
1005 | } | |
1006 | break; | |
1007 | } | |
1008 | case 1: /* high active */ | |
1009 | { | |
1010 | polarity = 0; | |
1011 | break; | |
1012 | } | |
1013 | case 2: /* reserved */ | |
1014 | { | |
1015 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1016 | polarity = 1; | |
1017 | break; | |
1018 | } | |
1019 | case 3: /* low active */ | |
1020 | { | |
1021 | polarity = 1; | |
1022 | break; | |
1023 | } | |
1024 | default: /* invalid */ | |
1025 | { | |
1026 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1027 | polarity = 1; | |
1028 | break; | |
1029 | } | |
1030 | } | |
1031 | return polarity; | |
1032 | } | |
1033 | ||
1034 | static int MPBIOS_trigger(int idx) | |
1035 | { | |
1036 | int bus = mp_irqs[idx].mpc_srcbus; | |
1037 | int trigger; | |
1038 | ||
1039 | /* | |
1040 | * Determine IRQ trigger mode (edge or level sensitive): | |
1041 | */ | |
1042 | switch ((mp_irqs[idx].mpc_irqflag>>2) & 3) | |
1043 | { | |
1044 | case 0: /* conforms, ie. bus-type dependent */ | |
1045 | { | |
1046 | switch (mp_bus_id_to_type[bus]) | |
1047 | { | |
1048 | case MP_BUS_ISA: /* ISA pin */ | |
1049 | { | |
1050 | trigger = default_ISA_trigger(idx); | |
1051 | break; | |
1052 | } | |
1053 | case MP_BUS_EISA: /* EISA pin */ | |
1054 | { | |
1055 | trigger = default_EISA_trigger(idx); | |
1056 | break; | |
1057 | } | |
1058 | case MP_BUS_PCI: /* PCI pin */ | |
1059 | { | |
1060 | trigger = default_PCI_trigger(idx); | |
1061 | break; | |
1062 | } | |
1063 | case MP_BUS_MCA: /* MCA pin */ | |
1064 | { | |
1065 | trigger = default_MCA_trigger(idx); | |
1066 | break; | |
1067 | } | |
1da177e4 LT |
1068 | default: |
1069 | { | |
1070 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1071 | trigger = 1; | |
1072 | break; | |
1073 | } | |
1074 | } | |
1075 | break; | |
1076 | } | |
1077 | case 1: /* edge */ | |
1078 | { | |
1079 | trigger = 0; | |
1080 | break; | |
1081 | } | |
1082 | case 2: /* reserved */ | |
1083 | { | |
1084 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1085 | trigger = 1; | |
1086 | break; | |
1087 | } | |
1088 | case 3: /* level */ | |
1089 | { | |
1090 | trigger = 1; | |
1091 | break; | |
1092 | } | |
1093 | default: /* invalid */ | |
1094 | { | |
1095 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1096 | trigger = 0; | |
1097 | break; | |
1098 | } | |
1099 | } | |
1100 | return trigger; | |
1101 | } | |
1102 | ||
1103 | static inline int irq_polarity(int idx) | |
1104 | { | |
1105 | return MPBIOS_polarity(idx); | |
1106 | } | |
1107 | ||
1108 | static inline int irq_trigger(int idx) | |
1109 | { | |
1110 | return MPBIOS_trigger(idx); | |
1111 | } | |
1112 | ||
1113 | static int pin_2_irq(int idx, int apic, int pin) | |
1114 | { | |
1115 | int irq, i; | |
1116 | int bus = mp_irqs[idx].mpc_srcbus; | |
1117 | ||
1118 | /* | |
1119 | * Debugging check, we are in big trouble if this message pops up! | |
1120 | */ | |
1121 | if (mp_irqs[idx].mpc_dstirq != pin) | |
1122 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); | |
1123 | ||
1124 | switch (mp_bus_id_to_type[bus]) | |
1125 | { | |
1126 | case MP_BUS_ISA: /* ISA pin */ | |
1127 | case MP_BUS_EISA: | |
1128 | case MP_BUS_MCA: | |
1da177e4 LT |
1129 | { |
1130 | irq = mp_irqs[idx].mpc_srcbusirq; | |
1131 | break; | |
1132 | } | |
1133 | case MP_BUS_PCI: /* PCI pin */ | |
1134 | { | |
1135 | /* | |
1136 | * PCI IRQs are mapped in order | |
1137 | */ | |
1138 | i = irq = 0; | |
1139 | while (i < apic) | |
1140 | irq += nr_ioapic_registers[i++]; | |
1141 | irq += pin; | |
1142 | ||
1143 | /* | |
1144 | * For MPS mode, so far only needed by ES7000 platform | |
1145 | */ | |
1146 | if (ioapic_renumber_irq) | |
1147 | irq = ioapic_renumber_irq(apic, irq); | |
1148 | ||
1149 | break; | |
1150 | } | |
1151 | default: | |
1152 | { | |
1153 | printk(KERN_ERR "unknown bus type %d.\n",bus); | |
1154 | irq = 0; | |
1155 | break; | |
1156 | } | |
1157 | } | |
1158 | ||
1159 | /* | |
1160 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
1161 | */ | |
1162 | if ((pin >= 16) && (pin <= 23)) { | |
1163 | if (pirq_entries[pin-16] != -1) { | |
1164 | if (!pirq_entries[pin-16]) { | |
1165 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1166 | "disabling PIRQ%d\n", pin-16); | |
1167 | } else { | |
1168 | irq = pirq_entries[pin-16]; | |
1169 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1170 | "using PIRQ%d -> IRQ %d\n", | |
1171 | pin-16, irq); | |
1172 | } | |
1173 | } | |
1174 | } | |
1175 | return irq; | |
1176 | } | |
1177 | ||
1178 | static inline int IO_APIC_irq_trigger(int irq) | |
1179 | { | |
1180 | int apic, idx, pin; | |
1181 | ||
1182 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1183 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1184 | idx = find_irq_entry(apic,pin,mp_INT); | |
1185 | if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin))) | |
1186 | return irq_trigger(idx); | |
1187 | } | |
1188 | } | |
1189 | /* | |
1190 | * nonexistent IRQs are edge default | |
1191 | */ | |
1192 | return 0; | |
1193 | } | |
1194 | ||
1195 | /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */ | |
7e95b593 | 1196 | static u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 }; |
1da177e4 | 1197 | |
ace80ab7 | 1198 | static int __assign_irq_vector(int irq) |
1da177e4 | 1199 | { |
8339f000 | 1200 | static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0; |
dbeb2be2 | 1201 | int vector, offset; |
1da177e4 | 1202 | |
ace80ab7 | 1203 | BUG_ON((unsigned)irq >= NR_IRQ_VECTORS); |
0a1ad60d | 1204 | |
b940d22d EB |
1205 | if (irq_vector[irq] > 0) |
1206 | return irq_vector[irq]; | |
ace80ab7 | 1207 | |
0a1ad60d | 1208 | vector = current_vector; |
8339f000 EB |
1209 | offset = current_offset; |
1210 | next: | |
1211 | vector += 8; | |
1212 | if (vector >= FIRST_SYSTEM_VECTOR) { | |
1213 | offset = (offset + 1) % 8; | |
1214 | vector = FIRST_DEVICE_VECTOR + offset; | |
1215 | } | |
1216 | if (vector == current_vector) | |
1217 | return -ENOSPC; | |
dbeb2be2 | 1218 | if (test_and_set_bit(vector, used_vectors)) |
8339f000 | 1219 | goto next; |
8339f000 EB |
1220 | |
1221 | current_vector = vector; | |
1222 | current_offset = offset; | |
b940d22d | 1223 | irq_vector[irq] = vector; |
ace80ab7 EB |
1224 | |
1225 | return vector; | |
1226 | } | |
0a1ad60d | 1227 | |
ace80ab7 EB |
1228 | static int assign_irq_vector(int irq) |
1229 | { | |
1230 | unsigned long flags; | |
1231 | int vector; | |
1232 | ||
1233 | spin_lock_irqsave(&vector_lock, flags); | |
1234 | vector = __assign_irq_vector(irq); | |
26a3c49c | 1235 | spin_unlock_irqrestore(&vector_lock, flags); |
1da177e4 | 1236 | |
0a1ad60d | 1237 | return vector; |
1da177e4 | 1238 | } |
f5b9ed7a | 1239 | static struct irq_chip ioapic_chip; |
1da177e4 LT |
1240 | |
1241 | #define IOAPIC_AUTO -1 | |
1242 | #define IOAPIC_EDGE 0 | |
1243 | #define IOAPIC_LEVEL 1 | |
1244 | ||
d1bef4ed | 1245 | static void ioapic_register_intr(int irq, int vector, unsigned long trigger) |
1da177e4 | 1246 | { |
6ebcc00e | 1247 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
cc75b92d TG |
1248 | trigger == IOAPIC_LEVEL) { |
1249 | irq_desc[irq].status |= IRQ_LEVEL; | |
a460e745 IM |
1250 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
1251 | handle_fasteoi_irq, "fasteoi"); | |
cc75b92d TG |
1252 | } else { |
1253 | irq_desc[irq].status &= ~IRQ_LEVEL; | |
a460e745 IM |
1254 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
1255 | handle_edge_irq, "edge"); | |
cc75b92d | 1256 | } |
ace80ab7 | 1257 | set_intr_gate(vector, interrupt[irq]); |
1da177e4 LT |
1258 | } |
1259 | ||
1260 | static void __init setup_IO_APIC_irqs(void) | |
1261 | { | |
1262 | struct IO_APIC_route_entry entry; | |
1263 | int apic, pin, idx, irq, first_notcon = 1, vector; | |
1264 | unsigned long flags; | |
1265 | ||
1266 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1267 | ||
1268 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1269 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1270 | ||
1271 | /* | |
1272 | * add it to the IO-APIC irq-routing table: | |
1273 | */ | |
1274 | memset(&entry,0,sizeof(entry)); | |
1275 | ||
1276 | entry.delivery_mode = INT_DELIVERY_MODE; | |
1277 | entry.dest_mode = INT_DEST_MODE; | |
1278 | entry.mask = 0; /* enable IRQ */ | |
1279 | entry.dest.logical.logical_dest = | |
1280 | cpu_mask_to_apicid(TARGET_CPUS); | |
1281 | ||
1282 | idx = find_irq_entry(apic,pin,mp_INT); | |
1283 | if (idx == -1) { | |
1284 | if (first_notcon) { | |
1285 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1286 | " IO-APIC (apicid-pin) %d-%d", | |
1287 | mp_ioapics[apic].mpc_apicid, | |
1288 | pin); | |
1289 | first_notcon = 0; | |
1290 | } else | |
1291 | apic_printk(APIC_VERBOSE, ", %d-%d", | |
1292 | mp_ioapics[apic].mpc_apicid, pin); | |
1293 | continue; | |
1294 | } | |
1295 | ||
20d225b9 YL |
1296 | if (!first_notcon) { |
1297 | apic_printk(APIC_VERBOSE, " not connected.\n"); | |
1298 | first_notcon = 1; | |
1299 | } | |
1300 | ||
1da177e4 LT |
1301 | entry.trigger = irq_trigger(idx); |
1302 | entry.polarity = irq_polarity(idx); | |
1303 | ||
1304 | if (irq_trigger(idx)) { | |
1305 | entry.trigger = 1; | |
1306 | entry.mask = 1; | |
1307 | } | |
1308 | ||
1309 | irq = pin_2_irq(idx, apic, pin); | |
1310 | /* | |
1311 | * skip adding the timer int on secondary nodes, which causes | |
1312 | * a small but painful rift in the time-space continuum | |
1313 | */ | |
1314 | if (multi_timer_check(apic, irq)) | |
1315 | continue; | |
1316 | else | |
1317 | add_pin_to_irq(irq, apic, pin); | |
1318 | ||
1319 | if (!apic && !IO_APIC_IRQ(irq)) | |
1320 | continue; | |
1321 | ||
1322 | if (IO_APIC_IRQ(irq)) { | |
1323 | vector = assign_irq_vector(irq); | |
1324 | entry.vector = vector; | |
1325 | ioapic_register_intr(irq, vector, IOAPIC_AUTO); | |
1326 | ||
1327 | if (!apic && (irq < 16)) | |
1328 | disable_8259A_irq(irq); | |
1329 | } | |
1330 | spin_lock_irqsave(&ioapic_lock, flags); | |
d15512f4 | 1331 | __ioapic_write_entry(apic, pin, entry); |
1da177e4 LT |
1332 | spin_unlock_irqrestore(&ioapic_lock, flags); |
1333 | } | |
1334 | } | |
1335 | ||
1336 | if (!first_notcon) | |
1337 | apic_printk(APIC_VERBOSE, " not connected.\n"); | |
1338 | } | |
1339 | ||
1340 | /* | |
1341 | * Set up the 8259A-master output pin: | |
1342 | */ | |
fcfd636a | 1343 | static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector) |
1da177e4 LT |
1344 | { |
1345 | struct IO_APIC_route_entry entry; | |
1da177e4 LT |
1346 | |
1347 | memset(&entry,0,sizeof(entry)); | |
1348 | ||
1349 | disable_8259A_irq(0); | |
1350 | ||
1351 | /* mask LVT0 */ | |
1352 | apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); | |
1353 | ||
1354 | /* | |
1355 | * We use logical delivery to get the timer IRQ | |
1356 | * to the first CPU. | |
1357 | */ | |
1358 | entry.dest_mode = INT_DEST_MODE; | |
1359 | entry.mask = 0; /* unmask IRQ now */ | |
1360 | entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS); | |
1361 | entry.delivery_mode = INT_DELIVERY_MODE; | |
1362 | entry.polarity = 0; | |
1363 | entry.trigger = 0; | |
1364 | entry.vector = vector; | |
1365 | ||
1366 | /* | |
1367 | * The timer IRQ doesn't have to know that behind the | |
1368 | * scene we have a 8259A-master in AEOI mode ... | |
1369 | */ | |
f5b9ed7a IM |
1370 | irq_desc[0].chip = &ioapic_chip; |
1371 | set_irq_handler(0, handle_edge_irq); | |
1da177e4 LT |
1372 | |
1373 | /* | |
1374 | * Add it to the IO-APIC irq-routing table: | |
1375 | */ | |
cf4c6a2f | 1376 | ioapic_write_entry(apic, pin, entry); |
1da177e4 LT |
1377 | |
1378 | enable_8259A_irq(0); | |
1379 | } | |
1380 | ||
1da177e4 LT |
1381 | void __init print_IO_APIC(void) |
1382 | { | |
1383 | int apic, i; | |
1384 | union IO_APIC_reg_00 reg_00; | |
1385 | union IO_APIC_reg_01 reg_01; | |
1386 | union IO_APIC_reg_02 reg_02; | |
1387 | union IO_APIC_reg_03 reg_03; | |
1388 | unsigned long flags; | |
1389 | ||
1390 | if (apic_verbosity == APIC_QUIET) | |
1391 | return; | |
1392 | ||
1393 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); | |
1394 | for (i = 0; i < nr_ioapics; i++) | |
1395 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", | |
1396 | mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]); | |
1397 | ||
1398 | /* | |
1399 | * We are a bit conservative about what we expect. We have to | |
1400 | * know about every hardware change ASAP. | |
1401 | */ | |
1402 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1403 | ||
1404 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1405 | ||
1406 | spin_lock_irqsave(&ioapic_lock, flags); | |
1407 | reg_00.raw = io_apic_read(apic, 0); | |
1408 | reg_01.raw = io_apic_read(apic, 1); | |
1409 | if (reg_01.bits.version >= 0x10) | |
1410 | reg_02.raw = io_apic_read(apic, 2); | |
1411 | if (reg_01.bits.version >= 0x20) | |
1412 | reg_03.raw = io_apic_read(apic, 3); | |
1413 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1414 | ||
1415 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid); | |
1416 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); | |
1417 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1418 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1419 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 LT |
1420 | |
1421 | printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw); | |
1422 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); | |
1da177e4 LT |
1423 | |
1424 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
1425 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); | |
1da177e4 LT |
1426 | |
1427 | /* | |
1428 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1429 | * but the value of reg_02 is read as the previous read register | |
1430 | * value, so ignore it if reg_02 == reg_01. | |
1431 | */ | |
1432 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1433 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1434 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1435 | } |
1436 | ||
1437 | /* | |
1438 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1439 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1440 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1441 | */ | |
1442 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1443 | reg_03.raw != reg_01.raw) { | |
1444 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1445 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1446 | } |
1447 | ||
1448 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1449 | ||
1450 | printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol" | |
1451 | " Stat Dest Deli Vect: \n"); | |
1452 | ||
1453 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
1454 | struct IO_APIC_route_entry entry; | |
1455 | ||
cf4c6a2f | 1456 | entry = ioapic_read_entry(apic, i); |
1da177e4 LT |
1457 | |
1458 | printk(KERN_DEBUG " %02x %03X %02X ", | |
1459 | i, | |
1460 | entry.dest.logical.logical_dest, | |
1461 | entry.dest.physical.physical_dest | |
1462 | ); | |
1463 | ||
1464 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", | |
1465 | entry.mask, | |
1466 | entry.trigger, | |
1467 | entry.irr, | |
1468 | entry.polarity, | |
1469 | entry.delivery_status, | |
1470 | entry.dest_mode, | |
1471 | entry.delivery_mode, | |
1472 | entry.vector | |
1473 | ); | |
1474 | } | |
1475 | } | |
1da177e4 LT |
1476 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
1477 | for (i = 0; i < NR_IRQS; i++) { | |
1478 | struct irq_pin_list *entry = irq_2_pin + i; | |
1479 | if (entry->pin < 0) | |
1480 | continue; | |
ace80ab7 | 1481 | printk(KERN_DEBUG "IRQ%d ", i); |
1da177e4 LT |
1482 | for (;;) { |
1483 | printk("-> %d:%d", entry->apic, entry->pin); | |
1484 | if (!entry->next) | |
1485 | break; | |
1486 | entry = irq_2_pin + entry->next; | |
1487 | } | |
1488 | printk("\n"); | |
1489 | } | |
1490 | ||
1491 | printk(KERN_INFO ".................................... done.\n"); | |
1492 | ||
1493 | return; | |
1494 | } | |
1495 | ||
1496 | #if 0 | |
1497 | ||
1498 | static void print_APIC_bitfield (int base) | |
1499 | { | |
1500 | unsigned int v; | |
1501 | int i, j; | |
1502 | ||
1503 | if (apic_verbosity == APIC_QUIET) | |
1504 | return; | |
1505 | ||
1506 | printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG); | |
1507 | for (i = 0; i < 8; i++) { | |
1508 | v = apic_read(base + i*0x10); | |
1509 | for (j = 0; j < 32; j++) { | |
1510 | if (v & (1<<j)) | |
1511 | printk("1"); | |
1512 | else | |
1513 | printk("0"); | |
1514 | } | |
1515 | printk("\n"); | |
1516 | } | |
1517 | } | |
1518 | ||
1519 | void /*__init*/ print_local_APIC(void * dummy) | |
1520 | { | |
1521 | unsigned int v, ver, maxlvt; | |
1522 | ||
1523 | if (apic_verbosity == APIC_QUIET) | |
1524 | return; | |
1525 | ||
1526 | printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", | |
1527 | smp_processor_id(), hard_smp_processor_id()); | |
1528 | v = apic_read(APIC_ID); | |
1529 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v)); | |
1530 | v = apic_read(APIC_LVR); | |
1531 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1532 | ver = GET_APIC_VERSION(v); | |
e05d723f | 1533 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1534 | |
1535 | v = apic_read(APIC_TASKPRI); | |
1536 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1537 | ||
1538 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ | |
1539 | v = apic_read(APIC_ARBPRI); | |
1540 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1541 | v & APIC_ARBPRI_MASK); | |
1542 | v = apic_read(APIC_PROCPRI); | |
1543 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1544 | } | |
1545 | ||
1546 | v = apic_read(APIC_EOI); | |
1547 | printk(KERN_DEBUG "... APIC EOI: %08x\n", v); | |
1548 | v = apic_read(APIC_RRR); | |
1549 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1550 | v = apic_read(APIC_LDR); | |
1551 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
1552 | v = apic_read(APIC_DFR); | |
1553 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1554 | v = apic_read(APIC_SPIV); | |
1555 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1556 | ||
1557 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
1558 | print_APIC_bitfield(APIC_ISR); | |
1559 | printk(KERN_DEBUG "... APIC TMR field:\n"); | |
1560 | print_APIC_bitfield(APIC_TMR); | |
1561 | printk(KERN_DEBUG "... APIC IRR field:\n"); | |
1562 | print_APIC_bitfield(APIC_IRR); | |
1563 | ||
1564 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ | |
1565 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1566 | apic_write(APIC_ESR, 0); | |
1567 | v = apic_read(APIC_ESR); | |
1568 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1569 | } | |
1570 | ||
1571 | v = apic_read(APIC_ICR); | |
1572 | printk(KERN_DEBUG "... APIC ICR: %08x\n", v); | |
1573 | v = apic_read(APIC_ICR2); | |
1574 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", v); | |
1575 | ||
1576 | v = apic_read(APIC_LVTT); | |
1577 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1578 | ||
1579 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1580 | v = apic_read(APIC_LVTPC); | |
1581 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1582 | } | |
1583 | v = apic_read(APIC_LVT0); | |
1584 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1585 | v = apic_read(APIC_LVT1); | |
1586 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1587 | ||
1588 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1589 | v = apic_read(APIC_LVTERR); | |
1590 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1591 | } | |
1592 | ||
1593 | v = apic_read(APIC_TMICT); | |
1594 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1595 | v = apic_read(APIC_TMCCT); | |
1596 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1597 | v = apic_read(APIC_TDCR); | |
1598 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
1599 | printk("\n"); | |
1600 | } | |
1601 | ||
1602 | void print_all_local_APICs (void) | |
1603 | { | |
1604 | on_each_cpu(print_local_APIC, NULL, 1, 1); | |
1605 | } | |
1606 | ||
1607 | void /*__init*/ print_PIC(void) | |
1608 | { | |
1da177e4 LT |
1609 | unsigned int v; |
1610 | unsigned long flags; | |
1611 | ||
1612 | if (apic_verbosity == APIC_QUIET) | |
1613 | return; | |
1614 | ||
1615 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1616 | ||
1617 | spin_lock_irqsave(&i8259A_lock, flags); | |
1618 | ||
1619 | v = inb(0xa1) << 8 | inb(0x21); | |
1620 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1621 | ||
1622 | v = inb(0xa0) << 8 | inb(0x20); | |
1623 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1624 | ||
1625 | outb(0x0b,0xa0); | |
1626 | outb(0x0b,0x20); | |
1627 | v = inb(0xa0) << 8 | inb(0x20); | |
1628 | outb(0x0a,0xa0); | |
1629 | outb(0x0a,0x20); | |
1630 | ||
1631 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
1632 | ||
1633 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1634 | ||
1635 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1636 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1637 | } | |
1638 | ||
1639 | #endif /* 0 */ | |
1640 | ||
1641 | static void __init enable_IO_APIC(void) | |
1642 | { | |
1643 | union IO_APIC_reg_01 reg_01; | |
fcfd636a EB |
1644 | int i8259_apic, i8259_pin; |
1645 | int i, apic; | |
1da177e4 LT |
1646 | unsigned long flags; |
1647 | ||
1648 | for (i = 0; i < PIN_MAP_SIZE; i++) { | |
1649 | irq_2_pin[i].pin = -1; | |
1650 | irq_2_pin[i].next = 0; | |
1651 | } | |
1652 | if (!pirqs_enabled) | |
1653 | for (i = 0; i < MAX_PIRQS; i++) | |
1654 | pirq_entries[i] = -1; | |
1655 | ||
1656 | /* | |
1657 | * The number of IO-APIC IRQ registers (== #pins): | |
1658 | */ | |
fcfd636a | 1659 | for (apic = 0; apic < nr_ioapics; apic++) { |
1da177e4 | 1660 | spin_lock_irqsave(&ioapic_lock, flags); |
fcfd636a | 1661 | reg_01.raw = io_apic_read(apic, 1); |
1da177e4 | 1662 | spin_unlock_irqrestore(&ioapic_lock, flags); |
fcfd636a EB |
1663 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; |
1664 | } | |
1665 | for(apic = 0; apic < nr_ioapics; apic++) { | |
1666 | int pin; | |
1667 | /* See if any of the pins is in ExtINT mode */ | |
1008fddc | 1668 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
fcfd636a | 1669 | struct IO_APIC_route_entry entry; |
cf4c6a2f | 1670 | entry = ioapic_read_entry(apic, pin); |
fcfd636a EB |
1671 | |
1672 | ||
1673 | /* If the interrupt line is enabled and in ExtInt mode | |
1674 | * I have found the pin where the i8259 is connected. | |
1675 | */ | |
1676 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1677 | ioapic_i8259.apic = apic; | |
1678 | ioapic_i8259.pin = pin; | |
1679 | goto found_i8259; | |
1680 | } | |
1681 | } | |
1682 | } | |
1683 | found_i8259: | |
1684 | /* Look to see what if the MP table has reported the ExtINT */ | |
1685 | /* If we could not find the appropriate pin by looking at the ioapic | |
1686 | * the i8259 probably is not connected the ioapic but give the | |
1687 | * mptable a chance anyway. | |
1688 | */ | |
1689 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1690 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1691 | /* Trust the MP table if nothing is setup in the hardware */ | |
1692 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1693 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1694 | ioapic_i8259.pin = i8259_pin; | |
1695 | ioapic_i8259.apic = i8259_apic; | |
1696 | } | |
1697 | /* Complain if the MP table and the hardware disagree */ | |
1698 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1699 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1700 | { | |
1701 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1702 | } |
1703 | ||
1704 | /* | |
1705 | * Do not trust the IO-APIC being empty at bootup | |
1706 | */ | |
1707 | clear_IO_APIC(); | |
1708 | } | |
1709 | ||
1710 | /* | |
1711 | * Not an __init, needed by the reboot code | |
1712 | */ | |
1713 | void disable_IO_APIC(void) | |
1714 | { | |
1715 | /* | |
1716 | * Clear the IO-APIC before rebooting: | |
1717 | */ | |
1718 | clear_IO_APIC(); | |
1719 | ||
650927ef | 1720 | /* |
0b968d23 | 1721 | * If the i8259 is routed through an IOAPIC |
650927ef | 1722 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 1723 | * so legacy interrupts can be delivered. |
650927ef | 1724 | */ |
fcfd636a | 1725 | if (ioapic_i8259.pin != -1) { |
650927ef | 1726 | struct IO_APIC_route_entry entry; |
650927ef EB |
1727 | |
1728 | memset(&entry, 0, sizeof(entry)); | |
1729 | entry.mask = 0; /* Enabled */ | |
1730 | entry.trigger = 0; /* Edge */ | |
1731 | entry.irr = 0; | |
1732 | entry.polarity = 0; /* High */ | |
1733 | entry.delivery_status = 0; | |
1734 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 1735 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 1736 | entry.vector = 0; |
76865c3f VG |
1737 | entry.dest.physical.physical_dest = |
1738 | GET_APIC_ID(apic_read(APIC_ID)); | |
650927ef EB |
1739 | |
1740 | /* | |
1741 | * Add it to the IO-APIC irq-routing table: | |
1742 | */ | |
cf4c6a2f | 1743 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 1744 | } |
fcfd636a | 1745 | disconnect_bsp_APIC(ioapic_i8259.pin != -1); |
1da177e4 LT |
1746 | } |
1747 | ||
1748 | /* | |
1749 | * function to set the IO-APIC physical IDs based on the | |
1750 | * values stored in the MPC table. | |
1751 | * | |
1752 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
1753 | */ | |
1754 | ||
1755 | #ifndef CONFIG_X86_NUMAQ | |
1756 | static void __init setup_ioapic_ids_from_mpc(void) | |
1757 | { | |
1758 | union IO_APIC_reg_00 reg_00; | |
1759 | physid_mask_t phys_id_present_map; | |
1760 | int apic; | |
1761 | int i; | |
1762 | unsigned char old_id; | |
1763 | unsigned long flags; | |
1764 | ||
ca05fea6 NP |
1765 | /* |
1766 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
1767 | * no meaning without the serial APIC bus. | |
1768 | */ | |
7c5c1e42 SL |
1769 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
1770 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
ca05fea6 | 1771 | return; |
1da177e4 LT |
1772 | /* |
1773 | * This is broken; anything with a real cpu count has to | |
1774 | * circumvent this idiocy regardless. | |
1775 | */ | |
1776 | phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map); | |
1777 | ||
1778 | /* | |
1779 | * Set the IOAPIC ID to the value stored in the MPC table. | |
1780 | */ | |
1781 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1782 | ||
1783 | /* Read the register 0 value */ | |
1784 | spin_lock_irqsave(&ioapic_lock, flags); | |
1785 | reg_00.raw = io_apic_read(apic, 0); | |
1786 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1787 | ||
1788 | old_id = mp_ioapics[apic].mpc_apicid; | |
1789 | ||
1790 | if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) { | |
1791 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", | |
1792 | apic, mp_ioapics[apic].mpc_apicid); | |
1793 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
1794 | reg_00.bits.ID); | |
1795 | mp_ioapics[apic].mpc_apicid = reg_00.bits.ID; | |
1796 | } | |
1797 | ||
1da177e4 LT |
1798 | /* |
1799 | * Sanity check, is the ID really free? Every APIC in a | |
1800 | * system must have a unique ID or we get lots of nice | |
1801 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
1802 | */ | |
1803 | if (check_apicid_used(phys_id_present_map, | |
1804 | mp_ioapics[apic].mpc_apicid)) { | |
1805 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", | |
1806 | apic, mp_ioapics[apic].mpc_apicid); | |
1807 | for (i = 0; i < get_physical_broadcast(); i++) | |
1808 | if (!physid_isset(i, phys_id_present_map)) | |
1809 | break; | |
1810 | if (i >= get_physical_broadcast()) | |
1811 | panic("Max APIC ID exceeded!\n"); | |
1812 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
1813 | i); | |
1814 | physid_set(i, phys_id_present_map); | |
1815 | mp_ioapics[apic].mpc_apicid = i; | |
1816 | } else { | |
1817 | physid_mask_t tmp; | |
1818 | tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid); | |
1819 | apic_printk(APIC_VERBOSE, "Setting %d in the " | |
1820 | "phys_id_present_map\n", | |
1821 | mp_ioapics[apic].mpc_apicid); | |
1822 | physids_or(phys_id_present_map, phys_id_present_map, tmp); | |
1823 | } | |
1824 | ||
1825 | ||
1826 | /* | |
1827 | * We need to adjust the IRQ routing table | |
1828 | * if the ID changed. | |
1829 | */ | |
1830 | if (old_id != mp_ioapics[apic].mpc_apicid) | |
1831 | for (i = 0; i < mp_irq_entries; i++) | |
1832 | if (mp_irqs[i].mpc_dstapic == old_id) | |
1833 | mp_irqs[i].mpc_dstapic | |
1834 | = mp_ioapics[apic].mpc_apicid; | |
1835 | ||
1836 | /* | |
1837 | * Read the right value from the MPC table and | |
1838 | * write it into the ID register. | |
1839 | */ | |
1840 | apic_printk(APIC_VERBOSE, KERN_INFO | |
1841 | "...changing IO-APIC physical APIC ID to %d ...", | |
1842 | mp_ioapics[apic].mpc_apicid); | |
1843 | ||
1844 | reg_00.bits.ID = mp_ioapics[apic].mpc_apicid; | |
1845 | spin_lock_irqsave(&ioapic_lock, flags); | |
1846 | io_apic_write(apic, 0, reg_00.raw); | |
1847 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1848 | ||
1849 | /* | |
1850 | * Sanity check | |
1851 | */ | |
1852 | spin_lock_irqsave(&ioapic_lock, flags); | |
1853 | reg_00.raw = io_apic_read(apic, 0); | |
1854 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1855 | if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid) | |
1856 | printk("could not set ID!\n"); | |
1857 | else | |
1858 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
1859 | } | |
1860 | } | |
1861 | #else | |
1862 | static void __init setup_ioapic_ids_from_mpc(void) { } | |
1863 | #endif | |
1864 | ||
7ce0bcfd | 1865 | int no_timer_check __initdata; |
8542b200 ZA |
1866 | |
1867 | static int __init notimercheck(char *s) | |
1868 | { | |
1869 | no_timer_check = 1; | |
1870 | return 1; | |
1871 | } | |
1872 | __setup("no_timer_check", notimercheck); | |
1873 | ||
1da177e4 LT |
1874 | /* |
1875 | * There is a nasty bug in some older SMP boards, their mptable lies | |
1876 | * about the timer IRQ. We do the following to work around the situation: | |
1877 | * | |
1878 | * - timer IRQ defaults to IO-APIC IRQ | |
1879 | * - if this function detects that timer IRQs are defunct, then we fall | |
1880 | * back to ISA timer IRQs | |
1881 | */ | |
f0a7a5c9 | 1882 | static int __init timer_irq_works(void) |
1da177e4 LT |
1883 | { |
1884 | unsigned long t1 = jiffies; | |
1885 | ||
8542b200 ZA |
1886 | if (no_timer_check) |
1887 | return 1; | |
1888 | ||
1da177e4 LT |
1889 | local_irq_enable(); |
1890 | /* Let ten ticks pass... */ | |
1891 | mdelay((10 * 1000) / HZ); | |
1892 | ||
1893 | /* | |
1894 | * Expect a few ticks at least, to be sure some possible | |
1895 | * glue logic does not lock up after one or two first | |
1896 | * ticks in a non-ExtINT mode. Also the local APIC | |
1897 | * might have cached one ExtINT interrupt. Finally, at | |
1898 | * least one tick may be lost due to delays. | |
1899 | */ | |
1900 | if (jiffies - t1 > 4) | |
1901 | return 1; | |
1902 | ||
1903 | return 0; | |
1904 | } | |
1905 | ||
1906 | /* | |
1907 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
1908 | * number of pending IRQ events unhandled. These cases are very rare, | |
1909 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
1910 | * better to do it this way as thus we do not have to be aware of | |
1911 | * 'pending' interrupts in the IRQ path, except at this point. | |
1912 | */ | |
1913 | /* | |
1914 | * Edge triggered needs to resend any interrupt | |
1915 | * that was delayed but this is now handled in the device | |
1916 | * independent code. | |
1917 | */ | |
1918 | ||
1919 | /* | |
f5b9ed7a IM |
1920 | * Startup quirk: |
1921 | * | |
1da177e4 LT |
1922 | * Starting up a edge-triggered IO-APIC interrupt is |
1923 | * nasty - we need to make sure that we get the edge. | |
1924 | * If it is already asserted for some reason, we need | |
1925 | * return 1 to indicate that is was pending. | |
1926 | * | |
1927 | * This is not complete - we should be able to fake | |
1928 | * an edge even if it isn't on the 8259A... | |
f5b9ed7a IM |
1929 | * |
1930 | * (We do this for level-triggered IRQs too - it cannot hurt.) | |
1da177e4 | 1931 | */ |
f5b9ed7a | 1932 | static unsigned int startup_ioapic_irq(unsigned int irq) |
1da177e4 LT |
1933 | { |
1934 | int was_pending = 0; | |
1935 | unsigned long flags; | |
1936 | ||
1937 | spin_lock_irqsave(&ioapic_lock, flags); | |
1938 | if (irq < 16) { | |
1939 | disable_8259A_irq(irq); | |
1940 | if (i8259A_irq_pending(irq)) | |
1941 | was_pending = 1; | |
1942 | } | |
1943 | __unmask_IO_APIC_irq(irq); | |
1944 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1945 | ||
1946 | return was_pending; | |
1947 | } | |
1948 | ||
f5b9ed7a | 1949 | static void ack_ioapic_irq(unsigned int irq) |
1da177e4 | 1950 | { |
ace80ab7 | 1951 | move_native_irq(irq); |
1da177e4 LT |
1952 | ack_APIC_irq(); |
1953 | } | |
1954 | ||
f5b9ed7a | 1955 | static void ack_ioapic_quirk_irq(unsigned int irq) |
1da177e4 LT |
1956 | { |
1957 | unsigned long v; | |
1958 | int i; | |
1959 | ||
ace80ab7 | 1960 | move_native_irq(irq); |
1da177e4 LT |
1961 | /* |
1962 | * It appears there is an erratum which affects at least version 0x11 | |
1963 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
1964 | * chipsets). Under certain conditions a level-triggered interrupt is | |
1965 | * erroneously delivered as edge-triggered one but the respective IRR | |
1966 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
1967 | * message but it will never arrive and further interrupts are blocked | |
1968 | * from the source. The exact reason is so far unknown, but the | |
1969 | * phenomenon was observed when two consecutive interrupt requests | |
1970 | * from a given source get delivered to the same CPU and the source is | |
1971 | * temporarily disabled in between. | |
1972 | * | |
1973 | * A workaround is to simulate an EOI message manually. We achieve it | |
1974 | * by setting the trigger mode to edge and then to level when the edge | |
1975 | * trigger mode gets detected in the TMR of a local APIC for a | |
1976 | * level-triggered interrupt. We mask the source for the time of the | |
1977 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
1978 | * The idea is from Manfred Spraul. --macro | |
1979 | */ | |
b940d22d | 1980 | i = irq_vector[irq]; |
1da177e4 LT |
1981 | |
1982 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); | |
1983 | ||
1984 | ack_APIC_irq(); | |
1985 | ||
1986 | if (!(v & (1 << (i & 0x1f)))) { | |
1987 | atomic_inc(&irq_mis_count); | |
1988 | spin_lock(&ioapic_lock); | |
1989 | __mask_and_edge_IO_APIC_irq(irq); | |
1990 | __unmask_and_level_IO_APIC_irq(irq); | |
1991 | spin_unlock(&ioapic_lock); | |
1992 | } | |
1993 | } | |
1994 | ||
ace80ab7 | 1995 | static int ioapic_retrigger_irq(unsigned int irq) |
1da177e4 | 1996 | { |
b940d22d | 1997 | send_IPI_self(irq_vector[irq]); |
c0ad90a3 IM |
1998 | |
1999 | return 1; | |
2000 | } | |
2001 | ||
f5b9ed7a IM |
2002 | static struct irq_chip ioapic_chip __read_mostly = { |
2003 | .name = "IO-APIC", | |
ace80ab7 EB |
2004 | .startup = startup_ioapic_irq, |
2005 | .mask = mask_IO_APIC_irq, | |
2006 | .unmask = unmask_IO_APIC_irq, | |
2007 | .ack = ack_ioapic_irq, | |
2008 | .eoi = ack_ioapic_quirk_irq, | |
54d5d424 | 2009 | #ifdef CONFIG_SMP |
ace80ab7 | 2010 | .set_affinity = set_ioapic_affinity_irq, |
54d5d424 | 2011 | #endif |
ace80ab7 | 2012 | .retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
2013 | }; |
2014 | ||
1da177e4 LT |
2015 | |
2016 | static inline void init_IO_APIC_traps(void) | |
2017 | { | |
2018 | int irq; | |
2019 | ||
2020 | /* | |
2021 | * NOTE! The local APIC isn't very good at handling | |
2022 | * multiple interrupts at the same interrupt level. | |
2023 | * As the interrupt level is determined by taking the | |
2024 | * vector number and shifting that right by 4, we | |
2025 | * want to spread these out a bit so that they don't | |
2026 | * all fall in the same interrupt level. | |
2027 | * | |
2028 | * Also, we've got to be careful not to trash gate | |
2029 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
2030 | */ | |
2031 | for (irq = 0; irq < NR_IRQS ; irq++) { | |
2032 | int tmp = irq; | |
b940d22d | 2033 | if (IO_APIC_IRQ(tmp) && !irq_vector[tmp]) { |
1da177e4 LT |
2034 | /* |
2035 | * Hmm.. We don't have an entry for this, | |
2036 | * so default to an old-fashioned 8259 | |
2037 | * interrupt if we can.. | |
2038 | */ | |
2039 | if (irq < 16) | |
2040 | make_8259A_irq(irq); | |
2041 | else | |
2042 | /* Strange. Oh, well.. */ | |
f5b9ed7a | 2043 | irq_desc[irq].chip = &no_irq_chip; |
1da177e4 LT |
2044 | } |
2045 | } | |
2046 | } | |
2047 | ||
f5b9ed7a IM |
2048 | /* |
2049 | * The local APIC irq-chip implementation: | |
2050 | */ | |
1da177e4 | 2051 | |
f5b9ed7a IM |
2052 | static void ack_apic(unsigned int irq) |
2053 | { | |
2054 | ack_APIC_irq(); | |
1da177e4 LT |
2055 | } |
2056 | ||
f5b9ed7a | 2057 | static void mask_lapic_irq (unsigned int irq) |
1da177e4 LT |
2058 | { |
2059 | unsigned long v; | |
2060 | ||
2061 | v = apic_read(APIC_LVT0); | |
2062 | apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED); | |
2063 | } | |
2064 | ||
f5b9ed7a | 2065 | static void unmask_lapic_irq (unsigned int irq) |
1da177e4 | 2066 | { |
f5b9ed7a | 2067 | unsigned long v; |
1da177e4 | 2068 | |
f5b9ed7a IM |
2069 | v = apic_read(APIC_LVT0); |
2070 | apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED); | |
2071 | } | |
1da177e4 | 2072 | |
f5b9ed7a IM |
2073 | static struct irq_chip lapic_chip __read_mostly = { |
2074 | .name = "local-APIC-edge", | |
2075 | .mask = mask_lapic_irq, | |
2076 | .unmask = unmask_lapic_irq, | |
2077 | .eoi = ack_apic, | |
1da177e4 LT |
2078 | }; |
2079 | ||
2080 | static void setup_nmi (void) | |
2081 | { | |
2082 | /* | |
2083 | * Dirty trick to enable the NMI watchdog ... | |
2084 | * We put the 8259A master into AEOI mode and | |
2085 | * unmask on all local APICs LVT0 as NMI. | |
2086 | * | |
2087 | * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') | |
2088 | * is from Maciej W. Rozycki - so we do not have to EOI from | |
2089 | * the NMI handler or the timer interrupt. | |
2090 | */ | |
2091 | apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ..."); | |
2092 | ||
2093 | on_each_cpu(enable_NMI_through_LVT0, NULL, 1, 1); | |
2094 | ||
2095 | apic_printk(APIC_VERBOSE, " done.\n"); | |
2096 | } | |
2097 | ||
2098 | /* | |
2099 | * This looks a bit hackish but it's about the only one way of sending | |
2100 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2101 | * not support the ExtINT mode, unfortunately. We need to send these | |
2102 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2103 | * 8259A interrupt line asserted until INTA. --macro | |
2104 | */ | |
2105 | static inline void unlock_ExtINT_logic(void) | |
2106 | { | |
fcfd636a | 2107 | int apic, pin, i; |
1da177e4 LT |
2108 | struct IO_APIC_route_entry entry0, entry1; |
2109 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2110 | |
fcfd636a | 2111 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2112 | if (pin == -1) { |
2113 | WARN_ON_ONCE(1); | |
2114 | return; | |
2115 | } | |
fcfd636a | 2116 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2117 | if (apic == -1) { |
2118 | WARN_ON_ONCE(1); | |
1da177e4 | 2119 | return; |
956fb531 | 2120 | } |
1da177e4 | 2121 | |
cf4c6a2f | 2122 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2123 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2124 | |
2125 | memset(&entry1, 0, sizeof(entry1)); | |
2126 | ||
2127 | entry1.dest_mode = 0; /* physical delivery */ | |
2128 | entry1.mask = 0; /* unmask IRQ now */ | |
2129 | entry1.dest.physical.physical_dest = hard_smp_processor_id(); | |
2130 | entry1.delivery_mode = dest_ExtINT; | |
2131 | entry1.polarity = entry0.polarity; | |
2132 | entry1.trigger = 0; | |
2133 | entry1.vector = 0; | |
2134 | ||
cf4c6a2f | 2135 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2136 | |
2137 | save_control = CMOS_READ(RTC_CONTROL); | |
2138 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2139 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2140 | RTC_FREQ_SELECT); | |
2141 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2142 | ||
2143 | i = 100; | |
2144 | while (i-- > 0) { | |
2145 | mdelay(10); | |
2146 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2147 | i -= 10; | |
2148 | } | |
2149 | ||
2150 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2151 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2152 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2153 | |
cf4c6a2f | 2154 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2155 | } |
2156 | ||
e0c1e9bf KM |
2157 | int timer_uses_ioapic_pin_0; |
2158 | ||
1da177e4 LT |
2159 | /* |
2160 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2161 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2162 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2163 | * fanatically on his truly buggy board. | |
2164 | */ | |
8542b200 | 2165 | static inline void __init check_timer(void) |
1da177e4 | 2166 | { |
fcfd636a | 2167 | int apic1, pin1, apic2, pin2; |
1da177e4 | 2168 | int vector; |
d4d25dec MR |
2169 | unsigned int ver; |
2170 | ||
2171 | ver = apic_read(APIC_LVR); | |
2172 | ver = GET_APIC_VERSION(ver); | |
1da177e4 LT |
2173 | |
2174 | /* | |
2175 | * get/set the timer IRQ vector: | |
2176 | */ | |
2177 | disable_8259A_irq(0); | |
2178 | vector = assign_irq_vector(0); | |
2179 | set_intr_gate(vector, interrupt[0]); | |
2180 | ||
2181 | /* | |
2182 | * Subtle, code in do_timer_interrupt() expects an AEOI | |
2183 | * mode for the 8259A whenever interrupts are routed | |
2184 | * through I/O APICs. Also IRQ0 has to be enabled in | |
2185 | * the 8259A which implies the virtual wire has to be | |
d4d25dec MR |
2186 | * disabled in the local APIC. Finally timer interrupts |
2187 | * need to be acknowledged manually in the 8259A for | |
2188 | * timer_interrupt() and for the i82489DX when using | |
2189 | * the NMI watchdog. | |
1da177e4 LT |
2190 | */ |
2191 | apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); | |
2192 | init_8259A(1); | |
d4d25dec MR |
2193 | timer_ack = !cpu_has_tsc; |
2194 | timer_ack |= (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver)); | |
f9262c12 AK |
2195 | if (timer_over_8254 > 0) |
2196 | enable_8259A_irq(0); | |
1da177e4 | 2197 | |
fcfd636a EB |
2198 | pin1 = find_isa_irq_pin(0, mp_INT); |
2199 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2200 | pin2 = ioapic_i8259.pin; | |
2201 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2202 | |
e0c1e9bf KM |
2203 | if (pin1 == 0) |
2204 | timer_uses_ioapic_pin_0 = 1; | |
2205 | ||
fcfd636a EB |
2206 | printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n", |
2207 | vector, apic1, pin1, apic2, pin2); | |
1da177e4 LT |
2208 | |
2209 | if (pin1 != -1) { | |
2210 | /* | |
2211 | * Ok, does IRQ0 through the IOAPIC work? | |
2212 | */ | |
2213 | unmask_IO_APIC_irq(0); | |
2214 | if (timer_irq_works()) { | |
2215 | if (nmi_watchdog == NMI_IO_APIC) { | |
2216 | disable_8259A_irq(0); | |
2217 | setup_nmi(); | |
2218 | enable_8259A_irq(0); | |
1da177e4 | 2219 | } |
66759a01 CE |
2220 | if (disable_timer_pin_1 > 0) |
2221 | clear_IO_APIC_pin(0, pin1); | |
1da177e4 LT |
2222 | return; |
2223 | } | |
fcfd636a EB |
2224 | clear_IO_APIC_pin(apic1, pin1); |
2225 | printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to " | |
2226 | "IO-APIC\n"); | |
1da177e4 LT |
2227 | } |
2228 | ||
2229 | printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... "); | |
2230 | if (pin2 != -1) { | |
2231 | printk("\n..... (found pin %d) ...", pin2); | |
2232 | /* | |
2233 | * legacy devices should be connected to IO APIC #0 | |
2234 | */ | |
fcfd636a | 2235 | setup_ExtINT_IRQ0_pin(apic2, pin2, vector); |
1da177e4 LT |
2236 | if (timer_irq_works()) { |
2237 | printk("works.\n"); | |
2238 | if (pin1 != -1) | |
fcfd636a | 2239 | replace_pin_at_irq(0, apic1, pin1, apic2, pin2); |
1da177e4 | 2240 | else |
fcfd636a | 2241 | add_pin_to_irq(0, apic2, pin2); |
1da177e4 LT |
2242 | if (nmi_watchdog == NMI_IO_APIC) { |
2243 | setup_nmi(); | |
1da177e4 LT |
2244 | } |
2245 | return; | |
2246 | } | |
2247 | /* | |
2248 | * Cleanup, just in case ... | |
2249 | */ | |
fcfd636a | 2250 | clear_IO_APIC_pin(apic2, pin2); |
1da177e4 LT |
2251 | } |
2252 | printk(" failed.\n"); | |
2253 | ||
2254 | if (nmi_watchdog == NMI_IO_APIC) { | |
2255 | printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n"); | |
2256 | nmi_watchdog = 0; | |
2257 | } | |
2258 | ||
2259 | printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ..."); | |
2260 | ||
2261 | disable_8259A_irq(0); | |
a460e745 | 2262 | set_irq_chip_and_handler_name(0, &lapic_chip, handle_fasteoi_irq, |
2e188938 | 2263 | "fasteoi"); |
1da177e4 LT |
2264 | apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */ |
2265 | enable_8259A_irq(0); | |
2266 | ||
2267 | if (timer_irq_works()) { | |
2268 | printk(" works.\n"); | |
2269 | return; | |
2270 | } | |
2271 | apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector); | |
2272 | printk(" failed.\n"); | |
2273 | ||
2274 | printk(KERN_INFO "...trying to set up timer as ExtINT IRQ..."); | |
2275 | ||
2276 | timer_ack = 0; | |
2277 | init_8259A(0); | |
2278 | make_8259A_irq(0); | |
2279 | apic_write_around(APIC_LVT0, APIC_DM_EXTINT); | |
2280 | ||
2281 | unlock_ExtINT_logic(); | |
2282 | ||
2283 | if (timer_irq_works()) { | |
2284 | printk(" works.\n"); | |
2285 | return; | |
2286 | } | |
2287 | printk(" failed :(.\n"); | |
2288 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " | |
2289 | "report. Then try booting with the 'noapic' option"); | |
2290 | } | |
2291 | ||
2292 | /* | |
2293 | * | |
2294 | * IRQ's that are handled by the PIC in the MPS IOAPIC case. | |
2295 | * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ. | |
2296 | * Linux doesn't really care, as it's not actually used | |
2297 | * for any interrupt handling anyway. | |
2298 | */ | |
2299 | #define PIC_IRQS (1 << PIC_CASCADE_IR) | |
2300 | ||
2301 | void __init setup_IO_APIC(void) | |
2302 | { | |
dbeb2be2 RR |
2303 | int i; |
2304 | ||
2305 | /* Reserve all the system vectors. */ | |
2306 | for (i = FIRST_SYSTEM_VECTOR; i < NR_VECTORS; i++) | |
2307 | set_bit(i, used_vectors); | |
2308 | ||
1da177e4 LT |
2309 | enable_IO_APIC(); |
2310 | ||
2311 | if (acpi_ioapic) | |
2312 | io_apic_irqs = ~0; /* all IRQs go through IOAPIC */ | |
2313 | else | |
2314 | io_apic_irqs = ~PIC_IRQS; | |
2315 | ||
2316 | printk("ENABLING IO-APIC IRQs\n"); | |
2317 | ||
2318 | /* | |
2319 | * Set up IO-APIC IRQ routing. | |
2320 | */ | |
2321 | if (!acpi_ioapic) | |
2322 | setup_ioapic_ids_from_mpc(); | |
2323 | sync_Arb_IDs(); | |
2324 | setup_IO_APIC_irqs(); | |
2325 | init_IO_APIC_traps(); | |
1e4c85f9 | 2326 | check_timer(); |
1da177e4 LT |
2327 | if (!acpi_ioapic) |
2328 | print_IO_APIC(); | |
2329 | } | |
2330 | ||
f9262c12 AK |
2331 | static int __init setup_disable_8254_timer(char *s) |
2332 | { | |
2333 | timer_over_8254 = -1; | |
2334 | return 1; | |
2335 | } | |
2336 | static int __init setup_enable_8254_timer(char *s) | |
2337 | { | |
2338 | timer_over_8254 = 2; | |
2339 | return 1; | |
2340 | } | |
2341 | ||
2342 | __setup("disable_8254_timer", setup_disable_8254_timer); | |
2343 | __setup("enable_8254_timer", setup_enable_8254_timer); | |
2344 | ||
1da177e4 LT |
2345 | /* |
2346 | * Called after all the initialization is done. If we didnt find any | |
2347 | * APIC bugs then we can allow the modify fast path | |
2348 | */ | |
2349 | ||
2350 | static int __init io_apic_bug_finalize(void) | |
2351 | { | |
2352 | if(sis_apic_bug == -1) | |
2353 | sis_apic_bug = 0; | |
2354 | return 0; | |
2355 | } | |
2356 | ||
2357 | late_initcall(io_apic_bug_finalize); | |
2358 | ||
2359 | struct sysfs_ioapic_data { | |
2360 | struct sys_device dev; | |
2361 | struct IO_APIC_route_entry entry[0]; | |
2362 | }; | |
2363 | static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS]; | |
2364 | ||
438510f6 | 2365 | static int ioapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
2366 | { |
2367 | struct IO_APIC_route_entry *entry; | |
2368 | struct sysfs_ioapic_data *data; | |
1da177e4 LT |
2369 | int i; |
2370 | ||
2371 | data = container_of(dev, struct sysfs_ioapic_data, dev); | |
2372 | entry = data->entry; | |
cf4c6a2f AK |
2373 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++) |
2374 | entry[i] = ioapic_read_entry(dev->id, i); | |
1da177e4 LT |
2375 | |
2376 | return 0; | |
2377 | } | |
2378 | ||
2379 | static int ioapic_resume(struct sys_device *dev) | |
2380 | { | |
2381 | struct IO_APIC_route_entry *entry; | |
2382 | struct sysfs_ioapic_data *data; | |
2383 | unsigned long flags; | |
2384 | union IO_APIC_reg_00 reg_00; | |
2385 | int i; | |
2386 | ||
2387 | data = container_of(dev, struct sysfs_ioapic_data, dev); | |
2388 | entry = data->entry; | |
2389 | ||
2390 | spin_lock_irqsave(&ioapic_lock, flags); | |
2391 | reg_00.raw = io_apic_read(dev->id, 0); | |
2392 | if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) { | |
2393 | reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid; | |
2394 | io_apic_write(dev->id, 0, reg_00.raw); | |
2395 | } | |
1da177e4 | 2396 | spin_unlock_irqrestore(&ioapic_lock, flags); |
cf4c6a2f AK |
2397 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++) |
2398 | ioapic_write_entry(dev->id, i, entry[i]); | |
1da177e4 LT |
2399 | |
2400 | return 0; | |
2401 | } | |
2402 | ||
2403 | static struct sysdev_class ioapic_sysdev_class = { | |
2404 | set_kset_name("ioapic"), | |
2405 | .suspend = ioapic_suspend, | |
2406 | .resume = ioapic_resume, | |
2407 | }; | |
2408 | ||
2409 | static int __init ioapic_init_sysfs(void) | |
2410 | { | |
2411 | struct sys_device * dev; | |
2412 | int i, size, error = 0; | |
2413 | ||
2414 | error = sysdev_class_register(&ioapic_sysdev_class); | |
2415 | if (error) | |
2416 | return error; | |
2417 | ||
2418 | for (i = 0; i < nr_ioapics; i++ ) { | |
2419 | size = sizeof(struct sys_device) + nr_ioapic_registers[i] | |
2420 | * sizeof(struct IO_APIC_route_entry); | |
2421 | mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL); | |
2422 | if (!mp_ioapic_data[i]) { | |
2423 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
2424 | continue; | |
2425 | } | |
2426 | memset(mp_ioapic_data[i], 0, size); | |
2427 | dev = &mp_ioapic_data[i]->dev; | |
2428 | dev->id = i; | |
2429 | dev->cls = &ioapic_sysdev_class; | |
2430 | error = sysdev_register(dev); | |
2431 | if (error) { | |
2432 | kfree(mp_ioapic_data[i]); | |
2433 | mp_ioapic_data[i] = NULL; | |
2434 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
2435 | continue; | |
2436 | } | |
2437 | } | |
2438 | ||
2439 | return 0; | |
2440 | } | |
2441 | ||
2442 | device_initcall(ioapic_init_sysfs); | |
2443 | ||
3fc471ed | 2444 | /* |
95d77884 | 2445 | * Dynamic irq allocate and deallocation |
3fc471ed EB |
2446 | */ |
2447 | int create_irq(void) | |
2448 | { | |
ace80ab7 | 2449 | /* Allocate an unused irq */ |
306a22c2 | 2450 | int irq, new, vector = 0; |
3fc471ed | 2451 | unsigned long flags; |
3fc471ed | 2452 | |
ace80ab7 EB |
2453 | irq = -ENOSPC; |
2454 | spin_lock_irqsave(&vector_lock, flags); | |
2455 | for (new = (NR_IRQS - 1); new >= 0; new--) { | |
2456 | if (platform_legacy_irq(new)) | |
2457 | continue; | |
2458 | if (irq_vector[new] != 0) | |
2459 | continue; | |
2460 | vector = __assign_irq_vector(new); | |
2461 | if (likely(vector > 0)) | |
2462 | irq = new; | |
2463 | break; | |
2464 | } | |
2465 | spin_unlock_irqrestore(&vector_lock, flags); | |
3fc471ed | 2466 | |
ace80ab7 | 2467 | if (irq >= 0) { |
3fc471ed | 2468 | set_intr_gate(vector, interrupt[irq]); |
3fc471ed EB |
2469 | dynamic_irq_init(irq); |
2470 | } | |
2471 | return irq; | |
2472 | } | |
2473 | ||
2474 | void destroy_irq(unsigned int irq) | |
2475 | { | |
2476 | unsigned long flags; | |
3fc471ed EB |
2477 | |
2478 | dynamic_irq_cleanup(irq); | |
2479 | ||
2480 | spin_lock_irqsave(&vector_lock, flags); | |
3fc471ed EB |
2481 | irq_vector[irq] = 0; |
2482 | spin_unlock_irqrestore(&vector_lock, flags); | |
2483 | } | |
3fc471ed | 2484 | |
2d3fcc1c | 2485 | /* |
27b46d76 | 2486 | * MSI message composition |
2d3fcc1c EB |
2487 | */ |
2488 | #ifdef CONFIG_PCI_MSI | |
3b7d1921 | 2489 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg) |
2d3fcc1c | 2490 | { |
2d3fcc1c EB |
2491 | int vector; |
2492 | unsigned dest; | |
2493 | ||
2494 | vector = assign_irq_vector(irq); | |
2495 | if (vector >= 0) { | |
2496 | dest = cpu_mask_to_apicid(TARGET_CPUS); | |
2497 | ||
2498 | msg->address_hi = MSI_ADDR_BASE_HI; | |
2499 | msg->address_lo = | |
2500 | MSI_ADDR_BASE_LO | | |
2501 | ((INT_DEST_MODE == 0) ? | |
2502 | MSI_ADDR_DEST_MODE_PHYSICAL: | |
2503 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
2504 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
2505 | MSI_ADDR_REDIRECTION_CPU: | |
2506 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
2507 | MSI_ADDR_DEST_ID(dest); | |
2508 | ||
2509 | msg->data = | |
2510 | MSI_DATA_TRIGGER_EDGE | | |
2511 | MSI_DATA_LEVEL_ASSERT | | |
2512 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
2513 | MSI_DATA_DELIVERY_FIXED: | |
2514 | MSI_DATA_DELIVERY_LOWPRI) | | |
2515 | MSI_DATA_VECTOR(vector); | |
2516 | } | |
2517 | return vector; | |
2518 | } | |
2519 | ||
3b7d1921 EB |
2520 | #ifdef CONFIG_SMP |
2521 | static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask) | |
2d3fcc1c | 2522 | { |
3b7d1921 EB |
2523 | struct msi_msg msg; |
2524 | unsigned int dest; | |
2525 | cpumask_t tmp; | |
2d3fcc1c | 2526 | int vector; |
3b7d1921 EB |
2527 | |
2528 | cpus_and(tmp, mask, cpu_online_map); | |
2529 | if (cpus_empty(tmp)) | |
2530 | tmp = TARGET_CPUS; | |
2d3fcc1c EB |
2531 | |
2532 | vector = assign_irq_vector(irq); | |
3b7d1921 EB |
2533 | if (vector < 0) |
2534 | return; | |
2d3fcc1c | 2535 | |
3b7d1921 EB |
2536 | dest = cpu_mask_to_apicid(mask); |
2537 | ||
2538 | read_msi_msg(irq, &msg); | |
2539 | ||
2540 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
2541 | msg.data |= MSI_DATA_VECTOR(vector); | |
2542 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
2543 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
2544 | ||
2545 | write_msi_msg(irq, &msg); | |
9f0a5ba5 | 2546 | irq_desc[irq].affinity = mask; |
2d3fcc1c | 2547 | } |
3b7d1921 | 2548 | #endif /* CONFIG_SMP */ |
2d3fcc1c | 2549 | |
3b7d1921 EB |
2550 | /* |
2551 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
2552 | * which implement the MSI or MSI-X Capability Structure. | |
2553 | */ | |
2554 | static struct irq_chip msi_chip = { | |
2555 | .name = "PCI-MSI", | |
2556 | .unmask = unmask_msi_irq, | |
2557 | .mask = mask_msi_irq, | |
2558 | .ack = ack_ioapic_irq, | |
2559 | #ifdef CONFIG_SMP | |
2560 | .set_affinity = set_msi_irq_affinity, | |
2561 | #endif | |
2562 | .retrigger = ioapic_retrigger_irq, | |
2d3fcc1c EB |
2563 | }; |
2564 | ||
f7feaca7 | 2565 | int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) |
3b7d1921 EB |
2566 | { |
2567 | struct msi_msg msg; | |
f7feaca7 EB |
2568 | int irq, ret; |
2569 | irq = create_irq(); | |
2570 | if (irq < 0) | |
2571 | return irq; | |
2572 | ||
3b7d1921 | 2573 | ret = msi_compose_msg(dev, irq, &msg); |
f7feaca7 EB |
2574 | if (ret < 0) { |
2575 | destroy_irq(irq); | |
3b7d1921 | 2576 | return ret; |
f7feaca7 | 2577 | } |
3b7d1921 | 2578 | |
7fe3730d | 2579 | set_irq_msi(irq, desc); |
3b7d1921 EB |
2580 | write_msi_msg(irq, &msg); |
2581 | ||
a460e745 IM |
2582 | set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, |
2583 | "edge"); | |
3b7d1921 | 2584 | |
7fe3730d | 2585 | return 0; |
3b7d1921 EB |
2586 | } |
2587 | ||
2588 | void arch_teardown_msi_irq(unsigned int irq) | |
2589 | { | |
f7feaca7 | 2590 | destroy_irq(irq); |
3b7d1921 EB |
2591 | } |
2592 | ||
2d3fcc1c EB |
2593 | #endif /* CONFIG_PCI_MSI */ |
2594 | ||
8b955b0d EB |
2595 | /* |
2596 | * Hypertransport interrupt support | |
2597 | */ | |
2598 | #ifdef CONFIG_HT_IRQ | |
2599 | ||
2600 | #ifdef CONFIG_SMP | |
2601 | ||
2602 | static void target_ht_irq(unsigned int irq, unsigned int dest) | |
2603 | { | |
ec68307c EB |
2604 | struct ht_irq_msg msg; |
2605 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 2606 | |
ec68307c EB |
2607 | msg.address_lo &= ~(HT_IRQ_LOW_DEST_ID_MASK); |
2608 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); | |
8b955b0d | 2609 | |
ec68307c EB |
2610 | msg.address_lo |= HT_IRQ_LOW_DEST_ID(dest); |
2611 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); | |
8b955b0d | 2612 | |
ec68307c | 2613 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
2614 | } |
2615 | ||
2616 | static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask) | |
2617 | { | |
2618 | unsigned int dest; | |
2619 | cpumask_t tmp; | |
2620 | ||
2621 | cpus_and(tmp, mask, cpu_online_map); | |
2622 | if (cpus_empty(tmp)) | |
2623 | tmp = TARGET_CPUS; | |
2624 | ||
2625 | cpus_and(mask, tmp, CPU_MASK_ALL); | |
2626 | ||
2627 | dest = cpu_mask_to_apicid(mask); | |
2628 | ||
2629 | target_ht_irq(irq, dest); | |
9f0a5ba5 | 2630 | irq_desc[irq].affinity = mask; |
8b955b0d EB |
2631 | } |
2632 | #endif | |
2633 | ||
c37e108d | 2634 | static struct irq_chip ht_irq_chip = { |
8b955b0d EB |
2635 | .name = "PCI-HT", |
2636 | .mask = mask_ht_irq, | |
2637 | .unmask = unmask_ht_irq, | |
2638 | .ack = ack_ioapic_irq, | |
2639 | #ifdef CONFIG_SMP | |
2640 | .set_affinity = set_ht_irq_affinity, | |
2641 | #endif | |
2642 | .retrigger = ioapic_retrigger_irq, | |
2643 | }; | |
2644 | ||
2645 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
2646 | { | |
2647 | int vector; | |
2648 | ||
2649 | vector = assign_irq_vector(irq); | |
2650 | if (vector >= 0) { | |
ec68307c | 2651 | struct ht_irq_msg msg; |
8b955b0d EB |
2652 | unsigned dest; |
2653 | cpumask_t tmp; | |
2654 | ||
2655 | cpus_clear(tmp); | |
2656 | cpu_set(vector >> 8, tmp); | |
2657 | dest = cpu_mask_to_apicid(tmp); | |
2658 | ||
ec68307c | 2659 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 2660 | |
ec68307c EB |
2661 | msg.address_lo = |
2662 | HT_IRQ_LOW_BASE | | |
8b955b0d EB |
2663 | HT_IRQ_LOW_DEST_ID(dest) | |
2664 | HT_IRQ_LOW_VECTOR(vector) | | |
2665 | ((INT_DEST_MODE == 0) ? | |
2666 | HT_IRQ_LOW_DM_PHYSICAL : | |
2667 | HT_IRQ_LOW_DM_LOGICAL) | | |
2668 | HT_IRQ_LOW_RQEOI_EDGE | | |
2669 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
2670 | HT_IRQ_LOW_MT_FIXED : | |
2671 | HT_IRQ_LOW_MT_ARBITRATED) | | |
2672 | HT_IRQ_LOW_IRQ_MASKED; | |
2673 | ||
ec68307c | 2674 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 2675 | |
a460e745 IM |
2676 | set_irq_chip_and_handler_name(irq, &ht_irq_chip, |
2677 | handle_edge_irq, "edge"); | |
8b955b0d EB |
2678 | } |
2679 | return vector; | |
2680 | } | |
2681 | #endif /* CONFIG_HT_IRQ */ | |
2682 | ||
1da177e4 LT |
2683 | /* -------------------------------------------------------------------------- |
2684 | ACPI-based IOAPIC Configuration | |
2685 | -------------------------------------------------------------------------- */ | |
2686 | ||
888ba6c6 | 2687 | #ifdef CONFIG_ACPI |
1da177e4 LT |
2688 | |
2689 | int __init io_apic_get_unique_id (int ioapic, int apic_id) | |
2690 | { | |
2691 | union IO_APIC_reg_00 reg_00; | |
2692 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
2693 | physid_mask_t tmp; | |
2694 | unsigned long flags; | |
2695 | int i = 0; | |
2696 | ||
2697 | /* | |
2698 | * The P4 platform supports up to 256 APIC IDs on two separate APIC | |
2699 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
2700 | * supports up to 16 on one shared APIC bus. | |
2701 | * | |
2702 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full | |
2703 | * advantage of new APIC bus architecture. | |
2704 | */ | |
2705 | ||
2706 | if (physids_empty(apic_id_map)) | |
2707 | apic_id_map = ioapic_phys_id_map(phys_cpu_present_map); | |
2708 | ||
2709 | spin_lock_irqsave(&ioapic_lock, flags); | |
2710 | reg_00.raw = io_apic_read(ioapic, 0); | |
2711 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2712 | ||
2713 | if (apic_id >= get_physical_broadcast()) { | |
2714 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
2715 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
2716 | apic_id = reg_00.bits.ID; | |
2717 | } | |
2718 | ||
2719 | /* | |
2720 | * Every APIC in a system must have a unique ID or we get lots of nice | |
2721 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
2722 | */ | |
2723 | if (check_apicid_used(apic_id_map, apic_id)) { | |
2724 | ||
2725 | for (i = 0; i < get_physical_broadcast(); i++) { | |
2726 | if (!check_apicid_used(apic_id_map, i)) | |
2727 | break; | |
2728 | } | |
2729 | ||
2730 | if (i == get_physical_broadcast()) | |
2731 | panic("Max apic_id exceeded!\n"); | |
2732 | ||
2733 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
2734 | "trying %d\n", ioapic, apic_id, i); | |
2735 | ||
2736 | apic_id = i; | |
2737 | } | |
2738 | ||
2739 | tmp = apicid_to_cpu_present(apic_id); | |
2740 | physids_or(apic_id_map, apic_id_map, tmp); | |
2741 | ||
2742 | if (reg_00.bits.ID != apic_id) { | |
2743 | reg_00.bits.ID = apic_id; | |
2744 | ||
2745 | spin_lock_irqsave(&ioapic_lock, flags); | |
2746 | io_apic_write(ioapic, 0, reg_00.raw); | |
2747 | reg_00.raw = io_apic_read(ioapic, 0); | |
2748 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2749 | ||
2750 | /* Sanity check */ | |
6070f9ec AD |
2751 | if (reg_00.bits.ID != apic_id) { |
2752 | printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); | |
2753 | return -1; | |
2754 | } | |
1da177e4 LT |
2755 | } |
2756 | ||
2757 | apic_printk(APIC_VERBOSE, KERN_INFO | |
2758 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
2759 | ||
2760 | return apic_id; | |
2761 | } | |
2762 | ||
2763 | ||
2764 | int __init io_apic_get_version (int ioapic) | |
2765 | { | |
2766 | union IO_APIC_reg_01 reg_01; | |
2767 | unsigned long flags; | |
2768 | ||
2769 | spin_lock_irqsave(&ioapic_lock, flags); | |
2770 | reg_01.raw = io_apic_read(ioapic, 1); | |
2771 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2772 | ||
2773 | return reg_01.bits.version; | |
2774 | } | |
2775 | ||
2776 | ||
2777 | int __init io_apic_get_redir_entries (int ioapic) | |
2778 | { | |
2779 | union IO_APIC_reg_01 reg_01; | |
2780 | unsigned long flags; | |
2781 | ||
2782 | spin_lock_irqsave(&ioapic_lock, flags); | |
2783 | reg_01.raw = io_apic_read(ioapic, 1); | |
2784 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2785 | ||
2786 | return reg_01.bits.entries; | |
2787 | } | |
2788 | ||
2789 | ||
2790 | int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low) | |
2791 | { | |
2792 | struct IO_APIC_route_entry entry; | |
2793 | unsigned long flags; | |
2794 | ||
2795 | if (!IO_APIC_IRQ(irq)) { | |
2796 | printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", | |
2797 | ioapic); | |
2798 | return -EINVAL; | |
2799 | } | |
2800 | ||
2801 | /* | |
2802 | * Generate a PCI IRQ routing entry and program the IOAPIC accordingly. | |
2803 | * Note that we mask (disable) IRQs now -- these get enabled when the | |
2804 | * corresponding device driver registers for this IRQ. | |
2805 | */ | |
2806 | ||
2807 | memset(&entry,0,sizeof(entry)); | |
2808 | ||
2809 | entry.delivery_mode = INT_DELIVERY_MODE; | |
2810 | entry.dest_mode = INT_DEST_MODE; | |
2811 | entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS); | |
2812 | entry.trigger = edge_level; | |
2813 | entry.polarity = active_high_low; | |
2814 | entry.mask = 1; | |
2815 | ||
2816 | /* | |
2817 | * IRQs < 16 are already in the irq_2_pin[] map | |
2818 | */ | |
2819 | if (irq >= 16) | |
2820 | add_pin_to_irq(irq, ioapic, pin); | |
2821 | ||
2822 | entry.vector = assign_irq_vector(irq); | |
2823 | ||
2824 | apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry " | |
2825 | "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic, | |
2826 | mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq, | |
2827 | edge_level, active_high_low); | |
2828 | ||
2829 | ioapic_register_intr(irq, entry.vector, edge_level); | |
2830 | ||
2831 | if (!ioapic && (irq < 16)) | |
2832 | disable_8259A_irq(irq); | |
2833 | ||
2834 | spin_lock_irqsave(&ioapic_lock, flags); | |
d15512f4 | 2835 | __ioapic_write_entry(ioapic, pin, entry); |
1da177e4 LT |
2836 | spin_unlock_irqrestore(&ioapic_lock, flags); |
2837 | ||
2838 | return 0; | |
2839 | } | |
2840 | ||
61fd47e0 SL |
2841 | int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity) |
2842 | { | |
2843 | int i; | |
2844 | ||
2845 | if (skip_ioapic_setup) | |
2846 | return -1; | |
2847 | ||
2848 | for (i = 0; i < mp_irq_entries; i++) | |
2849 | if (mp_irqs[i].mpc_irqtype == mp_INT && | |
2850 | mp_irqs[i].mpc_srcbusirq == bus_irq) | |
2851 | break; | |
2852 | if (i >= mp_irq_entries) | |
2853 | return -1; | |
2854 | ||
2855 | *trigger = irq_trigger(i); | |
2856 | *polarity = irq_polarity(i); | |
2857 | return 0; | |
2858 | } | |
2859 | ||
888ba6c6 | 2860 | #endif /* CONFIG_ACPI */ |
1a3f239d RR |
2861 | |
2862 | static int __init parse_disable_timer_pin_1(char *arg) | |
2863 | { | |
2864 | disable_timer_pin_1 = 1; | |
2865 | return 0; | |
2866 | } | |
2867 | early_param("disable_timer_pin_1", parse_disable_timer_pin_1); | |
2868 | ||
2869 | static int __init parse_enable_timer_pin_1(char *arg) | |
2870 | { | |
2871 | disable_timer_pin_1 = -1; | |
2872 | return 0; | |
2873 | } | |
2874 | early_param("enable_timer_pin_1", parse_enable_timer_pin_1); | |
2875 | ||
2876 | static int __init parse_noapic(char *arg) | |
2877 | { | |
2878 | /* disable IO-APIC */ | |
2879 | disable_ioapic_setup(); | |
2880 | return 0; | |
2881 | } | |
2882 | early_param("noapic", parse_noapic); |