Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
4 | * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo | |
5 | * | |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
589e367f | 28 | #include <linux/pci.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/acpi.h> | |
31 | #include <linux/sysdev.h> | |
3b7d1921 | 32 | #include <linux/msi.h> |
95d77884 | 33 | #include <linux/htirq.h> |
3460a6d9 | 34 | #include <linux/dmar.h> |
1d16b53e | 35 | #include <linux/jiffies.h> |
ab688059 AK |
36 | #ifdef CONFIG_ACPI |
37 | #include <acpi/acpi_bus.h> | |
38 | #endif | |
3e35a0e5 | 39 | #include <linux/bootmem.h> |
1da177e4 | 40 | |
61014292 | 41 | #include <asm/idle.h> |
1da177e4 LT |
42 | #include <asm/io.h> |
43 | #include <asm/smp.h> | |
44 | #include <asm/desc.h> | |
45 | #include <asm/proto.h> | |
8d916406 | 46 | #include <asm/acpi.h> |
ca8642f6 | 47 | #include <asm/dma.h> |
3e4ff115 | 48 | #include <asm/nmi.h> |
589e367f | 49 | #include <asm/msidef.h> |
8b955b0d | 50 | #include <asm/hypertransport.h> |
1da177e4 | 51 | |
5af5573e | 52 | #include <mach_ipi.h> |
dd46e3ca | 53 | #include <mach_apic.h> |
5af5573e | 54 | |
13a79503 EB |
55 | struct irq_cfg { |
56 | cpumask_t domain; | |
61014292 EB |
57 | cpumask_t old_domain; |
58 | unsigned move_cleanup_count; | |
13a79503 | 59 | u8 vector; |
61014292 | 60 | u8 move_in_progress : 1; |
13a79503 EB |
61 | }; |
62 | ||
63 | /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */ | |
64 | struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = { | |
bc5e81a1 EB |
65 | [0] = { .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, }, |
66 | [1] = { .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, }, | |
67 | [2] = { .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, }, | |
68 | [3] = { .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, }, | |
69 | [4] = { .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, }, | |
70 | [5] = { .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, }, | |
71 | [6] = { .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, }, | |
72 | [7] = { .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, }, | |
73 | [8] = { .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, }, | |
74 | [9] = { .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, }, | |
75 | [10] = { .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, }, | |
76 | [11] = { .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, }, | |
77 | [12] = { .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, }, | |
78 | [13] = { .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, }, | |
79 | [14] = { .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, }, | |
80 | [15] = { .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, }, | |
13a79503 EB |
81 | }; |
82 | ||
dfbffdd8 | 83 | static int assign_irq_vector(int irq, cpumask_t mask); |
04b9267b | 84 | |
1da177e4 LT |
85 | #define __apicdebuginit __init |
86 | ||
87 | int sis_apic_bug; /* not actually supported, dummy for compile */ | |
88 | ||
14d98cad AK |
89 | static int no_timer_check; |
90 | ||
fea5f1e1 LT |
91 | static int disable_timer_pin_1 __initdata; |
92 | ||
93 | int timer_over_8254 __initdata = 1; | |
94 | ||
1008fddc EB |
95 | /* Where if anywhere is the i8259 connect in external int mode */ |
96 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
97 | ||
1da177e4 | 98 | static DEFINE_SPINLOCK(ioapic_lock); |
70a0a535 | 99 | DEFINE_SPINLOCK(vector_lock); |
1da177e4 LT |
100 | |
101 | /* | |
102 | * # of IRQ routing registers | |
103 | */ | |
104 | int nr_ioapic_registers[MAX_IO_APICS]; | |
105 | ||
9c7408f3 AS |
106 | /* I/O APIC entries */ |
107 | struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS]; | |
108 | int nr_ioapics; | |
109 | ||
350bae1d AS |
110 | /* MP IRQ source entries */ |
111 | struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES]; | |
112 | ||
113 | /* # of MP IRQ source entries */ | |
114 | int mp_irq_entries; | |
115 | ||
1da177e4 LT |
116 | /* |
117 | * Rough estimation of how many shared IRQs there are, can | |
118 | * be changed anytime. | |
119 | */ | |
e273d140 | 120 | #define MAX_PLUS_SHARED_IRQS NR_IRQS |
1da177e4 LT |
121 | #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS) |
122 | ||
123 | /* | |
124 | * This is performance-critical, we want to do it O(1) | |
125 | * | |
126 | * the indexing order of this array favors 1:1 mappings | |
127 | * between pins and IRQs. | |
128 | */ | |
129 | ||
130 | static struct irq_pin_list { | |
131 | short apic, pin, next; | |
132 | } irq_2_pin[PIN_MAP_SIZE]; | |
133 | ||
6c0ffb9d LT |
134 | struct io_apic { |
135 | unsigned int index; | |
136 | unsigned int unused[3]; | |
137 | unsigned int data; | |
138 | }; | |
139 | ||
140 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
141 | { | |
142 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
143 | + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK); | |
144 | } | |
145 | ||
146 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) | |
147 | { | |
148 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
149 | writel(reg, &io_apic->index); | |
150 | return readl(&io_apic->data); | |
151 | } | |
152 | ||
153 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) | |
154 | { | |
155 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
156 | writel(reg, &io_apic->index); | |
157 | writel(value, &io_apic->data); | |
158 | } | |
159 | ||
160 | /* | |
161 | * Re-write a value: to be used for read-modify-write | |
162 | * cycles where the read already set up the index register. | |
163 | */ | |
164 | static inline void io_apic_modify(unsigned int apic, unsigned int value) | |
165 | { | |
166 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
167 | writel(value, &io_apic->data); | |
168 | } | |
169 | ||
ef3e28c5 EB |
170 | static int io_apic_level_ack_pending(unsigned int irq) |
171 | { | |
172 | struct irq_pin_list *entry; | |
173 | unsigned long flags; | |
174 | int pending = 0; | |
175 | ||
176 | spin_lock_irqsave(&ioapic_lock, flags); | |
177 | entry = irq_2_pin + irq; | |
178 | for (;;) { | |
179 | unsigned int reg; | |
180 | int pin; | |
181 | ||
182 | pin = entry->pin; | |
183 | if (pin == -1) | |
184 | break; | |
185 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
186 | /* Is the remote IRR bit set? */ | |
187 | pending |= (reg >> 14) & 1; | |
188 | if (!entry->next) | |
189 | break; | |
190 | entry = irq_2_pin + entry->next; | |
191 | } | |
192 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
193 | return pending; | |
194 | } | |
195 | ||
6c0ffb9d LT |
196 | /* |
197 | * Synchronize the IO-APIC and the CPU by doing | |
198 | * a dummy read from the IO-APIC | |
199 | */ | |
200 | static inline void io_apic_sync(unsigned int apic) | |
201 | { | |
202 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
203 | readl(&io_apic->data); | |
204 | } | |
205 | ||
54d5d424 AR |
206 | #define __DO_ACTION(R, ACTION, FINAL) \ |
207 | \ | |
208 | { \ | |
209 | int pin; \ | |
210 | struct irq_pin_list *entry = irq_2_pin + irq; \ | |
211 | \ | |
6004e1b7 | 212 | BUG_ON(irq >= NR_IRQS); \ |
54d5d424 AR |
213 | for (;;) { \ |
214 | unsigned int reg; \ | |
215 | pin = entry->pin; \ | |
216 | if (pin == -1) \ | |
217 | break; \ | |
218 | reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \ | |
219 | reg ACTION; \ | |
220 | io_apic_modify(entry->apic, reg); \ | |
f45bcd70 | 221 | FINAL; \ |
54d5d424 AR |
222 | if (!entry->next) \ |
223 | break; \ | |
224 | entry = irq_2_pin + entry->next; \ | |
225 | } \ | |
54d5d424 AR |
226 | } |
227 | ||
eea0e11c AK |
228 | union entry_union { |
229 | struct { u32 w1, w2; }; | |
230 | struct IO_APIC_route_entry entry; | |
231 | }; | |
232 | ||
233 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) | |
234 | { | |
235 | union entry_union eu; | |
236 | unsigned long flags; | |
237 | spin_lock_irqsave(&ioapic_lock, flags); | |
238 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); | |
239 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
240 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
241 | return eu.entry; | |
242 | } | |
243 | ||
48797ebd LT |
244 | /* |
245 | * When we write a new IO APIC routing entry, we need to write the high | |
246 | * word first! If the mask bit in the low word is clear, we will enable | |
247 | * the interrupt, and we need to make sure the entry is fully populated | |
248 | * before that happens. | |
249 | */ | |
516d2836 AK |
250 | static void |
251 | __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
eea0e11c | 252 | { |
eea0e11c AK |
253 | union entry_union eu; |
254 | eu.entry = e; | |
48797ebd LT |
255 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
256 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
516d2836 AK |
257 | } |
258 | ||
259 | static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
260 | { | |
261 | unsigned long flags; | |
262 | spin_lock_irqsave(&ioapic_lock, flags); | |
263 | __ioapic_write_entry(apic, pin, e); | |
48797ebd LT |
264 | spin_unlock_irqrestore(&ioapic_lock, flags); |
265 | } | |
266 | ||
267 | /* | |
268 | * When we mask an IO APIC routing entry, we need to write the low | |
269 | * word first, in order to set the mask bit before we change the | |
270 | * high bits! | |
271 | */ | |
272 | static void ioapic_mask_entry(int apic, int pin) | |
273 | { | |
274 | unsigned long flags; | |
275 | union entry_union eu = { .entry.mask = 1 }; | |
276 | ||
eea0e11c AK |
277 | spin_lock_irqsave(&ioapic_lock, flags); |
278 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
279 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
280 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
281 | } | |
282 | ||
54d5d424 | 283 | #ifdef CONFIG_SMP |
550f2299 EB |
284 | static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector) |
285 | { | |
286 | int apic, pin; | |
287 | struct irq_pin_list *entry = irq_2_pin + irq; | |
288 | ||
289 | BUG_ON(irq >= NR_IRQS); | |
290 | for (;;) { | |
291 | unsigned int reg; | |
292 | apic = entry->apic; | |
293 | pin = entry->pin; | |
294 | if (pin == -1) | |
295 | break; | |
296 | io_apic_write(apic, 0x11 + pin*2, dest); | |
297 | reg = io_apic_read(apic, 0x10 + pin*2); | |
298 | reg &= ~0x000000ff; | |
299 | reg |= vector; | |
300 | io_apic_modify(apic, reg); | |
301 | if (!entry->next) | |
302 | break; | |
303 | entry = irq_2_pin + entry->next; | |
304 | } | |
305 | } | |
306 | ||
54d5d424 AR |
307 | static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask) |
308 | { | |
dfbffdd8 | 309 | struct irq_cfg *cfg = irq_cfg + irq; |
54d5d424 AR |
310 | unsigned long flags; |
311 | unsigned int dest; | |
312 | cpumask_t tmp; | |
313 | ||
314 | cpus_and(tmp, mask, cpu_online_map); | |
315 | if (cpus_empty(tmp)) | |
5ff5115e | 316 | return; |
54d5d424 | 317 | |
dfbffdd8 | 318 | if (assign_irq_vector(irq, mask)) |
550f2299 EB |
319 | return; |
320 | ||
dfbffdd8 | 321 | cpus_and(tmp, cfg->domain, mask); |
550f2299 | 322 | dest = cpu_mask_to_apicid(tmp); |
54d5d424 AR |
323 | |
324 | /* | |
325 | * Only the high 8 bits are valid. | |
326 | */ | |
327 | dest = SET_APIC_LOGICAL_ID(dest); | |
328 | ||
329 | spin_lock_irqsave(&ioapic_lock, flags); | |
dfbffdd8 | 330 | __target_IO_APIC_irq(irq, dest, cfg->vector); |
9f0a5ba5 | 331 | irq_desc[irq].affinity = mask; |
54d5d424 AR |
332 | spin_unlock_irqrestore(&ioapic_lock, flags); |
333 | } | |
334 | #endif | |
335 | ||
1da177e4 LT |
336 | /* |
337 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
338 | * shared ISA-space IRQs, so we have to support them. We are super | |
339 | * fast in the common case, and fast for shared ISA-space IRQs. | |
340 | */ | |
341 | static void add_pin_to_irq(unsigned int irq, int apic, int pin) | |
342 | { | |
343 | static int first_free_entry = NR_IRQS; | |
344 | struct irq_pin_list *entry = irq_2_pin + irq; | |
345 | ||
6004e1b7 | 346 | BUG_ON(irq >= NR_IRQS); |
1da177e4 LT |
347 | while (entry->next) |
348 | entry = irq_2_pin + entry->next; | |
349 | ||
350 | if (entry->pin != -1) { | |
351 | entry->next = first_free_entry; | |
352 | entry = irq_2_pin + entry->next; | |
353 | if (++first_free_entry >= PIN_MAP_SIZE) | |
6004e1b7 | 354 | panic("io_apic.c: ran out of irq_2_pin entries!"); |
1da177e4 LT |
355 | } |
356 | entry->apic = apic; | |
357 | entry->pin = pin; | |
358 | } | |
359 | ||
1da177e4 LT |
360 | |
361 | #define DO_ACTION(name,R,ACTION, FINAL) \ | |
362 | \ | |
363 | static void name##_IO_APIC_irq (unsigned int irq) \ | |
364 | __DO_ACTION(R, ACTION, FINAL) | |
365 | ||
366 | DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) ) | |
367 | /* mask = 1 */ | |
368 | DO_ACTION( __unmask, 0, &= 0xfffeffff, ) | |
369 | /* mask = 0 */ | |
370 | ||
371 | static void mask_IO_APIC_irq (unsigned int irq) | |
372 | { | |
373 | unsigned long flags; | |
374 | ||
375 | spin_lock_irqsave(&ioapic_lock, flags); | |
376 | __mask_IO_APIC_irq(irq); | |
377 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
378 | } | |
379 | ||
380 | static void unmask_IO_APIC_irq (unsigned int irq) | |
381 | { | |
382 | unsigned long flags; | |
383 | ||
384 | spin_lock_irqsave(&ioapic_lock, flags); | |
385 | __unmask_IO_APIC_irq(irq); | |
386 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
387 | } | |
388 | ||
389 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) | |
390 | { | |
391 | struct IO_APIC_route_entry entry; | |
1da177e4 LT |
392 | |
393 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ | |
eea0e11c | 394 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
395 | if (entry.delivery_mode == dest_SMI) |
396 | return; | |
397 | /* | |
398 | * Disable it in the IO-APIC irq-routing table: | |
399 | */ | |
48797ebd | 400 | ioapic_mask_entry(apic, pin); |
1da177e4 LT |
401 | } |
402 | ||
403 | static void clear_IO_APIC (void) | |
404 | { | |
405 | int apic, pin; | |
406 | ||
407 | for (apic = 0; apic < nr_ioapics; apic++) | |
408 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) | |
409 | clear_IO_APIC_pin(apic, pin); | |
410 | } | |
411 | ||
1da177e4 LT |
412 | int skip_ioapic_setup; |
413 | int ioapic_force; | |
414 | ||
61ec7567 | 415 | static int __init parse_noapic(char *str) |
1da177e4 | 416 | { |
61ec7567 | 417 | disable_ioapic_setup(); |
2c8c0e6b | 418 | return 0; |
1da177e4 | 419 | } |
61ec7567 | 420 | early_param("noapic", parse_noapic); |
1da177e4 | 421 | |
fea5f1e1 LT |
422 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
423 | static int __init disable_timer_pin_setup(char *arg) | |
424 | { | |
425 | disable_timer_pin_1 = 1; | |
426 | return 1; | |
427 | } | |
428 | __setup("disable_timer_pin_1", disable_timer_pin_setup); | |
429 | ||
430 | static int __init setup_disable_8254_timer(char *s) | |
431 | { | |
432 | timer_over_8254 = -1; | |
433 | return 1; | |
434 | } | |
435 | static int __init setup_enable_8254_timer(char *s) | |
436 | { | |
437 | timer_over_8254 = 2; | |
438 | return 1; | |
439 | } | |
440 | ||
441 | __setup("disable_8254_timer", setup_disable_8254_timer); | |
442 | __setup("enable_8254_timer", setup_enable_8254_timer); | |
443 | ||
444 | ||
1da177e4 LT |
445 | /* |
446 | * Find the IRQ entry number of a certain pin. | |
447 | */ | |
448 | static int find_irq_entry(int apic, int pin, int type) | |
449 | { | |
450 | int i; | |
451 | ||
452 | for (i = 0; i < mp_irq_entries; i++) | |
453 | if (mp_irqs[i].mpc_irqtype == type && | |
454 | (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid || | |
455 | mp_irqs[i].mpc_dstapic == MP_APIC_ALL) && | |
456 | mp_irqs[i].mpc_dstirq == pin) | |
457 | return i; | |
458 | ||
459 | return -1; | |
460 | } | |
461 | ||
462 | /* | |
463 | * Find the pin to which IRQ[irq] (ISA) is connected | |
464 | */ | |
1008fddc | 465 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
466 | { |
467 | int i; | |
468 | ||
469 | for (i = 0; i < mp_irq_entries; i++) { | |
470 | int lbus = mp_irqs[i].mpc_srcbus; | |
471 | ||
55f05ffa | 472 | if (test_bit(lbus, mp_bus_not_pci) && |
1da177e4 LT |
473 | (mp_irqs[i].mpc_irqtype == type) && |
474 | (mp_irqs[i].mpc_srcbusirq == irq)) | |
475 | ||
476 | return mp_irqs[i].mpc_dstirq; | |
477 | } | |
478 | return -1; | |
479 | } | |
480 | ||
1008fddc EB |
481 | static int __init find_isa_irq_apic(int irq, int type) |
482 | { | |
483 | int i; | |
484 | ||
485 | for (i = 0; i < mp_irq_entries; i++) { | |
486 | int lbus = mp_irqs[i].mpc_srcbus; | |
487 | ||
55f05ffa | 488 | if (test_bit(lbus, mp_bus_not_pci) && |
1008fddc EB |
489 | (mp_irqs[i].mpc_irqtype == type) && |
490 | (mp_irqs[i].mpc_srcbusirq == irq)) | |
491 | break; | |
492 | } | |
493 | if (i < mp_irq_entries) { | |
494 | int apic; | |
495 | for(apic = 0; apic < nr_ioapics; apic++) { | |
496 | if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic) | |
497 | return apic; | |
498 | } | |
499 | } | |
500 | ||
501 | return -1; | |
502 | } | |
503 | ||
1da177e4 LT |
504 | /* |
505 | * Find a specific PCI IRQ entry. | |
506 | * Not an __init, possibly needed by modules | |
507 | */ | |
508 | static int pin_2_irq(int idx, int apic, int pin); | |
509 | ||
510 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin) | |
511 | { | |
512 | int apic, i, best_guess = -1; | |
513 | ||
514 | apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", | |
515 | bus, slot, pin); | |
516 | if (mp_bus_id_to_pci_bus[bus] == -1) { | |
517 | apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus); | |
518 | return -1; | |
519 | } | |
520 | for (i = 0; i < mp_irq_entries; i++) { | |
521 | int lbus = mp_irqs[i].mpc_srcbus; | |
522 | ||
523 | for (apic = 0; apic < nr_ioapics; apic++) | |
524 | if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic || | |
525 | mp_irqs[i].mpc_dstapic == MP_APIC_ALL) | |
526 | break; | |
527 | ||
55f05ffa | 528 | if (!test_bit(lbus, mp_bus_not_pci) && |
1da177e4 LT |
529 | !mp_irqs[i].mpc_irqtype && |
530 | (bus == lbus) && | |
531 | (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) { | |
532 | int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq); | |
533 | ||
534 | if (!(apic || IO_APIC_IRQ(irq))) | |
535 | continue; | |
536 | ||
537 | if (pin == (mp_irqs[i].mpc_srcbusirq & 3)) | |
538 | return irq; | |
539 | /* | |
540 | * Use the first all-but-pin matching entry as a | |
541 | * best-guess fuzzy result for broken mptables. | |
542 | */ | |
543 | if (best_guess < 0) | |
544 | best_guess = irq; | |
545 | } | |
546 | } | |
6004e1b7 | 547 | BUG_ON(best_guess >= NR_IRQS); |
1da177e4 LT |
548 | return best_guess; |
549 | } | |
550 | ||
1da177e4 LT |
551 | /* ISA interrupts are always polarity zero edge triggered, |
552 | * when listed as conforming in the MP table. */ | |
553 | ||
554 | #define default_ISA_trigger(idx) (0) | |
555 | #define default_ISA_polarity(idx) (0) | |
556 | ||
557 | /* PCI interrupts are always polarity one level triggered, | |
558 | * when listed as conforming in the MP table. */ | |
559 | ||
560 | #define default_PCI_trigger(idx) (1) | |
561 | #define default_PCI_polarity(idx) (1) | |
562 | ||
61fd47e0 | 563 | static int MPBIOS_polarity(int idx) |
1da177e4 LT |
564 | { |
565 | int bus = mp_irqs[idx].mpc_srcbus; | |
566 | int polarity; | |
567 | ||
568 | /* | |
569 | * Determine IRQ line polarity (high active or low active): | |
570 | */ | |
571 | switch (mp_irqs[idx].mpc_irqflag & 3) | |
572 | { | |
573 | case 0: /* conforms, ie. bus-type dependent polarity */ | |
55f05ffa AK |
574 | if (test_bit(bus, mp_bus_not_pci)) |
575 | polarity = default_ISA_polarity(idx); | |
576 | else | |
577 | polarity = default_PCI_polarity(idx); | |
1da177e4 | 578 | break; |
1da177e4 LT |
579 | case 1: /* high active */ |
580 | { | |
581 | polarity = 0; | |
582 | break; | |
583 | } | |
584 | case 2: /* reserved */ | |
585 | { | |
586 | printk(KERN_WARNING "broken BIOS!!\n"); | |
587 | polarity = 1; | |
588 | break; | |
589 | } | |
590 | case 3: /* low active */ | |
591 | { | |
592 | polarity = 1; | |
593 | break; | |
594 | } | |
595 | default: /* invalid */ | |
596 | { | |
597 | printk(KERN_WARNING "broken BIOS!!\n"); | |
598 | polarity = 1; | |
599 | break; | |
600 | } | |
601 | } | |
602 | return polarity; | |
603 | } | |
604 | ||
605 | static int MPBIOS_trigger(int idx) | |
606 | { | |
607 | int bus = mp_irqs[idx].mpc_srcbus; | |
608 | int trigger; | |
609 | ||
610 | /* | |
611 | * Determine IRQ trigger mode (edge or level sensitive): | |
612 | */ | |
613 | switch ((mp_irqs[idx].mpc_irqflag>>2) & 3) | |
614 | { | |
615 | case 0: /* conforms, ie. bus-type dependent */ | |
55f05ffa AK |
616 | if (test_bit(bus, mp_bus_not_pci)) |
617 | trigger = default_ISA_trigger(idx); | |
618 | else | |
619 | trigger = default_PCI_trigger(idx); | |
1da177e4 | 620 | break; |
1da177e4 LT |
621 | case 1: /* edge */ |
622 | { | |
623 | trigger = 0; | |
624 | break; | |
625 | } | |
626 | case 2: /* reserved */ | |
627 | { | |
628 | printk(KERN_WARNING "broken BIOS!!\n"); | |
629 | trigger = 1; | |
630 | break; | |
631 | } | |
632 | case 3: /* level */ | |
633 | { | |
634 | trigger = 1; | |
635 | break; | |
636 | } | |
637 | default: /* invalid */ | |
638 | { | |
639 | printk(KERN_WARNING "broken BIOS!!\n"); | |
640 | trigger = 0; | |
641 | break; | |
642 | } | |
643 | } | |
644 | return trigger; | |
645 | } | |
646 | ||
647 | static inline int irq_polarity(int idx) | |
648 | { | |
649 | return MPBIOS_polarity(idx); | |
650 | } | |
651 | ||
652 | static inline int irq_trigger(int idx) | |
653 | { | |
654 | return MPBIOS_trigger(idx); | |
655 | } | |
656 | ||
657 | static int pin_2_irq(int idx, int apic, int pin) | |
658 | { | |
659 | int irq, i; | |
660 | int bus = mp_irqs[idx].mpc_srcbus; | |
661 | ||
662 | /* | |
663 | * Debugging check, we are in big trouble if this message pops up! | |
664 | */ | |
665 | if (mp_irqs[idx].mpc_dstirq != pin) | |
666 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); | |
667 | ||
55f05ffa AK |
668 | if (test_bit(bus, mp_bus_not_pci)) { |
669 | irq = mp_irqs[idx].mpc_srcbusirq; | |
670 | } else { | |
671 | /* | |
672 | * PCI IRQs are mapped in order | |
673 | */ | |
674 | i = irq = 0; | |
675 | while (i < apic) | |
676 | irq += nr_ioapic_registers[i++]; | |
677 | irq += pin; | |
1da177e4 | 678 | } |
6004e1b7 | 679 | BUG_ON(irq >= NR_IRQS); |
1da177e4 LT |
680 | return irq; |
681 | } | |
682 | ||
dfbffdd8 | 683 | static int __assign_irq_vector(int irq, cpumask_t mask) |
1da177e4 | 684 | { |
550f2299 EB |
685 | /* |
686 | * NOTE! The local APIC isn't very good at handling | |
687 | * multiple interrupts at the same interrupt level. | |
688 | * As the interrupt level is determined by taking the | |
689 | * vector number and shifting that right by 4, we | |
690 | * want to spread these out a bit so that they don't | |
691 | * all fall in the same interrupt level. | |
692 | * | |
693 | * Also, we've got to be careful not to trash gate | |
694 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
695 | */ | |
d1752aa8 | 696 | static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0; |
dfbffdd8 | 697 | unsigned int old_vector; |
550f2299 | 698 | int cpu; |
13a79503 | 699 | struct irq_cfg *cfg; |
1da177e4 | 700 | |
e273d140 | 701 | BUG_ON((unsigned)irq >= NR_IRQS); |
13a79503 | 702 | cfg = &irq_cfg[irq]; |
0a1ad60d | 703 | |
70a0a535 EB |
704 | /* Only try and allocate irqs on cpus that are present */ |
705 | cpus_and(mask, mask, cpu_online_map); | |
706 | ||
61014292 EB |
707 | if ((cfg->move_in_progress) || cfg->move_cleanup_count) |
708 | return -EBUSY; | |
709 | ||
dfbffdd8 EB |
710 | old_vector = cfg->vector; |
711 | if (old_vector) { | |
712 | cpumask_t tmp; | |
713 | cpus_and(tmp, cfg->domain, mask); | |
714 | if (!cpus_empty(tmp)) | |
715 | return 0; | |
0a1ad60d | 716 | } |
550f2299 EB |
717 | |
718 | for_each_cpu_mask(cpu, mask) { | |
70a0a535 | 719 | cpumask_t domain, new_mask; |
61014292 | 720 | int new_cpu; |
550f2299 | 721 | int vector, offset; |
c7111c13 EB |
722 | |
723 | domain = vector_allocation_domain(cpu); | |
70a0a535 | 724 | cpus_and(new_mask, domain, cpu_online_map); |
c7111c13 | 725 | |
d1752aa8 EB |
726 | vector = current_vector; |
727 | offset = current_offset; | |
1da177e4 | 728 | next: |
550f2299 EB |
729 | vector += 8; |
730 | if (vector >= FIRST_SYSTEM_VECTOR) { | |
731 | /* If we run out of vectors on large boxen, must share them. */ | |
732 | offset = (offset + 1) % 8; | |
733 | vector = FIRST_DEVICE_VECTOR + offset; | |
734 | } | |
d1752aa8 | 735 | if (unlikely(current_vector == vector)) |
550f2299 EB |
736 | continue; |
737 | if (vector == IA32_SYSCALL_VECTOR) | |
738 | goto next; | |
70a0a535 | 739 | for_each_cpu_mask(new_cpu, new_mask) |
45edfd1d | 740 | if (per_cpu(vector_irq, new_cpu)[vector] != -1) |
c7111c13 | 741 | goto next; |
550f2299 | 742 | /* Found one! */ |
d1752aa8 EB |
743 | current_vector = vector; |
744 | current_offset = offset; | |
61014292 EB |
745 | if (old_vector) { |
746 | cfg->move_in_progress = 1; | |
747 | cfg->old_domain = cfg->domain; | |
748 | } | |
70a0a535 | 749 | for_each_cpu_mask(new_cpu, new_mask) |
c7111c13 | 750 | per_cpu(vector_irq, new_cpu)[vector] = irq; |
13a79503 EB |
751 | cfg->vector = vector; |
752 | cfg->domain = domain; | |
dfbffdd8 | 753 | return 0; |
1da177e4 | 754 | } |
550f2299 | 755 | return -ENOSPC; |
04b9267b EB |
756 | } |
757 | ||
dfbffdd8 | 758 | static int assign_irq_vector(int irq, cpumask_t mask) |
04b9267b | 759 | { |
dfbffdd8 | 760 | int err; |
04b9267b | 761 | unsigned long flags; |
0a1ad60d | 762 | |
04b9267b | 763 | spin_lock_irqsave(&vector_lock, flags); |
dfbffdd8 | 764 | err = __assign_irq_vector(irq, mask); |
26a3c49c | 765 | spin_unlock_irqrestore(&vector_lock, flags); |
dfbffdd8 | 766 | return err; |
1da177e4 LT |
767 | } |
768 | ||
5df0287e YL |
769 | static void __clear_irq_vector(int irq) |
770 | { | |
13a79503 | 771 | struct irq_cfg *cfg; |
5df0287e YL |
772 | cpumask_t mask; |
773 | int cpu, vector; | |
774 | ||
13a79503 EB |
775 | BUG_ON((unsigned)irq >= NR_IRQS); |
776 | cfg = &irq_cfg[irq]; | |
777 | BUG_ON(!cfg->vector); | |
5df0287e | 778 | |
13a79503 EB |
779 | vector = cfg->vector; |
780 | cpus_and(mask, cfg->domain, cpu_online_map); | |
5df0287e YL |
781 | for_each_cpu_mask(cpu, mask) |
782 | per_cpu(vector_irq, cpu)[vector] = -1; | |
783 | ||
13a79503 EB |
784 | cfg->vector = 0; |
785 | cfg->domain = CPU_MASK_NONE; | |
5df0287e YL |
786 | } |
787 | ||
70a0a535 EB |
788 | void __setup_vector_irq(int cpu) |
789 | { | |
790 | /* Initialize vector_irq on a new cpu */ | |
791 | /* This function must be called with vector_lock held */ | |
70a0a535 EB |
792 | int irq, vector; |
793 | ||
70a0a535 | 794 | /* Mark the inuse vectors */ |
e273d140 | 795 | for (irq = 0; irq < NR_IRQS; ++irq) { |
13a79503 | 796 | if (!cpu_isset(cpu, irq_cfg[irq].domain)) |
70a0a535 | 797 | continue; |
13a79503 | 798 | vector = irq_cfg[irq].vector; |
70a0a535 EB |
799 | per_cpu(vector_irq, cpu)[vector] = irq; |
800 | } | |
801 | /* Mark the free vectors */ | |
802 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
803 | irq = per_cpu(vector_irq, cpu)[vector]; | |
804 | if (irq < 0) | |
805 | continue; | |
13a79503 | 806 | if (!cpu_isset(cpu, irq_cfg[irq].domain)) |
70a0a535 EB |
807 | per_cpu(vector_irq, cpu)[vector] = -1; |
808 | } | |
809 | } | |
810 | ||
811 | ||
f29bd1ba | 812 | static struct irq_chip ioapic_chip; |
1da177e4 | 813 | |
a27bc06d | 814 | static void ioapic_register_intr(int irq, unsigned long trigger) |
1da177e4 | 815 | { |
cc75b92d TG |
816 | if (trigger) { |
817 | irq_desc[irq].status |= IRQ_LEVEL; | |
a460e745 IM |
818 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
819 | handle_fasteoi_irq, "fasteoi"); | |
cc75b92d TG |
820 | } else { |
821 | irq_desc[irq].status &= ~IRQ_LEVEL; | |
a460e745 IM |
822 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
823 | handle_edge_irq, "edge"); | |
cc75b92d | 824 | } |
1da177e4 | 825 | } |
a8c8a367 EB |
826 | |
827 | static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq, | |
828 | int trigger, int polarity) | |
1da177e4 | 829 | { |
dfbffdd8 | 830 | struct irq_cfg *cfg = irq_cfg + irq; |
1da177e4 | 831 | struct IO_APIC_route_entry entry; |
a8c8a367 | 832 | cpumask_t mask; |
1da177e4 | 833 | |
a8c8a367 EB |
834 | if (!IO_APIC_IRQ(irq)) |
835 | return; | |
836 | ||
dfbffdd8 EB |
837 | mask = TARGET_CPUS; |
838 | if (assign_irq_vector(irq, mask)) | |
a8c8a367 EB |
839 | return; |
840 | ||
dfbffdd8 EB |
841 | cpus_and(mask, cfg->domain, mask); |
842 | ||
a8c8a367 EB |
843 | apic_printk(APIC_VERBOSE,KERN_DEBUG |
844 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " | |
845 | "IRQ %d Mode:%i Active:%i)\n", | |
dfbffdd8 | 846 | apic, mp_ioapics[apic].mpc_apicid, pin, cfg->vector, |
a8c8a367 | 847 | irq, trigger, polarity); |
1da177e4 | 848 | |
ad892f5e YL |
849 | /* |
850 | * add it to the IO-APIC irq-routing table: | |
851 | */ | |
852 | memset(&entry,0,sizeof(entry)); | |
1da177e4 | 853 | |
ad892f5e YL |
854 | entry.delivery_mode = INT_DELIVERY_MODE; |
855 | entry.dest_mode = INT_DEST_MODE; | |
a8c8a367 | 856 | entry.dest = cpu_mask_to_apicid(mask); |
ad892f5e | 857 | entry.mask = 0; /* enable IRQ */ |
a8c8a367 EB |
858 | entry.trigger = trigger; |
859 | entry.polarity = polarity; | |
dfbffdd8 | 860 | entry.vector = cfg->vector; |
1da177e4 | 861 | |
a8c8a367 EB |
862 | /* Mask level triggered irqs. |
863 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. | |
864 | */ | |
865 | if (trigger) | |
ad892f5e | 866 | entry.mask = 1; |
ad892f5e | 867 | |
a8c8a367 EB |
868 | ioapic_register_intr(irq, trigger); |
869 | if (irq < 16) | |
870 | disable_8259A_irq(irq); | |
ad892f5e YL |
871 | |
872 | ioapic_write_entry(apic, pin, entry); | |
ad892f5e YL |
873 | } |
874 | ||
875 | static void __init setup_IO_APIC_irqs(void) | |
876 | { | |
877 | int apic, pin, idx, irq, first_notcon = 1; | |
878 | ||
879 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
880 | ||
881 | for (apic = 0; apic < nr_ioapics; apic++) { | |
882 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1da177e4 LT |
883 | |
884 | idx = find_irq_entry(apic,pin,mp_INT); | |
885 | if (idx == -1) { | |
886 | if (first_notcon) { | |
887 | apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin); | |
888 | first_notcon = 0; | |
889 | } else | |
890 | apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin); | |
891 | continue; | |
892 | } | |
20d225b9 YL |
893 | if (!first_notcon) { |
894 | apic_printk(APIC_VERBOSE, " not connected.\n"); | |
895 | first_notcon = 1; | |
896 | } | |
1da177e4 | 897 | |
1da177e4 LT |
898 | irq = pin_2_irq(idx, apic, pin); |
899 | add_pin_to_irq(irq, apic, pin); | |
900 | ||
a8c8a367 EB |
901 | setup_IO_APIC_irq(apic, pin, irq, |
902 | irq_trigger(idx), irq_polarity(idx)); | |
1da177e4 LT |
903 | } |
904 | } | |
905 | ||
906 | if (!first_notcon) | |
20d225b9 | 907 | apic_printk(APIC_VERBOSE, " not connected.\n"); |
1da177e4 LT |
908 | } |
909 | ||
910 | /* | |
911 | * Set up the 8259A-master output pin as broadcast to all | |
912 | * CPUs. | |
913 | */ | |
1008fddc | 914 | static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector) |
1da177e4 LT |
915 | { |
916 | struct IO_APIC_route_entry entry; | |
917 | unsigned long flags; | |
918 | ||
919 | memset(&entry,0,sizeof(entry)); | |
920 | ||
921 | disable_8259A_irq(0); | |
922 | ||
923 | /* mask LVT0 */ | |
11a8e778 | 924 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
1da177e4 LT |
925 | |
926 | /* | |
927 | * We use logical delivery to get the timer IRQ | |
928 | * to the first CPU. | |
929 | */ | |
930 | entry.dest_mode = INT_DEST_MODE; | |
931 | entry.mask = 0; /* unmask IRQ now */ | |
ee4eff6f | 932 | entry.dest = cpu_mask_to_apicid(TARGET_CPUS); |
1da177e4 LT |
933 | entry.delivery_mode = INT_DELIVERY_MODE; |
934 | entry.polarity = 0; | |
935 | entry.trigger = 0; | |
936 | entry.vector = vector; | |
937 | ||
938 | /* | |
939 | * The timer IRQ doesn't have to know that behind the | |
940 | * scene we have a 8259A-master in AEOI mode ... | |
941 | */ | |
a460e745 | 942 | set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge"); |
1da177e4 LT |
943 | |
944 | /* | |
945 | * Add it to the IO-APIC irq-routing table: | |
946 | */ | |
947 | spin_lock_irqsave(&ioapic_lock, flags); | |
1008fddc EB |
948 | io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1)); |
949 | io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0)); | |
1da177e4 LT |
950 | spin_unlock_irqrestore(&ioapic_lock, flags); |
951 | ||
952 | enable_8259A_irq(0); | |
953 | } | |
954 | ||
1da177e4 LT |
955 | void __apicdebuginit print_IO_APIC(void) |
956 | { | |
957 | int apic, i; | |
958 | union IO_APIC_reg_00 reg_00; | |
959 | union IO_APIC_reg_01 reg_01; | |
960 | union IO_APIC_reg_02 reg_02; | |
961 | unsigned long flags; | |
962 | ||
963 | if (apic_verbosity == APIC_QUIET) | |
964 | return; | |
965 | ||
966 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); | |
967 | for (i = 0; i < nr_ioapics; i++) | |
968 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", | |
969 | mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]); | |
970 | ||
971 | /* | |
972 | * We are a bit conservative about what we expect. We have to | |
973 | * know about every hardware change ASAP. | |
974 | */ | |
975 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
976 | ||
977 | for (apic = 0; apic < nr_ioapics; apic++) { | |
978 | ||
979 | spin_lock_irqsave(&ioapic_lock, flags); | |
980 | reg_00.raw = io_apic_read(apic, 0); | |
981 | reg_01.raw = io_apic_read(apic, 1); | |
982 | if (reg_01.bits.version >= 0x10) | |
983 | reg_02.raw = io_apic_read(apic, 2); | |
984 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
985 | ||
986 | printk("\n"); | |
987 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid); | |
988 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); | |
989 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1da177e4 LT |
990 | |
991 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); | |
992 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); | |
1da177e4 LT |
993 | |
994 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
995 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); | |
1da177e4 LT |
996 | |
997 | if (reg_01.bits.version >= 0x10) { | |
998 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
999 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1000 | } |
1001 | ||
1002 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1003 | ||
ee4eff6f BR |
1004 | printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol" |
1005 | " Stat Dmod Deli Vect: \n"); | |
1da177e4 LT |
1006 | |
1007 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
1008 | struct IO_APIC_route_entry entry; | |
1009 | ||
eea0e11c | 1010 | entry = ioapic_read_entry(apic, i); |
1da177e4 | 1011 | |
ee4eff6f | 1012 | printk(KERN_DEBUG " %02x %03X ", |
1da177e4 | 1013 | i, |
ee4eff6f | 1014 | entry.dest |
1da177e4 LT |
1015 | ); |
1016 | ||
1017 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", | |
1018 | entry.mask, | |
1019 | entry.trigger, | |
1020 | entry.irr, | |
1021 | entry.polarity, | |
1022 | entry.delivery_status, | |
1023 | entry.dest_mode, | |
1024 | entry.delivery_mode, | |
1025 | entry.vector | |
1026 | ); | |
1027 | } | |
1028 | } | |
1da177e4 LT |
1029 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
1030 | for (i = 0; i < NR_IRQS; i++) { | |
1031 | struct irq_pin_list *entry = irq_2_pin + i; | |
1032 | if (entry->pin < 0) | |
1033 | continue; | |
04b9267b | 1034 | printk(KERN_DEBUG "IRQ%d ", i); |
1da177e4 LT |
1035 | for (;;) { |
1036 | printk("-> %d:%d", entry->apic, entry->pin); | |
1037 | if (!entry->next) | |
1038 | break; | |
1039 | entry = irq_2_pin + entry->next; | |
1040 | } | |
1041 | printk("\n"); | |
1042 | } | |
1043 | ||
1044 | printk(KERN_INFO ".................................... done.\n"); | |
1045 | ||
1046 | return; | |
1047 | } | |
1048 | ||
1049 | #if 0 | |
1050 | ||
1051 | static __apicdebuginit void print_APIC_bitfield (int base) | |
1052 | { | |
1053 | unsigned int v; | |
1054 | int i, j; | |
1055 | ||
1056 | if (apic_verbosity == APIC_QUIET) | |
1057 | return; | |
1058 | ||
1059 | printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG); | |
1060 | for (i = 0; i < 8; i++) { | |
1061 | v = apic_read(base + i*0x10); | |
1062 | for (j = 0; j < 32; j++) { | |
1063 | if (v & (1<<j)) | |
1064 | printk("1"); | |
1065 | else | |
1066 | printk("0"); | |
1067 | } | |
1068 | printk("\n"); | |
1069 | } | |
1070 | } | |
1071 | ||
1072 | void __apicdebuginit print_local_APIC(void * dummy) | |
1073 | { | |
1074 | unsigned int v, ver, maxlvt; | |
1075 | ||
1076 | if (apic_verbosity == APIC_QUIET) | |
1077 | return; | |
1078 | ||
1079 | printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", | |
1080 | smp_processor_id(), hard_smp_processor_id()); | |
05f2d12c | 1081 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(read_apic_id())); |
1da177e4 LT |
1082 | v = apic_read(APIC_LVR); |
1083 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1084 | ver = GET_APIC_VERSION(v); | |
37e650c7 | 1085 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1086 | |
1087 | v = apic_read(APIC_TASKPRI); | |
1088 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1089 | ||
5a40b7c2 AK |
1090 | v = apic_read(APIC_ARBPRI); |
1091 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1092 | v & APIC_ARBPRI_MASK); | |
1093 | v = apic_read(APIC_PROCPRI); | |
1094 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1da177e4 LT |
1095 | |
1096 | v = apic_read(APIC_EOI); | |
1097 | printk(KERN_DEBUG "... APIC EOI: %08x\n", v); | |
1098 | v = apic_read(APIC_RRR); | |
1099 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1100 | v = apic_read(APIC_LDR); | |
1101 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
1102 | v = apic_read(APIC_DFR); | |
1103 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1104 | v = apic_read(APIC_SPIV); | |
1105 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1106 | ||
1107 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
1108 | print_APIC_bitfield(APIC_ISR); | |
1109 | printk(KERN_DEBUG "... APIC TMR field:\n"); | |
1110 | print_APIC_bitfield(APIC_TMR); | |
1111 | printk(KERN_DEBUG "... APIC IRR field:\n"); | |
1112 | print_APIC_bitfield(APIC_IRR); | |
1113 | ||
5a40b7c2 AK |
1114 | v = apic_read(APIC_ESR); |
1115 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1da177e4 LT |
1116 | |
1117 | v = apic_read(APIC_ICR); | |
1118 | printk(KERN_DEBUG "... APIC ICR: %08x\n", v); | |
1119 | v = apic_read(APIC_ICR2); | |
1120 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", v); | |
1121 | ||
1122 | v = apic_read(APIC_LVTT); | |
1123 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1124 | ||
1125 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1126 | v = apic_read(APIC_LVTPC); | |
1127 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1128 | } | |
1129 | v = apic_read(APIC_LVT0); | |
1130 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1131 | v = apic_read(APIC_LVT1); | |
1132 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1133 | ||
1134 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1135 | v = apic_read(APIC_LVTERR); | |
1136 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1137 | } | |
1138 | ||
1139 | v = apic_read(APIC_TMICT); | |
1140 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1141 | v = apic_read(APIC_TMCCT); | |
1142 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1143 | v = apic_read(APIC_TDCR); | |
1144 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
1145 | printk("\n"); | |
1146 | } | |
1147 | ||
1148 | void print_all_local_APICs (void) | |
1149 | { | |
1150 | on_each_cpu(print_local_APIC, NULL, 1, 1); | |
1151 | } | |
1152 | ||
1153 | void __apicdebuginit print_PIC(void) | |
1154 | { | |
1da177e4 LT |
1155 | unsigned int v; |
1156 | unsigned long flags; | |
1157 | ||
1158 | if (apic_verbosity == APIC_QUIET) | |
1159 | return; | |
1160 | ||
1161 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1162 | ||
1163 | spin_lock_irqsave(&i8259A_lock, flags); | |
1164 | ||
1165 | v = inb(0xa1) << 8 | inb(0x21); | |
1166 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1167 | ||
1168 | v = inb(0xa0) << 8 | inb(0x20); | |
1169 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1170 | ||
1171 | outb(0x0b,0xa0); | |
1172 | outb(0x0b,0x20); | |
1173 | v = inb(0xa0) << 8 | inb(0x20); | |
1174 | outb(0x0a,0xa0); | |
1175 | outb(0x0a,0x20); | |
1176 | ||
1177 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
1178 | ||
1179 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1180 | ||
1181 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1182 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1183 | } | |
1184 | ||
1185 | #endif /* 0 */ | |
1186 | ||
1c69524c | 1187 | void __init enable_IO_APIC(void) |
1da177e4 LT |
1188 | { |
1189 | union IO_APIC_reg_01 reg_01; | |
1008fddc EB |
1190 | int i8259_apic, i8259_pin; |
1191 | int i, apic; | |
1da177e4 LT |
1192 | unsigned long flags; |
1193 | ||
1194 | for (i = 0; i < PIN_MAP_SIZE; i++) { | |
1195 | irq_2_pin[i].pin = -1; | |
1196 | irq_2_pin[i].next = 0; | |
1197 | } | |
1da177e4 LT |
1198 | |
1199 | /* | |
1200 | * The number of IO-APIC IRQ registers (== #pins): | |
1201 | */ | |
1008fddc | 1202 | for (apic = 0; apic < nr_ioapics; apic++) { |
1da177e4 | 1203 | spin_lock_irqsave(&ioapic_lock, flags); |
1008fddc | 1204 | reg_01.raw = io_apic_read(apic, 1); |
1da177e4 | 1205 | spin_unlock_irqrestore(&ioapic_lock, flags); |
1008fddc EB |
1206 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; |
1207 | } | |
1208 | for(apic = 0; apic < nr_ioapics; apic++) { | |
1209 | int pin; | |
1210 | /* See if any of the pins is in ExtINT mode */ | |
1211 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1212 | struct IO_APIC_route_entry entry; | |
eea0e11c | 1213 | entry = ioapic_read_entry(apic, pin); |
1008fddc EB |
1214 | |
1215 | /* If the interrupt line is enabled and in ExtInt mode | |
1216 | * I have found the pin where the i8259 is connected. | |
1217 | */ | |
1218 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1219 | ioapic_i8259.apic = apic; | |
1220 | ioapic_i8259.pin = pin; | |
1221 | goto found_i8259; | |
1222 | } | |
1223 | } | |
1224 | } | |
1225 | found_i8259: | |
1226 | /* Look to see what if the MP table has reported the ExtINT */ | |
1227 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1228 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1229 | /* Trust the MP table if nothing is setup in the hardware */ | |
1230 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1231 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1232 | ioapic_i8259.pin = i8259_pin; | |
1233 | ioapic_i8259.apic = i8259_apic; | |
1234 | } | |
1235 | /* Complain if the MP table and the hardware disagree */ | |
1236 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1237 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1238 | { | |
1239 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1240 | } |
1241 | ||
1242 | /* | |
1243 | * Do not trust the IO-APIC being empty at bootup | |
1244 | */ | |
1245 | clear_IO_APIC(); | |
1246 | } | |
1247 | ||
1248 | /* | |
1249 | * Not an __init, needed by the reboot code | |
1250 | */ | |
1251 | void disable_IO_APIC(void) | |
1252 | { | |
1253 | /* | |
1254 | * Clear the IO-APIC before rebooting: | |
1255 | */ | |
1256 | clear_IO_APIC(); | |
1257 | ||
208fb931 | 1258 | /* |
0b968d23 | 1259 | * If the i8259 is routed through an IOAPIC |
208fb931 | 1260 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 1261 | * so legacy interrupts can be delivered. |
208fb931 | 1262 | */ |
1008fddc | 1263 | if (ioapic_i8259.pin != -1) { |
208fb931 | 1264 | struct IO_APIC_route_entry entry; |
208fb931 EB |
1265 | |
1266 | memset(&entry, 0, sizeof(entry)); | |
1267 | entry.mask = 0; /* Enabled */ | |
1268 | entry.trigger = 0; /* Edge */ | |
1269 | entry.irr = 0; | |
1270 | entry.polarity = 0; /* High */ | |
1271 | entry.delivery_status = 0; | |
1272 | entry.dest_mode = 0; /* Physical */ | |
1008fddc | 1273 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
208fb931 | 1274 | entry.vector = 0; |
05f2d12c | 1275 | entry.dest = GET_APIC_ID(read_apic_id()); |
208fb931 | 1276 | |
208fb931 EB |
1277 | /* |
1278 | * Add it to the IO-APIC irq-routing table: | |
1279 | */ | |
eea0e11c | 1280 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
208fb931 EB |
1281 | } |
1282 | ||
1008fddc | 1283 | disconnect_bsp_APIC(ioapic_i8259.pin != -1); |
1da177e4 LT |
1284 | } |
1285 | ||
1da177e4 LT |
1286 | /* |
1287 | * There is a nasty bug in some older SMP boards, their mptable lies | |
1288 | * about the timer IRQ. We do the following to work around the situation: | |
1289 | * | |
1290 | * - timer IRQ defaults to IO-APIC IRQ | |
1291 | * - if this function detects that timer IRQs are defunct, then we fall | |
1292 | * back to ISA timer IRQs | |
1293 | */ | |
1294 | static int __init timer_irq_works(void) | |
1295 | { | |
1296 | unsigned long t1 = jiffies; | |
4aae0702 | 1297 | unsigned long flags; |
1da177e4 | 1298 | |
4aae0702 | 1299 | local_save_flags(flags); |
1da177e4 LT |
1300 | local_irq_enable(); |
1301 | /* Let ten ticks pass... */ | |
1302 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 1303 | local_irq_restore(flags); |
1da177e4 LT |
1304 | |
1305 | /* | |
1306 | * Expect a few ticks at least, to be sure some possible | |
1307 | * glue logic does not lock up after one or two first | |
1308 | * ticks in a non-ExtINT mode. Also the local APIC | |
1309 | * might have cached one ExtINT interrupt. Finally, at | |
1310 | * least one tick may be lost due to delays. | |
1311 | */ | |
1312 | ||
1313 | /* jiffies wrap? */ | |
1d16b53e | 1314 | if (time_after(jiffies, t1 + 4)) |
1da177e4 LT |
1315 | return 1; |
1316 | return 0; | |
1317 | } | |
1318 | ||
1319 | /* | |
1320 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
1321 | * number of pending IRQ events unhandled. These cases are very rare, | |
1322 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
1323 | * better to do it this way as thus we do not have to be aware of | |
1324 | * 'pending' interrupts in the IRQ path, except at this point. | |
1325 | */ | |
1326 | /* | |
1327 | * Edge triggered needs to resend any interrupt | |
1328 | * that was delayed but this is now handled in the device | |
1329 | * independent code. | |
1330 | */ | |
1331 | ||
1332 | /* | |
1333 | * Starting up a edge-triggered IO-APIC interrupt is | |
1334 | * nasty - we need to make sure that we get the edge. | |
1335 | * If it is already asserted for some reason, we need | |
1336 | * return 1 to indicate that is was pending. | |
1337 | * | |
1338 | * This is not complete - we should be able to fake | |
1339 | * an edge even if it isn't on the 8259A... | |
1340 | */ | |
1341 | ||
f29bd1ba | 1342 | static unsigned int startup_ioapic_irq(unsigned int irq) |
1da177e4 LT |
1343 | { |
1344 | int was_pending = 0; | |
1345 | unsigned long flags; | |
1346 | ||
1347 | spin_lock_irqsave(&ioapic_lock, flags); | |
1348 | if (irq < 16) { | |
1349 | disable_8259A_irq(irq); | |
1350 | if (i8259A_irq_pending(irq)) | |
1351 | was_pending = 1; | |
1352 | } | |
1353 | __unmask_IO_APIC_irq(irq); | |
1354 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1355 | ||
1356 | return was_pending; | |
1357 | } | |
1358 | ||
04b9267b | 1359 | static int ioapic_retrigger_irq(unsigned int irq) |
c0ad90a3 | 1360 | { |
13a79503 | 1361 | struct irq_cfg *cfg = &irq_cfg[irq]; |
550f2299 | 1362 | cpumask_t mask; |
6bf2dafa | 1363 | unsigned long flags; |
550f2299 | 1364 | |
6bf2dafa | 1365 | spin_lock_irqsave(&vector_lock, flags); |
550f2299 | 1366 | cpus_clear(mask); |
13a79503 | 1367 | cpu_set(first_cpu(cfg->domain), mask); |
550f2299 | 1368 | |
13a79503 | 1369 | send_IPI_mask(mask, cfg->vector); |
6bf2dafa | 1370 | spin_unlock_irqrestore(&vector_lock, flags); |
c0ad90a3 IM |
1371 | |
1372 | return 1; | |
1373 | } | |
1374 | ||
1da177e4 LT |
1375 | /* |
1376 | * Level and edge triggered IO-APIC interrupts need different handling, | |
1377 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be | |
1378 | * handled with the level-triggered descriptor, but that one has slightly | |
1379 | * more overhead. Level-triggered interrupts cannot be handled with the | |
1380 | * edge-triggered handler, without risking IRQ storms and other ugly | |
1381 | * races. | |
1382 | */ | |
1383 | ||
61014292 EB |
1384 | #ifdef CONFIG_SMP |
1385 | asmlinkage void smp_irq_move_cleanup_interrupt(void) | |
1386 | { | |
1387 | unsigned vector, me; | |
1388 | ack_APIC_irq(); | |
1389 | exit_idle(); | |
1390 | irq_enter(); | |
1391 | ||
1392 | me = smp_processor_id(); | |
1393 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
1394 | unsigned int irq; | |
1395 | struct irq_desc *desc; | |
1396 | struct irq_cfg *cfg; | |
1397 | irq = __get_cpu_var(vector_irq)[vector]; | |
1398 | if (irq >= NR_IRQS) | |
1399 | continue; | |
1400 | ||
1401 | desc = irq_desc + irq; | |
1402 | cfg = irq_cfg + irq; | |
1403 | spin_lock(&desc->lock); | |
1404 | if (!cfg->move_cleanup_count) | |
1405 | goto unlock; | |
1406 | ||
1407 | if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) | |
1408 | goto unlock; | |
1409 | ||
1410 | __get_cpu_var(vector_irq)[vector] = -1; | |
1411 | cfg->move_cleanup_count--; | |
1412 | unlock: | |
1413 | spin_unlock(&desc->lock); | |
1414 | } | |
1415 | ||
1416 | irq_exit(); | |
1417 | } | |
1418 | ||
1419 | static void irq_complete_move(unsigned int irq) | |
1420 | { | |
1421 | struct irq_cfg *cfg = irq_cfg + irq; | |
1422 | unsigned vector, me; | |
1423 | ||
1424 | if (likely(!cfg->move_in_progress)) | |
1425 | return; | |
1426 | ||
65ea5b03 | 1427 | vector = ~get_irq_regs()->orig_ax; |
61014292 | 1428 | me = smp_processor_id(); |
f0e13ae7 | 1429 | if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) { |
61014292 EB |
1430 | cpumask_t cleanup_mask; |
1431 | ||
1432 | cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map); | |
1433 | cfg->move_cleanup_count = cpus_weight(cleanup_mask); | |
1434 | send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); | |
1435 | cfg->move_in_progress = 0; | |
1436 | } | |
1437 | } | |
1438 | #else | |
1439 | static inline void irq_complete_move(unsigned int irq) {} | |
1440 | #endif | |
1441 | ||
0be6652f EB |
1442 | static void ack_apic_edge(unsigned int irq) |
1443 | { | |
61014292 | 1444 | irq_complete_move(irq); |
0be6652f EB |
1445 | move_native_irq(irq); |
1446 | ack_APIC_irq(); | |
1447 | } | |
1448 | ||
1449 | static void ack_apic_level(unsigned int irq) | |
1450 | { | |
1451 | int do_unmask_irq = 0; | |
1452 | ||
61014292 | 1453 | irq_complete_move(irq); |
52e3d90d | 1454 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
0be6652f EB |
1455 | /* If we are moving the irq we need to mask it */ |
1456 | if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) { | |
1457 | do_unmask_irq = 1; | |
1458 | mask_IO_APIC_irq(irq); | |
1459 | } | |
1460 | #endif | |
1461 | ||
1462 | /* | |
1463 | * We must acknowledge the irq before we move it or the acknowledge will | |
beb7dd86 | 1464 | * not propagate properly. |
0be6652f EB |
1465 | */ |
1466 | ack_APIC_irq(); | |
1467 | ||
1468 | /* Now we can move and renable the irq */ | |
ef3e28c5 EB |
1469 | if (unlikely(do_unmask_irq)) { |
1470 | /* Only migrate the irq if the ack has been received. | |
1471 | * | |
1472 | * On rare occasions the broadcast level triggered ack gets | |
1473 | * delayed going to ioapics, and if we reprogram the | |
1474 | * vector while Remote IRR is still set the irq will never | |
1475 | * fire again. | |
1476 | * | |
1477 | * To prevent this scenario we read the Remote IRR bit | |
1478 | * of the ioapic. This has two effects. | |
1479 | * - On any sane system the read of the ioapic will | |
1480 | * flush writes (and acks) going to the ioapic from | |
1481 | * this cpu. | |
1482 | * - We get to see if the ACK has actually been delivered. | |
1483 | * | |
1484 | * Based on failed experiments of reprogramming the | |
1485 | * ioapic entry from outside of irq context starting | |
1486 | * with masking the ioapic entry and then polling until | |
1487 | * Remote IRR was clear before reprogramming the | |
1488 | * ioapic I don't trust the Remote IRR bit to be | |
1489 | * completey accurate. | |
1490 | * | |
1491 | * However there appears to be no other way to plug | |
1492 | * this race, so if the Remote IRR bit is not | |
1493 | * accurate and is causing problems then it is a hardware bug | |
1494 | * and you can go talk to the chipset vendor about it. | |
1495 | */ | |
1496 | if (!io_apic_level_ack_pending(irq)) | |
1497 | move_masked_irq(irq); | |
0be6652f | 1498 | unmask_IO_APIC_irq(irq); |
ef3e28c5 | 1499 | } |
0be6652f EB |
1500 | } |
1501 | ||
f29bd1ba IM |
1502 | static struct irq_chip ioapic_chip __read_mostly = { |
1503 | .name = "IO-APIC", | |
04b9267b EB |
1504 | .startup = startup_ioapic_irq, |
1505 | .mask = mask_IO_APIC_irq, | |
1506 | .unmask = unmask_IO_APIC_irq, | |
0be6652f EB |
1507 | .ack = ack_apic_edge, |
1508 | .eoi = ack_apic_level, | |
54d5d424 | 1509 | #ifdef CONFIG_SMP |
04b9267b | 1510 | .set_affinity = set_ioapic_affinity_irq, |
54d5d424 | 1511 | #endif |
04b9267b | 1512 | .retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
1513 | }; |
1514 | ||
1515 | static inline void init_IO_APIC_traps(void) | |
1516 | { | |
1517 | int irq; | |
1518 | ||
1519 | /* | |
1520 | * NOTE! The local APIC isn't very good at handling | |
1521 | * multiple interrupts at the same interrupt level. | |
1522 | * As the interrupt level is determined by taking the | |
1523 | * vector number and shifting that right by 4, we | |
1524 | * want to spread these out a bit so that they don't | |
1525 | * all fall in the same interrupt level. | |
1526 | * | |
1527 | * Also, we've got to be careful not to trash gate | |
1528 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
1529 | */ | |
1530 | for (irq = 0; irq < NR_IRQS ; irq++) { | |
1531 | int tmp = irq; | |
13a79503 | 1532 | if (IO_APIC_IRQ(tmp) && !irq_cfg[tmp].vector) { |
1da177e4 LT |
1533 | /* |
1534 | * Hmm.. We don't have an entry for this, | |
1535 | * so default to an old-fashioned 8259 | |
1536 | * interrupt if we can.. | |
1537 | */ | |
1538 | if (irq < 16) | |
1539 | make_8259A_irq(irq); | |
1540 | else | |
1541 | /* Strange. Oh, well.. */ | |
f29bd1ba | 1542 | irq_desc[irq].chip = &no_irq_chip; |
1da177e4 LT |
1543 | } |
1544 | } | |
1545 | } | |
1546 | ||
1547 | static void enable_lapic_irq (unsigned int irq) | |
1548 | { | |
1549 | unsigned long v; | |
1550 | ||
1551 | v = apic_read(APIC_LVT0); | |
11a8e778 | 1552 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
1da177e4 LT |
1553 | } |
1554 | ||
1555 | static void disable_lapic_irq (unsigned int irq) | |
1556 | { | |
1557 | unsigned long v; | |
1558 | ||
1559 | v = apic_read(APIC_LVT0); | |
11a8e778 | 1560 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
1561 | } |
1562 | ||
1563 | static void ack_lapic_irq (unsigned int irq) | |
1564 | { | |
1565 | ack_APIC_irq(); | |
1566 | } | |
1567 | ||
1568 | static void end_lapic_irq (unsigned int i) { /* nothing */ } | |
1569 | ||
6c231b7b | 1570 | static struct hw_interrupt_type lapic_irq_type __read_mostly = { |
c47e285d | 1571 | .name = "local-APIC", |
1da177e4 LT |
1572 | .typename = "local-APIC-edge", |
1573 | .startup = NULL, /* startup_irq() not used for IRQ0 */ | |
1574 | .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */ | |
1575 | .enable = enable_lapic_irq, | |
1576 | .disable = disable_lapic_irq, | |
1577 | .ack = ack_lapic_irq, | |
1578 | .end = end_lapic_irq, | |
1579 | }; | |
1580 | ||
e9427101 | 1581 | static void __init setup_nmi(void) |
1da177e4 LT |
1582 | { |
1583 | /* | |
1584 | * Dirty trick to enable the NMI watchdog ... | |
1585 | * We put the 8259A master into AEOI mode and | |
1586 | * unmask on all local APICs LVT0 as NMI. | |
1587 | * | |
1588 | * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') | |
1589 | * is from Maciej W. Rozycki - so we do not have to EOI from | |
1590 | * the NMI handler or the timer interrupt. | |
1591 | */ | |
1592 | printk(KERN_INFO "activating NMI Watchdog ..."); | |
1593 | ||
e9427101 | 1594 | enable_NMI_through_LVT0(); |
1da177e4 LT |
1595 | |
1596 | printk(" done.\n"); | |
1597 | } | |
1598 | ||
1599 | /* | |
1600 | * This looks a bit hackish but it's about the only one way of sending | |
1601 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
1602 | * not support the ExtINT mode, unfortunately. We need to send these | |
1603 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
1604 | * 8259A interrupt line asserted until INTA. --macro | |
1605 | */ | |
1606 | static inline void unlock_ExtINT_logic(void) | |
1607 | { | |
1008fddc | 1608 | int apic, pin, i; |
1da177e4 LT |
1609 | struct IO_APIC_route_entry entry0, entry1; |
1610 | unsigned char save_control, save_freq_select; | |
1611 | unsigned long flags; | |
1612 | ||
1008fddc EB |
1613 | pin = find_isa_irq_pin(8, mp_INT); |
1614 | apic = find_isa_irq_apic(8, mp_INT); | |
1da177e4 LT |
1615 | if (pin == -1) |
1616 | return; | |
1617 | ||
1618 | spin_lock_irqsave(&ioapic_lock, flags); | |
1008fddc EB |
1619 | *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin); |
1620 | *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin); | |
1da177e4 | 1621 | spin_unlock_irqrestore(&ioapic_lock, flags); |
1008fddc | 1622 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
1623 | |
1624 | memset(&entry1, 0, sizeof(entry1)); | |
1625 | ||
1626 | entry1.dest_mode = 0; /* physical delivery */ | |
1627 | entry1.mask = 0; /* unmask IRQ now */ | |
ee4eff6f | 1628 | entry1.dest = hard_smp_processor_id(); |
1da177e4 LT |
1629 | entry1.delivery_mode = dest_ExtINT; |
1630 | entry1.polarity = entry0.polarity; | |
1631 | entry1.trigger = 0; | |
1632 | entry1.vector = 0; | |
1633 | ||
1634 | spin_lock_irqsave(&ioapic_lock, flags); | |
1008fddc EB |
1635 | io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1)); |
1636 | io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0)); | |
1da177e4 LT |
1637 | spin_unlock_irqrestore(&ioapic_lock, flags); |
1638 | ||
1639 | save_control = CMOS_READ(RTC_CONTROL); | |
1640 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
1641 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
1642 | RTC_FREQ_SELECT); | |
1643 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
1644 | ||
1645 | i = 100; | |
1646 | while (i-- > 0) { | |
1647 | mdelay(10); | |
1648 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
1649 | i -= 10; | |
1650 | } | |
1651 | ||
1652 | CMOS_WRITE(save_control, RTC_CONTROL); | |
1653 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
1008fddc | 1654 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
1655 | |
1656 | spin_lock_irqsave(&ioapic_lock, flags); | |
1008fddc EB |
1657 | io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1)); |
1658 | io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0)); | |
1da177e4 LT |
1659 | spin_unlock_irqrestore(&ioapic_lock, flags); |
1660 | } | |
1661 | ||
1662 | /* | |
1663 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
1664 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
1665 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
1666 | * fanatically on his truly buggy board. | |
fea5f1e1 LT |
1667 | * |
1668 | * FIXME: really need to revamp this for modern platforms only. | |
1da177e4 | 1669 | */ |
e9427101 | 1670 | static inline void __init check_timer(void) |
1da177e4 | 1671 | { |
dfbffdd8 | 1672 | struct irq_cfg *cfg = irq_cfg + 0; |
1008fddc | 1673 | int apic1, pin1, apic2, pin2; |
4aae0702 IM |
1674 | unsigned long flags; |
1675 | ||
1676 | local_irq_save(flags); | |
1da177e4 LT |
1677 | |
1678 | /* | |
1679 | * get/set the timer IRQ vector: | |
1680 | */ | |
1681 | disable_8259A_irq(0); | |
dfbffdd8 | 1682 | assign_irq_vector(0, TARGET_CPUS); |
1da177e4 LT |
1683 | |
1684 | /* | |
1685 | * Subtle, code in do_timer_interrupt() expects an AEOI | |
1686 | * mode for the 8259A whenever interrupts are routed | |
1687 | * through I/O APICs. Also IRQ0 has to be enabled in | |
1688 | * the 8259A which implies the virtual wire has to be | |
1689 | * disabled in the local APIC. | |
1690 | */ | |
11a8e778 | 1691 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
1da177e4 | 1692 | init_8259A(1); |
fea5f1e1 LT |
1693 | if (timer_over_8254 > 0) |
1694 | enable_8259A_irq(0); | |
1da177e4 | 1695 | |
1008fddc EB |
1696 | pin1 = find_isa_irq_pin(0, mp_INT); |
1697 | apic1 = find_isa_irq_apic(0, mp_INT); | |
1698 | pin2 = ioapic_i8259.pin; | |
1699 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 1700 | |
fea5f1e1 | 1701 | apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n", |
dfbffdd8 | 1702 | cfg->vector, apic1, pin1, apic2, pin2); |
b0268726 | 1703 | |
fea5f1e1 LT |
1704 | if (pin1 != -1) { |
1705 | /* | |
1706 | * Ok, does IRQ0 through the IOAPIC work? | |
1707 | */ | |
1708 | unmask_IO_APIC_irq(0); | |
1709 | if (!no_timer_check && timer_irq_works()) { | |
1710 | nmi_watchdog_default(); | |
1711 | if (nmi_watchdog == NMI_IO_APIC) { | |
1712 | disable_8259A_irq(0); | |
1713 | setup_nmi(); | |
1714 | enable_8259A_irq(0); | |
1715 | } | |
1716 | if (disable_timer_pin_1 > 0) | |
1717 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 1718 | goto out; |
fea5f1e1 LT |
1719 | } |
1720 | clear_IO_APIC_pin(apic1, pin1); | |
1721 | apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not " | |
1722 | "connected to IO-APIC\n"); | |
1723 | } | |
1da177e4 | 1724 | |
fea5f1e1 LT |
1725 | apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) " |
1726 | "through the 8259A ... "); | |
1da177e4 | 1727 | if (pin2 != -1) { |
fea5f1e1 LT |
1728 | apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...", |
1729 | apic2, pin2); | |
1730 | /* | |
1731 | * legacy devices should be connected to IO APIC #0 | |
1732 | */ | |
dfbffdd8 | 1733 | setup_ExtINT_IRQ0_pin(apic2, pin2, cfg->vector); |
fea5f1e1 LT |
1734 | if (timer_irq_works()) { |
1735 | apic_printk(APIC_VERBOSE," works.\n"); | |
1736 | nmi_watchdog_default(); | |
1737 | if (nmi_watchdog == NMI_IO_APIC) { | |
1738 | setup_nmi(); | |
1739 | } | |
4aae0702 | 1740 | goto out; |
fea5f1e1 LT |
1741 | } |
1742 | /* | |
1743 | * Cleanup, just in case ... | |
1744 | */ | |
1745 | clear_IO_APIC_pin(apic2, pin2); | |
1da177e4 | 1746 | } |
fea5f1e1 | 1747 | apic_printk(APIC_VERBOSE," failed.\n"); |
1da177e4 | 1748 | |
1f992153 | 1749 | if (nmi_watchdog == NMI_IO_APIC) { |
1da177e4 LT |
1750 | printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n"); |
1751 | nmi_watchdog = 0; | |
1752 | } | |
1753 | ||
1754 | apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ..."); | |
1755 | ||
1756 | disable_8259A_irq(0); | |
d1bef4ed | 1757 | irq_desc[0].chip = &lapic_irq_type; |
dfbffdd8 | 1758 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ |
1da177e4 LT |
1759 | enable_8259A_irq(0); |
1760 | ||
1761 | if (timer_irq_works()) { | |
5b922cd4 | 1762 | apic_printk(APIC_VERBOSE," works.\n"); |
4aae0702 | 1763 | goto out; |
1da177e4 | 1764 | } |
dfbffdd8 | 1765 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
1da177e4 LT |
1766 | apic_printk(APIC_VERBOSE," failed.\n"); |
1767 | ||
1768 | apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ..."); | |
1769 | ||
1770 | init_8259A(0); | |
1771 | make_8259A_irq(0); | |
11a8e778 | 1772 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
1773 | |
1774 | unlock_ExtINT_logic(); | |
1775 | ||
1776 | if (timer_irq_works()) { | |
1777 | apic_printk(APIC_VERBOSE," works.\n"); | |
4aae0702 | 1778 | goto out; |
1da177e4 LT |
1779 | } |
1780 | apic_printk(APIC_VERBOSE," failed :(.\n"); | |
1781 | panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n"); | |
4aae0702 IM |
1782 | out: |
1783 | local_irq_restore(flags); | |
1da177e4 LT |
1784 | } |
1785 | ||
14d98cad AK |
1786 | static int __init notimercheck(char *s) |
1787 | { | |
1788 | no_timer_check = 1; | |
1789 | return 1; | |
1790 | } | |
1791 | __setup("no_timer_check", notimercheck); | |
1792 | ||
1da177e4 LT |
1793 | /* |
1794 | * | |
676b1855 | 1795 | * IRQs that are handled by the PIC in the MPS IOAPIC case. |
1da177e4 LT |
1796 | * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ. |
1797 | * Linux doesn't really care, as it's not actually used | |
1798 | * for any interrupt handling anyway. | |
1799 | */ | |
1800 | #define PIC_IRQS (1<<2) | |
1801 | ||
1802 | void __init setup_IO_APIC(void) | |
1803 | { | |
1c69524c YL |
1804 | |
1805 | /* | |
1806 | * calling enable_IO_APIC() is moved to setup_local_APIC for BP | |
1807 | */ | |
1da177e4 LT |
1808 | |
1809 | if (acpi_ioapic) | |
1810 | io_apic_irqs = ~0; /* all IRQs go through IOAPIC */ | |
1811 | else | |
1812 | io_apic_irqs = ~PIC_IRQS; | |
1813 | ||
1814 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); | |
1815 | ||
1da177e4 LT |
1816 | sync_Arb_IDs(); |
1817 | setup_IO_APIC_irqs(); | |
1818 | init_IO_APIC_traps(); | |
1819 | check_timer(); | |
1820 | if (!acpi_ioapic) | |
1821 | print_IO_APIC(); | |
1822 | } | |
1823 | ||
1824 | struct sysfs_ioapic_data { | |
1825 | struct sys_device dev; | |
1826 | struct IO_APIC_route_entry entry[0]; | |
1827 | }; | |
1828 | static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS]; | |
1829 | ||
0b9c33a7 | 1830 | static int ioapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
1831 | { |
1832 | struct IO_APIC_route_entry *entry; | |
1833 | struct sysfs_ioapic_data *data; | |
1da177e4 LT |
1834 | int i; |
1835 | ||
1836 | data = container_of(dev, struct sysfs_ioapic_data, dev); | |
1837 | entry = data->entry; | |
eea0e11c AK |
1838 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) |
1839 | *entry = ioapic_read_entry(dev->id, i); | |
1da177e4 LT |
1840 | |
1841 | return 0; | |
1842 | } | |
1843 | ||
1844 | static int ioapic_resume(struct sys_device *dev) | |
1845 | { | |
1846 | struct IO_APIC_route_entry *entry; | |
1847 | struct sysfs_ioapic_data *data; | |
1848 | unsigned long flags; | |
1849 | union IO_APIC_reg_00 reg_00; | |
1850 | int i; | |
1851 | ||
1852 | data = container_of(dev, struct sysfs_ioapic_data, dev); | |
1853 | entry = data->entry; | |
1854 | ||
1855 | spin_lock_irqsave(&ioapic_lock, flags); | |
1856 | reg_00.raw = io_apic_read(dev->id, 0); | |
1857 | if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) { | |
1858 | reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid; | |
1859 | io_apic_write(dev->id, 0, reg_00.raw); | |
1860 | } | |
1da177e4 | 1861 | spin_unlock_irqrestore(&ioapic_lock, flags); |
eea0e11c AK |
1862 | for (i = 0; i < nr_ioapic_registers[dev->id]; i++) |
1863 | ioapic_write_entry(dev->id, i, entry[i]); | |
1da177e4 LT |
1864 | |
1865 | return 0; | |
1866 | } | |
1867 | ||
1868 | static struct sysdev_class ioapic_sysdev_class = { | |
af5ca3f4 | 1869 | .name = "ioapic", |
1da177e4 LT |
1870 | .suspend = ioapic_suspend, |
1871 | .resume = ioapic_resume, | |
1872 | }; | |
1873 | ||
1874 | static int __init ioapic_init_sysfs(void) | |
1875 | { | |
1876 | struct sys_device * dev; | |
cddf7ff7 | 1877 | int i, size, error; |
1da177e4 LT |
1878 | |
1879 | error = sysdev_class_register(&ioapic_sysdev_class); | |
1880 | if (error) | |
1881 | return error; | |
1882 | ||
1883 | for (i = 0; i < nr_ioapics; i++ ) { | |
1884 | size = sizeof(struct sys_device) + nr_ioapic_registers[i] | |
1885 | * sizeof(struct IO_APIC_route_entry); | |
cddf7ff7 | 1886 | mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL); |
1da177e4 LT |
1887 | if (!mp_ioapic_data[i]) { |
1888 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
1889 | continue; | |
1890 | } | |
1da177e4 LT |
1891 | dev = &mp_ioapic_data[i]->dev; |
1892 | dev->id = i; | |
1893 | dev->cls = &ioapic_sysdev_class; | |
1894 | error = sysdev_register(dev); | |
1895 | if (error) { | |
1896 | kfree(mp_ioapic_data[i]); | |
1897 | mp_ioapic_data[i] = NULL; | |
1898 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
1899 | continue; | |
1900 | } | |
1901 | } | |
1902 | ||
1903 | return 0; | |
1904 | } | |
1905 | ||
1906 | device_initcall(ioapic_init_sysfs); | |
1907 | ||
c4fa0bbf | 1908 | /* |
04b9267b | 1909 | * Dynamic irq allocate and deallocation |
c4fa0bbf EB |
1910 | */ |
1911 | int create_irq(void) | |
1912 | { | |
04b9267b EB |
1913 | /* Allocate an unused irq */ |
1914 | int irq; | |
1915 | int new; | |
c4fa0bbf | 1916 | unsigned long flags; |
c4fa0bbf | 1917 | |
04b9267b EB |
1918 | irq = -ENOSPC; |
1919 | spin_lock_irqsave(&vector_lock, flags); | |
1920 | for (new = (NR_IRQS - 1); new >= 0; new--) { | |
1921 | if (platform_legacy_irq(new)) | |
1922 | continue; | |
13a79503 | 1923 | if (irq_cfg[new].vector != 0) |
04b9267b | 1924 | continue; |
dfbffdd8 | 1925 | if (__assign_irq_vector(new, TARGET_CPUS) == 0) |
04b9267b EB |
1926 | irq = new; |
1927 | break; | |
1928 | } | |
1929 | spin_unlock_irqrestore(&vector_lock, flags); | |
c4fa0bbf | 1930 | |
04b9267b | 1931 | if (irq >= 0) { |
c4fa0bbf EB |
1932 | dynamic_irq_init(irq); |
1933 | } | |
1934 | return irq; | |
1935 | } | |
1936 | ||
1937 | void destroy_irq(unsigned int irq) | |
1938 | { | |
1939 | unsigned long flags; | |
c4fa0bbf EB |
1940 | |
1941 | dynamic_irq_cleanup(irq); | |
1942 | ||
1943 | spin_lock_irqsave(&vector_lock, flags); | |
5df0287e | 1944 | __clear_irq_vector(irq); |
c4fa0bbf EB |
1945 | spin_unlock_irqrestore(&vector_lock, flags); |
1946 | } | |
c4fa0bbf | 1947 | |
589e367f | 1948 | /* |
676b1855 | 1949 | * MSI message composition |
589e367f EB |
1950 | */ |
1951 | #ifdef CONFIG_PCI_MSI | |
3b7d1921 | 1952 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg) |
589e367f | 1953 | { |
dfbffdd8 EB |
1954 | struct irq_cfg *cfg = irq_cfg + irq; |
1955 | int err; | |
589e367f | 1956 | unsigned dest; |
c7111c13 | 1957 | cpumask_t tmp; |
589e367f | 1958 | |
dfbffdd8 EB |
1959 | tmp = TARGET_CPUS; |
1960 | err = assign_irq_vector(irq, tmp); | |
1961 | if (!err) { | |
1962 | cpus_and(tmp, cfg->domain, tmp); | |
589e367f EB |
1963 | dest = cpu_mask_to_apicid(tmp); |
1964 | ||
1965 | msg->address_hi = MSI_ADDR_BASE_HI; | |
1966 | msg->address_lo = | |
1967 | MSI_ADDR_BASE_LO | | |
1968 | ((INT_DEST_MODE == 0) ? | |
1969 | MSI_ADDR_DEST_MODE_PHYSICAL: | |
1970 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
1971 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
1972 | MSI_ADDR_REDIRECTION_CPU: | |
1973 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
1974 | MSI_ADDR_DEST_ID(dest); | |
1975 | ||
1976 | msg->data = | |
1977 | MSI_DATA_TRIGGER_EDGE | | |
1978 | MSI_DATA_LEVEL_ASSERT | | |
1979 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
1980 | MSI_DATA_DELIVERY_FIXED: | |
1981 | MSI_DATA_DELIVERY_LOWPRI) | | |
dfbffdd8 | 1982 | MSI_DATA_VECTOR(cfg->vector); |
589e367f | 1983 | } |
dfbffdd8 | 1984 | return err; |
589e367f EB |
1985 | } |
1986 | ||
3b7d1921 EB |
1987 | #ifdef CONFIG_SMP |
1988 | static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask) | |
589e367f | 1989 | { |
dfbffdd8 | 1990 | struct irq_cfg *cfg = irq_cfg + irq; |
3b7d1921 EB |
1991 | struct msi_msg msg; |
1992 | unsigned int dest; | |
1993 | cpumask_t tmp; | |
3b7d1921 EB |
1994 | |
1995 | cpus_and(tmp, mask, cpu_online_map); | |
1996 | if (cpus_empty(tmp)) | |
5ff5115e | 1997 | return; |
589e367f | 1998 | |
dfbffdd8 | 1999 | if (assign_irq_vector(irq, mask)) |
3b7d1921 | 2000 | return; |
550f2299 | 2001 | |
dfbffdd8 | 2002 | cpus_and(tmp, cfg->domain, mask); |
3b7d1921 | 2003 | dest = cpu_mask_to_apicid(tmp); |
589e367f | 2004 | |
3b7d1921 EB |
2005 | read_msi_msg(irq, &msg); |
2006 | ||
2007 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
dfbffdd8 | 2008 | msg.data |= MSI_DATA_VECTOR(cfg->vector); |
3b7d1921 EB |
2009 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; |
2010 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
2011 | ||
2012 | write_msi_msg(irq, &msg); | |
9f0a5ba5 | 2013 | irq_desc[irq].affinity = mask; |
589e367f | 2014 | } |
3b7d1921 | 2015 | #endif /* CONFIG_SMP */ |
589e367f | 2016 | |
3b7d1921 EB |
2017 | /* |
2018 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
2019 | * which implement the MSI or MSI-X Capability Structure. | |
2020 | */ | |
2021 | static struct irq_chip msi_chip = { | |
2022 | .name = "PCI-MSI", | |
2023 | .unmask = unmask_msi_irq, | |
2024 | .mask = mask_msi_irq, | |
2025 | .ack = ack_apic_edge, | |
2026 | #ifdef CONFIG_SMP | |
2027 | .set_affinity = set_msi_irq_affinity, | |
2028 | #endif | |
2029 | .retrigger = ioapic_retrigger_irq, | |
589e367f EB |
2030 | }; |
2031 | ||
f7feaca7 | 2032 | int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) |
3b7d1921 EB |
2033 | { |
2034 | struct msi_msg msg; | |
f7feaca7 EB |
2035 | int irq, ret; |
2036 | irq = create_irq(); | |
2037 | if (irq < 0) | |
2038 | return irq; | |
2039 | ||
3b7d1921 | 2040 | ret = msi_compose_msg(dev, irq, &msg); |
f7feaca7 EB |
2041 | if (ret < 0) { |
2042 | destroy_irq(irq); | |
3b7d1921 | 2043 | return ret; |
f7feaca7 | 2044 | } |
3b7d1921 | 2045 | |
7fe3730d | 2046 | set_irq_msi(irq, desc); |
3b7d1921 EB |
2047 | write_msi_msg(irq, &msg); |
2048 | ||
a460e745 | 2049 | set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge"); |
3b7d1921 | 2050 | |
7fe3730d | 2051 | return 0; |
3b7d1921 EB |
2052 | } |
2053 | ||
2054 | void arch_teardown_msi_irq(unsigned int irq) | |
2055 | { | |
f7feaca7 | 2056 | destroy_irq(irq); |
3b7d1921 EB |
2057 | } |
2058 | ||
3460a6d9 KA |
2059 | #ifdef CONFIG_DMAR |
2060 | #ifdef CONFIG_SMP | |
2061 | static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask) | |
2062 | { | |
2063 | struct irq_cfg *cfg = irq_cfg + irq; | |
2064 | struct msi_msg msg; | |
2065 | unsigned int dest; | |
2066 | cpumask_t tmp; | |
2067 | ||
2068 | cpus_and(tmp, mask, cpu_online_map); | |
2069 | if (cpus_empty(tmp)) | |
2070 | return; | |
2071 | ||
2072 | if (assign_irq_vector(irq, mask)) | |
2073 | return; | |
2074 | ||
2075 | cpus_and(tmp, cfg->domain, mask); | |
2076 | dest = cpu_mask_to_apicid(tmp); | |
2077 | ||
2078 | dmar_msi_read(irq, &msg); | |
2079 | ||
2080 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
2081 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
2082 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
2083 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
2084 | ||
2085 | dmar_msi_write(irq, &msg); | |
2086 | irq_desc[irq].affinity = mask; | |
2087 | } | |
2088 | #endif /* CONFIG_SMP */ | |
2089 | ||
2090 | struct irq_chip dmar_msi_type = { | |
2091 | .name = "DMAR_MSI", | |
2092 | .unmask = dmar_msi_unmask, | |
2093 | .mask = dmar_msi_mask, | |
2094 | .ack = ack_apic_edge, | |
2095 | #ifdef CONFIG_SMP | |
2096 | .set_affinity = dmar_msi_set_affinity, | |
2097 | #endif | |
2098 | .retrigger = ioapic_retrigger_irq, | |
2099 | }; | |
2100 | ||
2101 | int arch_setup_dmar_msi(unsigned int irq) | |
2102 | { | |
2103 | int ret; | |
2104 | struct msi_msg msg; | |
2105 | ||
2106 | ret = msi_compose_msg(NULL, irq, &msg); | |
2107 | if (ret < 0) | |
2108 | return ret; | |
2109 | dmar_msi_write(irq, &msg); | |
2110 | set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, | |
2111 | "edge"); | |
2112 | return 0; | |
2113 | } | |
2114 | #endif | |
589e367f | 2115 | |
3460a6d9 | 2116 | #endif /* CONFIG_PCI_MSI */ |
8b955b0d EB |
2117 | /* |
2118 | * Hypertransport interrupt support | |
2119 | */ | |
2120 | #ifdef CONFIG_HT_IRQ | |
2121 | ||
2122 | #ifdef CONFIG_SMP | |
2123 | ||
2124 | static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) | |
2125 | { | |
ec68307c EB |
2126 | struct ht_irq_msg msg; |
2127 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 2128 | |
ec68307c EB |
2129 | msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); |
2130 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); | |
8b955b0d | 2131 | |
ec68307c EB |
2132 | msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); |
2133 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); | |
8b955b0d | 2134 | |
ec68307c | 2135 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
2136 | } |
2137 | ||
2138 | static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask) | |
2139 | { | |
dfbffdd8 | 2140 | struct irq_cfg *cfg = irq_cfg + irq; |
8b955b0d EB |
2141 | unsigned int dest; |
2142 | cpumask_t tmp; | |
8b955b0d EB |
2143 | |
2144 | cpus_and(tmp, mask, cpu_online_map); | |
2145 | if (cpus_empty(tmp)) | |
5ff5115e | 2146 | return; |
8b955b0d | 2147 | |
dfbffdd8 | 2148 | if (assign_irq_vector(irq, mask)) |
8b955b0d EB |
2149 | return; |
2150 | ||
dfbffdd8 | 2151 | cpus_and(tmp, cfg->domain, mask); |
8b955b0d EB |
2152 | dest = cpu_mask_to_apicid(tmp); |
2153 | ||
dfbffdd8 | 2154 | target_ht_irq(irq, dest, cfg->vector); |
9f0a5ba5 | 2155 | irq_desc[irq].affinity = mask; |
8b955b0d EB |
2156 | } |
2157 | #endif | |
2158 | ||
c37e108d | 2159 | static struct irq_chip ht_irq_chip = { |
8b955b0d EB |
2160 | .name = "PCI-HT", |
2161 | .mask = mask_ht_irq, | |
2162 | .unmask = unmask_ht_irq, | |
2163 | .ack = ack_apic_edge, | |
2164 | #ifdef CONFIG_SMP | |
2165 | .set_affinity = set_ht_irq_affinity, | |
2166 | #endif | |
2167 | .retrigger = ioapic_retrigger_irq, | |
2168 | }; | |
2169 | ||
2170 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
2171 | { | |
dfbffdd8 EB |
2172 | struct irq_cfg *cfg = irq_cfg + irq; |
2173 | int err; | |
c7111c13 | 2174 | cpumask_t tmp; |
8b955b0d | 2175 | |
dfbffdd8 EB |
2176 | tmp = TARGET_CPUS; |
2177 | err = assign_irq_vector(irq, tmp); | |
2178 | if (!err) { | |
ec68307c | 2179 | struct ht_irq_msg msg; |
8b955b0d | 2180 | unsigned dest; |
8b955b0d | 2181 | |
dfbffdd8 | 2182 | cpus_and(tmp, cfg->domain, tmp); |
8b955b0d EB |
2183 | dest = cpu_mask_to_apicid(tmp); |
2184 | ||
ec68307c | 2185 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 2186 | |
ec68307c EB |
2187 | msg.address_lo = |
2188 | HT_IRQ_LOW_BASE | | |
8b955b0d | 2189 | HT_IRQ_LOW_DEST_ID(dest) | |
dfbffdd8 | 2190 | HT_IRQ_LOW_VECTOR(cfg->vector) | |
8b955b0d EB |
2191 | ((INT_DEST_MODE == 0) ? |
2192 | HT_IRQ_LOW_DM_PHYSICAL : | |
2193 | HT_IRQ_LOW_DM_LOGICAL) | | |
2194 | HT_IRQ_LOW_RQEOI_EDGE | | |
2195 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
2196 | HT_IRQ_LOW_MT_FIXED : | |
ec68307c EB |
2197 | HT_IRQ_LOW_MT_ARBITRATED) | |
2198 | HT_IRQ_LOW_IRQ_MASKED; | |
8b955b0d | 2199 | |
ec68307c | 2200 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 2201 | |
a460e745 IM |
2202 | set_irq_chip_and_handler_name(irq, &ht_irq_chip, |
2203 | handle_edge_irq, "edge"); | |
8b955b0d | 2204 | } |
dfbffdd8 | 2205 | return err; |
8b955b0d EB |
2206 | } |
2207 | #endif /* CONFIG_HT_IRQ */ | |
2208 | ||
1da177e4 LT |
2209 | /* -------------------------------------------------------------------------- |
2210 | ACPI-based IOAPIC Configuration | |
2211 | -------------------------------------------------------------------------- */ | |
2212 | ||
888ba6c6 | 2213 | #ifdef CONFIG_ACPI |
1da177e4 LT |
2214 | |
2215 | #define IO_APIC_MAX_ID 0xFE | |
2216 | ||
1da177e4 LT |
2217 | int __init io_apic_get_redir_entries (int ioapic) |
2218 | { | |
2219 | union IO_APIC_reg_01 reg_01; | |
2220 | unsigned long flags; | |
2221 | ||
2222 | spin_lock_irqsave(&ioapic_lock, flags); | |
2223 | reg_01.raw = io_apic_read(ioapic, 1); | |
2224 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2225 | ||
2226 | return reg_01.bits.entries; | |
2227 | } | |
2228 | ||
2229 | ||
50eca3eb | 2230 | int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity) |
1da177e4 | 2231 | { |
1da177e4 LT |
2232 | if (!IO_APIC_IRQ(irq)) { |
2233 | apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", | |
2234 | ioapic); | |
2235 | return -EINVAL; | |
2236 | } | |
2237 | ||
550f2299 EB |
2238 | /* |
2239 | * IRQs < 16 are already in the irq_2_pin[] map | |
2240 | */ | |
2241 | if (irq >= 16) | |
2242 | add_pin_to_irq(irq, ioapic, pin); | |
2243 | ||
a8c8a367 | 2244 | setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity); |
1da177e4 LT |
2245 | |
2246 | return 0; | |
2247 | } | |
2248 | ||
1da177e4 | 2249 | |
61fd47e0 SL |
2250 | int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity) |
2251 | { | |
2252 | int i; | |
2253 | ||
2254 | if (skip_ioapic_setup) | |
2255 | return -1; | |
2256 | ||
2257 | for (i = 0; i < mp_irq_entries; i++) | |
2258 | if (mp_irqs[i].mpc_irqtype == mp_INT && | |
2259 | mp_irqs[i].mpc_srcbusirq == bus_irq) | |
2260 | break; | |
2261 | if (i >= mp_irq_entries) | |
2262 | return -1; | |
2263 | ||
2264 | *trigger = irq_trigger(i); | |
2265 | *polarity = irq_polarity(i); | |
2266 | return 0; | |
2267 | } | |
2268 | ||
2269 | #endif /* CONFIG_ACPI */ | |
1da177e4 LT |
2270 | |
2271 | /* | |
2272 | * This function currently is only a helper for the i386 smp boot process where | |
2273 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
2274 | * so mask in all cases should simply be TARGET_CPUS | |
2275 | */ | |
54d5d424 | 2276 | #ifdef CONFIG_SMP |
1da177e4 LT |
2277 | void __init setup_ioapic_dest(void) |
2278 | { | |
2279 | int pin, ioapic, irq, irq_entry; | |
2280 | ||
2281 | if (skip_ioapic_setup == 1) | |
2282 | return; | |
2283 | ||
2284 | for (ioapic = 0; ioapic < nr_ioapics; ioapic++) { | |
2285 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { | |
2286 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); | |
2287 | if (irq_entry == -1) | |
2288 | continue; | |
2289 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
ad892f5e YL |
2290 | |
2291 | /* setup_IO_APIC_irqs could fail to get vector for some device | |
2292 | * when you have too many devices, because at that time only boot | |
2293 | * cpu is online. | |
2294 | */ | |
13a79503 | 2295 | if (!irq_cfg[irq].vector) |
a8c8a367 EB |
2296 | setup_IO_APIC_irq(ioapic, pin, irq, |
2297 | irq_trigger(irq_entry), | |
2298 | irq_polarity(irq_entry)); | |
ad892f5e YL |
2299 | else |
2300 | set_ioapic_affinity_irq(irq, TARGET_CPUS); | |
1da177e4 LT |
2301 | } |
2302 | ||
2303 | } | |
2304 | } | |
54d5d424 | 2305 | #endif |
61fd47e0 | 2306 | |
3e35a0e5 TG |
2307 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
2308 | ||
2309 | static struct resource *ioapic_resources; | |
2310 | ||
2311 | static struct resource * __init ioapic_setup_resources(void) | |
2312 | { | |
2313 | unsigned long n; | |
2314 | struct resource *res; | |
2315 | char *mem; | |
2316 | int i; | |
2317 | ||
2318 | if (nr_ioapics <= 0) | |
2319 | return NULL; | |
2320 | ||
2321 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); | |
2322 | n *= nr_ioapics; | |
2323 | ||
2324 | mem = alloc_bootmem(n); | |
2325 | res = (void *)mem; | |
2326 | ||
2327 | if (mem != NULL) { | |
2328 | memset(mem, 0, n); | |
2329 | mem += sizeof(struct resource) * nr_ioapics; | |
2330 | ||
2331 | for (i = 0; i < nr_ioapics; i++) { | |
2332 | res[i].name = mem; | |
2333 | res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
2334 | sprintf(mem, "IOAPIC %u", i); | |
2335 | mem += IOAPIC_RESOURCE_NAME_SIZE; | |
2336 | } | |
2337 | } | |
2338 | ||
2339 | ioapic_resources = res; | |
2340 | ||
2341 | return res; | |
2342 | } | |
2343 | ||
2344 | void __init ioapic_init_mappings(void) | |
2345 | { | |
2346 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
2347 | struct resource *ioapic_res; | |
2348 | int i; | |
2349 | ||
2350 | ioapic_res = ioapic_setup_resources(); | |
2351 | for (i = 0; i < nr_ioapics; i++) { | |
2352 | if (smp_found_config) { | |
2353 | ioapic_phys = mp_ioapics[i].mpc_apicaddr; | |
2354 | } else { | |
2355 | ioapic_phys = (unsigned long) | |
2356 | alloc_bootmem_pages(PAGE_SIZE); | |
2357 | ioapic_phys = __pa(ioapic_phys); | |
2358 | } | |
2359 | set_fixmap_nocache(idx, ioapic_phys); | |
2360 | apic_printk(APIC_VERBOSE, | |
2361 | "mapped IOAPIC to %016lx (%016lx)\n", | |
2362 | __fix_to_virt(idx), ioapic_phys); | |
2363 | idx++; | |
2364 | ||
2365 | if (ioapic_res != NULL) { | |
2366 | ioapic_res->start = ioapic_phys; | |
2367 | ioapic_res->end = ioapic_phys + (4 * 1024) - 1; | |
2368 | ioapic_res++; | |
2369 | } | |
2370 | } | |
2371 | } | |
2372 | ||
2373 | static int __init ioapic_insert_resources(void) | |
2374 | { | |
2375 | int i; | |
2376 | struct resource *r = ioapic_resources; | |
2377 | ||
2378 | if (!r) { | |
2379 | printk(KERN_ERR | |
2380 | "IO APIC resources could be not be allocated.\n"); | |
2381 | return -1; | |
2382 | } | |
2383 | ||
2384 | for (i = 0; i < nr_ioapics; i++) { | |
2385 | insert_resource(&iomem_resource, r); | |
2386 | r++; | |
2387 | } | |
2388 | ||
2389 | return 0; | |
2390 | } | |
2391 | ||
2392 | /* Insert the IO APIC resources after PCI initialization has occured to handle | |
2393 | * IO APICS that are mapped in on a BAR in PCI space. */ | |
2394 | late_initcall(ioapic_insert_resources); | |
2395 |