Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
4 | * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo | |
5 | * | |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
589e367f | 28 | #include <linux/pci.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/acpi.h> | |
31 | #include <linux/sysdev.h> | |
3b7d1921 | 32 | #include <linux/msi.h> |
95d77884 | 33 | #include <linux/htirq.h> |
3460a6d9 | 34 | #include <linux/dmar.h> |
1d16b53e | 35 | #include <linux/jiffies.h> |
ab688059 AK |
36 | #ifdef CONFIG_ACPI |
37 | #include <acpi/acpi_bus.h> | |
38 | #endif | |
3e35a0e5 | 39 | #include <linux/bootmem.h> |
89027d35 | 40 | #include <linux/dmar.h> |
1da177e4 | 41 | |
61014292 | 42 | #include <asm/idle.h> |
1da177e4 LT |
43 | #include <asm/io.h> |
44 | #include <asm/smp.h> | |
45 | #include <asm/desc.h> | |
46 | #include <asm/proto.h> | |
8d916406 | 47 | #include <asm/acpi.h> |
ca8642f6 | 48 | #include <asm/dma.h> |
17c44697 | 49 | #include <asm/i8259.h> |
3e4ff115 | 50 | #include <asm/nmi.h> |
589e367f | 51 | #include <asm/msidef.h> |
8b955b0d | 52 | #include <asm/hypertransport.h> |
89027d35 | 53 | #include <asm/irq_remapping.h> |
1da177e4 | 54 | |
5af5573e | 55 | #include <mach_ipi.h> |
dd46e3ca | 56 | #include <mach_apic.h> |
5af5573e | 57 | |
32f71aff MR |
58 | #define __apicdebuginit(type) static type __init |
59 | ||
3ac2de48 | 60 | struct irq_cfg; |
e5a53714 | 61 | struct irq_pin_list; |
13a79503 | 62 | struct irq_cfg { |
3ac2de48 YL |
63 | unsigned int irq; |
64 | struct irq_cfg *next; | |
e5a53714 | 65 | struct irq_pin_list *irq_2_pin; |
13a79503 | 66 | cpumask_t domain; |
61014292 EB |
67 | cpumask_t old_domain; |
68 | unsigned move_cleanup_count; | |
13a79503 | 69 | u8 vector; |
61014292 | 70 | u8 move_in_progress : 1; |
13a79503 EB |
71 | }; |
72 | ||
73 | /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */ | |
301e6190 | 74 | static struct irq_cfg irq_cfg_legacy[] __initdata = { |
3ac2de48 YL |
75 | [0] = { .irq = 0, .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, }, |
76 | [1] = { .irq = 1, .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, }, | |
77 | [2] = { .irq = 2, .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, }, | |
78 | [3] = { .irq = 3, .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, }, | |
79 | [4] = { .irq = 4, .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, }, | |
80 | [5] = { .irq = 5, .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, }, | |
81 | [6] = { .irq = 6, .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, }, | |
82 | [7] = { .irq = 7, .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, }, | |
83 | [8] = { .irq = 8, .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, }, | |
84 | [9] = { .irq = 9, .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, }, | |
85 | [10] = { .irq = 10, .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, }, | |
86 | [11] = { .irq = 11, .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, }, | |
87 | [12] = { .irq = 12, .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, }, | |
88 | [13] = { .irq = 13, .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, }, | |
89 | [14] = { .irq = 14, .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, }, | |
90 | [15] = { .irq = 15, .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, }, | |
13a79503 EB |
91 | }; |
92 | ||
3ac2de48 YL |
93 | static struct irq_cfg irq_cfg_init = { .irq = -1U, }; |
94 | /* need to be biger than size of irq_cfg_legacy */ | |
95 | static int nr_irq_cfg = 32; | |
96 | ||
97 | static int __init parse_nr_irq_cfg(char *arg) | |
98 | { | |
99 | if (arg) { | |
100 | nr_irq_cfg = simple_strtoul(arg, NULL, 0); | |
101 | if (nr_irq_cfg < 32) | |
102 | nr_irq_cfg = 32; | |
103 | } | |
104 | return 0; | |
105 | } | |
106 | ||
107 | early_param("nr_irq_cfg", parse_nr_irq_cfg); | |
108 | ||
109 | static void init_one_irq_cfg(struct irq_cfg *cfg) | |
110 | { | |
111 | memcpy(cfg, &irq_cfg_init, sizeof(struct irq_cfg)); | |
112 | } | |
301e6190 YL |
113 | |
114 | static void __init init_work(void *data) | |
115 | { | |
116 | struct dyn_array *da = data; | |
3ac2de48 YL |
117 | struct irq_cfg *cfg; |
118 | int i; | |
301e6190 | 119 | |
3ac2de48 YL |
120 | cfg = *da->name; |
121 | ||
122 | memcpy(cfg, irq_cfg_legacy, sizeof(irq_cfg_legacy)); | |
123 | ||
124 | i = sizeof(irq_cfg_legacy)/sizeof(irq_cfg_legacy[0]); | |
125 | for (; i < *da->nr; i++) | |
126 | init_one_irq_cfg(&cfg[i]); | |
127 | ||
128 | for (i = 1; i < *da->nr; i++) | |
129 | cfg[i-1].next = &cfg[i]; | |
301e6190 YL |
130 | } |
131 | ||
46b8214d YL |
132 | #define for_each_irq_cfg(cfg) \ |
133 | for (cfg = irq_cfgx; cfg && cfg->irq != -1U; cfg = cfg->next) | |
134 | ||
3ac2de48 YL |
135 | static struct irq_cfg *irq_cfgx; |
136 | DEFINE_DYN_ARRAY(irq_cfgx, sizeof(struct irq_cfg), nr_irq_cfg, PAGE_SIZE, init_work); | |
137 | ||
138 | static struct irq_cfg *irq_cfg(unsigned int irq) | |
139 | { | |
140 | struct irq_cfg *cfg; | |
141 | ||
142 | BUG_ON(irq == -1U); | |
143 | ||
144 | cfg = &irq_cfgx[0]; | |
145 | while (cfg) { | |
146 | if (cfg->irq == irq) | |
147 | return cfg; | |
148 | ||
149 | if (cfg->irq == -1U) | |
150 | return NULL; | |
151 | ||
152 | cfg = cfg->next; | |
153 | } | |
154 | ||
155 | return NULL; | |
156 | } | |
157 | ||
158 | static struct irq_cfg *irq_cfg_alloc(unsigned int irq) | |
159 | { | |
160 | struct irq_cfg *cfg, *cfg_pri; | |
161 | int i; | |
162 | int count = 0; | |
163 | ||
164 | BUG_ON(irq == -1U); | |
165 | ||
166 | cfg_pri = cfg = &irq_cfgx[0]; | |
167 | while (cfg) { | |
168 | if (cfg->irq == irq) | |
169 | return cfg; | |
170 | ||
171 | if (cfg->irq == -1U) { | |
172 | cfg->irq = irq; | |
173 | return cfg; | |
174 | } | |
175 | cfg_pri = cfg; | |
176 | cfg = cfg->next; | |
177 | count++; | |
178 | } | |
179 | ||
180 | /* | |
181 | * we run out of pre-allocate ones, allocate more | |
182 | */ | |
183 | printk(KERN_DEBUG "try to get more irq_cfg %d\n", nr_irq_cfg); | |
184 | ||
185 | if (after_bootmem) | |
186 | cfg = kzalloc(sizeof(struct irq_cfg)*nr_irq_cfg, GFP_ATOMIC); | |
187 | else | |
188 | cfg = __alloc_bootmem_nopanic(sizeof(struct irq_cfg)*nr_irq_cfg, PAGE_SIZE, 0); | |
189 | ||
190 | if (!cfg) | |
191 | panic("please boot with nr_irq_cfg= %d\n", count * 2); | |
192 | ||
193 | for (i = 0; i < nr_irq_cfg; i++) | |
194 | init_one_irq_cfg(&cfg[i]); | |
195 | ||
196 | for (i = 1; i < nr_irq_cfg; i++) | |
197 | cfg[i-1].next = &cfg[i]; | |
198 | ||
199 | cfg->irq = irq; | |
200 | cfg_pri->next = cfg; | |
201 | ||
202 | return cfg; | |
203 | } | |
301e6190 | 204 | |
dfbffdd8 | 205 | static int assign_irq_vector(int irq, cpumask_t mask); |
04b9267b | 206 | |
305b92a2 AM |
207 | int first_system_vector = 0xfe; |
208 | ||
209 | char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE}; | |
210 | ||
1da177e4 LT |
211 | int sis_apic_bug; /* not actually supported, dummy for compile */ |
212 | ||
14d98cad AK |
213 | static int no_timer_check; |
214 | ||
fea5f1e1 LT |
215 | static int disable_timer_pin_1 __initdata; |
216 | ||
35542c5e | 217 | int timer_through_8259 __initdata; |
fea5f1e1 | 218 | |
1008fddc EB |
219 | /* Where if anywhere is the i8259 connect in external int mode */ |
220 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
221 | ||
1da177e4 | 222 | static DEFINE_SPINLOCK(ioapic_lock); |
d388e5fd | 223 | static DEFINE_SPINLOCK(vector_lock); |
1da177e4 LT |
224 | |
225 | /* | |
226 | * # of IRQ routing registers | |
227 | */ | |
228 | int nr_ioapic_registers[MAX_IO_APICS]; | |
229 | ||
4dc2f96c SS |
230 | /* I/O APIC RTE contents at the OS boot up */ |
231 | struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS]; | |
232 | ||
9c7408f3 | 233 | /* I/O APIC entries */ |
ec2cd0a2 | 234 | struct mp_config_ioapic mp_ioapics[MAX_IO_APICS]; |
9c7408f3 AS |
235 | int nr_ioapics; |
236 | ||
350bae1d | 237 | /* MP IRQ source entries */ |
2fddb6e2 | 238 | struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
350bae1d AS |
239 | |
240 | /* # of MP IRQ source entries */ | |
241 | int mp_irq_entries; | |
242 | ||
8732fc4b AS |
243 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); |
244 | ||
1da177e4 LT |
245 | /* |
246 | * Rough estimation of how many shared IRQs there are, can | |
247 | * be changed anytime. | |
248 | */ | |
1da177e4 | 249 | |
301e6190 YL |
250 | int pin_map_size; |
251 | ||
1da177e4 LT |
252 | /* |
253 | * This is performance-critical, we want to do it O(1) | |
254 | * | |
255 | * the indexing order of this array favors 1:1 mappings | |
256 | * between pins and IRQs. | |
257 | */ | |
258 | ||
e5a53714 YL |
259 | struct irq_pin_list { |
260 | int apic, pin; | |
261 | struct irq_pin_list *next; | |
262 | }; | |
263 | ||
264 | static struct irq_pin_list *irq_2_pin_head; | |
265 | /* fill one page ? */ | |
266 | static int nr_irq_2_pin = 0x100; | |
267 | static struct irq_pin_list *irq_2_pin_ptr; | |
268 | static void __init irq_2_pin_init_work(void *data) | |
269 | { | |
270 | struct dyn_array *da = data; | |
271 | struct irq_pin_list *pin; | |
272 | int i; | |
273 | ||
274 | pin = *da->name; | |
275 | ||
276 | for (i = 1; i < *da->nr; i++) | |
277 | pin[i-1].next = &pin[i]; | |
278 | ||
279 | irq_2_pin_ptr = &pin[0]; | |
280 | } | |
281 | DEFINE_DYN_ARRAY(irq_2_pin_head, sizeof(struct irq_pin_list), nr_irq_2_pin, PAGE_SIZE, irq_2_pin_init_work); | |
282 | ||
283 | static struct irq_pin_list *get_one_free_irq_2_pin(void) | |
284 | { | |
285 | struct irq_pin_list *pin; | |
286 | int i; | |
287 | ||
288 | pin = irq_2_pin_ptr; | |
289 | ||
290 | if (pin) { | |
291 | irq_2_pin_ptr = pin->next; | |
292 | pin->next = NULL; | |
293 | return pin; | |
294 | } | |
295 | ||
296 | /* | |
297 | * we run out of pre-allocate ones, allocate more | |
298 | */ | |
299 | printk(KERN_DEBUG "try to get more irq_2_pin %d\n", nr_irq_2_pin); | |
300 | ||
301 | if (after_bootmem) | |
302 | pin = kzalloc(sizeof(struct irq_pin_list)*nr_irq_2_pin, | |
303 | GFP_ATOMIC); | |
304 | else | |
305 | pin = __alloc_bootmem_nopanic(sizeof(struct irq_pin_list) * | |
306 | nr_irq_2_pin, PAGE_SIZE, 0); | |
307 | ||
308 | if (!pin) | |
309 | panic("can not get more irq_2_pin\n"); | |
301e6190 | 310 | |
e5a53714 YL |
311 | for (i = 1; i < nr_irq_2_pin; i++) |
312 | pin[i-1].next = &pin[i]; | |
301e6190 | 313 | |
e5a53714 YL |
314 | irq_2_pin_ptr = pin->next; |
315 | pin->next = NULL; | |
316 | ||
317 | return pin; | |
318 | } | |
1da177e4 | 319 | |
6c0ffb9d LT |
320 | struct io_apic { |
321 | unsigned int index; | |
322 | unsigned int unused[3]; | |
323 | unsigned int data; | |
324 | }; | |
325 | ||
326 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
327 | { | |
328 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
ec2cd0a2 | 329 | + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK); |
6c0ffb9d LT |
330 | } |
331 | ||
332 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) | |
333 | { | |
334 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
335 | writel(reg, &io_apic->index); | |
336 | return readl(&io_apic->data); | |
337 | } | |
338 | ||
339 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) | |
340 | { | |
341 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
342 | writel(reg, &io_apic->index); | |
343 | writel(value, &io_apic->data); | |
344 | } | |
345 | ||
346 | /* | |
347 | * Re-write a value: to be used for read-modify-write | |
348 | * cycles where the read already set up the index register. | |
349 | */ | |
350 | static inline void io_apic_modify(unsigned int apic, unsigned int value) | |
351 | { | |
352 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
353 | writel(value, &io_apic->data); | |
354 | } | |
355 | ||
9d25cb08 | 356 | static bool io_apic_level_ack_pending(unsigned int irq) |
ef3e28c5 EB |
357 | { |
358 | struct irq_pin_list *entry; | |
359 | unsigned long flags; | |
e5a53714 | 360 | struct irq_cfg *cfg = irq_cfg(irq); |
ef3e28c5 EB |
361 | |
362 | spin_lock_irqsave(&ioapic_lock, flags); | |
e5a53714 | 363 | entry = cfg->irq_2_pin; |
ef3e28c5 EB |
364 | for (;;) { |
365 | unsigned int reg; | |
366 | int pin; | |
367 | ||
e5a53714 | 368 | if (!entry) |
ef3e28c5 | 369 | break; |
e5a53714 | 370 | pin = entry->pin; |
ef3e28c5 EB |
371 | reg = io_apic_read(entry->apic, 0x10 + pin*2); |
372 | /* Is the remote IRR bit set? */ | |
46b3b4ef | 373 | if (reg & IO_APIC_REDIR_REMOTE_IRR) { |
9d25cb08 AM |
374 | spin_unlock_irqrestore(&ioapic_lock, flags); |
375 | return true; | |
376 | } | |
ef3e28c5 EB |
377 | if (!entry->next) |
378 | break; | |
e5a53714 | 379 | entry = entry->next; |
ef3e28c5 EB |
380 | } |
381 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
9d25cb08 AM |
382 | |
383 | return false; | |
ef3e28c5 EB |
384 | } |
385 | ||
6c0ffb9d LT |
386 | /* |
387 | * Synchronize the IO-APIC and the CPU by doing | |
388 | * a dummy read from the IO-APIC | |
389 | */ | |
390 | static inline void io_apic_sync(unsigned int apic) | |
391 | { | |
392 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
393 | readl(&io_apic->data); | |
394 | } | |
395 | ||
54d5d424 AR |
396 | #define __DO_ACTION(R, ACTION, FINAL) \ |
397 | \ | |
398 | { \ | |
399 | int pin; \ | |
e5a53714 YL |
400 | struct irq_cfg *cfg; \ |
401 | struct irq_pin_list *entry; \ | |
54d5d424 | 402 | \ |
0799e432 | 403 | BUG_ON(irq >= nr_irqs); \ |
e5a53714 YL |
404 | cfg = irq_cfg(irq); \ |
405 | entry = cfg->irq_2_pin; \ | |
54d5d424 AR |
406 | for (;;) { \ |
407 | unsigned int reg; \ | |
e5a53714 | 408 | if (!entry) \ |
54d5d424 | 409 | break; \ |
e5a53714 | 410 | pin = entry->pin; \ |
54d5d424 AR |
411 | reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \ |
412 | reg ACTION; \ | |
413 | io_apic_modify(entry->apic, reg); \ | |
f45bcd70 | 414 | FINAL; \ |
54d5d424 AR |
415 | if (!entry->next) \ |
416 | break; \ | |
e5a53714 | 417 | entry = entry->next; \ |
54d5d424 | 418 | } \ |
54d5d424 AR |
419 | } |
420 | ||
eea0e11c AK |
421 | union entry_union { |
422 | struct { u32 w1, w2; }; | |
423 | struct IO_APIC_route_entry entry; | |
424 | }; | |
425 | ||
426 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) | |
427 | { | |
428 | union entry_union eu; | |
429 | unsigned long flags; | |
430 | spin_lock_irqsave(&ioapic_lock, flags); | |
431 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); | |
432 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
433 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
434 | return eu.entry; | |
435 | } | |
436 | ||
48797ebd LT |
437 | /* |
438 | * When we write a new IO APIC routing entry, we need to write the high | |
439 | * word first! If the mask bit in the low word is clear, we will enable | |
440 | * the interrupt, and we need to make sure the entry is fully populated | |
441 | * before that happens. | |
442 | */ | |
516d2836 AK |
443 | static void |
444 | __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
eea0e11c | 445 | { |
eea0e11c AK |
446 | union entry_union eu; |
447 | eu.entry = e; | |
48797ebd LT |
448 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
449 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
516d2836 AK |
450 | } |
451 | ||
452 | static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
453 | { | |
454 | unsigned long flags; | |
455 | spin_lock_irqsave(&ioapic_lock, flags); | |
456 | __ioapic_write_entry(apic, pin, e); | |
48797ebd LT |
457 | spin_unlock_irqrestore(&ioapic_lock, flags); |
458 | } | |
459 | ||
460 | /* | |
461 | * When we mask an IO APIC routing entry, we need to write the low | |
462 | * word first, in order to set the mask bit before we change the | |
463 | * high bits! | |
464 | */ | |
465 | static void ioapic_mask_entry(int apic, int pin) | |
466 | { | |
467 | unsigned long flags; | |
468 | union entry_union eu = { .entry.mask = 1 }; | |
469 | ||
eea0e11c AK |
470 | spin_lock_irqsave(&ioapic_lock, flags); |
471 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
472 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
473 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
474 | } | |
475 | ||
54d5d424 | 476 | #ifdef CONFIG_SMP |
550f2299 EB |
477 | static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector) |
478 | { | |
479 | int apic, pin; | |
e5a53714 YL |
480 | struct irq_cfg *cfg; |
481 | struct irq_pin_list *entry; | |
550f2299 | 482 | |
0799e432 | 483 | BUG_ON(irq >= nr_irqs); |
e5a53714 YL |
484 | cfg = irq_cfg(irq); |
485 | entry = cfg->irq_2_pin; | |
550f2299 EB |
486 | for (;;) { |
487 | unsigned int reg; | |
e5a53714 YL |
488 | |
489 | if (!entry) | |
490 | break; | |
491 | ||
550f2299 EB |
492 | apic = entry->apic; |
493 | pin = entry->pin; | |
89027d35 SS |
494 | /* |
495 | * With interrupt-remapping, destination information comes | |
496 | * from interrupt-remapping table entry. | |
497 | */ | |
498 | if (!irq_remapped(irq)) | |
499 | io_apic_write(apic, 0x11 + pin*2, dest); | |
550f2299 | 500 | reg = io_apic_read(apic, 0x10 + pin*2); |
46b3b4ef | 501 | reg &= ~IO_APIC_REDIR_VECTOR_MASK; |
550f2299 EB |
502 | reg |= vector; |
503 | io_apic_modify(apic, reg); | |
504 | if (!entry->next) | |
505 | break; | |
e5a53714 | 506 | entry = entry->next; |
550f2299 EB |
507 | } |
508 | } | |
509 | ||
54d5d424 AR |
510 | static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask) |
511 | { | |
3ac2de48 | 512 | struct irq_cfg *cfg = irq_cfg(irq); |
54d5d424 AR |
513 | unsigned long flags; |
514 | unsigned int dest; | |
515 | cpumask_t tmp; | |
08678b08 | 516 | struct irq_desc *desc; |
54d5d424 AR |
517 | |
518 | cpus_and(tmp, mask, cpu_online_map); | |
519 | if (cpus_empty(tmp)) | |
5ff5115e | 520 | return; |
54d5d424 | 521 | |
dfbffdd8 | 522 | if (assign_irq_vector(irq, mask)) |
550f2299 EB |
523 | return; |
524 | ||
dfbffdd8 | 525 | cpus_and(tmp, cfg->domain, mask); |
550f2299 | 526 | dest = cpu_mask_to_apicid(tmp); |
54d5d424 AR |
527 | |
528 | /* | |
529 | * Only the high 8 bits are valid. | |
530 | */ | |
531 | dest = SET_APIC_LOGICAL_ID(dest); | |
532 | ||
08678b08 | 533 | desc = irq_to_desc(irq); |
54d5d424 | 534 | spin_lock_irqsave(&ioapic_lock, flags); |
dfbffdd8 | 535 | __target_IO_APIC_irq(irq, dest, cfg->vector); |
08678b08 | 536 | desc->affinity = mask; |
54d5d424 AR |
537 | spin_unlock_irqrestore(&ioapic_lock, flags); |
538 | } | |
539 | #endif | |
540 | ||
1da177e4 LT |
541 | /* |
542 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
543 | * shared ISA-space IRQs, so we have to support them. We are super | |
544 | * fast in the common case, and fast for shared ISA-space IRQs. | |
545 | */ | |
301e6190 | 546 | int first_free_entry; |
1da177e4 LT |
547 | static void add_pin_to_irq(unsigned int irq, int apic, int pin) |
548 | { | |
e5a53714 YL |
549 | struct irq_cfg *cfg; |
550 | struct irq_pin_list *entry; | |
1da177e4 | 551 | |
0799e432 | 552 | BUG_ON(irq >= nr_irqs); |
e5a53714 YL |
553 | /* first time to refer irq_cfg, so with new */ |
554 | cfg = irq_cfg_alloc(irq); | |
555 | entry = cfg->irq_2_pin; | |
556 | if (!entry) { | |
557 | entry = get_one_free_irq_2_pin(); | |
558 | cfg->irq_2_pin = entry; | |
559 | entry->apic = apic; | |
560 | entry->pin = pin; | |
561 | printk(KERN_DEBUG " 0 add_pin_to_irq: irq %d --> apic %d pin %d\n", irq, apic, pin); | |
562 | return; | |
563 | } | |
3ac2de48 | 564 | |
e5a53714 YL |
565 | while (entry->next) { |
566 | /* not again, please */ | |
567 | if (entry->apic == apic && entry->pin == pin) | |
568 | return; | |
1da177e4 | 569 | |
e5a53714 | 570 | entry = entry->next; |
1da177e4 | 571 | } |
e5a53714 YL |
572 | |
573 | entry->next = get_one_free_irq_2_pin(); | |
574 | entry = entry->next; | |
1da177e4 LT |
575 | entry->apic = apic; |
576 | entry->pin = pin; | |
e5a53714 | 577 | printk(KERN_DEBUG " x add_pin_to_irq: irq %d --> apic %d pin %d\n", irq, apic, pin); |
1da177e4 LT |
578 | } |
579 | ||
0b9f4f49 MR |
580 | /* |
581 | * Reroute an IRQ to a different pin. | |
582 | */ | |
583 | static void __init replace_pin_at_irq(unsigned int irq, | |
584 | int oldapic, int oldpin, | |
585 | int newapic, int newpin) | |
586 | { | |
e5a53714 YL |
587 | struct irq_cfg *cfg = irq_cfg(irq); |
588 | struct irq_pin_list *entry = cfg->irq_2_pin; | |
589 | int replaced = 0; | |
0b9f4f49 | 590 | |
e5a53714 | 591 | while (entry) { |
0b9f4f49 MR |
592 | if (entry->apic == oldapic && entry->pin == oldpin) { |
593 | entry->apic = newapic; | |
594 | entry->pin = newpin; | |
e5a53714 YL |
595 | replaced = 1; |
596 | /* every one is different, right? */ | |
0b9f4f49 | 597 | break; |
e5a53714 YL |
598 | } |
599 | entry = entry->next; | |
0b9f4f49 | 600 | } |
e5a53714 YL |
601 | |
602 | /* why? call replace before add? */ | |
603 | if (!replaced) | |
604 | add_pin_to_irq(irq, newapic, newpin); | |
0b9f4f49 MR |
605 | } |
606 | ||
1da177e4 LT |
607 | |
608 | #define DO_ACTION(name,R,ACTION, FINAL) \ | |
609 | \ | |
610 | static void name##_IO_APIC_irq (unsigned int irq) \ | |
611 | __DO_ACTION(R, ACTION, FINAL) | |
612 | ||
46b3b4ef CG |
613 | /* mask = 1 */ |
614 | DO_ACTION(__mask, 0, |= IO_APIC_REDIR_MASKED, io_apic_sync(entry->apic)) | |
615 | ||
616 | /* mask = 0 */ | |
617 | DO_ACTION(__unmask, 0, &= ~IO_APIC_REDIR_MASKED, ) | |
1da177e4 LT |
618 | |
619 | static void mask_IO_APIC_irq (unsigned int irq) | |
620 | { | |
621 | unsigned long flags; | |
622 | ||
623 | spin_lock_irqsave(&ioapic_lock, flags); | |
624 | __mask_IO_APIC_irq(irq); | |
625 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
626 | } | |
627 | ||
628 | static void unmask_IO_APIC_irq (unsigned int irq) | |
629 | { | |
630 | unsigned long flags; | |
631 | ||
632 | spin_lock_irqsave(&ioapic_lock, flags); | |
633 | __unmask_IO_APIC_irq(irq); | |
634 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
635 | } | |
636 | ||
637 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) | |
638 | { | |
639 | struct IO_APIC_route_entry entry; | |
1da177e4 LT |
640 | |
641 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ | |
eea0e11c | 642 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
643 | if (entry.delivery_mode == dest_SMI) |
644 | return; | |
645 | /* | |
646 | * Disable it in the IO-APIC irq-routing table: | |
647 | */ | |
48797ebd | 648 | ioapic_mask_entry(apic, pin); |
1da177e4 LT |
649 | } |
650 | ||
651 | static void clear_IO_APIC (void) | |
652 | { | |
653 | int apic, pin; | |
654 | ||
655 | for (apic = 0; apic < nr_ioapics; apic++) | |
656 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) | |
657 | clear_IO_APIC_pin(apic, pin); | |
658 | } | |
659 | ||
4dc2f96c SS |
660 | /* |
661 | * Saves and masks all the unmasked IO-APIC RTE's | |
662 | */ | |
663 | int save_mask_IO_APIC_setup(void) | |
664 | { | |
665 | union IO_APIC_reg_01 reg_01; | |
666 | unsigned long flags; | |
667 | int apic, pin; | |
668 | ||
669 | /* | |
670 | * The number of IO-APIC IRQ registers (== #pins): | |
671 | */ | |
672 | for (apic = 0; apic < nr_ioapics; apic++) { | |
673 | spin_lock_irqsave(&ioapic_lock, flags); | |
674 | reg_01.raw = io_apic_read(apic, 1); | |
675 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
676 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; | |
677 | } | |
678 | ||
679 | for (apic = 0; apic < nr_ioapics; apic++) { | |
680 | early_ioapic_entries[apic] = | |
681 | kzalloc(sizeof(struct IO_APIC_route_entry) * | |
682 | nr_ioapic_registers[apic], GFP_KERNEL); | |
683 | if (!early_ioapic_entries[apic]) | |
684 | return -ENOMEM; | |
685 | } | |
686 | ||
687 | for (apic = 0; apic < nr_ioapics; apic++) | |
688 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
689 | struct IO_APIC_route_entry entry; | |
690 | ||
691 | entry = early_ioapic_entries[apic][pin] = | |
692 | ioapic_read_entry(apic, pin); | |
693 | if (!entry.mask) { | |
694 | entry.mask = 1; | |
695 | ioapic_write_entry(apic, pin, entry); | |
696 | } | |
697 | } | |
698 | return 0; | |
699 | } | |
700 | ||
701 | void restore_IO_APIC_setup(void) | |
702 | { | |
703 | int apic, pin; | |
704 | ||
705 | for (apic = 0; apic < nr_ioapics; apic++) | |
706 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) | |
707 | ioapic_write_entry(apic, pin, | |
708 | early_ioapic_entries[apic][pin]); | |
709 | } | |
710 | ||
711 | void reinit_intr_remapped_IO_APIC(int intr_remapping) | |
712 | { | |
713 | /* | |
714 | * for now plain restore of previous settings. | |
715 | * TBD: In the case of OS enabling interrupt-remapping, | |
716 | * IO-APIC RTE's need to be setup to point to interrupt-remapping | |
717 | * table entries. for now, do a plain restore, and wait for | |
718 | * the setup_IO_APIC_irqs() to do proper initialization. | |
719 | */ | |
720 | restore_IO_APIC_setup(); | |
721 | } | |
722 | ||
1da177e4 LT |
723 | int skip_ioapic_setup; |
724 | int ioapic_force; | |
725 | ||
61ec7567 | 726 | static int __init parse_noapic(char *str) |
1da177e4 | 727 | { |
61ec7567 | 728 | disable_ioapic_setup(); |
2c8c0e6b | 729 | return 0; |
1da177e4 | 730 | } |
61ec7567 | 731 | early_param("noapic", parse_noapic); |
1da177e4 | 732 | |
fea5f1e1 LT |
733 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
734 | static int __init disable_timer_pin_setup(char *arg) | |
735 | { | |
736 | disable_timer_pin_1 = 1; | |
737 | return 1; | |
738 | } | |
739 | __setup("disable_timer_pin_1", disable_timer_pin_setup); | |
740 | ||
fea5f1e1 | 741 | |
1da177e4 LT |
742 | /* |
743 | * Find the IRQ entry number of a certain pin. | |
744 | */ | |
745 | static int find_irq_entry(int apic, int pin, int type) | |
746 | { | |
747 | int i; | |
748 | ||
749 | for (i = 0; i < mp_irq_entries; i++) | |
2fddb6e2 AS |
750 | if (mp_irqs[i].mp_irqtype == type && |
751 | (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid || | |
752 | mp_irqs[i].mp_dstapic == MP_APIC_ALL) && | |
753 | mp_irqs[i].mp_dstirq == pin) | |
1da177e4 LT |
754 | return i; |
755 | ||
756 | return -1; | |
757 | } | |
758 | ||
759 | /* | |
760 | * Find the pin to which IRQ[irq] (ISA) is connected | |
761 | */ | |
1008fddc | 762 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
763 | { |
764 | int i; | |
765 | ||
766 | for (i = 0; i < mp_irq_entries; i++) { | |
2fddb6e2 | 767 | int lbus = mp_irqs[i].mp_srcbus; |
1da177e4 | 768 | |
55f05ffa | 769 | if (test_bit(lbus, mp_bus_not_pci) && |
2fddb6e2 AS |
770 | (mp_irqs[i].mp_irqtype == type) && |
771 | (mp_irqs[i].mp_srcbusirq == irq)) | |
1da177e4 | 772 | |
2fddb6e2 | 773 | return mp_irqs[i].mp_dstirq; |
1da177e4 LT |
774 | } |
775 | return -1; | |
776 | } | |
777 | ||
1008fddc EB |
778 | static int __init find_isa_irq_apic(int irq, int type) |
779 | { | |
780 | int i; | |
781 | ||
782 | for (i = 0; i < mp_irq_entries; i++) { | |
2fddb6e2 | 783 | int lbus = mp_irqs[i].mp_srcbus; |
1008fddc | 784 | |
55f05ffa | 785 | if (test_bit(lbus, mp_bus_not_pci) && |
2fddb6e2 AS |
786 | (mp_irqs[i].mp_irqtype == type) && |
787 | (mp_irqs[i].mp_srcbusirq == irq)) | |
1008fddc EB |
788 | break; |
789 | } | |
790 | if (i < mp_irq_entries) { | |
791 | int apic; | |
792 | for(apic = 0; apic < nr_ioapics; apic++) { | |
2fddb6e2 | 793 | if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic) |
1008fddc EB |
794 | return apic; |
795 | } | |
796 | } | |
797 | ||
798 | return -1; | |
799 | } | |
800 | ||
1da177e4 LT |
801 | /* |
802 | * Find a specific PCI IRQ entry. | |
803 | * Not an __init, possibly needed by modules | |
804 | */ | |
805 | static int pin_2_irq(int idx, int apic, int pin); | |
806 | ||
807 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin) | |
808 | { | |
809 | int apic, i, best_guess = -1; | |
810 | ||
811 | apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", | |
812 | bus, slot, pin); | |
ce6444d3 | 813 | if (test_bit(bus, mp_bus_not_pci)) { |
1da177e4 LT |
814 | apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus); |
815 | return -1; | |
816 | } | |
817 | for (i = 0; i < mp_irq_entries; i++) { | |
2fddb6e2 | 818 | int lbus = mp_irqs[i].mp_srcbus; |
1da177e4 LT |
819 | |
820 | for (apic = 0; apic < nr_ioapics; apic++) | |
2fddb6e2 AS |
821 | if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic || |
822 | mp_irqs[i].mp_dstapic == MP_APIC_ALL) | |
1da177e4 LT |
823 | break; |
824 | ||
55f05ffa | 825 | if (!test_bit(lbus, mp_bus_not_pci) && |
2fddb6e2 | 826 | !mp_irqs[i].mp_irqtype && |
1da177e4 | 827 | (bus == lbus) && |
2fddb6e2 AS |
828 | (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) { |
829 | int irq = pin_2_irq(i,apic,mp_irqs[i].mp_dstirq); | |
1da177e4 LT |
830 | |
831 | if (!(apic || IO_APIC_IRQ(irq))) | |
832 | continue; | |
833 | ||
2fddb6e2 | 834 | if (pin == (mp_irqs[i].mp_srcbusirq & 3)) |
1da177e4 LT |
835 | return irq; |
836 | /* | |
837 | * Use the first all-but-pin matching entry as a | |
838 | * best-guess fuzzy result for broken mptables. | |
839 | */ | |
840 | if (best_guess < 0) | |
841 | best_guess = irq; | |
842 | } | |
843 | } | |
0799e432 | 844 | BUG_ON(best_guess >= nr_irqs); |
1da177e4 LT |
845 | return best_guess; |
846 | } | |
847 | ||
1da177e4 LT |
848 | /* ISA interrupts are always polarity zero edge triggered, |
849 | * when listed as conforming in the MP table. */ | |
850 | ||
851 | #define default_ISA_trigger(idx) (0) | |
852 | #define default_ISA_polarity(idx) (0) | |
853 | ||
854 | /* PCI interrupts are always polarity one level triggered, | |
855 | * when listed as conforming in the MP table. */ | |
856 | ||
857 | #define default_PCI_trigger(idx) (1) | |
858 | #define default_PCI_polarity(idx) (1) | |
859 | ||
61fd47e0 | 860 | static int MPBIOS_polarity(int idx) |
1da177e4 | 861 | { |
2fddb6e2 | 862 | int bus = mp_irqs[idx].mp_srcbus; |
1da177e4 LT |
863 | int polarity; |
864 | ||
865 | /* | |
866 | * Determine IRQ line polarity (high active or low active): | |
867 | */ | |
2fddb6e2 | 868 | switch (mp_irqs[idx].mp_irqflag & 3) |
1da177e4 LT |
869 | { |
870 | case 0: /* conforms, ie. bus-type dependent polarity */ | |
55f05ffa AK |
871 | if (test_bit(bus, mp_bus_not_pci)) |
872 | polarity = default_ISA_polarity(idx); | |
873 | else | |
874 | polarity = default_PCI_polarity(idx); | |
1da177e4 | 875 | break; |
1da177e4 LT |
876 | case 1: /* high active */ |
877 | { | |
878 | polarity = 0; | |
879 | break; | |
880 | } | |
881 | case 2: /* reserved */ | |
882 | { | |
883 | printk(KERN_WARNING "broken BIOS!!\n"); | |
884 | polarity = 1; | |
885 | break; | |
886 | } | |
887 | case 3: /* low active */ | |
888 | { | |
889 | polarity = 1; | |
890 | break; | |
891 | } | |
892 | default: /* invalid */ | |
893 | { | |
894 | printk(KERN_WARNING "broken BIOS!!\n"); | |
895 | polarity = 1; | |
896 | break; | |
897 | } | |
898 | } | |
899 | return polarity; | |
900 | } | |
901 | ||
902 | static int MPBIOS_trigger(int idx) | |
903 | { | |
2fddb6e2 | 904 | int bus = mp_irqs[idx].mp_srcbus; |
1da177e4 LT |
905 | int trigger; |
906 | ||
907 | /* | |
908 | * Determine IRQ trigger mode (edge or level sensitive): | |
909 | */ | |
2fddb6e2 | 910 | switch ((mp_irqs[idx].mp_irqflag>>2) & 3) |
1da177e4 LT |
911 | { |
912 | case 0: /* conforms, ie. bus-type dependent */ | |
55f05ffa AK |
913 | if (test_bit(bus, mp_bus_not_pci)) |
914 | trigger = default_ISA_trigger(idx); | |
915 | else | |
916 | trigger = default_PCI_trigger(idx); | |
1da177e4 | 917 | break; |
1da177e4 LT |
918 | case 1: /* edge */ |
919 | { | |
920 | trigger = 0; | |
921 | break; | |
922 | } | |
923 | case 2: /* reserved */ | |
924 | { | |
925 | printk(KERN_WARNING "broken BIOS!!\n"); | |
926 | trigger = 1; | |
927 | break; | |
928 | } | |
929 | case 3: /* level */ | |
930 | { | |
931 | trigger = 1; | |
932 | break; | |
933 | } | |
934 | default: /* invalid */ | |
935 | { | |
936 | printk(KERN_WARNING "broken BIOS!!\n"); | |
937 | trigger = 0; | |
938 | break; | |
939 | } | |
940 | } | |
941 | return trigger; | |
942 | } | |
943 | ||
944 | static inline int irq_polarity(int idx) | |
945 | { | |
946 | return MPBIOS_polarity(idx); | |
947 | } | |
948 | ||
949 | static inline int irq_trigger(int idx) | |
950 | { | |
951 | return MPBIOS_trigger(idx); | |
952 | } | |
953 | ||
954 | static int pin_2_irq(int idx, int apic, int pin) | |
955 | { | |
956 | int irq, i; | |
2fddb6e2 | 957 | int bus = mp_irqs[idx].mp_srcbus; |
1da177e4 LT |
958 | |
959 | /* | |
960 | * Debugging check, we are in big trouble if this message pops up! | |
961 | */ | |
2fddb6e2 | 962 | if (mp_irqs[idx].mp_dstirq != pin) |
1da177e4 LT |
963 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); |
964 | ||
55f05ffa | 965 | if (test_bit(bus, mp_bus_not_pci)) { |
2fddb6e2 | 966 | irq = mp_irqs[idx].mp_srcbusirq; |
55f05ffa AK |
967 | } else { |
968 | /* | |
969 | * PCI IRQs are mapped in order | |
970 | */ | |
971 | i = irq = 0; | |
972 | while (i < apic) | |
973 | irq += nr_ioapic_registers[i++]; | |
974 | irq += pin; | |
1da177e4 | 975 | } |
0799e432 | 976 | BUG_ON(irq >= nr_irqs); |
1da177e4 LT |
977 | return irq; |
978 | } | |
979 | ||
d388e5fd EB |
980 | void lock_vector_lock(void) |
981 | { | |
982 | /* Used to the online set of cpus does not change | |
983 | * during assign_irq_vector. | |
984 | */ | |
985 | spin_lock(&vector_lock); | |
986 | } | |
987 | ||
988 | void unlock_vector_lock(void) | |
989 | { | |
990 | spin_unlock(&vector_lock); | |
991 | } | |
992 | ||
dfbffdd8 | 993 | static int __assign_irq_vector(int irq, cpumask_t mask) |
1da177e4 | 994 | { |
550f2299 EB |
995 | /* |
996 | * NOTE! The local APIC isn't very good at handling | |
997 | * multiple interrupts at the same interrupt level. | |
998 | * As the interrupt level is determined by taking the | |
999 | * vector number and shifting that right by 4, we | |
1000 | * want to spread these out a bit so that they don't | |
1001 | * all fall in the same interrupt level. | |
1002 | * | |
1003 | * Also, we've got to be careful not to trash gate | |
1004 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
1005 | */ | |
d1752aa8 | 1006 | static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0; |
dfbffdd8 | 1007 | unsigned int old_vector; |
550f2299 | 1008 | int cpu; |
13a79503 | 1009 | struct irq_cfg *cfg; |
1da177e4 | 1010 | |
0799e432 | 1011 | BUG_ON((unsigned)irq >= nr_irqs); |
3ac2de48 | 1012 | cfg = irq_cfg(irq); |
0a1ad60d | 1013 | |
70a0a535 EB |
1014 | /* Only try and allocate irqs on cpus that are present */ |
1015 | cpus_and(mask, mask, cpu_online_map); | |
1016 | ||
61014292 EB |
1017 | if ((cfg->move_in_progress) || cfg->move_cleanup_count) |
1018 | return -EBUSY; | |
1019 | ||
dfbffdd8 EB |
1020 | old_vector = cfg->vector; |
1021 | if (old_vector) { | |
1022 | cpumask_t tmp; | |
1023 | cpus_and(tmp, cfg->domain, mask); | |
1024 | if (!cpus_empty(tmp)) | |
1025 | return 0; | |
0a1ad60d | 1026 | } |
550f2299 | 1027 | |
334ef7a7 | 1028 | for_each_cpu_mask_nr(cpu, mask) { |
70a0a535 | 1029 | cpumask_t domain, new_mask; |
61014292 | 1030 | int new_cpu; |
550f2299 | 1031 | int vector, offset; |
c7111c13 EB |
1032 | |
1033 | domain = vector_allocation_domain(cpu); | |
70a0a535 | 1034 | cpus_and(new_mask, domain, cpu_online_map); |
c7111c13 | 1035 | |
d1752aa8 EB |
1036 | vector = current_vector; |
1037 | offset = current_offset; | |
1da177e4 | 1038 | next: |
550f2299 | 1039 | vector += 8; |
305b92a2 | 1040 | if (vector >= first_system_vector) { |
550f2299 EB |
1041 | /* If we run out of vectors on large boxen, must share them. */ |
1042 | offset = (offset + 1) % 8; | |
1043 | vector = FIRST_DEVICE_VECTOR + offset; | |
1044 | } | |
d1752aa8 | 1045 | if (unlikely(current_vector == vector)) |
550f2299 EB |
1046 | continue; |
1047 | if (vector == IA32_SYSCALL_VECTOR) | |
1048 | goto next; | |
334ef7a7 | 1049 | for_each_cpu_mask_nr(new_cpu, new_mask) |
45edfd1d | 1050 | if (per_cpu(vector_irq, new_cpu)[vector] != -1) |
c7111c13 | 1051 | goto next; |
550f2299 | 1052 | /* Found one! */ |
d1752aa8 EB |
1053 | current_vector = vector; |
1054 | current_offset = offset; | |
61014292 EB |
1055 | if (old_vector) { |
1056 | cfg->move_in_progress = 1; | |
1057 | cfg->old_domain = cfg->domain; | |
1058 | } | |
334ef7a7 | 1059 | for_each_cpu_mask_nr(new_cpu, new_mask) |
c7111c13 | 1060 | per_cpu(vector_irq, new_cpu)[vector] = irq; |
13a79503 EB |
1061 | cfg->vector = vector; |
1062 | cfg->domain = domain; | |
dfbffdd8 | 1063 | return 0; |
1da177e4 | 1064 | } |
550f2299 | 1065 | return -ENOSPC; |
04b9267b EB |
1066 | } |
1067 | ||
dfbffdd8 | 1068 | static int assign_irq_vector(int irq, cpumask_t mask) |
04b9267b | 1069 | { |
dfbffdd8 | 1070 | int err; |
04b9267b | 1071 | unsigned long flags; |
0a1ad60d | 1072 | |
04b9267b | 1073 | spin_lock_irqsave(&vector_lock, flags); |
dfbffdd8 | 1074 | err = __assign_irq_vector(irq, mask); |
26a3c49c | 1075 | spin_unlock_irqrestore(&vector_lock, flags); |
dfbffdd8 | 1076 | return err; |
1da177e4 LT |
1077 | } |
1078 | ||
5df0287e YL |
1079 | static void __clear_irq_vector(int irq) |
1080 | { | |
13a79503 | 1081 | struct irq_cfg *cfg; |
5df0287e YL |
1082 | cpumask_t mask; |
1083 | int cpu, vector; | |
1084 | ||
0799e432 | 1085 | BUG_ON((unsigned)irq >= nr_irqs); |
3ac2de48 | 1086 | cfg = irq_cfg(irq); |
13a79503 | 1087 | BUG_ON(!cfg->vector); |
5df0287e | 1088 | |
13a79503 EB |
1089 | vector = cfg->vector; |
1090 | cpus_and(mask, cfg->domain, cpu_online_map); | |
334ef7a7 | 1091 | for_each_cpu_mask_nr(cpu, mask) |
5df0287e YL |
1092 | per_cpu(vector_irq, cpu)[vector] = -1; |
1093 | ||
13a79503 | 1094 | cfg->vector = 0; |
d366f8cb | 1095 | cpus_clear(cfg->domain); |
5df0287e YL |
1096 | } |
1097 | ||
d388e5fd | 1098 | void __setup_vector_irq(int cpu) |
70a0a535 EB |
1099 | { |
1100 | /* Initialize vector_irq on a new cpu */ | |
1101 | /* This function must be called with vector_lock held */ | |
70a0a535 | 1102 | int irq, vector; |
46b8214d | 1103 | struct irq_cfg *cfg; |
70a0a535 | 1104 | |
70a0a535 | 1105 | /* Mark the inuse vectors */ |
46b8214d | 1106 | for_each_irq_cfg(cfg) { |
3ac2de48 | 1107 | if (!cpu_isset(cpu, cfg->domain)) |
70a0a535 | 1108 | continue; |
3ac2de48 | 1109 | vector = cfg->vector; |
46b8214d | 1110 | irq = cfg->irq; |
70a0a535 EB |
1111 | per_cpu(vector_irq, cpu)[vector] = irq; |
1112 | } | |
1113 | /* Mark the free vectors */ | |
1114 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
1115 | irq = per_cpu(vector_irq, cpu)[vector]; | |
1116 | if (irq < 0) | |
1117 | continue; | |
3ac2de48 YL |
1118 | |
1119 | cfg = irq_cfg(irq); | |
1120 | if (!cpu_isset(cpu, cfg->domain)) | |
70a0a535 EB |
1121 | per_cpu(vector_irq, cpu)[vector] = -1; |
1122 | } | |
1123 | } | |
1124 | ||
f29bd1ba | 1125 | static struct irq_chip ioapic_chip; |
89027d35 SS |
1126 | #ifdef CONFIG_INTR_REMAP |
1127 | static struct irq_chip ir_ioapic_chip; | |
1128 | #endif | |
1da177e4 | 1129 | |
a27bc06d | 1130 | static void ioapic_register_intr(int irq, unsigned long trigger) |
1da177e4 | 1131 | { |
08678b08 YL |
1132 | struct irq_desc *desc; |
1133 | ||
1134 | desc = irq_to_desc(irq); | |
89027d35 | 1135 | if (trigger) |
08678b08 | 1136 | desc->status |= IRQ_LEVEL; |
89027d35 | 1137 | else |
08678b08 | 1138 | desc->status &= ~IRQ_LEVEL; |
89027d35 SS |
1139 | |
1140 | #ifdef CONFIG_INTR_REMAP | |
1141 | if (irq_remapped(irq)) { | |
08678b08 | 1142 | desc->status |= IRQ_MOVE_PCNTXT; |
89027d35 SS |
1143 | if (trigger) |
1144 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1145 | handle_fasteoi_irq, | |
1146 | "fasteoi"); | |
1147 | else | |
1148 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1149 | handle_edge_irq, "edge"); | |
1150 | return; | |
1151 | } | |
1152 | #endif | |
1153 | if (trigger) | |
1154 | set_irq_chip_and_handler_name(irq, &ioapic_chip, | |
1155 | handle_fasteoi_irq, | |
1156 | "fasteoi"); | |
1157 | else | |
a460e745 IM |
1158 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
1159 | handle_edge_irq, "edge"); | |
89027d35 SS |
1160 | } |
1161 | ||
1162 | static int setup_ioapic_entry(int apic, int irq, | |
1163 | struct IO_APIC_route_entry *entry, | |
1164 | unsigned int destination, int trigger, | |
1165 | int polarity, int vector) | |
1166 | { | |
1167 | /* | |
1168 | * add it to the IO-APIC irq-routing table: | |
1169 | */ | |
1170 | memset(entry,0,sizeof(*entry)); | |
1171 | ||
1172 | #ifdef CONFIG_INTR_REMAP | |
1173 | if (intr_remapping_enabled) { | |
1174 | struct intel_iommu *iommu = map_ioapic_to_ir(apic); | |
1175 | struct irte irte; | |
1176 | struct IR_IO_APIC_route_entry *ir_entry = | |
1177 | (struct IR_IO_APIC_route_entry *) entry; | |
1178 | int index; | |
1179 | ||
1180 | if (!iommu) | |
1181 | panic("No mapping iommu for ioapic %d\n", apic); | |
1182 | ||
1183 | index = alloc_irte(iommu, irq, 1); | |
1184 | if (index < 0) | |
1185 | panic("Failed to allocate IRTE for ioapic %d\n", apic); | |
1186 | ||
1187 | memset(&irte, 0, sizeof(irte)); | |
1188 | ||
1189 | irte.present = 1; | |
1190 | irte.dst_mode = INT_DEST_MODE; | |
1191 | irte.trigger_mode = trigger; | |
1192 | irte.dlvry_mode = INT_DELIVERY_MODE; | |
1193 | irte.vector = vector; | |
1194 | irte.dest_id = IRTE_DEST(destination); | |
1195 | ||
1196 | modify_irte(irq, &irte); | |
1197 | ||
1198 | ir_entry->index2 = (index >> 15) & 0x1; | |
1199 | ir_entry->zero = 0; | |
1200 | ir_entry->format = 1; | |
1201 | ir_entry->index = (index & 0x7fff); | |
1202 | } else | |
1203 | #endif | |
1204 | { | |
1205 | entry->delivery_mode = INT_DELIVERY_MODE; | |
1206 | entry->dest_mode = INT_DEST_MODE; | |
1207 | entry->dest = destination; | |
cc75b92d | 1208 | } |
89027d35 SS |
1209 | |
1210 | entry->mask = 0; /* enable IRQ */ | |
1211 | entry->trigger = trigger; | |
1212 | entry->polarity = polarity; | |
1213 | entry->vector = vector; | |
1214 | ||
1215 | /* Mask level triggered irqs. | |
1216 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. | |
1217 | */ | |
1218 | if (trigger) | |
1219 | entry->mask = 1; | |
1220 | return 0; | |
1da177e4 | 1221 | } |
a8c8a367 EB |
1222 | |
1223 | static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq, | |
1224 | int trigger, int polarity) | |
1da177e4 | 1225 | { |
3ac2de48 | 1226 | struct irq_cfg *cfg; |
1da177e4 | 1227 | struct IO_APIC_route_entry entry; |
a8c8a367 | 1228 | cpumask_t mask; |
1da177e4 | 1229 | |
a8c8a367 EB |
1230 | if (!IO_APIC_IRQ(irq)) |
1231 | return; | |
1232 | ||
3ac2de48 YL |
1233 | cfg = irq_cfg(irq); |
1234 | ||
dfbffdd8 EB |
1235 | mask = TARGET_CPUS; |
1236 | if (assign_irq_vector(irq, mask)) | |
a8c8a367 EB |
1237 | return; |
1238 | ||
dfbffdd8 EB |
1239 | cpus_and(mask, cfg->domain, mask); |
1240 | ||
a8c8a367 EB |
1241 | apic_printk(APIC_VERBOSE,KERN_DEBUG |
1242 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " | |
1243 | "IRQ %d Mode:%i Active:%i)\n", | |
ec2cd0a2 | 1244 | apic, mp_ioapics[apic].mp_apicid, pin, cfg->vector, |
a8c8a367 | 1245 | irq, trigger, polarity); |
1da177e4 | 1246 | |
1da177e4 | 1247 | |
89027d35 SS |
1248 | if (setup_ioapic_entry(mp_ioapics[apic].mp_apicid, irq, &entry, |
1249 | cpu_mask_to_apicid(mask), trigger, polarity, | |
1250 | cfg->vector)) { | |
1251 | printk("Failed to setup ioapic entry for ioapic %d, pin %d\n", | |
1252 | mp_ioapics[apic].mp_apicid, pin); | |
1253 | __clear_irq_vector(irq); | |
1254 | return; | |
1255 | } | |
ad892f5e | 1256 | |
a8c8a367 EB |
1257 | ioapic_register_intr(irq, trigger); |
1258 | if (irq < 16) | |
1259 | disable_8259A_irq(irq); | |
ad892f5e YL |
1260 | |
1261 | ioapic_write_entry(apic, pin, entry); | |
ad892f5e YL |
1262 | } |
1263 | ||
1264 | static void __init setup_IO_APIC_irqs(void) | |
1265 | { | |
1266 | int apic, pin, idx, irq, first_notcon = 1; | |
1267 | ||
1268 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1269 | ||
1270 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1271 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1da177e4 LT |
1272 | |
1273 | idx = find_irq_entry(apic,pin,mp_INT); | |
1274 | if (idx == -1) { | |
1275 | if (first_notcon) { | |
ec2cd0a2 | 1276 | apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mp_apicid, pin); |
1da177e4 LT |
1277 | first_notcon = 0; |
1278 | } else | |
ec2cd0a2 | 1279 | apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mp_apicid, pin); |
1da177e4 LT |
1280 | continue; |
1281 | } | |
20d225b9 YL |
1282 | if (!first_notcon) { |
1283 | apic_printk(APIC_VERBOSE, " not connected.\n"); | |
1284 | first_notcon = 1; | |
1285 | } | |
1da177e4 | 1286 | |
1da177e4 LT |
1287 | irq = pin_2_irq(idx, apic, pin); |
1288 | add_pin_to_irq(irq, apic, pin); | |
1289 | ||
a8c8a367 EB |
1290 | setup_IO_APIC_irq(apic, pin, irq, |
1291 | irq_trigger(idx), irq_polarity(idx)); | |
1da177e4 LT |
1292 | } |
1293 | } | |
1294 | ||
1295 | if (!first_notcon) | |
20d225b9 | 1296 | apic_printk(APIC_VERBOSE, " not connected.\n"); |
1da177e4 LT |
1297 | } |
1298 | ||
1299 | /* | |
f7633ce5 | 1300 | * Set up the timer pin, possibly with the 8259A-master behind. |
1da177e4 | 1301 | */ |
f7633ce5 MR |
1302 | static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin, |
1303 | int vector) | |
1da177e4 LT |
1304 | { |
1305 | struct IO_APIC_route_entry entry; | |
1da177e4 | 1306 | |
89027d35 SS |
1307 | if (intr_remapping_enabled) |
1308 | return; | |
1309 | ||
a2249cba | 1310 | memset(&entry, 0, sizeof(entry)); |
1da177e4 | 1311 | |
1da177e4 LT |
1312 | /* |
1313 | * We use logical delivery to get the timer IRQ | |
1314 | * to the first CPU. | |
1315 | */ | |
1316 | entry.dest_mode = INT_DEST_MODE; | |
03be7505 | 1317 | entry.mask = 1; /* mask IRQ now */ |
ee4eff6f | 1318 | entry.dest = cpu_mask_to_apicid(TARGET_CPUS); |
1da177e4 LT |
1319 | entry.delivery_mode = INT_DELIVERY_MODE; |
1320 | entry.polarity = 0; | |
1321 | entry.trigger = 0; | |
1322 | entry.vector = vector; | |
1323 | ||
1324 | /* | |
1325 | * The timer IRQ doesn't have to know that behind the | |
f7633ce5 | 1326 | * scene we may have a 8259A-master in AEOI mode ... |
1da177e4 | 1327 | */ |
a460e745 | 1328 | set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge"); |
1da177e4 LT |
1329 | |
1330 | /* | |
1331 | * Add it to the IO-APIC irq-routing table: | |
1332 | */ | |
a2249cba | 1333 | ioapic_write_entry(apic, pin, entry); |
1da177e4 LT |
1334 | } |
1335 | ||
32f71aff MR |
1336 | |
1337 | __apicdebuginit(void) print_IO_APIC(void) | |
1da177e4 LT |
1338 | { |
1339 | int apic, i; | |
1340 | union IO_APIC_reg_00 reg_00; | |
1341 | union IO_APIC_reg_01 reg_01; | |
1342 | union IO_APIC_reg_02 reg_02; | |
1343 | unsigned long flags; | |
46b8214d | 1344 | struct irq_cfg *cfg; |
1da177e4 LT |
1345 | |
1346 | if (apic_verbosity == APIC_QUIET) | |
1347 | return; | |
1348 | ||
1349 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); | |
1350 | for (i = 0; i < nr_ioapics; i++) | |
1351 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", | |
ec2cd0a2 | 1352 | mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]); |
1da177e4 LT |
1353 | |
1354 | /* | |
1355 | * We are a bit conservative about what we expect. We have to | |
1356 | * know about every hardware change ASAP. | |
1357 | */ | |
1358 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1359 | ||
1360 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1361 | ||
1362 | spin_lock_irqsave(&ioapic_lock, flags); | |
1363 | reg_00.raw = io_apic_read(apic, 0); | |
1364 | reg_01.raw = io_apic_read(apic, 1); | |
1365 | if (reg_01.bits.version >= 0x10) | |
1366 | reg_02.raw = io_apic_read(apic, 2); | |
1367 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1368 | ||
1369 | printk("\n"); | |
ec2cd0a2 | 1370 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
1371 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1372 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1da177e4 LT |
1373 | |
1374 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); | |
1375 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); | |
1da177e4 LT |
1376 | |
1377 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
1378 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); | |
1da177e4 LT |
1379 | |
1380 | if (reg_01.bits.version >= 0x10) { | |
1381 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1382 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1383 | } |
1384 | ||
1385 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1386 | ||
ee4eff6f BR |
1387 | printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol" |
1388 | " Stat Dmod Deli Vect: \n"); | |
1da177e4 LT |
1389 | |
1390 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
1391 | struct IO_APIC_route_entry entry; | |
1392 | ||
eea0e11c | 1393 | entry = ioapic_read_entry(apic, i); |
1da177e4 | 1394 | |
ee4eff6f | 1395 | printk(KERN_DEBUG " %02x %03X ", |
1da177e4 | 1396 | i, |
ee4eff6f | 1397 | entry.dest |
1da177e4 LT |
1398 | ); |
1399 | ||
1400 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", | |
1401 | entry.mask, | |
1402 | entry.trigger, | |
1403 | entry.irr, | |
1404 | entry.polarity, | |
1405 | entry.delivery_status, | |
1406 | entry.dest_mode, | |
1407 | entry.delivery_mode, | |
1408 | entry.vector | |
1409 | ); | |
1410 | } | |
1411 | } | |
1da177e4 | 1412 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
46b8214d | 1413 | for_each_irq_cfg(cfg) { |
e5a53714 YL |
1414 | struct irq_pin_list *entry = cfg->irq_2_pin; |
1415 | if (!entry) | |
1da177e4 | 1416 | continue; |
46b8214d | 1417 | printk(KERN_DEBUG "IRQ%d ", cfg->irq); |
1da177e4 LT |
1418 | for (;;) { |
1419 | printk("-> %d:%d", entry->apic, entry->pin); | |
1420 | if (!entry->next) | |
1421 | break; | |
e5a53714 | 1422 | entry = entry->next; |
1da177e4 LT |
1423 | } |
1424 | printk("\n"); | |
1425 | } | |
1426 | ||
1427 | printk(KERN_INFO ".................................... done.\n"); | |
1428 | ||
1429 | return; | |
1430 | } | |
1431 | ||
32f71aff | 1432 | __apicdebuginit(void) print_APIC_bitfield(int base) |
1da177e4 LT |
1433 | { |
1434 | unsigned int v; | |
1435 | int i, j; | |
1436 | ||
1437 | if (apic_verbosity == APIC_QUIET) | |
1438 | return; | |
1439 | ||
1440 | printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG); | |
1441 | for (i = 0; i < 8; i++) { | |
1442 | v = apic_read(base + i*0x10); | |
1443 | for (j = 0; j < 32; j++) { | |
1444 | if (v & (1<<j)) | |
1445 | printk("1"); | |
1446 | else | |
1447 | printk("0"); | |
1448 | } | |
1449 | printk("\n"); | |
1450 | } | |
1451 | } | |
1452 | ||
32f71aff | 1453 | __apicdebuginit(void) print_local_APIC(void *dummy) |
1da177e4 LT |
1454 | { |
1455 | unsigned int v, ver, maxlvt; | |
1b374e4d | 1456 | unsigned long icr; |
1da177e4 LT |
1457 | |
1458 | if (apic_verbosity == APIC_QUIET) | |
1459 | return; | |
1460 | ||
1461 | printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", | |
1462 | smp_processor_id(), hard_smp_processor_id()); | |
66823114 | 1463 | v = apic_read(APIC_ID); |
4c9961d5 | 1464 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
1da177e4 LT |
1465 | v = apic_read(APIC_LVR); |
1466 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1467 | ver = GET_APIC_VERSION(v); | |
37e650c7 | 1468 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1469 | |
1470 | v = apic_read(APIC_TASKPRI); | |
1471 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1472 | ||
5a40b7c2 AK |
1473 | v = apic_read(APIC_ARBPRI); |
1474 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1475 | v & APIC_ARBPRI_MASK); | |
1476 | v = apic_read(APIC_PROCPRI); | |
1477 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1da177e4 LT |
1478 | |
1479 | v = apic_read(APIC_EOI); | |
1480 | printk(KERN_DEBUG "... APIC EOI: %08x\n", v); | |
1481 | v = apic_read(APIC_RRR); | |
1482 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1483 | v = apic_read(APIC_LDR); | |
1484 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
1485 | v = apic_read(APIC_DFR); | |
1486 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1487 | v = apic_read(APIC_SPIV); | |
1488 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1489 | ||
1490 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
1491 | print_APIC_bitfield(APIC_ISR); | |
1492 | printk(KERN_DEBUG "... APIC TMR field:\n"); | |
1493 | print_APIC_bitfield(APIC_TMR); | |
1494 | printk(KERN_DEBUG "... APIC IRR field:\n"); | |
1495 | print_APIC_bitfield(APIC_IRR); | |
1496 | ||
5a40b7c2 AK |
1497 | v = apic_read(APIC_ESR); |
1498 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1da177e4 | 1499 | |
1b374e4d | 1500 | icr = apic_icr_read(); |
d562353a IM |
1501 | printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr); |
1502 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
1da177e4 LT |
1503 | |
1504 | v = apic_read(APIC_LVTT); | |
1505 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1506 | ||
1507 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1508 | v = apic_read(APIC_LVTPC); | |
1509 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1510 | } | |
1511 | v = apic_read(APIC_LVT0); | |
1512 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1513 | v = apic_read(APIC_LVT1); | |
1514 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1515 | ||
1516 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1517 | v = apic_read(APIC_LVTERR); | |
1518 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1519 | } | |
1520 | ||
1521 | v = apic_read(APIC_TMICT); | |
1522 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1523 | v = apic_read(APIC_TMCCT); | |
1524 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1525 | v = apic_read(APIC_TDCR); | |
1526 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
1527 | printk("\n"); | |
1528 | } | |
1529 | ||
32f71aff | 1530 | __apicdebuginit(void) print_all_local_APICs(void) |
1da177e4 | 1531 | { |
15c8b6c1 | 1532 | on_each_cpu(print_local_APIC, NULL, 1); |
1da177e4 LT |
1533 | } |
1534 | ||
32f71aff | 1535 | __apicdebuginit(void) print_PIC(void) |
1da177e4 | 1536 | { |
1da177e4 LT |
1537 | unsigned int v; |
1538 | unsigned long flags; | |
1539 | ||
1540 | if (apic_verbosity == APIC_QUIET) | |
1541 | return; | |
1542 | ||
1543 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1544 | ||
1545 | spin_lock_irqsave(&i8259A_lock, flags); | |
1546 | ||
1547 | v = inb(0xa1) << 8 | inb(0x21); | |
1548 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1549 | ||
1550 | v = inb(0xa0) << 8 | inb(0x20); | |
1551 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1552 | ||
1553 | outb(0x0b,0xa0); | |
1554 | outb(0x0b,0x20); | |
1555 | v = inb(0xa0) << 8 | inb(0x20); | |
1556 | outb(0x0a,0xa0); | |
1557 | outb(0x0a,0x20); | |
1558 | ||
1559 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
1560 | ||
1561 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1562 | ||
1563 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1564 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1565 | } | |
1566 | ||
32f71aff MR |
1567 | __apicdebuginit(int) print_all_ICs(void) |
1568 | { | |
1569 | print_PIC(); | |
1570 | print_all_local_APICs(); | |
1571 | print_IO_APIC(); | |
1572 | ||
1573 | return 0; | |
1574 | } | |
1575 | ||
1576 | fs_initcall(print_all_ICs); | |
1577 | ||
1da177e4 | 1578 | |
1c69524c | 1579 | void __init enable_IO_APIC(void) |
1da177e4 LT |
1580 | { |
1581 | union IO_APIC_reg_01 reg_01; | |
1008fddc | 1582 | int i8259_apic, i8259_pin; |
e5a53714 | 1583 | int apic; |
1da177e4 LT |
1584 | unsigned long flags; |
1585 | ||
1da177e4 LT |
1586 | /* |
1587 | * The number of IO-APIC IRQ registers (== #pins): | |
1588 | */ | |
1008fddc | 1589 | for (apic = 0; apic < nr_ioapics; apic++) { |
1da177e4 | 1590 | spin_lock_irqsave(&ioapic_lock, flags); |
1008fddc | 1591 | reg_01.raw = io_apic_read(apic, 1); |
1da177e4 | 1592 | spin_unlock_irqrestore(&ioapic_lock, flags); |
1008fddc EB |
1593 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; |
1594 | } | |
1595 | for(apic = 0; apic < nr_ioapics; apic++) { | |
1596 | int pin; | |
1597 | /* See if any of the pins is in ExtINT mode */ | |
1598 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1599 | struct IO_APIC_route_entry entry; | |
eea0e11c | 1600 | entry = ioapic_read_entry(apic, pin); |
1008fddc EB |
1601 | |
1602 | /* If the interrupt line is enabled and in ExtInt mode | |
1603 | * I have found the pin where the i8259 is connected. | |
1604 | */ | |
1605 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1606 | ioapic_i8259.apic = apic; | |
1607 | ioapic_i8259.pin = pin; | |
1608 | goto found_i8259; | |
1609 | } | |
1610 | } | |
1611 | } | |
1612 | found_i8259: | |
1613 | /* Look to see what if the MP table has reported the ExtINT */ | |
1614 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1615 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1616 | /* Trust the MP table if nothing is setup in the hardware */ | |
1617 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1618 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1619 | ioapic_i8259.pin = i8259_pin; | |
1620 | ioapic_i8259.apic = i8259_apic; | |
1621 | } | |
1622 | /* Complain if the MP table and the hardware disagree */ | |
1623 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1624 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1625 | { | |
1626 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1627 | } |
1628 | ||
1629 | /* | |
1630 | * Do not trust the IO-APIC being empty at bootup | |
1631 | */ | |
1632 | clear_IO_APIC(); | |
1633 | } | |
1634 | ||
1635 | /* | |
1636 | * Not an __init, needed by the reboot code | |
1637 | */ | |
1638 | void disable_IO_APIC(void) | |
1639 | { | |
1640 | /* | |
1641 | * Clear the IO-APIC before rebooting: | |
1642 | */ | |
1643 | clear_IO_APIC(); | |
1644 | ||
208fb931 | 1645 | /* |
0b968d23 | 1646 | * If the i8259 is routed through an IOAPIC |
208fb931 | 1647 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 1648 | * so legacy interrupts can be delivered. |
208fb931 | 1649 | */ |
1008fddc | 1650 | if (ioapic_i8259.pin != -1) { |
208fb931 | 1651 | struct IO_APIC_route_entry entry; |
208fb931 EB |
1652 | |
1653 | memset(&entry, 0, sizeof(entry)); | |
1654 | entry.mask = 0; /* Enabled */ | |
1655 | entry.trigger = 0; /* Edge */ | |
1656 | entry.irr = 0; | |
1657 | entry.polarity = 0; /* High */ | |
1658 | entry.delivery_status = 0; | |
1659 | entry.dest_mode = 0; /* Physical */ | |
1008fddc | 1660 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
208fb931 | 1661 | entry.vector = 0; |
4c9961d5 | 1662 | entry.dest = read_apic_id(); |
208fb931 | 1663 | |
208fb931 EB |
1664 | /* |
1665 | * Add it to the IO-APIC irq-routing table: | |
1666 | */ | |
eea0e11c | 1667 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
208fb931 EB |
1668 | } |
1669 | ||
1008fddc | 1670 | disconnect_bsp_APIC(ioapic_i8259.pin != -1); |
1da177e4 LT |
1671 | } |
1672 | ||
1da177e4 LT |
1673 | /* |
1674 | * There is a nasty bug in some older SMP boards, their mptable lies | |
1675 | * about the timer IRQ. We do the following to work around the situation: | |
1676 | * | |
1677 | * - timer IRQ defaults to IO-APIC IRQ | |
1678 | * - if this function detects that timer IRQs are defunct, then we fall | |
1679 | * back to ISA timer IRQs | |
1680 | */ | |
1681 | static int __init timer_irq_works(void) | |
1682 | { | |
1683 | unsigned long t1 = jiffies; | |
4aae0702 | 1684 | unsigned long flags; |
1da177e4 | 1685 | |
4aae0702 | 1686 | local_save_flags(flags); |
1da177e4 LT |
1687 | local_irq_enable(); |
1688 | /* Let ten ticks pass... */ | |
1689 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 1690 | local_irq_restore(flags); |
1da177e4 LT |
1691 | |
1692 | /* | |
1693 | * Expect a few ticks at least, to be sure some possible | |
1694 | * glue logic does not lock up after one or two first | |
1695 | * ticks in a non-ExtINT mode. Also the local APIC | |
1696 | * might have cached one ExtINT interrupt. Finally, at | |
1697 | * least one tick may be lost due to delays. | |
1698 | */ | |
1699 | ||
1700 | /* jiffies wrap? */ | |
1d16b53e | 1701 | if (time_after(jiffies, t1 + 4)) |
1da177e4 LT |
1702 | return 1; |
1703 | return 0; | |
1704 | } | |
1705 | ||
1706 | /* | |
1707 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
1708 | * number of pending IRQ events unhandled. These cases are very rare, | |
1709 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
1710 | * better to do it this way as thus we do not have to be aware of | |
1711 | * 'pending' interrupts in the IRQ path, except at this point. | |
1712 | */ | |
1713 | /* | |
1714 | * Edge triggered needs to resend any interrupt | |
1715 | * that was delayed but this is now handled in the device | |
1716 | * independent code. | |
1717 | */ | |
1718 | ||
1719 | /* | |
1720 | * Starting up a edge-triggered IO-APIC interrupt is | |
1721 | * nasty - we need to make sure that we get the edge. | |
1722 | * If it is already asserted for some reason, we need | |
1723 | * return 1 to indicate that is was pending. | |
1724 | * | |
1725 | * This is not complete - we should be able to fake | |
1726 | * an edge even if it isn't on the 8259A... | |
1727 | */ | |
1728 | ||
f29bd1ba | 1729 | static unsigned int startup_ioapic_irq(unsigned int irq) |
1da177e4 LT |
1730 | { |
1731 | int was_pending = 0; | |
1732 | unsigned long flags; | |
1733 | ||
1734 | spin_lock_irqsave(&ioapic_lock, flags); | |
1735 | if (irq < 16) { | |
1736 | disable_8259A_irq(irq); | |
1737 | if (i8259A_irq_pending(irq)) | |
1738 | was_pending = 1; | |
1739 | } | |
1740 | __unmask_IO_APIC_irq(irq); | |
1741 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1742 | ||
1743 | return was_pending; | |
1744 | } | |
1745 | ||
04b9267b | 1746 | static int ioapic_retrigger_irq(unsigned int irq) |
c0ad90a3 | 1747 | { |
3ac2de48 | 1748 | struct irq_cfg *cfg = irq_cfg(irq); |
6bf2dafa | 1749 | unsigned long flags; |
550f2299 | 1750 | |
6bf2dafa | 1751 | spin_lock_irqsave(&vector_lock, flags); |
cb6d2be6 | 1752 | send_IPI_mask(cpumask_of_cpu(first_cpu(cfg->domain)), cfg->vector); |
6bf2dafa | 1753 | spin_unlock_irqrestore(&vector_lock, flags); |
c0ad90a3 IM |
1754 | |
1755 | return 1; | |
1756 | } | |
1757 | ||
1da177e4 LT |
1758 | /* |
1759 | * Level and edge triggered IO-APIC interrupts need different handling, | |
1760 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be | |
1761 | * handled with the level-triggered descriptor, but that one has slightly | |
1762 | * more overhead. Level-triggered interrupts cannot be handled with the | |
1763 | * edge-triggered handler, without risking IRQ storms and other ugly | |
1764 | * races. | |
1765 | */ | |
1766 | ||
61014292 | 1767 | #ifdef CONFIG_SMP |
89027d35 SS |
1768 | |
1769 | #ifdef CONFIG_INTR_REMAP | |
1770 | static void ir_irq_migration(struct work_struct *work); | |
1771 | ||
1772 | static DECLARE_DELAYED_WORK(ir_migration_work, ir_irq_migration); | |
1773 | ||
1774 | /* | |
1775 | * Migrate the IO-APIC irq in the presence of intr-remapping. | |
1776 | * | |
1777 | * For edge triggered, irq migration is a simple atomic update(of vector | |
1778 | * and cpu destination) of IRTE and flush the hardware cache. | |
1779 | * | |
1780 | * For level triggered, we need to modify the io-apic RTE aswell with the update | |
1781 | * vector information, along with modifying IRTE with vector and destination. | |
1782 | * So irq migration for level triggered is little bit more complex compared to | |
1783 | * edge triggered migration. But the good news is, we use the same algorithm | |
1784 | * for level triggered migration as we have today, only difference being, | |
1785 | * we now initiate the irq migration from process context instead of the | |
1786 | * interrupt context. | |
1787 | * | |
1788 | * In future, when we do a directed EOI (combined with cpu EOI broadcast | |
1789 | * suppression) to the IO-APIC, level triggered irq migration will also be | |
1790 | * as simple as edge triggered migration and we can do the irq migration | |
1791 | * with a simple atomic update to IO-APIC RTE. | |
1792 | */ | |
1793 | static void migrate_ioapic_irq(int irq, cpumask_t mask) | |
1794 | { | |
3ac2de48 | 1795 | struct irq_cfg *cfg; |
08678b08 | 1796 | struct irq_desc *desc; |
89027d35 SS |
1797 | cpumask_t tmp, cleanup_mask; |
1798 | struct irte irte; | |
08678b08 | 1799 | int modify_ioapic_rte; |
89027d35 SS |
1800 | unsigned int dest; |
1801 | unsigned long flags; | |
1802 | ||
1803 | cpus_and(tmp, mask, cpu_online_map); | |
1804 | if (cpus_empty(tmp)) | |
1805 | return; | |
1806 | ||
1807 | if (get_irte(irq, &irte)) | |
1808 | return; | |
1809 | ||
1810 | if (assign_irq_vector(irq, mask)) | |
1811 | return; | |
1812 | ||
3ac2de48 | 1813 | cfg = irq_cfg(irq); |
89027d35 SS |
1814 | cpus_and(tmp, cfg->domain, mask); |
1815 | dest = cpu_mask_to_apicid(tmp); | |
1816 | ||
08678b08 YL |
1817 | desc = irq_to_desc(irq); |
1818 | modify_ioapic_rte = desc->status & IRQ_LEVEL; | |
89027d35 SS |
1819 | if (modify_ioapic_rte) { |
1820 | spin_lock_irqsave(&ioapic_lock, flags); | |
1821 | __target_IO_APIC_irq(irq, dest, cfg->vector); | |
1822 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1823 | } | |
1824 | ||
1825 | irte.vector = cfg->vector; | |
1826 | irte.dest_id = IRTE_DEST(dest); | |
1827 | ||
1828 | /* | |
1829 | * Modified the IRTE and flushes the Interrupt entry cache. | |
1830 | */ | |
1831 | modify_irte(irq, &irte); | |
1832 | ||
1833 | if (cfg->move_in_progress) { | |
1834 | cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map); | |
1835 | cfg->move_cleanup_count = cpus_weight(cleanup_mask); | |
1836 | send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); | |
1837 | cfg->move_in_progress = 0; | |
1838 | } | |
1839 | ||
08678b08 | 1840 | desc->affinity = mask; |
89027d35 SS |
1841 | } |
1842 | ||
1843 | static int migrate_irq_remapped_level(int irq) | |
1844 | { | |
1845 | int ret = -1; | |
08678b08 | 1846 | struct irq_desc *desc = irq_to_desc(irq); |
89027d35 SS |
1847 | |
1848 | mask_IO_APIC_irq(irq); | |
1849 | ||
1850 | if (io_apic_level_ack_pending(irq)) { | |
1851 | /* | |
1852 | * Interrupt in progress. Migrating irq now will change the | |
1853 | * vector information in the IO-APIC RTE and that will confuse | |
1854 | * the EOI broadcast performed by cpu. | |
1855 | * So, delay the irq migration to the next instance. | |
1856 | */ | |
1857 | schedule_delayed_work(&ir_migration_work, 1); | |
1858 | goto unmask; | |
1859 | } | |
1860 | ||
1861 | /* everthing is clear. we have right of way */ | |
08678b08 | 1862 | migrate_ioapic_irq(irq, desc->pending_mask); |
89027d35 SS |
1863 | |
1864 | ret = 0; | |
08678b08 YL |
1865 | desc->status &= ~IRQ_MOVE_PENDING; |
1866 | cpus_clear(desc->pending_mask); | |
89027d35 SS |
1867 | |
1868 | unmask: | |
1869 | unmask_IO_APIC_irq(irq); | |
1870 | return ret; | |
1871 | } | |
1872 | ||
1873 | static void ir_irq_migration(struct work_struct *work) | |
1874 | { | |
2c6927a3 YL |
1875 | unsigned int irq; |
1876 | struct irq_desc *desc; | |
89027d35 | 1877 | |
2c6927a3 | 1878 | for_each_irq_desc(irq, desc) { |
89027d35 SS |
1879 | if (desc->status & IRQ_MOVE_PENDING) { |
1880 | unsigned long flags; | |
1881 | ||
1882 | spin_lock_irqsave(&desc->lock, flags); | |
1883 | if (!desc->chip->set_affinity || | |
1884 | !(desc->status & IRQ_MOVE_PENDING)) { | |
1885 | desc->status &= ~IRQ_MOVE_PENDING; | |
1886 | spin_unlock_irqrestore(&desc->lock, flags); | |
1887 | continue; | |
1888 | } | |
1889 | ||
08678b08 | 1890 | desc->chip->set_affinity(irq, desc->pending_mask); |
89027d35 SS |
1891 | spin_unlock_irqrestore(&desc->lock, flags); |
1892 | } | |
1893 | } | |
1894 | } | |
1895 | ||
1896 | /* | |
1897 | * Migrates the IRQ destination in the process context. | |
1898 | */ | |
1899 | static void set_ir_ioapic_affinity_irq(unsigned int irq, cpumask_t mask) | |
1900 | { | |
08678b08 YL |
1901 | struct irq_desc *desc = irq_to_desc(irq); |
1902 | ||
1903 | if (desc->status & IRQ_LEVEL) { | |
1904 | desc->status |= IRQ_MOVE_PENDING; | |
1905 | desc->pending_mask = mask; | |
89027d35 SS |
1906 | migrate_irq_remapped_level(irq); |
1907 | return; | |
1908 | } | |
1909 | ||
1910 | migrate_ioapic_irq(irq, mask); | |
1911 | } | |
1912 | #endif | |
1913 | ||
61014292 EB |
1914 | asmlinkage void smp_irq_move_cleanup_interrupt(void) |
1915 | { | |
1916 | unsigned vector, me; | |
1917 | ack_APIC_irq(); | |
1918 | exit_idle(); | |
1919 | irq_enter(); | |
1920 | ||
1921 | me = smp_processor_id(); | |
1922 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
1923 | unsigned int irq; | |
1924 | struct irq_desc *desc; | |
1925 | struct irq_cfg *cfg; | |
1926 | irq = __get_cpu_var(vector_irq)[vector]; | |
0799e432 | 1927 | if (irq >= nr_irqs) |
61014292 EB |
1928 | continue; |
1929 | ||
08678b08 | 1930 | desc = irq_to_desc(irq); |
3ac2de48 | 1931 | cfg = irq_cfg(irq); |
61014292 EB |
1932 | spin_lock(&desc->lock); |
1933 | if (!cfg->move_cleanup_count) | |
1934 | goto unlock; | |
1935 | ||
1936 | if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) | |
1937 | goto unlock; | |
1938 | ||
1939 | __get_cpu_var(vector_irq)[vector] = -1; | |
1940 | cfg->move_cleanup_count--; | |
1941 | unlock: | |
1942 | spin_unlock(&desc->lock); | |
1943 | } | |
1944 | ||
1945 | irq_exit(); | |
1946 | } | |
1947 | ||
1948 | static void irq_complete_move(unsigned int irq) | |
1949 | { | |
3ac2de48 | 1950 | struct irq_cfg *cfg = irq_cfg(irq); |
61014292 EB |
1951 | unsigned vector, me; |
1952 | ||
1953 | if (likely(!cfg->move_in_progress)) | |
1954 | return; | |
1955 | ||
65ea5b03 | 1956 | vector = ~get_irq_regs()->orig_ax; |
61014292 | 1957 | me = smp_processor_id(); |
f0e13ae7 | 1958 | if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) { |
61014292 EB |
1959 | cpumask_t cleanup_mask; |
1960 | ||
1961 | cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map); | |
1962 | cfg->move_cleanup_count = cpus_weight(cleanup_mask); | |
1963 | send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); | |
1964 | cfg->move_in_progress = 0; | |
1965 | } | |
1966 | } | |
1967 | #else | |
1968 | static inline void irq_complete_move(unsigned int irq) {} | |
1969 | #endif | |
89027d35 SS |
1970 | #ifdef CONFIG_INTR_REMAP |
1971 | static void ack_x2apic_level(unsigned int irq) | |
1972 | { | |
1973 | ack_x2APIC_irq(); | |
1974 | } | |
1975 | ||
1976 | static void ack_x2apic_edge(unsigned int irq) | |
1977 | { | |
1978 | ack_x2APIC_irq(); | |
1979 | } | |
1980 | #endif | |
61014292 | 1981 | |
0be6652f EB |
1982 | static void ack_apic_edge(unsigned int irq) |
1983 | { | |
61014292 | 1984 | irq_complete_move(irq); |
0be6652f EB |
1985 | move_native_irq(irq); |
1986 | ack_APIC_irq(); | |
1987 | } | |
1988 | ||
1989 | static void ack_apic_level(unsigned int irq) | |
1990 | { | |
1991 | int do_unmask_irq = 0; | |
1992 | ||
61014292 | 1993 | irq_complete_move(irq); |
52e3d90d | 1994 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
0be6652f | 1995 | /* If we are moving the irq we need to mask it */ |
08678b08 | 1996 | if (unlikely(irq_to_desc(irq)->status & IRQ_MOVE_PENDING)) { |
0be6652f EB |
1997 | do_unmask_irq = 1; |
1998 | mask_IO_APIC_irq(irq); | |
1999 | } | |
2000 | #endif | |
2001 | ||
2002 | /* | |
2003 | * We must acknowledge the irq before we move it or the acknowledge will | |
beb7dd86 | 2004 | * not propagate properly. |
0be6652f EB |
2005 | */ |
2006 | ack_APIC_irq(); | |
2007 | ||
2008 | /* Now we can move and renable the irq */ | |
ef3e28c5 EB |
2009 | if (unlikely(do_unmask_irq)) { |
2010 | /* Only migrate the irq if the ack has been received. | |
2011 | * | |
2012 | * On rare occasions the broadcast level triggered ack gets | |
2013 | * delayed going to ioapics, and if we reprogram the | |
2014 | * vector while Remote IRR is still set the irq will never | |
2015 | * fire again. | |
2016 | * | |
2017 | * To prevent this scenario we read the Remote IRR bit | |
2018 | * of the ioapic. This has two effects. | |
2019 | * - On any sane system the read of the ioapic will | |
2020 | * flush writes (and acks) going to the ioapic from | |
2021 | * this cpu. | |
2022 | * - We get to see if the ACK has actually been delivered. | |
2023 | * | |
2024 | * Based on failed experiments of reprogramming the | |
2025 | * ioapic entry from outside of irq context starting | |
2026 | * with masking the ioapic entry and then polling until | |
2027 | * Remote IRR was clear before reprogramming the | |
2028 | * ioapic I don't trust the Remote IRR bit to be | |
2029 | * completey accurate. | |
2030 | * | |
2031 | * However there appears to be no other way to plug | |
2032 | * this race, so if the Remote IRR bit is not | |
2033 | * accurate and is causing problems then it is a hardware bug | |
2034 | * and you can go talk to the chipset vendor about it. | |
2035 | */ | |
2036 | if (!io_apic_level_ack_pending(irq)) | |
2037 | move_masked_irq(irq); | |
0be6652f | 2038 | unmask_IO_APIC_irq(irq); |
ef3e28c5 | 2039 | } |
0be6652f EB |
2040 | } |
2041 | ||
f29bd1ba IM |
2042 | static struct irq_chip ioapic_chip __read_mostly = { |
2043 | .name = "IO-APIC", | |
04b9267b EB |
2044 | .startup = startup_ioapic_irq, |
2045 | .mask = mask_IO_APIC_irq, | |
2046 | .unmask = unmask_IO_APIC_irq, | |
0be6652f EB |
2047 | .ack = ack_apic_edge, |
2048 | .eoi = ack_apic_level, | |
54d5d424 | 2049 | #ifdef CONFIG_SMP |
04b9267b | 2050 | .set_affinity = set_ioapic_affinity_irq, |
54d5d424 | 2051 | #endif |
04b9267b | 2052 | .retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
2053 | }; |
2054 | ||
89027d35 SS |
2055 | #ifdef CONFIG_INTR_REMAP |
2056 | static struct irq_chip ir_ioapic_chip __read_mostly = { | |
2057 | .name = "IR-IO-APIC", | |
2058 | .startup = startup_ioapic_irq, | |
2059 | .mask = mask_IO_APIC_irq, | |
2060 | .unmask = unmask_IO_APIC_irq, | |
2061 | .ack = ack_x2apic_edge, | |
2062 | .eoi = ack_x2apic_level, | |
2063 | #ifdef CONFIG_SMP | |
2064 | .set_affinity = set_ir_ioapic_affinity_irq, | |
2065 | #endif | |
2066 | .retrigger = ioapic_retrigger_irq, | |
2067 | }; | |
2068 | #endif | |
2069 | ||
1da177e4 LT |
2070 | static inline void init_IO_APIC_traps(void) |
2071 | { | |
2072 | int irq; | |
08678b08 | 2073 | struct irq_desc *desc; |
46b8214d | 2074 | struct irq_cfg *cfg; |
1da177e4 LT |
2075 | |
2076 | /* | |
2077 | * NOTE! The local APIC isn't very good at handling | |
2078 | * multiple interrupts at the same interrupt level. | |
2079 | * As the interrupt level is determined by taking the | |
2080 | * vector number and shifting that right by 4, we | |
2081 | * want to spread these out a bit so that they don't | |
2082 | * all fall in the same interrupt level. | |
2083 | * | |
2084 | * Also, we've got to be careful not to trash gate | |
2085 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
2086 | */ | |
46b8214d YL |
2087 | for_each_irq_cfg(cfg) { |
2088 | irq = cfg->irq; | |
3ac2de48 | 2089 | if (IO_APIC_IRQ(irq) && !cfg->vector) { |
1da177e4 LT |
2090 | /* |
2091 | * Hmm.. We don't have an entry for this, | |
2092 | * so default to an old-fashioned 8259 | |
2093 | * interrupt if we can.. | |
2094 | */ | |
2095 | if (irq < 16) | |
2096 | make_8259A_irq(irq); | |
08678b08 YL |
2097 | else { |
2098 | desc = irq_to_desc(irq); | |
1da177e4 | 2099 | /* Strange. Oh, well.. */ |
08678b08 YL |
2100 | desc->chip = &no_irq_chip; |
2101 | } | |
1da177e4 LT |
2102 | } |
2103 | } | |
2104 | } | |
2105 | ||
c88ac1df | 2106 | static void unmask_lapic_irq(unsigned int irq) |
1da177e4 LT |
2107 | { |
2108 | unsigned long v; | |
2109 | ||
2110 | v = apic_read(APIC_LVT0); | |
11a8e778 | 2111 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
1da177e4 LT |
2112 | } |
2113 | ||
c88ac1df | 2114 | static void mask_lapic_irq(unsigned int irq) |
1da177e4 LT |
2115 | { |
2116 | unsigned long v; | |
2117 | ||
2118 | v = apic_read(APIC_LVT0); | |
11a8e778 | 2119 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
2120 | } |
2121 | ||
2122 | static void ack_lapic_irq (unsigned int irq) | |
2123 | { | |
2124 | ack_APIC_irq(); | |
2125 | } | |
2126 | ||
c88ac1df MR |
2127 | static struct irq_chip lapic_chip __read_mostly = { |
2128 | .name = "local-APIC", | |
2129 | .mask = mask_lapic_irq, | |
2130 | .unmask = unmask_lapic_irq, | |
2131 | .ack = ack_lapic_irq, | |
1da177e4 LT |
2132 | }; |
2133 | ||
c88ac1df MR |
2134 | static void lapic_register_intr(int irq) |
2135 | { | |
08678b08 YL |
2136 | struct irq_desc *desc; |
2137 | ||
2138 | desc = irq_to_desc(irq); | |
2139 | desc->status &= ~IRQ_LEVEL; | |
c88ac1df MR |
2140 | set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
2141 | "edge"); | |
2142 | } | |
2143 | ||
e9427101 | 2144 | static void __init setup_nmi(void) |
1da177e4 LT |
2145 | { |
2146 | /* | |
2147 | * Dirty trick to enable the NMI watchdog ... | |
2148 | * We put the 8259A master into AEOI mode and | |
2149 | * unmask on all local APICs LVT0 as NMI. | |
2150 | * | |
2151 | * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') | |
2152 | * is from Maciej W. Rozycki - so we do not have to EOI from | |
2153 | * the NMI handler or the timer interrupt. | |
2154 | */ | |
2155 | printk(KERN_INFO "activating NMI Watchdog ..."); | |
2156 | ||
e9427101 | 2157 | enable_NMI_through_LVT0(); |
1da177e4 LT |
2158 | |
2159 | printk(" done.\n"); | |
2160 | } | |
2161 | ||
2162 | /* | |
2163 | * This looks a bit hackish but it's about the only one way of sending | |
2164 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2165 | * not support the ExtINT mode, unfortunately. We need to send these | |
2166 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2167 | * 8259A interrupt line asserted until INTA. --macro | |
2168 | */ | |
5afca33a | 2169 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2170 | { |
1008fddc | 2171 | int apic, pin, i; |
1da177e4 LT |
2172 | struct IO_APIC_route_entry entry0, entry1; |
2173 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2174 | |
1008fddc EB |
2175 | pin = find_isa_irq_pin(8, mp_INT); |
2176 | apic = find_isa_irq_apic(8, mp_INT); | |
1da177e4 LT |
2177 | if (pin == -1) |
2178 | return; | |
2179 | ||
a2249cba AM |
2180 | entry0 = ioapic_read_entry(apic, pin); |
2181 | ||
1008fddc | 2182 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2183 | |
2184 | memset(&entry1, 0, sizeof(entry1)); | |
2185 | ||
2186 | entry1.dest_mode = 0; /* physical delivery */ | |
2187 | entry1.mask = 0; /* unmask IRQ now */ | |
ee4eff6f | 2188 | entry1.dest = hard_smp_processor_id(); |
1da177e4 LT |
2189 | entry1.delivery_mode = dest_ExtINT; |
2190 | entry1.polarity = entry0.polarity; | |
2191 | entry1.trigger = 0; | |
2192 | entry1.vector = 0; | |
2193 | ||
a2249cba | 2194 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2195 | |
2196 | save_control = CMOS_READ(RTC_CONTROL); | |
2197 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2198 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2199 | RTC_FREQ_SELECT); | |
2200 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2201 | ||
2202 | i = 100; | |
2203 | while (i-- > 0) { | |
2204 | mdelay(10); | |
2205 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2206 | i -= 10; | |
2207 | } | |
2208 | ||
2209 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2210 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
1008fddc | 2211 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2212 | |
a2249cba | 2213 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2214 | } |
2215 | ||
2216 | /* | |
2217 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2218 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2219 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2220 | * fanatically on his truly buggy board. | |
fea5f1e1 LT |
2221 | * |
2222 | * FIXME: really need to revamp this for modern platforms only. | |
1da177e4 | 2223 | */ |
e9427101 | 2224 | static inline void __init check_timer(void) |
1da177e4 | 2225 | { |
3ac2de48 | 2226 | struct irq_cfg *cfg = irq_cfg(0); |
1008fddc | 2227 | int apic1, pin1, apic2, pin2; |
4aae0702 | 2228 | unsigned long flags; |
691874fa | 2229 | int no_pin1 = 0; |
4aae0702 IM |
2230 | |
2231 | local_irq_save(flags); | |
1da177e4 LT |
2232 | |
2233 | /* | |
2234 | * get/set the timer IRQ vector: | |
2235 | */ | |
2236 | disable_8259A_irq(0); | |
dfbffdd8 | 2237 | assign_irq_vector(0, TARGET_CPUS); |
1da177e4 LT |
2238 | |
2239 | /* | |
d11d5794 MR |
2240 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2241 | * wire has to be disabled in the local APIC. | |
1da177e4 | 2242 | */ |
11a8e778 | 2243 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
1da177e4 | 2244 | init_8259A(1); |
1da177e4 | 2245 | |
1008fddc EB |
2246 | pin1 = find_isa_irq_pin(0, mp_INT); |
2247 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2248 | pin2 = ioapic_i8259.pin; | |
2249 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2250 | |
49a66a0b MR |
2251 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
2252 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", | |
2253 | cfg->vector, apic1, pin1, apic2, pin2); | |
b0268726 | 2254 | |
691874fa MR |
2255 | /* |
2256 | * Some BIOS writers are clueless and report the ExtINTA | |
2257 | * I/O APIC input from the cascaded 8259A as the timer | |
2258 | * interrupt input. So just in case, if only one pin | |
2259 | * was found above, try it both directly and through the | |
2260 | * 8259A. | |
2261 | */ | |
2262 | if (pin1 == -1) { | |
89027d35 SS |
2263 | if (intr_remapping_enabled) |
2264 | panic("BIOS bug: timer not connected to IO-APIC"); | |
691874fa MR |
2265 | pin1 = pin2; |
2266 | apic1 = apic2; | |
2267 | no_pin1 = 1; | |
2268 | } else if (pin2 == -1) { | |
2269 | pin2 = pin1; | |
2270 | apic2 = apic1; | |
2271 | } | |
2272 | ||
fea5f1e1 LT |
2273 | if (pin1 != -1) { |
2274 | /* | |
2275 | * Ok, does IRQ0 through the IOAPIC work? | |
2276 | */ | |
691874fa MR |
2277 | if (no_pin1) { |
2278 | add_pin_to_irq(0, apic1, pin1); | |
b1b57ee1 | 2279 | setup_timer_IRQ0_pin(apic1, pin1, cfg->vector); |
691874fa | 2280 | } |
fea5f1e1 LT |
2281 | unmask_IO_APIC_irq(0); |
2282 | if (!no_timer_check && timer_irq_works()) { | |
fea5f1e1 | 2283 | if (nmi_watchdog == NMI_IO_APIC) { |
fea5f1e1 LT |
2284 | setup_nmi(); |
2285 | enable_8259A_irq(0); | |
2286 | } | |
2287 | if (disable_timer_pin_1 > 0) | |
2288 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 2289 | goto out; |
fea5f1e1 | 2290 | } |
89027d35 SS |
2291 | if (intr_remapping_enabled) |
2292 | panic("timer doesn't work through Interrupt-remapped IO-APIC"); | |
fea5f1e1 | 2293 | clear_IO_APIC_pin(apic1, pin1); |
691874fa | 2294 | if (!no_pin1) |
49a66a0b | 2295 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
691874fa | 2296 | "8254 timer not connected to IO-APIC\n"); |
1da177e4 | 2297 | |
49a66a0b MR |
2298 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
2299 | "(IRQ0) through the 8259A ...\n"); | |
2300 | apic_printk(APIC_QUIET, KERN_INFO | |
2301 | "..... (found apic %d pin %d) ...\n", apic2, pin2); | |
fea5f1e1 LT |
2302 | /* |
2303 | * legacy devices should be connected to IO APIC #0 | |
2304 | */ | |
0b9f4f49 | 2305 | replace_pin_at_irq(0, apic1, pin1, apic2, pin2); |
f7633ce5 | 2306 | setup_timer_IRQ0_pin(apic2, pin2, cfg->vector); |
24742ece | 2307 | unmask_IO_APIC_irq(0); |
ecd29476 | 2308 | enable_8259A_irq(0); |
fea5f1e1 | 2309 | if (timer_irq_works()) { |
49a66a0b | 2310 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
35542c5e | 2311 | timer_through_8259 = 1; |
fea5f1e1 | 2312 | if (nmi_watchdog == NMI_IO_APIC) { |
60134ebe | 2313 | disable_8259A_irq(0); |
fea5f1e1 | 2314 | setup_nmi(); |
60134ebe | 2315 | enable_8259A_irq(0); |
fea5f1e1 | 2316 | } |
4aae0702 | 2317 | goto out; |
fea5f1e1 LT |
2318 | } |
2319 | /* | |
2320 | * Cleanup, just in case ... | |
2321 | */ | |
ecd29476 | 2322 | disable_8259A_irq(0); |
fea5f1e1 | 2323 | clear_IO_APIC_pin(apic2, pin2); |
49a66a0b | 2324 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
1da177e4 | 2325 | } |
1da177e4 | 2326 | |
1f992153 | 2327 | if (nmi_watchdog == NMI_IO_APIC) { |
49a66a0b MR |
2328 | apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work " |
2329 | "through the IO-APIC - disabling NMI Watchdog!\n"); | |
067fa0ff | 2330 | nmi_watchdog = NMI_NONE; |
1da177e4 LT |
2331 | } |
2332 | ||
49a66a0b MR |
2333 | apic_printk(APIC_QUIET, KERN_INFO |
2334 | "...trying to set up timer as Virtual Wire IRQ...\n"); | |
1da177e4 | 2335 | |
c88ac1df | 2336 | lapic_register_intr(0); |
dfbffdd8 | 2337 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ |
1da177e4 LT |
2338 | enable_8259A_irq(0); |
2339 | ||
2340 | if (timer_irq_works()) { | |
49a66a0b | 2341 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2342 | goto out; |
1da177e4 | 2343 | } |
e67465f1 | 2344 | disable_8259A_irq(0); |
dfbffdd8 | 2345 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
49a66a0b | 2346 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
1da177e4 | 2347 | |
49a66a0b MR |
2348 | apic_printk(APIC_QUIET, KERN_INFO |
2349 | "...trying to set up timer as ExtINT IRQ...\n"); | |
1da177e4 LT |
2350 | |
2351 | init_8259A(0); | |
2352 | make_8259A_irq(0); | |
11a8e778 | 2353 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
2354 | |
2355 | unlock_ExtINT_logic(); | |
2356 | ||
2357 | if (timer_irq_works()) { | |
49a66a0b | 2358 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2359 | goto out; |
1da177e4 | 2360 | } |
49a66a0b MR |
2361 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
2362 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " | |
2363 | "report. Then try booting with the 'noapic' option.\n"); | |
4aae0702 IM |
2364 | out: |
2365 | local_irq_restore(flags); | |
1da177e4 LT |
2366 | } |
2367 | ||
14d98cad AK |
2368 | static int __init notimercheck(char *s) |
2369 | { | |
2370 | no_timer_check = 1; | |
2371 | return 1; | |
2372 | } | |
2373 | __setup("no_timer_check", notimercheck); | |
2374 | ||
1da177e4 | 2375 | /* |
af174783 MR |
2376 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
2377 | * to devices. However there may be an I/O APIC pin available for | |
2378 | * this interrupt regardless. The pin may be left unconnected, but | |
2379 | * typically it will be reused as an ExtINT cascade interrupt for | |
2380 | * the master 8259A. In the MPS case such a pin will normally be | |
2381 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
2382 | * there is no provision for ExtINT interrupts, and in the absence | |
2383 | * of an override it would be treated as an ordinary ISA I/O APIC | |
2384 | * interrupt, that is edge-triggered and unmasked by default. We | |
2385 | * used to do this, but it caused problems on some systems because | |
2386 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
2387 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
2388 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
2389 | * the I/O APIC in all cases now. No actual device should request | |
2390 | * it anyway. --macro | |
1da177e4 LT |
2391 | */ |
2392 | #define PIC_IRQS (1<<2) | |
2393 | ||
2394 | void __init setup_IO_APIC(void) | |
2395 | { | |
1c69524c YL |
2396 | |
2397 | /* | |
2398 | * calling enable_IO_APIC() is moved to setup_local_APIC for BP | |
2399 | */ | |
1da177e4 | 2400 | |
af174783 | 2401 | io_apic_irqs = ~PIC_IRQS; |
1da177e4 LT |
2402 | |
2403 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); | |
2404 | ||
1da177e4 LT |
2405 | sync_Arb_IDs(); |
2406 | setup_IO_APIC_irqs(); | |
2407 | init_IO_APIC_traps(); | |
2408 | check_timer(); | |
1da177e4 LT |
2409 | } |
2410 | ||
2411 | struct sysfs_ioapic_data { | |
2412 | struct sys_device dev; | |
2413 | struct IO_APIC_route_entry entry[0]; | |
2414 | }; | |
2415 | static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS]; | |
2416 | ||
0b9c33a7 | 2417 | static int ioapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
2418 | { |
2419 | struct IO_APIC_route_entry *entry; | |
2420 | struct sysfs_ioapic_data *data; | |
1da177e4 LT |
2421 | int i; |
2422 | ||
2423 | data = container_of(dev, struct sysfs_ioapic_data, dev); | |
2424 | entry = data->entry; | |
eea0e11c AK |
2425 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) |
2426 | *entry = ioapic_read_entry(dev->id, i); | |
1da177e4 LT |
2427 | |
2428 | return 0; | |
2429 | } | |
2430 | ||
2431 | static int ioapic_resume(struct sys_device *dev) | |
2432 | { | |
2433 | struct IO_APIC_route_entry *entry; | |
2434 | struct sysfs_ioapic_data *data; | |
2435 | unsigned long flags; | |
2436 | union IO_APIC_reg_00 reg_00; | |
2437 | int i; | |
2438 | ||
2439 | data = container_of(dev, struct sysfs_ioapic_data, dev); | |
2440 | entry = data->entry; | |
2441 | ||
2442 | spin_lock_irqsave(&ioapic_lock, flags); | |
2443 | reg_00.raw = io_apic_read(dev->id, 0); | |
ec2cd0a2 AS |
2444 | if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) { |
2445 | reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid; | |
1da177e4 LT |
2446 | io_apic_write(dev->id, 0, reg_00.raw); |
2447 | } | |
1da177e4 | 2448 | spin_unlock_irqrestore(&ioapic_lock, flags); |
eea0e11c AK |
2449 | for (i = 0; i < nr_ioapic_registers[dev->id]; i++) |
2450 | ioapic_write_entry(dev->id, i, entry[i]); | |
1da177e4 LT |
2451 | |
2452 | return 0; | |
2453 | } | |
2454 | ||
2455 | static struct sysdev_class ioapic_sysdev_class = { | |
af5ca3f4 | 2456 | .name = "ioapic", |
1da177e4 LT |
2457 | .suspend = ioapic_suspend, |
2458 | .resume = ioapic_resume, | |
2459 | }; | |
2460 | ||
2461 | static int __init ioapic_init_sysfs(void) | |
2462 | { | |
2463 | struct sys_device * dev; | |
cddf7ff7 | 2464 | int i, size, error; |
1da177e4 LT |
2465 | |
2466 | error = sysdev_class_register(&ioapic_sysdev_class); | |
2467 | if (error) | |
2468 | return error; | |
2469 | ||
2470 | for (i = 0; i < nr_ioapics; i++ ) { | |
2471 | size = sizeof(struct sys_device) + nr_ioapic_registers[i] | |
2472 | * sizeof(struct IO_APIC_route_entry); | |
cddf7ff7 | 2473 | mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL); |
1da177e4 LT |
2474 | if (!mp_ioapic_data[i]) { |
2475 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
2476 | continue; | |
2477 | } | |
1da177e4 LT |
2478 | dev = &mp_ioapic_data[i]->dev; |
2479 | dev->id = i; | |
2480 | dev->cls = &ioapic_sysdev_class; | |
2481 | error = sysdev_register(dev); | |
2482 | if (error) { | |
2483 | kfree(mp_ioapic_data[i]); | |
2484 | mp_ioapic_data[i] = NULL; | |
2485 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
2486 | continue; | |
2487 | } | |
2488 | } | |
2489 | ||
2490 | return 0; | |
2491 | } | |
2492 | ||
2493 | device_initcall(ioapic_init_sysfs); | |
2494 | ||
c4fa0bbf | 2495 | /* |
04b9267b | 2496 | * Dynamic irq allocate and deallocation |
c4fa0bbf EB |
2497 | */ |
2498 | int create_irq(void) | |
2499 | { | |
04b9267b EB |
2500 | /* Allocate an unused irq */ |
2501 | int irq; | |
2502 | int new; | |
c4fa0bbf | 2503 | unsigned long flags; |
3ac2de48 | 2504 | struct irq_cfg *cfg_new; |
c4fa0bbf | 2505 | |
04b9267b EB |
2506 | irq = -ENOSPC; |
2507 | spin_lock_irqsave(&vector_lock, flags); | |
0799e432 | 2508 | for (new = (nr_irqs - 1); new >= 0; new--) { |
04b9267b EB |
2509 | if (platform_legacy_irq(new)) |
2510 | continue; | |
3ac2de48 YL |
2511 | cfg_new = irq_cfg(new); |
2512 | if (cfg_new && cfg_new->vector != 0) | |
04b9267b | 2513 | continue; |
3ac2de48 YL |
2514 | /* check if need to create one */ |
2515 | if (!cfg_new) | |
2516 | cfg_new = irq_cfg_alloc(new); | |
dfbffdd8 | 2517 | if (__assign_irq_vector(new, TARGET_CPUS) == 0) |
04b9267b EB |
2518 | irq = new; |
2519 | break; | |
2520 | } | |
2521 | spin_unlock_irqrestore(&vector_lock, flags); | |
c4fa0bbf | 2522 | |
04b9267b | 2523 | if (irq >= 0) { |
c4fa0bbf EB |
2524 | dynamic_irq_init(irq); |
2525 | } | |
2526 | return irq; | |
2527 | } | |
2528 | ||
2529 | void destroy_irq(unsigned int irq) | |
2530 | { | |
2531 | unsigned long flags; | |
c4fa0bbf EB |
2532 | |
2533 | dynamic_irq_cleanup(irq); | |
2534 | ||
75c46fa6 SS |
2535 | #ifdef CONFIG_INTR_REMAP |
2536 | free_irte(irq); | |
2537 | #endif | |
c4fa0bbf | 2538 | spin_lock_irqsave(&vector_lock, flags); |
5df0287e | 2539 | __clear_irq_vector(irq); |
c4fa0bbf EB |
2540 | spin_unlock_irqrestore(&vector_lock, flags); |
2541 | } | |
c4fa0bbf | 2542 | |
589e367f | 2543 | /* |
676b1855 | 2544 | * MSI message composition |
589e367f EB |
2545 | */ |
2546 | #ifdef CONFIG_PCI_MSI | |
3b7d1921 | 2547 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg) |
589e367f | 2548 | { |
3ac2de48 | 2549 | struct irq_cfg *cfg; |
dfbffdd8 | 2550 | int err; |
589e367f | 2551 | unsigned dest; |
c7111c13 | 2552 | cpumask_t tmp; |
589e367f | 2553 | |
dfbffdd8 EB |
2554 | tmp = TARGET_CPUS; |
2555 | err = assign_irq_vector(irq, tmp); | |
75c46fa6 SS |
2556 | if (err) |
2557 | return err; | |
2558 | ||
3ac2de48 | 2559 | cfg = irq_cfg(irq); |
75c46fa6 SS |
2560 | cpus_and(tmp, cfg->domain, tmp); |
2561 | dest = cpu_mask_to_apicid(tmp); | |
2562 | ||
2563 | #ifdef CONFIG_INTR_REMAP | |
2564 | if (irq_remapped(irq)) { | |
2565 | struct irte irte; | |
2566 | int ir_index; | |
2567 | u16 sub_handle; | |
2568 | ||
2569 | ir_index = map_irq_to_irte_handle(irq, &sub_handle); | |
2570 | BUG_ON(ir_index == -1); | |
2571 | ||
2572 | memset (&irte, 0, sizeof(irte)); | |
2573 | ||
2574 | irte.present = 1; | |
2575 | irte.dst_mode = INT_DEST_MODE; | |
2576 | irte.trigger_mode = 0; /* edge */ | |
2577 | irte.dlvry_mode = INT_DELIVERY_MODE; | |
2578 | irte.vector = cfg->vector; | |
2579 | irte.dest_id = IRTE_DEST(dest); | |
2580 | ||
2581 | modify_irte(irq, &irte); | |
589e367f | 2582 | |
75c46fa6 SS |
2583 | msg->address_hi = MSI_ADDR_BASE_HI; |
2584 | msg->data = sub_handle; | |
2585 | msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT | | |
2586 | MSI_ADDR_IR_SHV | | |
2587 | MSI_ADDR_IR_INDEX1(ir_index) | | |
2588 | MSI_ADDR_IR_INDEX2(ir_index); | |
2589 | } else | |
2590 | #endif | |
2591 | { | |
589e367f EB |
2592 | msg->address_hi = MSI_ADDR_BASE_HI; |
2593 | msg->address_lo = | |
2594 | MSI_ADDR_BASE_LO | | |
2595 | ((INT_DEST_MODE == 0) ? | |
2596 | MSI_ADDR_DEST_MODE_PHYSICAL: | |
2597 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
2598 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
2599 | MSI_ADDR_REDIRECTION_CPU: | |
2600 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
2601 | MSI_ADDR_DEST_ID(dest); | |
2602 | ||
2603 | msg->data = | |
2604 | MSI_DATA_TRIGGER_EDGE | | |
2605 | MSI_DATA_LEVEL_ASSERT | | |
2606 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
2607 | MSI_DATA_DELIVERY_FIXED: | |
2608 | MSI_DATA_DELIVERY_LOWPRI) | | |
dfbffdd8 | 2609 | MSI_DATA_VECTOR(cfg->vector); |
589e367f | 2610 | } |
dfbffdd8 | 2611 | return err; |
589e367f EB |
2612 | } |
2613 | ||
3b7d1921 EB |
2614 | #ifdef CONFIG_SMP |
2615 | static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask) | |
589e367f | 2616 | { |
3ac2de48 | 2617 | struct irq_cfg *cfg; |
3b7d1921 EB |
2618 | struct msi_msg msg; |
2619 | unsigned int dest; | |
2620 | cpumask_t tmp; | |
08678b08 | 2621 | struct irq_desc *desc; |
3b7d1921 EB |
2622 | |
2623 | cpus_and(tmp, mask, cpu_online_map); | |
2624 | if (cpus_empty(tmp)) | |
5ff5115e | 2625 | return; |
589e367f | 2626 | |
dfbffdd8 | 2627 | if (assign_irq_vector(irq, mask)) |
3b7d1921 | 2628 | return; |
550f2299 | 2629 | |
3ac2de48 | 2630 | cfg = irq_cfg(irq); |
dfbffdd8 | 2631 | cpus_and(tmp, cfg->domain, mask); |
3b7d1921 | 2632 | dest = cpu_mask_to_apicid(tmp); |
589e367f | 2633 | |
3b7d1921 EB |
2634 | read_msi_msg(irq, &msg); |
2635 | ||
2636 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
dfbffdd8 | 2637 | msg.data |= MSI_DATA_VECTOR(cfg->vector); |
3b7d1921 EB |
2638 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; |
2639 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
2640 | ||
2641 | write_msi_msg(irq, &msg); | |
08678b08 YL |
2642 | desc = irq_to_desc(irq); |
2643 | desc->affinity = mask; | |
589e367f | 2644 | } |
75c46fa6 SS |
2645 | |
2646 | #ifdef CONFIG_INTR_REMAP | |
2647 | /* | |
2648 | * Migrate the MSI irq to another cpumask. This migration is | |
2649 | * done in the process context using interrupt-remapping hardware. | |
2650 | */ | |
2651 | static void ir_set_msi_irq_affinity(unsigned int irq, cpumask_t mask) | |
2652 | { | |
3ac2de48 | 2653 | struct irq_cfg *cfg; |
75c46fa6 SS |
2654 | unsigned int dest; |
2655 | cpumask_t tmp, cleanup_mask; | |
2656 | struct irte irte; | |
08678b08 | 2657 | struct irq_desc *desc; |
75c46fa6 SS |
2658 | |
2659 | cpus_and(tmp, mask, cpu_online_map); | |
2660 | if (cpus_empty(tmp)) | |
2661 | return; | |
2662 | ||
2663 | if (get_irte(irq, &irte)) | |
2664 | return; | |
2665 | ||
2666 | if (assign_irq_vector(irq, mask)) | |
2667 | return; | |
2668 | ||
3ac2de48 | 2669 | cfg = irq_cfg(irq); |
75c46fa6 SS |
2670 | cpus_and(tmp, cfg->domain, mask); |
2671 | dest = cpu_mask_to_apicid(tmp); | |
2672 | ||
2673 | irte.vector = cfg->vector; | |
2674 | irte.dest_id = IRTE_DEST(dest); | |
2675 | ||
2676 | /* | |
2677 | * atomically update the IRTE with the new destination and vector. | |
2678 | */ | |
2679 | modify_irte(irq, &irte); | |
2680 | ||
2681 | /* | |
2682 | * After this point, all the interrupts will start arriving | |
2683 | * at the new destination. So, time to cleanup the previous | |
2684 | * vector allocation. | |
2685 | */ | |
2686 | if (cfg->move_in_progress) { | |
2687 | cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map); | |
2688 | cfg->move_cleanup_count = cpus_weight(cleanup_mask); | |
2689 | send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); | |
2690 | cfg->move_in_progress = 0; | |
2691 | } | |
2692 | ||
08678b08 YL |
2693 | desc = irq_to_desc(irq); |
2694 | desc->affinity = mask; | |
75c46fa6 SS |
2695 | } |
2696 | #endif | |
3b7d1921 | 2697 | #endif /* CONFIG_SMP */ |
589e367f | 2698 | |
3b7d1921 EB |
2699 | /* |
2700 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
2701 | * which implement the MSI or MSI-X Capability Structure. | |
2702 | */ | |
2703 | static struct irq_chip msi_chip = { | |
2704 | .name = "PCI-MSI", | |
2705 | .unmask = unmask_msi_irq, | |
2706 | .mask = mask_msi_irq, | |
2707 | .ack = ack_apic_edge, | |
2708 | #ifdef CONFIG_SMP | |
2709 | .set_affinity = set_msi_irq_affinity, | |
2710 | #endif | |
2711 | .retrigger = ioapic_retrigger_irq, | |
589e367f EB |
2712 | }; |
2713 | ||
75c46fa6 SS |
2714 | #ifdef CONFIG_INTR_REMAP |
2715 | static struct irq_chip msi_ir_chip = { | |
2716 | .name = "IR-PCI-MSI", | |
2717 | .unmask = unmask_msi_irq, | |
2718 | .mask = mask_msi_irq, | |
2719 | .ack = ack_x2apic_edge, | |
2720 | #ifdef CONFIG_SMP | |
2721 | .set_affinity = ir_set_msi_irq_affinity, | |
2722 | #endif | |
2723 | .retrigger = ioapic_retrigger_irq, | |
2724 | }; | |
2725 | ||
2726 | /* | |
2727 | * Map the PCI dev to the corresponding remapping hardware unit | |
2728 | * and allocate 'nvec' consecutive interrupt-remapping table entries | |
2729 | * in it. | |
2730 | */ | |
2731 | static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec) | |
3b7d1921 | 2732 | { |
75c46fa6 SS |
2733 | struct intel_iommu *iommu; |
2734 | int index; | |
2735 | ||
2736 | iommu = map_dev_to_ir(dev); | |
2737 | if (!iommu) { | |
2738 | printk(KERN_ERR | |
2739 | "Unable to map PCI %s to iommu\n", pci_name(dev)); | |
2740 | return -ENOENT; | |
2741 | } | |
2742 | ||
2743 | index = alloc_irte(iommu, irq, nvec); | |
2744 | if (index < 0) { | |
2745 | printk(KERN_ERR | |
2746 | "Unable to allocate %d IRTE for PCI %s\n", nvec, | |
2747 | pci_name(dev)); | |
2748 | return -ENOSPC; | |
2749 | } | |
2750 | return index; | |
2751 | } | |
2752 | #endif | |
2753 | ||
2754 | static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc, int irq) | |
2755 | { | |
2756 | int ret; | |
3b7d1921 | 2757 | struct msi_msg msg; |
75c46fa6 SS |
2758 | |
2759 | ret = msi_compose_msg(dev, irq, &msg); | |
2760 | if (ret < 0) | |
2761 | return ret; | |
2762 | ||
2763 | set_irq_msi(irq, desc); | |
2764 | write_msi_msg(irq, &msg); | |
2765 | ||
2766 | #ifdef CONFIG_INTR_REMAP | |
2767 | if (irq_remapped(irq)) { | |
08678b08 | 2768 | struct irq_desc *desc = irq_to_desc(irq); |
75c46fa6 SS |
2769 | /* |
2770 | * irq migration in process context | |
2771 | */ | |
2772 | desc->status |= IRQ_MOVE_PCNTXT; | |
2773 | set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge"); | |
2774 | } else | |
2775 | #endif | |
2776 | set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge"); | |
2777 | ||
2778 | return 0; | |
2779 | } | |
2780 | ||
2781 | int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) | |
2782 | { | |
f7feaca7 | 2783 | int irq, ret; |
75c46fa6 | 2784 | |
f7feaca7 EB |
2785 | irq = create_irq(); |
2786 | if (irq < 0) | |
2787 | return irq; | |
2788 | ||
75c46fa6 SS |
2789 | #ifdef CONFIG_INTR_REMAP |
2790 | if (!intr_remapping_enabled) | |
2791 | goto no_ir; | |
2792 | ||
2793 | ret = msi_alloc_irte(dev, irq, 1); | |
2794 | if (ret < 0) | |
2795 | goto error; | |
2796 | no_ir: | |
2797 | #endif | |
2798 | ret = setup_msi_irq(dev, desc, irq); | |
f7feaca7 EB |
2799 | if (ret < 0) { |
2800 | destroy_irq(irq); | |
3b7d1921 | 2801 | return ret; |
f7feaca7 | 2802 | } |
75c46fa6 | 2803 | return 0; |
3b7d1921 | 2804 | |
75c46fa6 SS |
2805 | #ifdef CONFIG_INTR_REMAP |
2806 | error: | |
2807 | destroy_irq(irq); | |
2808 | return ret; | |
2809 | #endif | |
2810 | } | |
3b7d1921 | 2811 | |
75c46fa6 SS |
2812 | int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
2813 | { | |
2814 | int irq, ret, sub_handle; | |
2815 | struct msi_desc *desc; | |
2816 | #ifdef CONFIG_INTR_REMAP | |
2817 | struct intel_iommu *iommu = 0; | |
2818 | int index = 0; | |
2819 | #endif | |
2820 | ||
2821 | sub_handle = 0; | |
2822 | list_for_each_entry(desc, &dev->msi_list, list) { | |
2823 | irq = create_irq(); | |
2824 | if (irq < 0) | |
2825 | return irq; | |
2826 | #ifdef CONFIG_INTR_REMAP | |
2827 | if (!intr_remapping_enabled) | |
2828 | goto no_ir; | |
3b7d1921 | 2829 | |
75c46fa6 SS |
2830 | if (!sub_handle) { |
2831 | /* | |
2832 | * allocate the consecutive block of IRTE's | |
2833 | * for 'nvec' | |
2834 | */ | |
2835 | index = msi_alloc_irte(dev, irq, nvec); | |
2836 | if (index < 0) { | |
2837 | ret = index; | |
2838 | goto error; | |
2839 | } | |
2840 | } else { | |
2841 | iommu = map_dev_to_ir(dev); | |
2842 | if (!iommu) { | |
2843 | ret = -ENOENT; | |
2844 | goto error; | |
2845 | } | |
2846 | /* | |
2847 | * setup the mapping between the irq and the IRTE | |
2848 | * base index, the sub_handle pointing to the | |
2849 | * appropriate interrupt remap table entry. | |
2850 | */ | |
2851 | set_irte_irq(irq, iommu, index, sub_handle); | |
2852 | } | |
2853 | no_ir: | |
2854 | #endif | |
2855 | ret = setup_msi_irq(dev, desc, irq); | |
2856 | if (ret < 0) | |
2857 | goto error; | |
2858 | sub_handle++; | |
2859 | } | |
7fe3730d | 2860 | return 0; |
75c46fa6 SS |
2861 | |
2862 | error: | |
2863 | destroy_irq(irq); | |
2864 | return ret; | |
3b7d1921 EB |
2865 | } |
2866 | ||
2867 | void arch_teardown_msi_irq(unsigned int irq) | |
2868 | { | |
f7feaca7 | 2869 | destroy_irq(irq); |
3b7d1921 EB |
2870 | } |
2871 | ||
3460a6d9 KA |
2872 | #ifdef CONFIG_DMAR |
2873 | #ifdef CONFIG_SMP | |
2874 | static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask) | |
2875 | { | |
3ac2de48 | 2876 | struct irq_cfg *cfg; |
3460a6d9 KA |
2877 | struct msi_msg msg; |
2878 | unsigned int dest; | |
2879 | cpumask_t tmp; | |
08678b08 | 2880 | struct irq_desc *desc; |
3460a6d9 KA |
2881 | |
2882 | cpus_and(tmp, mask, cpu_online_map); | |
2883 | if (cpus_empty(tmp)) | |
2884 | return; | |
2885 | ||
2886 | if (assign_irq_vector(irq, mask)) | |
2887 | return; | |
2888 | ||
3ac2de48 | 2889 | cfg = irq_cfg(irq); |
3460a6d9 KA |
2890 | cpus_and(tmp, cfg->domain, mask); |
2891 | dest = cpu_mask_to_apicid(tmp); | |
2892 | ||
2893 | dmar_msi_read(irq, &msg); | |
2894 | ||
2895 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
2896 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
2897 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
2898 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
2899 | ||
2900 | dmar_msi_write(irq, &msg); | |
08678b08 YL |
2901 | desc = irq_to_desc(irq); |
2902 | desc->affinity = mask; | |
3460a6d9 KA |
2903 | } |
2904 | #endif /* CONFIG_SMP */ | |
2905 | ||
2906 | struct irq_chip dmar_msi_type = { | |
2907 | .name = "DMAR_MSI", | |
2908 | .unmask = dmar_msi_unmask, | |
2909 | .mask = dmar_msi_mask, | |
2910 | .ack = ack_apic_edge, | |
2911 | #ifdef CONFIG_SMP | |
2912 | .set_affinity = dmar_msi_set_affinity, | |
2913 | #endif | |
2914 | .retrigger = ioapic_retrigger_irq, | |
2915 | }; | |
2916 | ||
2917 | int arch_setup_dmar_msi(unsigned int irq) | |
2918 | { | |
2919 | int ret; | |
2920 | struct msi_msg msg; | |
2921 | ||
2922 | ret = msi_compose_msg(NULL, irq, &msg); | |
2923 | if (ret < 0) | |
2924 | return ret; | |
2925 | dmar_msi_write(irq, &msg); | |
2926 | set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, | |
2927 | "edge"); | |
2928 | return 0; | |
2929 | } | |
2930 | #endif | |
589e367f | 2931 | |
3460a6d9 | 2932 | #endif /* CONFIG_PCI_MSI */ |
8b955b0d EB |
2933 | /* |
2934 | * Hypertransport interrupt support | |
2935 | */ | |
2936 | #ifdef CONFIG_HT_IRQ | |
2937 | ||
2938 | #ifdef CONFIG_SMP | |
2939 | ||
2940 | static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) | |
2941 | { | |
ec68307c EB |
2942 | struct ht_irq_msg msg; |
2943 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 2944 | |
ec68307c EB |
2945 | msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); |
2946 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); | |
8b955b0d | 2947 | |
ec68307c EB |
2948 | msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); |
2949 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); | |
8b955b0d | 2950 | |
ec68307c | 2951 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
2952 | } |
2953 | ||
2954 | static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask) | |
2955 | { | |
3ac2de48 | 2956 | struct irq_cfg *cfg; |
8b955b0d EB |
2957 | unsigned int dest; |
2958 | cpumask_t tmp; | |
08678b08 | 2959 | struct irq_desc *desc; |
8b955b0d EB |
2960 | |
2961 | cpus_and(tmp, mask, cpu_online_map); | |
2962 | if (cpus_empty(tmp)) | |
5ff5115e | 2963 | return; |
8b955b0d | 2964 | |
dfbffdd8 | 2965 | if (assign_irq_vector(irq, mask)) |
8b955b0d EB |
2966 | return; |
2967 | ||
3ac2de48 | 2968 | cfg = irq_cfg(irq); |
dfbffdd8 | 2969 | cpus_and(tmp, cfg->domain, mask); |
8b955b0d EB |
2970 | dest = cpu_mask_to_apicid(tmp); |
2971 | ||
dfbffdd8 | 2972 | target_ht_irq(irq, dest, cfg->vector); |
08678b08 YL |
2973 | desc = irq_to_desc(irq); |
2974 | desc->affinity = mask; | |
8b955b0d EB |
2975 | } |
2976 | #endif | |
2977 | ||
c37e108d | 2978 | static struct irq_chip ht_irq_chip = { |
8b955b0d EB |
2979 | .name = "PCI-HT", |
2980 | .mask = mask_ht_irq, | |
2981 | .unmask = unmask_ht_irq, | |
2982 | .ack = ack_apic_edge, | |
2983 | #ifdef CONFIG_SMP | |
2984 | .set_affinity = set_ht_irq_affinity, | |
2985 | #endif | |
2986 | .retrigger = ioapic_retrigger_irq, | |
2987 | }; | |
2988 | ||
2989 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
2990 | { | |
3ac2de48 | 2991 | struct irq_cfg *cfg; |
dfbffdd8 | 2992 | int err; |
c7111c13 | 2993 | cpumask_t tmp; |
8b955b0d | 2994 | |
dfbffdd8 EB |
2995 | tmp = TARGET_CPUS; |
2996 | err = assign_irq_vector(irq, tmp); | |
2997 | if (!err) { | |
ec68307c | 2998 | struct ht_irq_msg msg; |
8b955b0d | 2999 | unsigned dest; |
8b955b0d | 3000 | |
3ac2de48 | 3001 | cfg = irq_cfg(irq); |
dfbffdd8 | 3002 | cpus_and(tmp, cfg->domain, tmp); |
8b955b0d EB |
3003 | dest = cpu_mask_to_apicid(tmp); |
3004 | ||
ec68307c | 3005 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3006 | |
ec68307c EB |
3007 | msg.address_lo = |
3008 | HT_IRQ_LOW_BASE | | |
8b955b0d | 3009 | HT_IRQ_LOW_DEST_ID(dest) | |
dfbffdd8 | 3010 | HT_IRQ_LOW_VECTOR(cfg->vector) | |
8b955b0d EB |
3011 | ((INT_DEST_MODE == 0) ? |
3012 | HT_IRQ_LOW_DM_PHYSICAL : | |
3013 | HT_IRQ_LOW_DM_LOGICAL) | | |
3014 | HT_IRQ_LOW_RQEOI_EDGE | | |
3015 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
3016 | HT_IRQ_LOW_MT_FIXED : | |
ec68307c EB |
3017 | HT_IRQ_LOW_MT_ARBITRATED) | |
3018 | HT_IRQ_LOW_IRQ_MASKED; | |
8b955b0d | 3019 | |
ec68307c | 3020 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 3021 | |
a460e745 IM |
3022 | set_irq_chip_and_handler_name(irq, &ht_irq_chip, |
3023 | handle_edge_irq, "edge"); | |
8b955b0d | 3024 | } |
dfbffdd8 | 3025 | return err; |
8b955b0d EB |
3026 | } |
3027 | #endif /* CONFIG_HT_IRQ */ | |
3028 | ||
1da177e4 LT |
3029 | /* -------------------------------------------------------------------------- |
3030 | ACPI-based IOAPIC Configuration | |
3031 | -------------------------------------------------------------------------- */ | |
3032 | ||
888ba6c6 | 3033 | #ifdef CONFIG_ACPI |
1da177e4 LT |
3034 | |
3035 | #define IO_APIC_MAX_ID 0xFE | |
3036 | ||
1da177e4 LT |
3037 | int __init io_apic_get_redir_entries (int ioapic) |
3038 | { | |
3039 | union IO_APIC_reg_01 reg_01; | |
3040 | unsigned long flags; | |
3041 | ||
3042 | spin_lock_irqsave(&ioapic_lock, flags); | |
3043 | reg_01.raw = io_apic_read(ioapic, 1); | |
3044 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3045 | ||
3046 | return reg_01.bits.entries; | |
3047 | } | |
3048 | ||
3049 | ||
50eca3eb | 3050 | int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity) |
1da177e4 | 3051 | { |
1da177e4 LT |
3052 | if (!IO_APIC_IRQ(irq)) { |
3053 | apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", | |
3054 | ioapic); | |
3055 | return -EINVAL; | |
3056 | } | |
3057 | ||
550f2299 EB |
3058 | /* |
3059 | * IRQs < 16 are already in the irq_2_pin[] map | |
3060 | */ | |
3061 | if (irq >= 16) | |
3062 | add_pin_to_irq(irq, ioapic, pin); | |
3063 | ||
a8c8a367 | 3064 | setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity); |
1da177e4 LT |
3065 | |
3066 | return 0; | |
3067 | } | |
3068 | ||
1da177e4 | 3069 | |
61fd47e0 SL |
3070 | int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity) |
3071 | { | |
3072 | int i; | |
3073 | ||
3074 | if (skip_ioapic_setup) | |
3075 | return -1; | |
3076 | ||
3077 | for (i = 0; i < mp_irq_entries; i++) | |
2fddb6e2 AS |
3078 | if (mp_irqs[i].mp_irqtype == mp_INT && |
3079 | mp_irqs[i].mp_srcbusirq == bus_irq) | |
61fd47e0 SL |
3080 | break; |
3081 | if (i >= mp_irq_entries) | |
3082 | return -1; | |
3083 | ||
3084 | *trigger = irq_trigger(i); | |
3085 | *polarity = irq_polarity(i); | |
3086 | return 0; | |
3087 | } | |
3088 | ||
3089 | #endif /* CONFIG_ACPI */ | |
1da177e4 LT |
3090 | |
3091 | /* | |
3092 | * This function currently is only a helper for the i386 smp boot process where | |
3093 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
3094 | * so mask in all cases should simply be TARGET_CPUS | |
3095 | */ | |
54d5d424 | 3096 | #ifdef CONFIG_SMP |
1da177e4 LT |
3097 | void __init setup_ioapic_dest(void) |
3098 | { | |
3099 | int pin, ioapic, irq, irq_entry; | |
3ac2de48 | 3100 | struct irq_cfg *cfg; |
1da177e4 LT |
3101 | |
3102 | if (skip_ioapic_setup == 1) | |
3103 | return; | |
3104 | ||
3105 | for (ioapic = 0; ioapic < nr_ioapics; ioapic++) { | |
3106 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { | |
3107 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); | |
3108 | if (irq_entry == -1) | |
3109 | continue; | |
3110 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
ad892f5e YL |
3111 | |
3112 | /* setup_IO_APIC_irqs could fail to get vector for some device | |
3113 | * when you have too many devices, because at that time only boot | |
3114 | * cpu is online. | |
3115 | */ | |
3ac2de48 YL |
3116 | cfg = irq_cfg(irq); |
3117 | if (!cfg->vector) | |
a8c8a367 EB |
3118 | setup_IO_APIC_irq(ioapic, pin, irq, |
3119 | irq_trigger(irq_entry), | |
3120 | irq_polarity(irq_entry)); | |
89027d35 SS |
3121 | #ifdef CONFIG_INTR_REMAP |
3122 | else if (intr_remapping_enabled) | |
3123 | set_ir_ioapic_affinity_irq(irq, TARGET_CPUS); | |
3124 | #endif | |
ad892f5e YL |
3125 | else |
3126 | set_ioapic_affinity_irq(irq, TARGET_CPUS); | |
1da177e4 LT |
3127 | } |
3128 | ||
3129 | } | |
3130 | } | |
54d5d424 | 3131 | #endif |
61fd47e0 | 3132 | |
3e35a0e5 TG |
3133 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
3134 | ||
3135 | static struct resource *ioapic_resources; | |
3136 | ||
3137 | static struct resource * __init ioapic_setup_resources(void) | |
3138 | { | |
3139 | unsigned long n; | |
3140 | struct resource *res; | |
3141 | char *mem; | |
3142 | int i; | |
3143 | ||
3144 | if (nr_ioapics <= 0) | |
3145 | return NULL; | |
3146 | ||
3147 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); | |
3148 | n *= nr_ioapics; | |
3149 | ||
3150 | mem = alloc_bootmem(n); | |
3151 | res = (void *)mem; | |
3152 | ||
3153 | if (mem != NULL) { | |
3e35a0e5 TG |
3154 | mem += sizeof(struct resource) * nr_ioapics; |
3155 | ||
3156 | for (i = 0; i < nr_ioapics; i++) { | |
3157 | res[i].name = mem; | |
3158 | res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
3159 | sprintf(mem, "IOAPIC %u", i); | |
3160 | mem += IOAPIC_RESOURCE_NAME_SIZE; | |
3161 | } | |
3162 | } | |
3163 | ||
3164 | ioapic_resources = res; | |
3165 | ||
3166 | return res; | |
3167 | } | |
3168 | ||
3169 | void __init ioapic_init_mappings(void) | |
3170 | { | |
3171 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
3172 | struct resource *ioapic_res; | |
3173 | int i; | |
3174 | ||
3175 | ioapic_res = ioapic_setup_resources(); | |
3176 | for (i = 0; i < nr_ioapics; i++) { | |
3177 | if (smp_found_config) { | |
ec2cd0a2 | 3178 | ioapic_phys = mp_ioapics[i].mp_apicaddr; |
3e35a0e5 TG |
3179 | } else { |
3180 | ioapic_phys = (unsigned long) | |
3181 | alloc_bootmem_pages(PAGE_SIZE); | |
3182 | ioapic_phys = __pa(ioapic_phys); | |
3183 | } | |
3184 | set_fixmap_nocache(idx, ioapic_phys); | |
3185 | apic_printk(APIC_VERBOSE, | |
3186 | "mapped IOAPIC to %016lx (%016lx)\n", | |
3187 | __fix_to_virt(idx), ioapic_phys); | |
3188 | idx++; | |
3189 | ||
3190 | if (ioapic_res != NULL) { | |
3191 | ioapic_res->start = ioapic_phys; | |
3192 | ioapic_res->end = ioapic_phys + (4 * 1024) - 1; | |
3193 | ioapic_res++; | |
3194 | } | |
3195 | } | |
3196 | } | |
3197 | ||
3198 | static int __init ioapic_insert_resources(void) | |
3199 | { | |
3200 | int i; | |
3201 | struct resource *r = ioapic_resources; | |
3202 | ||
3203 | if (!r) { | |
3204 | printk(KERN_ERR | |
3205 | "IO APIC resources could be not be allocated.\n"); | |
3206 | return -1; | |
3207 | } | |
3208 | ||
3209 | for (i = 0; i < nr_ioapics; i++) { | |
3210 | insert_resource(&iomem_resource, r); | |
3211 | r++; | |
3212 | } | |
3213 | ||
3214 | return 0; | |
3215 | } | |
3216 | ||
3217 | /* Insert the IO APIC resources after PCI initialization has occured to handle | |
3218 | * IO APICS that are mapped in on a BAR in PCI space. */ | |
3219 | late_initcall(ioapic_insert_resources); | |
3220 |