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x86: use 28 bits irq NR for pci msi/msix and ht
[deliverable/linux.git] / arch / x86 / kernel / io_apic_64.c
CommitLineData
1da177e4
LT		 1/*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23#include <linux/mm.h>
1da177e4
LT		 24#include <linux/interrupt.h>
25#include <linux/init.h>
26#include <linux/delay.h>
27#include <linux/sched.h>
589e367f 28#include <linux/pci.h>
1da177e4
LT		 29#include <linux/mc146818rtc.h>
30#include <linux/acpi.h>
31#include <linux/sysdev.h>
3b7d1921 32#include <linux/msi.h>
95d77884 33#include <linux/htirq.h>
3460a6d9 34#include <linux/dmar.h>
1d16b53e 35#include <linux/jiffies.h>
ab688059
AK		 36#ifdef CONFIG_ACPI
37#include <acpi/acpi_bus.h>
38#endif
3e35a0e5 39#include <linux/bootmem.h>
89027d35 40#include <linux/dmar.h>
1da177e4 41
61014292 42#include <asm/idle.h>
1da177e4
LT		 43#include <asm/io.h>
44#include <asm/smp.h>
45#include <asm/desc.h>
46#include <asm/proto.h>
8d916406 47#include <asm/acpi.h>
ca8642f6 48#include <asm/dma.h>
17c44697 49#include <asm/i8259.h>
3e4ff115 50#include <asm/nmi.h>
589e367f 51#include <asm/msidef.h>
8b955b0d 52#include <asm/hypertransport.h>
89027d35 53#include <asm/irq_remapping.h>
1da177e4 54
5af5573e 55#include <mach_ipi.h>
dd46e3ca 56#include <mach_apic.h>
5af5573e 57
32f71aff
MR		 58#define __apicdebuginit(type) static type __init
59
3ac2de48 60struct irq_cfg;
e5a53714 61struct irq_pin_list;
13a79503 62struct irq_cfg {
3ac2de48
YL		 63 unsigned int irq;
64 struct irq_cfg *next;
e5a53714 65 struct irq_pin_list *irq_2_pin;
13a79503 66 cpumask_t domain;
61014292
EB		 67 cpumask_t old_domain;
68 unsigned move_cleanup_count;
13a79503 69 u8 vector;
61014292 70 u8 move_in_progress : 1;
13a79503
EB		 71};
72
73/* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
301e6190 74static struct irq_cfg irq_cfg_legacy[] __initdata = {
3ac2de48
YL		 75 [0] = { .irq = 0, .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
76 [1] = { .irq = 1, .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
77 [2] = { .irq = 2, .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
78 [3] = { .irq = 3, .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
79 [4] = { .irq = 4, .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
80 [5] = { .irq = 5, .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
81 [6] = { .irq = 6, .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
82 [7] = { .irq = 7, .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
83 [8] = { .irq = 8, .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
84 [9] = { .irq = 9, .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
85 [10] = { .irq = 10, .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
86 [11] = { .irq = 11, .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
87 [12] = { .irq = 12, .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
88 [13] = { .irq = 13, .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
89 [14] = { .irq = 14, .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
90 [15] = { .irq = 15, .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
13a79503
EB		 91};
92
3ac2de48
YL		 93static struct irq_cfg irq_cfg_init = { .irq = -1U, };
94/* need to be biger than size of irq_cfg_legacy */
95static int nr_irq_cfg = 32;
96
97static int __init parse_nr_irq_cfg(char *arg)
98{
99 if (arg) {
100 nr_irq_cfg = simple_strtoul(arg, NULL, 0);
101 if (nr_irq_cfg < 32)
102 nr_irq_cfg = 32;
103 }
104 return 0;
105}
106
107early_param("nr_irq_cfg", parse_nr_irq_cfg);
108
109static void init_one_irq_cfg(struct irq_cfg *cfg)
110{
111 memcpy(cfg, &irq_cfg_init, sizeof(struct irq_cfg));
112}
301e6190 113
a2f9f438
YL		 114static struct irq_cfg *irq_cfgx;
115static struct irq_cfg *irq_cfgx_free;
301e6190
YL		 116static void __init init_work(void *data)
117{
118 struct dyn_array *da = data;
3ac2de48 119 struct irq_cfg *cfg;
a2f9f438 120 int legacy_count;
3ac2de48 121 int i;
301e6190 122
3ac2de48
YL		 123 cfg = *da->name;
124
125 memcpy(cfg, irq_cfg_legacy, sizeof(irq_cfg_legacy));
126
a2f9f438
YL		 127 legacy_count = sizeof(irq_cfg_legacy)/sizeof(irq_cfg_legacy[0]);
128 for (i = legacy_count; i < *da->nr; i++)
3ac2de48
YL		 129 init_one_irq_cfg(&cfg[i]);
130
131 for (i = 1; i < *da->nr; i++)
132 cfg[i-1].next = &cfg[i];
a2f9f438
YL		 133
134 irq_cfgx_free = &irq_cfgx[legacy_count];
135 irq_cfgx[legacy_count - 1].next = NULL;
301e6190
YL		 136}
137
46b8214d 138#define for_each_irq_cfg(cfg) \
a2f9f438 139 for (cfg = irq_cfgx; cfg; cfg = cfg->next)
46b8214d 140
3ac2de48
YL		 141DEFINE_DYN_ARRAY(irq_cfgx, sizeof(struct irq_cfg), nr_irq_cfg, PAGE_SIZE, init_work);
142
143static struct irq_cfg *irq_cfg(unsigned int irq)
144{
145 struct irq_cfg *cfg;
146
a2f9f438 147 cfg = irq_cfgx;
3ac2de48
YL		 148 while (cfg) {
149 if (cfg->irq == irq)
150 return cfg;
151
3ac2de48
YL		 152 cfg = cfg->next;
153 }
154
155 return NULL;
156}
157
158static struct irq_cfg *irq_cfg_alloc(unsigned int irq)
159{
160 struct irq_cfg *cfg, *cfg_pri;
161 int i;
162 int count = 0;
163
a2f9f438 164 cfg_pri = cfg = irq_cfgx;
3ac2de48
YL		 165 while (cfg) {
166 if (cfg->irq == irq)
167 return cfg;
168
3ac2de48
YL		 169 cfg_pri = cfg;
170 cfg = cfg->next;
171 count++;
172 }
173
a2f9f438
YL		 174 if (!irq_cfgx_free) {
175 unsigned long phys;
176 unsigned long total_bytes;
177 /*
178 * we run out of pre-allocate ones, allocate more
179 */
180 printk(KERN_DEBUG "try to get more irq_cfg %d\n", nr_irq_cfg);
3ac2de48 181
a2f9f438
YL		 182 total_bytes = sizeof(struct irq_cfg) * nr_irq_cfg;
183 if (after_bootmem)
184 cfg = kzalloc(total_bytes, GFP_ATOMIC);
185 else
186 cfg = __alloc_bootmem_nopanic(total_bytes, PAGE_SIZE, 0);
3ac2de48 187
a2f9f438
YL		 188 if (!cfg)
189 panic("please boot with nr_irq_cfg= %d\n", count * 2);
3ac2de48 190
a2f9f438
YL		 191 phys = __pa(cfg);
192 printk(KERN_DEBUG "irq_irq ==> [%#lx - %#lx]\n", phys, phys + total_bytes);
3ac2de48 193
a2f9f438
YL		 194 for (i = 0; i < nr_irq_cfg; i++)
195 init_one_irq_cfg(&cfg[i]);
3ac2de48 196
a2f9f438
YL		 197 for (i = 1; i < nr_irq_cfg; i++)
198 cfg[i-1].next = &cfg[i];
3ac2de48 199
a2f9f438
YL		 200 irq_cfgx_free = cfg;
201 }
202
203 cfg = irq_cfgx_free;
204 irq_cfgx_free = irq_cfgx_free->next;
205 cfg->next = NULL;
206 if (cfg_pri)
207 cfg_pri->next = cfg;
208 else
209 irq_cfgx = cfg;
210 cfg->irq = irq;
211 printk(KERN_DEBUG "found new irq_cfg for irq %d\n", cfg->irq);
212#ifdef CONFIG_HAVE_SPARSE_IRQ_DEBUG
213 {
214 /* dump the results */
215 struct irq_cfg *cfg;
216 unsigned long phys;
217 unsigned long bytes = sizeof(struct irq_cfg);
218
219 printk(KERN_DEBUG "=========================== %d\n", irq);
220 printk(KERN_DEBUG "irq_cfg dump after get that for %d\n", irq);
221 for_each_irq_cfg(cfg) {
222 phys = __pa(cfg);
223 printk(KERN_DEBUG "irq_cfg %d ==> [%#lx - %#lx]\n", cfg->irq, phys, phys + bytes);
224 }
225 printk(KERN_DEBUG "===========================\n");
226 }
227#endif
3ac2de48
YL		 228 return cfg;
229}
301e6190 230
dfbffdd8 231static int assign_irq_vector(int irq, cpumask_t mask);
04b9267b 232
305b92a2
AM		 233int first_system_vector = 0xfe;
234
235char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE};
236
1da177e4
LT		 237int sis_apic_bug; /* not actually supported, dummy for compile */
238
14d98cad
AK		 239static int no_timer_check;
240
fea5f1e1
LT		 241static int disable_timer_pin_1 __initdata;
242
35542c5e 243int timer_through_8259 __initdata;
fea5f1e1 244
1008fddc
EB		 245/* Where if anywhere is the i8259 connect in external int mode */
246static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
247
1da177e4 248static DEFINE_SPINLOCK(ioapic_lock);
d388e5fd 249static DEFINE_SPINLOCK(vector_lock);
1da177e4
LT		 250
251/*
252 * # of IRQ routing registers
253 */
254int nr_ioapic_registers[MAX_IO_APICS];
255
4dc2f96c
SS		 256/* I/O APIC RTE contents at the OS boot up */
257struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS];
258
9c7408f3 259/* I/O APIC entries */
ec2cd0a2 260struct mp_config_ioapic mp_ioapics[MAX_IO_APICS];
9c7408f3
AS		 261int nr_ioapics;
262
350bae1d 263/* MP IRQ source entries */
2fddb6e2 264struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
350bae1d
AS		 265
266/* # of MP IRQ source entries */
267int mp_irq_entries;
268
8732fc4b
AS		 269DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
270
1da177e4
LT		 271/*
272 * Rough estimation of how many shared IRQs there are, can
273 * be changed anytime.
274 */
1da177e4 275
301e6190
YL		 276int pin_map_size;
277
1da177e4
LT		 278/*
279 * This is performance-critical, we want to do it O(1)
280 *
281 * the indexing order of this array favors 1:1 mappings
282 * between pins and IRQs.
283 */
284
e5a53714
YL		 285struct irq_pin_list {
286 int apic, pin;
287 struct irq_pin_list *next;
288};
289
290static struct irq_pin_list *irq_2_pin_head;
291/* fill one page ? */
292static int nr_irq_2_pin = 0x100;
293static struct irq_pin_list *irq_2_pin_ptr;
294static void __init irq_2_pin_init_work(void *data)
295{
296 struct dyn_array *da = data;
297 struct irq_pin_list *pin;
298 int i;
299
300 pin = *da->name;
301
302 for (i = 1; i < *da->nr; i++)
303 pin[i-1].next = &pin[i];
304
305 irq_2_pin_ptr = &pin[0];
306}
307DEFINE_DYN_ARRAY(irq_2_pin_head, sizeof(struct irq_pin_list), nr_irq_2_pin, PAGE_SIZE, irq_2_pin_init_work);
308
309static struct irq_pin_list *get_one_free_irq_2_pin(void)
310{
311 struct irq_pin_list *pin;
312 int i;
313
314 pin = irq_2_pin_ptr;
315
316 if (pin) {
317 irq_2_pin_ptr = pin->next;
318 pin->next = NULL;
319 return pin;
320 }
321
322 /*
323 * we run out of pre-allocate ones, allocate more
324 */
325 printk(KERN_DEBUG "try to get more irq_2_pin %d\n", nr_irq_2_pin);
326
327 if (after_bootmem)
328 pin = kzalloc(sizeof(struct irq_pin_list)*nr_irq_2_pin,
329 GFP_ATOMIC);
330 else
331 pin = __alloc_bootmem_nopanic(sizeof(struct irq_pin_list) *
332 nr_irq_2_pin, PAGE_SIZE, 0);
333
334 if (!pin)
335 panic("can not get more irq_2_pin\n");
301e6190 336
e5a53714
YL		 337 for (i = 1; i < nr_irq_2_pin; i++)
338 pin[i-1].next = &pin[i];
301e6190 339
e5a53714
YL		 340 irq_2_pin_ptr = pin->next;
341 pin->next = NULL;
342
343 return pin;
344}
1da177e4 345
6c0ffb9d
LT		 346struct io_apic {
347 unsigned int index;
348 unsigned int unused[3];
349 unsigned int data;
350};
351
352static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
353{
354 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
ec2cd0a2 355 + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK);
6c0ffb9d
LT		 356}
357
358static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
359{
360 struct io_apic __iomem *io_apic = io_apic_base(apic);
361 writel(reg, &io_apic->index);
362 return readl(&io_apic->data);
363}
364
365static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
366{
367 struct io_apic __iomem *io_apic = io_apic_base(apic);
368 writel(reg, &io_apic->index);
369 writel(value, &io_apic->data);
370}
371
372/*
373 * Re-write a value: to be used for read-modify-write
374 * cycles where the read already set up the index register.
375 */
376static inline void io_apic_modify(unsigned int apic, unsigned int value)
377{
378 struct io_apic __iomem *io_apic = io_apic_base(apic);
379 writel(value, &io_apic->data);
380}
381
9d25cb08 382static bool io_apic_level_ack_pending(unsigned int irq)
ef3e28c5
EB		 383{
384 struct irq_pin_list *entry;
385 unsigned long flags;
e5a53714 386 struct irq_cfg *cfg = irq_cfg(irq);
ef3e28c5
EB		 387
388 spin_lock_irqsave(&ioapic_lock, flags);
e5a53714 389 entry = cfg->irq_2_pin;
ef3e28c5
EB		 390 for (;;) {
391 unsigned int reg;
392 int pin;
393
e5a53714 394 if (!entry)
ef3e28c5 395 break;
e5a53714 396 pin = entry->pin;
ef3e28c5
EB		 397 reg = io_apic_read(entry->apic, 0x10 + pin*2);
398 /* Is the remote IRR bit set? */
46b3b4ef 399 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
9d25cb08
AM		 400 spin_unlock_irqrestore(&ioapic_lock, flags);
401 return true;
402 }
ef3e28c5
EB		 403 if (!entry->next)
404 break;
e5a53714 405 entry = entry->next;
ef3e28c5
EB		 406 }
407 spin_unlock_irqrestore(&ioapic_lock, flags);
9d25cb08
AM		 408
409 return false;
ef3e28c5
EB		 410}
411
6c0ffb9d
LT		 412/*
413 * Synchronize the IO-APIC and the CPU by doing
414 * a dummy read from the IO-APIC
415 */
416static inline void io_apic_sync(unsigned int apic)
417{
418 struct io_apic __iomem *io_apic = io_apic_base(apic);
419 readl(&io_apic->data);
420}
421
54d5d424
AR		 422#define __DO_ACTION(R, ACTION, FINAL) \
423 \
424{ \
425 int pin; \
e5a53714
YL		 426 struct irq_cfg *cfg; \
427 struct irq_pin_list *entry; \
54d5d424 428 \
e5a53714
YL		 429 cfg = irq_cfg(irq); \
430 entry = cfg->irq_2_pin; \
54d5d424
AR		 431 for (;;) { \
432 unsigned int reg; \
e5a53714 433 if (!entry) \
54d5d424 434 break; \
e5a53714 435 pin = entry->pin; \
54d5d424
AR		 436 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
437 reg ACTION; \
438 io_apic_modify(entry->apic, reg); \
f45bcd70 439 FINAL; \
54d5d424
AR		 440 if (!entry->next) \
441 break; \
e5a53714 442 entry = entry->next; \
54d5d424 443 } \
54d5d424
AR		 444}
445
eea0e11c
AK		 446union entry_union {
447 struct { u32 w1, w2; };
448 struct IO_APIC_route_entry entry;
449};
450
451static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
452{
453 union entry_union eu;
454 unsigned long flags;
455 spin_lock_irqsave(&ioapic_lock, flags);
456 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
457 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
458 spin_unlock_irqrestore(&ioapic_lock, flags);
459 return eu.entry;
460}
461
48797ebd
LT		 462/*
463 * When we write a new IO APIC routing entry, we need to write the high
464 * word first! If the mask bit in the low word is clear, we will enable
465 * the interrupt, and we need to make sure the entry is fully populated
466 * before that happens.
467 */
516d2836
AK		 468static void
469__ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
eea0e11c 470{
eea0e11c
AK		 471 union entry_union eu;
472 eu.entry = e;
48797ebd
LT		 473 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
474 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
516d2836
AK		 475}
476
477static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
478{
479 unsigned long flags;
480 spin_lock_irqsave(&ioapic_lock, flags);
481 __ioapic_write_entry(apic, pin, e);
48797ebd
LT		 482 spin_unlock_irqrestore(&ioapic_lock, flags);
483}
484
485/*
486 * When we mask an IO APIC routing entry, we need to write the low
487 * word first, in order to set the mask bit before we change the
488 * high bits!
489 */
490static void ioapic_mask_entry(int apic, int pin)
491{
492 unsigned long flags;
493 union entry_union eu = { .entry.mask = 1 };
494
eea0e11c
AK		 495 spin_lock_irqsave(&ioapic_lock, flags);
496 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
497 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
498 spin_unlock_irqrestore(&ioapic_lock, flags);
499}
500
54d5d424 501#ifdef CONFIG_SMP
550f2299
EB		 502static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
503{
504 int apic, pin;
e5a53714
YL		 505 struct irq_cfg *cfg;
506 struct irq_pin_list *entry;
550f2299 507
e5a53714
YL		 508 cfg = irq_cfg(irq);
509 entry = cfg->irq_2_pin;
550f2299
EB		 510 for (;;) {
511 unsigned int reg;
e5a53714
YL		 512
513 if (!entry)
514 break;
515
550f2299
EB		 516 apic = entry->apic;
517 pin = entry->pin;
89027d35
SS		 518 /*
519 * With interrupt-remapping, destination information comes
520 * from interrupt-remapping table entry.
521 */
522 if (!irq_remapped(irq))
523 io_apic_write(apic, 0x11 + pin*2, dest);
550f2299 524 reg = io_apic_read(apic, 0x10 + pin*2);
46b3b4ef 525 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
550f2299
EB		 526 reg |= vector;
527 io_apic_modify(apic, reg);
528 if (!entry->next)
529 break;
e5a53714 530 entry = entry->next;
550f2299
EB		 531 }
532}
533
54d5d424
AR		 534static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
535{
3ac2de48 536 struct irq_cfg *cfg = irq_cfg(irq);
54d5d424
AR		 537 unsigned long flags;
538 unsigned int dest;
539 cpumask_t tmp;
08678b08 540 struct irq_desc *desc;
54d5d424
AR		 541
542 cpus_and(tmp, mask, cpu_online_map);
543 if (cpus_empty(tmp))
5ff5115e 544 return;
54d5d424 545
dfbffdd8 546 if (assign_irq_vector(irq, mask))
550f2299
EB		 547 return;
548
dfbffdd8 549 cpus_and(tmp, cfg->domain, mask);
550f2299 550 dest = cpu_mask_to_apicid(tmp);
54d5d424
AR		 551
552 /*
553 * Only the high 8 bits are valid.
554 */
555 dest = SET_APIC_LOGICAL_ID(dest);
556
08678b08 557 desc = irq_to_desc(irq);
54d5d424 558 spin_lock_irqsave(&ioapic_lock, flags);
dfbffdd8 559 __target_IO_APIC_irq(irq, dest, cfg->vector);
08678b08 560 desc->affinity = mask;
54d5d424
AR		 561 spin_unlock_irqrestore(&ioapic_lock, flags);
562}
563#endif
564
1da177e4
LT		 565/*
566 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
567 * shared ISA-space IRQs, so we have to support them. We are super
568 * fast in the common case, and fast for shared ISA-space IRQs.
569 */
301e6190 570int first_free_entry;
1da177e4
LT		 571static void add_pin_to_irq(unsigned int irq, int apic, int pin)
572{
e5a53714
YL		 573 struct irq_cfg *cfg;
574 struct irq_pin_list *entry;
1da177e4 575
e5a53714
YL		 576 /* first time to refer irq_cfg, so with new */
577 cfg = irq_cfg_alloc(irq);
578 entry = cfg->irq_2_pin;
579 if (!entry) {
580 entry = get_one_free_irq_2_pin();
581 cfg->irq_2_pin = entry;
582 entry->apic = apic;
583 entry->pin = pin;
584 printk(KERN_DEBUG " 0 add_pin_to_irq: irq %d --> apic %d pin %d\n", irq, apic, pin);
585 return;
586 }
3ac2de48 587
e5a53714
YL		 588 while (entry->next) {
589 /* not again, please */
590 if (entry->apic == apic && entry->pin == pin)
591 return;
1da177e4 592
e5a53714 593 entry = entry->next;
1da177e4 594 }
e5a53714
YL		 595
596 entry->next = get_one_free_irq_2_pin();
597 entry = entry->next;
1da177e4
LT		 598 entry->apic = apic;
599 entry->pin = pin;
e5a53714 600 printk(KERN_DEBUG " x add_pin_to_irq: irq %d --> apic %d pin %d\n", irq, apic, pin);
1da177e4
LT		 601}
602
0b9f4f49
MR		 603/*
604 * Reroute an IRQ to a different pin.
605 */
606static void __init replace_pin_at_irq(unsigned int irq,
607 int oldapic, int oldpin,
608 int newapic, int newpin)
609{
e5a53714
YL		 610 struct irq_cfg *cfg = irq_cfg(irq);
611 struct irq_pin_list *entry = cfg->irq_2_pin;
612 int replaced = 0;
0b9f4f49 613
e5a53714 614 while (entry) {
0b9f4f49
MR		 615 if (entry->apic == oldapic && entry->pin == oldpin) {
616 entry->apic = newapic;
617 entry->pin = newpin;
e5a53714
YL		 618 replaced = 1;
619 /* every one is different, right? */
0b9f4f49 620 break;
e5a53714
YL		 621 }
622 entry = entry->next;
0b9f4f49 623 }
e5a53714
YL		 624
625 /* why? call replace before add? */
626 if (!replaced)
627 add_pin_to_irq(irq, newapic, newpin);
0b9f4f49
MR		 628}
629
1da177e4
LT		 630
631#define DO_ACTION(name,R,ACTION, FINAL) \
632 \
633 static void name##_IO_APIC_irq (unsigned int irq) \
634 __DO_ACTION(R, ACTION, FINAL)
635
46b3b4ef
CG		 636/* mask = 1 */
637DO_ACTION(__mask, 0, |= IO_APIC_REDIR_MASKED, io_apic_sync(entry->apic))
638
639/* mask = 0 */
640DO_ACTION(__unmask, 0, &= ~IO_APIC_REDIR_MASKED, )
1da177e4
LT		 641
642static void mask_IO_APIC_irq (unsigned int irq)
643{
644 unsigned long flags;
645
646 spin_lock_irqsave(&ioapic_lock, flags);
647 __mask_IO_APIC_irq(irq);
648 spin_unlock_irqrestore(&ioapic_lock, flags);
649}
650
651static void unmask_IO_APIC_irq (unsigned int irq)
652{
653 unsigned long flags;
654
655 spin_lock_irqsave(&ioapic_lock, flags);
656 __unmask_IO_APIC_irq(irq);
657 spin_unlock_irqrestore(&ioapic_lock, flags);
658}
659
660static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
661{
662 struct IO_APIC_route_entry entry;
1da177e4
LT		 663
664 /* Check delivery_mode to be sure we're not clearing an SMI pin */
eea0e11c 665 entry = ioapic_read_entry(apic, pin);
1da177e4
LT		 666 if (entry.delivery_mode == dest_SMI)
667 return;
668 /*
669 * Disable it in the IO-APIC irq-routing table:
670 */
48797ebd 671 ioapic_mask_entry(apic, pin);
1da177e4
LT		 672}
673
674static void clear_IO_APIC (void)
675{
676 int apic, pin;
677
678 for (apic = 0; apic < nr_ioapics; apic++)
679 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
680 clear_IO_APIC_pin(apic, pin);
681}
682
4dc2f96c
SS		 683/*
684 * Saves and masks all the unmasked IO-APIC RTE's
685 */
686int save_mask_IO_APIC_setup(void)
687{
688 union IO_APIC_reg_01 reg_01;
689 unsigned long flags;
690 int apic, pin;
691
692 /*
693 * The number of IO-APIC IRQ registers (== #pins):
694 */
695 for (apic = 0; apic < nr_ioapics; apic++) {
696 spin_lock_irqsave(&ioapic_lock, flags);
697 reg_01.raw = io_apic_read(apic, 1);
698 spin_unlock_irqrestore(&ioapic_lock, flags);
699 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
700 }
701
702 for (apic = 0; apic < nr_ioapics; apic++) {
703 early_ioapic_entries[apic] =
704 kzalloc(sizeof(struct IO_APIC_route_entry) *
705 nr_ioapic_registers[apic], GFP_KERNEL);
706 if (!early_ioapic_entries[apic])
707 return -ENOMEM;
708 }
709
710 for (apic = 0; apic < nr_ioapics; apic++)
711 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
712 struct IO_APIC_route_entry entry;
713
714 entry = early_ioapic_entries[apic][pin] =
715 ioapic_read_entry(apic, pin);
716 if (!entry.mask) {
717 entry.mask = 1;
718 ioapic_write_entry(apic, pin, entry);
719 }
720 }
721 return 0;
722}
723
724void restore_IO_APIC_setup(void)
725{
726 int apic, pin;
727
728 for (apic = 0; apic < nr_ioapics; apic++)
729 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
730 ioapic_write_entry(apic, pin,
731 early_ioapic_entries[apic][pin]);
732}
733
734void reinit_intr_remapped_IO_APIC(int intr_remapping)
735{
736 /*
737 * for now plain restore of previous settings.
738 * TBD: In the case of OS enabling interrupt-remapping,
739 * IO-APIC RTE's need to be setup to point to interrupt-remapping
740 * table entries. for now, do a plain restore, and wait for
741 * the setup_IO_APIC_irqs() to do proper initialization.
742 */
743 restore_IO_APIC_setup();
744}
745
1da177e4
LT		 746int skip_ioapic_setup;
747int ioapic_force;
748
61ec7567 749static int __init parse_noapic(char *str)
1da177e4 750{
61ec7567 751 disable_ioapic_setup();
2c8c0e6b 752 return 0;
1da177e4 753}
61ec7567 754early_param("noapic", parse_noapic);
1da177e4 755
fea5f1e1
LT		 756/* Actually the next is obsolete, but keep it for paranoid reasons -AK */
757static int __init disable_timer_pin_setup(char *arg)
758{
759 disable_timer_pin_1 = 1;
760 return 1;
761}
762__setup("disable_timer_pin_1", disable_timer_pin_setup);
763
fea5f1e1 764
1da177e4
LT		 765/*
766 * Find the IRQ entry number of a certain pin.
767 */
768static int find_irq_entry(int apic, int pin, int type)
769{
770 int i;
771
772 for (i = 0; i < mp_irq_entries; i++)
2fddb6e2
AS		 773 if (mp_irqs[i].mp_irqtype == type &&
774 (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid ||
775 mp_irqs[i].mp_dstapic == MP_APIC_ALL) &&
776 mp_irqs[i].mp_dstirq == pin)
1da177e4
LT		 777 return i;
778
779 return -1;
780}
781
782/*
783 * Find the pin to which IRQ[irq] (ISA) is connected
784 */
1008fddc 785static int __init find_isa_irq_pin(int irq, int type)
1da177e4
LT		 786{
787 int i;
788
789 for (i = 0; i < mp_irq_entries; i++) {
2fddb6e2 790 int lbus = mp_irqs[i].mp_srcbus;
1da177e4 791
55f05ffa 792 if (test_bit(lbus, mp_bus_not_pci) &&
2fddb6e2
AS		 793 (mp_irqs[i].mp_irqtype == type) &&
794 (mp_irqs[i].mp_srcbusirq == irq))
1da177e4 795
2fddb6e2 796 return mp_irqs[i].mp_dstirq;
1da177e4
LT		 797 }
798 return -1;
799}
800
1008fddc
EB		 801static int __init find_isa_irq_apic(int irq, int type)
802{
803 int i;
804
805 for (i = 0; i < mp_irq_entries; i++) {
2fddb6e2 806 int lbus = mp_irqs[i].mp_srcbus;
1008fddc 807
55f05ffa 808 if (test_bit(lbus, mp_bus_not_pci) &&
2fddb6e2
AS		 809 (mp_irqs[i].mp_irqtype == type) &&
810 (mp_irqs[i].mp_srcbusirq == irq))
1008fddc
EB		 811 break;
812 }
813 if (i < mp_irq_entries) {
814 int apic;
815 for(apic = 0; apic < nr_ioapics; apic++) {
2fddb6e2 816 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic)
1008fddc
EB		 817 return apic;
818 }
819 }
820
821 return -1;
822}
823
1da177e4
LT		 824/*
825 * Find a specific PCI IRQ entry.
826 * Not an __init, possibly needed by modules
827 */
828static int pin_2_irq(int idx, int apic, int pin);
829
830int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
831{
832 int apic, i, best_guess = -1;
833
834 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
835 bus, slot, pin);
ce6444d3 836 if (test_bit(bus, mp_bus_not_pci)) {
1da177e4
LT		 837 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
838 return -1;
839 }
840 for (i = 0; i < mp_irq_entries; i++) {
2fddb6e2 841 int lbus = mp_irqs[i].mp_srcbus;
1da177e4
LT		 842
843 for (apic = 0; apic < nr_ioapics; apic++)
2fddb6e2
AS		 844 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic ||
845 mp_irqs[i].mp_dstapic == MP_APIC_ALL)
1da177e4
LT		 846 break;
847
55f05ffa 848 if (!test_bit(lbus, mp_bus_not_pci) &&
2fddb6e2 849 !mp_irqs[i].mp_irqtype &&
1da177e4 850 (bus == lbus) &&
2fddb6e2
AS		 851 (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) {
852 int irq = pin_2_irq(i,apic,mp_irqs[i].mp_dstirq);
1da177e4
LT		 853
854 if (!(apic || IO_APIC_IRQ(irq)))
855 continue;
856
2fddb6e2 857 if (pin == (mp_irqs[i].mp_srcbusirq & 3))
1da177e4
LT		 858 return irq;
859 /*
860 * Use the first all-but-pin matching entry as a
861 * best-guess fuzzy result for broken mptables.
862 */
863 if (best_guess < 0)
864 best_guess = irq;
865 }
866 }
867 return best_guess;
868}
869
1da177e4
LT		 870/* ISA interrupts are always polarity zero edge triggered,
871 * when listed as conforming in the MP table. */
872
873#define default_ISA_trigger(idx) (0)
874#define default_ISA_polarity(idx) (0)
875
876/* PCI interrupts are always polarity one level triggered,
877 * when listed as conforming in the MP table. */
878
879#define default_PCI_trigger(idx) (1)
880#define default_PCI_polarity(idx) (1)
881
61fd47e0 882static int MPBIOS_polarity(int idx)
1da177e4 883{
2fddb6e2 884 int bus = mp_irqs[idx].mp_srcbus;
1da177e4
LT		 885 int polarity;
886
887 /*
888 * Determine IRQ line polarity (high active or low active):
889 */
2fddb6e2 890 switch (mp_irqs[idx].mp_irqflag & 3)
1da177e4
LT		 891 {
892 case 0: /* conforms, ie. bus-type dependent polarity */
55f05ffa
AK		 893 if (test_bit(bus, mp_bus_not_pci))
894 polarity = default_ISA_polarity(idx);
895 else
896 polarity = default_PCI_polarity(idx);
1da177e4 897 break;
1da177e4
LT		 898 case 1: /* high active */
899 {
900 polarity = 0;
901 break;
902 }
903 case 2: /* reserved */
904 {
905 printk(KERN_WARNING "broken BIOS!!\n");
906 polarity = 1;
907 break;
908 }
909 case 3: /* low active */
910 {
911 polarity = 1;
912 break;
913 }
914 default: /* invalid */
915 {
916 printk(KERN_WARNING "broken BIOS!!\n");
917 polarity = 1;
918 break;
919 }
920 }
921 return polarity;
922}
923
924static int MPBIOS_trigger(int idx)
925{
2fddb6e2 926 int bus = mp_irqs[idx].mp_srcbus;
1da177e4
LT		 927 int trigger;
928
929 /*
930 * Determine IRQ trigger mode (edge or level sensitive):
931 */
2fddb6e2 932 switch ((mp_irqs[idx].mp_irqflag>>2) & 3)
1da177e4
LT		 933 {
934 case 0: /* conforms, ie. bus-type dependent */
55f05ffa
AK		 935 if (test_bit(bus, mp_bus_not_pci))
936 trigger = default_ISA_trigger(idx);
937 else
938 trigger = default_PCI_trigger(idx);
1da177e4 939 break;
1da177e4
LT		 940 case 1: /* edge */
941 {
942 trigger = 0;
943 break;
944 }
945 case 2: /* reserved */
946 {
947 printk(KERN_WARNING "broken BIOS!!\n");
948 trigger = 1;
949 break;
950 }
951 case 3: /* level */
952 {
953 trigger = 1;
954 break;
955 }
956 default: /* invalid */
957 {
958 printk(KERN_WARNING "broken BIOS!!\n");
959 trigger = 0;
960 break;
961 }
962 }
963 return trigger;
964}
965
966static inline int irq_polarity(int idx)
967{
968 return MPBIOS_polarity(idx);
969}
970
971static inline int irq_trigger(int idx)
972{
973 return MPBIOS_trigger(idx);
974}
975
976static int pin_2_irq(int idx, int apic, int pin)
977{
978 int irq, i;
2fddb6e2 979 int bus = mp_irqs[idx].mp_srcbus;
1da177e4
LT		 980
981 /*
982 * Debugging check, we are in big trouble if this message pops up!
983 */
2fddb6e2 984 if (mp_irqs[idx].mp_dstirq != pin)
1da177e4
LT		 985 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
986
55f05ffa 987 if (test_bit(bus, mp_bus_not_pci)) {
2fddb6e2 988 irq = mp_irqs[idx].mp_srcbusirq;
55f05ffa
AK		 989 } else {
990 /*
991 * PCI IRQs are mapped in order
992 */
993 i = irq = 0;
994 while (i < apic)
995 irq += nr_ioapic_registers[i++];
996 irq += pin;
1da177e4 997 }
1da177e4
LT		 998 return irq;
999}
1000
d388e5fd
EB		 1001void lock_vector_lock(void)
1002{
1003 /* Used to the online set of cpus does not change
1004 * during assign_irq_vector.
1005 */
1006 spin_lock(&vector_lock);
1007}
1008
1009void unlock_vector_lock(void)
1010{
1011 spin_unlock(&vector_lock);
1012}
1013
dfbffdd8 1014static int __assign_irq_vector(int irq, cpumask_t mask)
1da177e4 1015{
550f2299
EB		 1016 /*
1017 * NOTE! The local APIC isn't very good at handling
1018 * multiple interrupts at the same interrupt level.
1019 * As the interrupt level is determined by taking the
1020 * vector number and shifting that right by 4, we
1021 * want to spread these out a bit so that they don't
1022 * all fall in the same interrupt level.
1023 *
1024 * Also, we've got to be careful not to trash gate
1025 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1026 */
d1752aa8 1027 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
dfbffdd8 1028 unsigned int old_vector;
550f2299 1029 int cpu;
13a79503 1030 struct irq_cfg *cfg;
1da177e4 1031
3ac2de48 1032 cfg = irq_cfg(irq);
0a1ad60d 1033
70a0a535
EB		 1034 /* Only try and allocate irqs on cpus that are present */
1035 cpus_and(mask, mask, cpu_online_map);
1036
61014292
EB		 1037 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1038 return -EBUSY;
1039
dfbffdd8
EB		 1040 old_vector = cfg->vector;
1041 if (old_vector) {
1042 cpumask_t tmp;
1043 cpus_and(tmp, cfg->domain, mask);
1044 if (!cpus_empty(tmp))
1045 return 0;
0a1ad60d 1046 }
550f2299 1047
334ef7a7 1048 for_each_cpu_mask_nr(cpu, mask) {
70a0a535 1049 cpumask_t domain, new_mask;
61014292 1050 int new_cpu;
550f2299 1051 int vector, offset;
c7111c13
EB		 1052
1053 domain = vector_allocation_domain(cpu);
70a0a535 1054 cpus_and(new_mask, domain, cpu_online_map);
c7111c13 1055
d1752aa8
EB		 1056 vector = current_vector;
1057 offset = current_offset;
1da177e4 1058next:
550f2299 1059 vector += 8;
305b92a2 1060 if (vector >= first_system_vector) {
550f2299
EB		 1061 /* If we run out of vectors on large boxen, must share them. */
1062 offset = (offset + 1) % 8;
1063 vector = FIRST_DEVICE_VECTOR + offset;
1064 }
d1752aa8 1065 if (unlikely(current_vector == vector))
550f2299
EB		 1066 continue;
1067 if (vector == IA32_SYSCALL_VECTOR)
1068 goto next;
334ef7a7 1069 for_each_cpu_mask_nr(new_cpu, new_mask)
45edfd1d 1070 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
c7111c13 1071 goto next;
550f2299 1072 /* Found one! */
d1752aa8
EB		 1073 current_vector = vector;
1074 current_offset = offset;
61014292
EB		 1075 if (old_vector) {
1076 cfg->move_in_progress = 1;
1077 cfg->old_domain = cfg->domain;
1078 }
334ef7a7 1079 for_each_cpu_mask_nr(new_cpu, new_mask)
c7111c13 1080 per_cpu(vector_irq, new_cpu)[vector] = irq;
13a79503
EB		 1081 cfg->vector = vector;
1082 cfg->domain = domain;
dfbffdd8 1083 return 0;
1da177e4 1084 }
550f2299 1085 return -ENOSPC;
04b9267b
EB		 1086}
1087
dfbffdd8 1088static int assign_irq_vector(int irq, cpumask_t mask)
04b9267b 1089{
dfbffdd8 1090 int err;
04b9267b 1091 unsigned long flags;
0a1ad60d 1092
04b9267b 1093 spin_lock_irqsave(&vector_lock, flags);
dfbffdd8 1094 err = __assign_irq_vector(irq, mask);
26a3c49c 1095 spin_unlock_irqrestore(&vector_lock, flags);
dfbffdd8 1096 return err;
1da177e4
LT		 1097}
1098
5df0287e
YL		 1099static void __clear_irq_vector(int irq)
1100{
13a79503 1101 struct irq_cfg *cfg;
5df0287e
YL		 1102 cpumask_t mask;
1103 int cpu, vector;
1104
3ac2de48 1105 cfg = irq_cfg(irq);
13a79503 1106 BUG_ON(!cfg->vector);
5df0287e 1107
13a79503
EB		 1108 vector = cfg->vector;
1109 cpus_and(mask, cfg->domain, cpu_online_map);
334ef7a7 1110 for_each_cpu_mask_nr(cpu, mask)
5df0287e
YL		 1111 per_cpu(vector_irq, cpu)[vector] = -1;
1112
13a79503 1113 cfg->vector = 0;
d366f8cb 1114 cpus_clear(cfg->domain);
5df0287e
YL		 1115}
1116
d388e5fd 1117void __setup_vector_irq(int cpu)
70a0a535
EB		 1118{
1119 /* Initialize vector_irq on a new cpu */
1120 /* This function must be called with vector_lock held */
70a0a535 1121 int irq, vector;
46b8214d 1122 struct irq_cfg *cfg;
70a0a535 1123
70a0a535 1124 /* Mark the inuse vectors */
46b8214d 1125 for_each_irq_cfg(cfg) {
3ac2de48 1126 if (!cpu_isset(cpu, cfg->domain))
70a0a535 1127 continue;
3ac2de48 1128 vector = cfg->vector;
46b8214d 1129 irq = cfg->irq;
70a0a535
EB		 1130 per_cpu(vector_irq, cpu)[vector] = irq;
1131 }
1132 /* Mark the free vectors */
1133 for (vector = 0; vector < NR_VECTORS; ++vector) {
1134 irq = per_cpu(vector_irq, cpu)[vector];
1135 if (irq < 0)
1136 continue;
3ac2de48
YL		 1137
1138 cfg = irq_cfg(irq);
1139 if (!cpu_isset(cpu, cfg->domain))
70a0a535
EB		 1140 per_cpu(vector_irq, cpu)[vector] = -1;
1141 }
1142}
1143
f29bd1ba 1144static struct irq_chip ioapic_chip;
89027d35
SS		 1145#ifdef CONFIG_INTR_REMAP
1146static struct irq_chip ir_ioapic_chip;
1147#endif
1da177e4 1148
a27bc06d 1149static void ioapic_register_intr(int irq, unsigned long trigger)
1da177e4 1150{
08678b08
YL		 1151 struct irq_desc *desc;
1152
cb5bc832
YL		 1153 /* first time to use this irq_desc */
1154 if (irq < 16)
1155 desc = irq_to_desc(irq);
1156 else
1157 desc = irq_to_desc_alloc(irq);
1158
89027d35 1159 if (trigger)
08678b08 1160 desc->status |= IRQ_LEVEL;
89027d35 1161 else
08678b08 1162 desc->status &= ~IRQ_LEVEL;
89027d35
SS		 1163
1164#ifdef CONFIG_INTR_REMAP
1165 if (irq_remapped(irq)) {
08678b08 1166 desc->status |= IRQ_MOVE_PCNTXT;
89027d35
SS		 1167 if (trigger)
1168 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1169 handle_fasteoi_irq,
1170 "fasteoi");
1171 else
1172 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1173 handle_edge_irq, "edge");
1174 return;
1175 }
1176#endif
1177 if (trigger)
1178 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1179 handle_fasteoi_irq,
1180 "fasteoi");
1181 else
a460e745
IM		 1182 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1183 handle_edge_irq, "edge");
89027d35
SS		 1184}
1185
1186static int setup_ioapic_entry(int apic, int irq,
1187 struct IO_APIC_route_entry *entry,
1188 unsigned int destination, int trigger,
1189 int polarity, int vector)
1190{
1191 /*
1192 * add it to the IO-APIC irq-routing table:
1193 */
1194 memset(entry,0,sizeof(*entry));
1195
1196#ifdef CONFIG_INTR_REMAP
1197 if (intr_remapping_enabled) {
1198 struct intel_iommu *iommu = map_ioapic_to_ir(apic);
1199 struct irte irte;
1200 struct IR_IO_APIC_route_entry *ir_entry =
1201 (struct IR_IO_APIC_route_entry *) entry;
1202 int index;
1203
1204 if (!iommu)
1205 panic("No mapping iommu for ioapic %d\n", apic);
1206
1207 index = alloc_irte(iommu, irq, 1);
1208 if (index < 0)
1209 panic("Failed to allocate IRTE for ioapic %d\n", apic);
1210
1211 memset(&irte, 0, sizeof(irte));
1212
1213 irte.present = 1;
1214 irte.dst_mode = INT_DEST_MODE;
1215 irte.trigger_mode = trigger;
1216 irte.dlvry_mode = INT_DELIVERY_MODE;
1217 irte.vector = vector;
1218 irte.dest_id = IRTE_DEST(destination);
1219
1220 modify_irte(irq, &irte);
1221
1222 ir_entry->index2 = (index >> 15) & 0x1;
1223 ir_entry->zero = 0;
1224 ir_entry->format = 1;
1225 ir_entry->index = (index & 0x7fff);
1226 } else
1227#endif
1228 {
1229 entry->delivery_mode = INT_DELIVERY_MODE;
1230 entry->dest_mode = INT_DEST_MODE;
1231 entry->dest = destination;
cc75b92d 1232 }
89027d35
SS		 1233
1234 entry->mask = 0; /* enable IRQ */
1235 entry->trigger = trigger;
1236 entry->polarity = polarity;
1237 entry->vector = vector;
1238
1239 /* Mask level triggered irqs.
1240 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1241 */
1242 if (trigger)
1243 entry->mask = 1;
1244 return 0;
1da177e4 1245}
a8c8a367
EB		 1246
1247static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
1248 int trigger, int polarity)
1da177e4 1249{
3ac2de48 1250 struct irq_cfg *cfg;
1da177e4 1251 struct IO_APIC_route_entry entry;
a8c8a367 1252 cpumask_t mask;
1da177e4 1253
a8c8a367
EB		 1254 if (!IO_APIC_IRQ(irq))
1255 return;
1256
3ac2de48
YL		 1257 cfg = irq_cfg(irq);
1258
dfbffdd8
EB		 1259 mask = TARGET_CPUS;
1260 if (assign_irq_vector(irq, mask))
a8c8a367
EB		 1261 return;
1262
dfbffdd8
EB		 1263 cpus_and(mask, cfg->domain, mask);
1264
a8c8a367
EB		 1265 apic_printk(APIC_VERBOSE,KERN_DEBUG
1266 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1267 "IRQ %d Mode:%i Active:%i)\n",
ec2cd0a2 1268 apic, mp_ioapics[apic].mp_apicid, pin, cfg->vector,
a8c8a367 1269 irq, trigger, polarity);
1da177e4 1270
1da177e4 1271
89027d35
SS		 1272 if (setup_ioapic_entry(mp_ioapics[apic].mp_apicid, irq, &entry,
1273 cpu_mask_to_apicid(mask), trigger, polarity,
1274 cfg->vector)) {
1275 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1276 mp_ioapics[apic].mp_apicid, pin);
1277 __clear_irq_vector(irq);
1278 return;
1279 }
ad892f5e 1280
a8c8a367
EB		 1281 ioapic_register_intr(irq, trigger);
1282 if (irq < 16)
1283 disable_8259A_irq(irq);
ad892f5e
YL		 1284
1285 ioapic_write_entry(apic, pin, entry);
ad892f5e
YL		 1286}
1287
1288static void __init setup_IO_APIC_irqs(void)
1289{
1290 int apic, pin, idx, irq, first_notcon = 1;
1291
1292 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1293
1294 for (apic = 0; apic < nr_ioapics; apic++) {
1295 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1da177e4
LT		 1296
1297 idx = find_irq_entry(apic,pin,mp_INT);
1298 if (idx == -1) {
1299 if (first_notcon) {
ec2cd0a2 1300 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mp_apicid, pin);
1da177e4
LT		 1301 first_notcon = 0;
1302 } else
ec2cd0a2 1303 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mp_apicid, pin);
1da177e4
LT		 1304 continue;
1305 }
20d225b9
YL		 1306 if (!first_notcon) {
1307 apic_printk(APIC_VERBOSE, " not connected.\n");
1308 first_notcon = 1;
1309 }
1da177e4 1310
1da177e4
LT		 1311 irq = pin_2_irq(idx, apic, pin);
1312 add_pin_to_irq(irq, apic, pin);
1313
a8c8a367
EB		 1314 setup_IO_APIC_irq(apic, pin, irq,
1315 irq_trigger(idx), irq_polarity(idx));
1da177e4
LT		 1316 }
1317 }
1318
1319 if (!first_notcon)
20d225b9 1320 apic_printk(APIC_VERBOSE, " not connected.\n");
1da177e4
LT		 1321}
1322
1323/*
f7633ce5 1324 * Set up the timer pin, possibly with the 8259A-master behind.
1da177e4 1325 */
f7633ce5
MR		 1326static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
1327 int vector)
1da177e4
LT		 1328{
1329 struct IO_APIC_route_entry entry;
1da177e4 1330
89027d35
SS		 1331 if (intr_remapping_enabled)
1332 return;
1333
a2249cba 1334 memset(&entry, 0, sizeof(entry));
1da177e4 1335
1da177e4
LT		 1336 /*
1337 * We use logical delivery to get the timer IRQ
1338 * to the first CPU.
1339 */
1340 entry.dest_mode = INT_DEST_MODE;
03be7505 1341 entry.mask = 1; /* mask IRQ now */
ee4eff6f 1342 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
1da177e4
LT		 1343 entry.delivery_mode = INT_DELIVERY_MODE;
1344 entry.polarity = 0;
1345 entry.trigger = 0;
1346 entry.vector = vector;
1347
1348 /*
1349 * The timer IRQ doesn't have to know that behind the
f7633ce5 1350 * scene we may have a 8259A-master in AEOI mode ...
1da177e4 1351 */
a460e745 1352 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1da177e4
LT		 1353
1354 /*
1355 * Add it to the IO-APIC irq-routing table:
1356 */
a2249cba 1357 ioapic_write_entry(apic, pin, entry);
1da177e4
LT		 1358}
1359
32f71aff
MR		 1360
1361__apicdebuginit(void) print_IO_APIC(void)
1da177e4
LT		 1362{
1363 int apic, i;
1364 union IO_APIC_reg_00 reg_00;
1365 union IO_APIC_reg_01 reg_01;
1366 union IO_APIC_reg_02 reg_02;
1367 unsigned long flags;
46b8214d 1368 struct irq_cfg *cfg;
1da177e4
LT		 1369
1370 if (apic_verbosity == APIC_QUIET)
1371 return;
1372
1373 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1374 for (i = 0; i < nr_ioapics; i++)
1375 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
ec2cd0a2 1376 mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]);
1da177e4
LT		 1377
1378 /*
1379 * We are a bit conservative about what we expect. We have to
1380 * know about every hardware change ASAP.
1381 */
1382 printk(KERN_INFO "testing the IO APIC.......................\n");
1383
1384 for (apic = 0; apic < nr_ioapics; apic++) {
1385
1386 spin_lock_irqsave(&ioapic_lock, flags);
1387 reg_00.raw = io_apic_read(apic, 0);
1388 reg_01.raw = io_apic_read(apic, 1);
1389 if (reg_01.bits.version >= 0x10)
1390 reg_02.raw = io_apic_read(apic, 2);
1391 spin_unlock_irqrestore(&ioapic_lock, flags);
1392
1393 printk("\n");
ec2cd0a2 1394 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid);
1da177e4
LT		 1395 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1396 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1da177e4
LT		 1397
1398 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1399 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1da177e4
LT		 1400
1401 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1402 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1da177e4
LT		 1403
1404 if (reg_01.bits.version >= 0x10) {
1405 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1406 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1da177e4
LT		 1407 }
1408
1409 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1410
ee4eff6f
BR		 1411 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1412 " Stat Dmod Deli Vect: \n");
1da177e4
LT		 1413
1414 for (i = 0; i <= reg_01.bits.entries; i++) {
1415 struct IO_APIC_route_entry entry;
1416
eea0e11c 1417 entry = ioapic_read_entry(apic, i);
1da177e4 1418
ee4eff6f 1419 printk(KERN_DEBUG " %02x %03X ",
1da177e4 1420 i,
ee4eff6f 1421 entry.dest
1da177e4
LT		 1422 );
1423
1424 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1425 entry.mask,
1426 entry.trigger,
1427 entry.irr,
1428 entry.polarity,
1429 entry.delivery_status,
1430 entry.dest_mode,
1431 entry.delivery_mode,
1432 entry.vector
1433 );
1434 }
1435 }
1da177e4 1436 printk(KERN_DEBUG "IRQ to pin mappings:\n");
46b8214d 1437 for_each_irq_cfg(cfg) {
e5a53714
YL		 1438 struct irq_pin_list *entry = cfg->irq_2_pin;
1439 if (!entry)
1da177e4 1440 continue;
46b8214d 1441 printk(KERN_DEBUG "IRQ%d ", cfg->irq);
1da177e4
LT		 1442 for (;;) {
1443 printk("-> %d:%d", entry->apic, entry->pin);
1444 if (!entry->next)
1445 break;
e5a53714 1446 entry = entry->next;
1da177e4
LT		 1447 }
1448 printk("\n");
1449 }
1450
1451 printk(KERN_INFO ".................................... done.\n");
1452
1453 return;
1454}
1455
32f71aff 1456__apicdebuginit(void) print_APIC_bitfield(int base)
1da177e4
LT		 1457{
1458 unsigned int v;
1459 int i, j;
1460
1461 if (apic_verbosity == APIC_QUIET)
1462 return;
1463
1464 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1465 for (i = 0; i < 8; i++) {
1466 v = apic_read(base + i*0x10);
1467 for (j = 0; j < 32; j++) {
1468 if (v & (1<<j))
1469 printk("1");
1470 else
1471 printk("0");
1472 }
1473 printk("\n");
1474 }
1475}
1476
32f71aff 1477__apicdebuginit(void) print_local_APIC(void *dummy)
1da177e4
LT		 1478{
1479 unsigned int v, ver, maxlvt;
1b374e4d 1480 unsigned long icr;
1da177e4
LT		 1481
1482 if (apic_verbosity == APIC_QUIET)
1483 return;
1484
1485 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1486 smp_processor_id(), hard_smp_processor_id());
66823114 1487 v = apic_read(APIC_ID);
4c9961d5 1488 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1da177e4
LT		 1489 v = apic_read(APIC_LVR);
1490 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1491 ver = GET_APIC_VERSION(v);
37e650c7 1492 maxlvt = lapic_get_maxlvt();
1da177e4
LT		 1493
1494 v = apic_read(APIC_TASKPRI);
1495 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1496
5a40b7c2
AK		 1497 v = apic_read(APIC_ARBPRI);
1498 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1499 v & APIC_ARBPRI_MASK);
1500 v = apic_read(APIC_PROCPRI);
1501 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1da177e4
LT		 1502
1503 v = apic_read(APIC_EOI);
1504 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1505 v = apic_read(APIC_RRR);
1506 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1507 v = apic_read(APIC_LDR);
1508 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1509 v = apic_read(APIC_DFR);
1510 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1511 v = apic_read(APIC_SPIV);
1512 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1513
1514 printk(KERN_DEBUG "... APIC ISR field:\n");
1515 print_APIC_bitfield(APIC_ISR);
1516 printk(KERN_DEBUG "... APIC TMR field:\n");
1517 print_APIC_bitfield(APIC_TMR);
1518 printk(KERN_DEBUG "... APIC IRR field:\n");
1519 print_APIC_bitfield(APIC_IRR);
1520
5a40b7c2
AK		 1521 v = apic_read(APIC_ESR);
1522 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1da177e4 1523
1b374e4d 1524 icr = apic_icr_read();
d562353a
IM		 1525 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1526 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1da177e4
LT		 1527
1528 v = apic_read(APIC_LVTT);
1529 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1530
1531 if (maxlvt > 3) { /* PC is LVT#4. */
1532 v = apic_read(APIC_LVTPC);
1533 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1534 }
1535 v = apic_read(APIC_LVT0);
1536 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1537 v = apic_read(APIC_LVT1);
1538 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1539
1540 if (maxlvt > 2) { /* ERR is LVT#3. */
1541 v = apic_read(APIC_LVTERR);
1542 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1543 }
1544
1545 v = apic_read(APIC_TMICT);
1546 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1547 v = apic_read(APIC_TMCCT);
1548 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1549 v = apic_read(APIC_TDCR);
1550 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1551 printk("\n");
1552}
1553
32f71aff 1554__apicdebuginit(void) print_all_local_APICs(void)
1da177e4 1555{
15c8b6c1 1556 on_each_cpu(print_local_APIC, NULL, 1);
1da177e4
LT		 1557}
1558
32f71aff 1559__apicdebuginit(void) print_PIC(void)
1da177e4 1560{
1da177e4
LT		 1561 unsigned int v;
1562 unsigned long flags;
1563
1564 if (apic_verbosity == APIC_QUIET)
1565 return;
1566
1567 printk(KERN_DEBUG "\nprinting PIC contents\n");
1568
1569 spin_lock_irqsave(&i8259A_lock, flags);
1570
1571 v = inb(0xa1) << 8 | inb(0x21);
1572 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1573
1574 v = inb(0xa0) << 8 | inb(0x20);
1575 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1576
1577 outb(0x0b,0xa0);
1578 outb(0x0b,0x20);
1579 v = inb(0xa0) << 8 | inb(0x20);
1580 outb(0x0a,0xa0);
1581 outb(0x0a,0x20);
1582
1583 spin_unlock_irqrestore(&i8259A_lock, flags);
1584
1585 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1586
1587 v = inb(0x4d1) << 8 | inb(0x4d0);
1588 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1589}
1590
32f71aff
MR		 1591__apicdebuginit(int) print_all_ICs(void)
1592{
1593 print_PIC();
1594 print_all_local_APICs();
1595 print_IO_APIC();
1596
1597 return 0;
1598}
1599
1600fs_initcall(print_all_ICs);
1601
1da177e4 1602
1c69524c 1603void __init enable_IO_APIC(void)
1da177e4
LT		 1604{
1605 union IO_APIC_reg_01 reg_01;
1008fddc 1606 int i8259_apic, i8259_pin;
e5a53714 1607 int apic;
1da177e4
LT		 1608 unsigned long flags;
1609
1da177e4
LT		 1610 /*
1611 * The number of IO-APIC IRQ registers (== #pins):
1612 */
1008fddc 1613 for (apic = 0; apic < nr_ioapics; apic++) {
1da177e4 1614 spin_lock_irqsave(&ioapic_lock, flags);
1008fddc 1615 reg_01.raw = io_apic_read(apic, 1);
1da177e4 1616 spin_unlock_irqrestore(&ioapic_lock, flags);
1008fddc
EB		 1617 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1618 }
1619 for(apic = 0; apic < nr_ioapics; apic++) {
1620 int pin;
1621 /* See if any of the pins is in ExtINT mode */
1622 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1623 struct IO_APIC_route_entry entry;
eea0e11c 1624 entry = ioapic_read_entry(apic, pin);
1008fddc
EB		 1625
1626 /* If the interrupt line is enabled and in ExtInt mode
1627 * I have found the pin where the i8259 is connected.
1628 */
1629 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1630 ioapic_i8259.apic = apic;
1631 ioapic_i8259.pin = pin;
1632 goto found_i8259;
1633 }
1634 }
1635 }
1636 found_i8259:
1637 /* Look to see what if the MP table has reported the ExtINT */
1638 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1639 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1640 /* Trust the MP table if nothing is setup in the hardware */
1641 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1642 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1643 ioapic_i8259.pin = i8259_pin;
1644 ioapic_i8259.apic = i8259_apic;
1645 }
1646 /* Complain if the MP table and the hardware disagree */
1647 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1648 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1649 {
1650 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1da177e4
LT		 1651 }
1652
1653 /*
1654 * Do not trust the IO-APIC being empty at bootup
1655 */
1656 clear_IO_APIC();
1657}
1658
1659/*
1660 * Not an __init, needed by the reboot code
1661 */
1662void disable_IO_APIC(void)
1663{
1664 /*
1665 * Clear the IO-APIC before rebooting:
1666 */
1667 clear_IO_APIC();
1668
208fb931 1669 /*
0b968d23 1670 * If the i8259 is routed through an IOAPIC
208fb931 1671 * Put that IOAPIC in virtual wire mode
0b968d23 1672 * so legacy interrupts can be delivered.
208fb931 1673 */
1008fddc 1674 if (ioapic_i8259.pin != -1) {
208fb931 1675 struct IO_APIC_route_entry entry;
208fb931
EB		 1676
1677 memset(&entry, 0, sizeof(entry));
1678 entry.mask = 0; /* Enabled */
1679 entry.trigger = 0; /* Edge */
1680 entry.irr = 0;
1681 entry.polarity = 0; /* High */
1682 entry.delivery_status = 0;
1683 entry.dest_mode = 0; /* Physical */
1008fddc 1684 entry.delivery_mode = dest_ExtINT; /* ExtInt */
208fb931 1685 entry.vector = 0;
4c9961d5 1686 entry.dest = read_apic_id();
208fb931 1687
208fb931
EB		 1688 /*
1689 * Add it to the IO-APIC irq-routing table:
1690 */
eea0e11c 1691 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
208fb931
EB		 1692 }
1693
1008fddc 1694 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1da177e4
LT		 1695}
1696
1da177e4
LT		 1697/*
1698 * There is a nasty bug in some older SMP boards, their mptable lies
1699 * about the timer IRQ. We do the following to work around the situation:
1700 *
1701 * - timer IRQ defaults to IO-APIC IRQ
1702 * - if this function detects that timer IRQs are defunct, then we fall
1703 * back to ISA timer IRQs
1704 */
1705static int __init timer_irq_works(void)
1706{
1707 unsigned long t1 = jiffies;
4aae0702 1708 unsigned long flags;
1da177e4 1709
4aae0702 1710 local_save_flags(flags);
1da177e4
LT		 1711 local_irq_enable();
1712 /* Let ten ticks pass... */
1713 mdelay((10 * 1000) / HZ);
4aae0702 1714 local_irq_restore(flags);
1da177e4
LT		 1715
1716 /*
1717 * Expect a few ticks at least, to be sure some possible
1718 * glue logic does not lock up after one or two first
1719 * ticks in a non-ExtINT mode. Also the local APIC
1720 * might have cached one ExtINT interrupt. Finally, at
1721 * least one tick may be lost due to delays.
1722 */
1723
1724 /* jiffies wrap? */
1d16b53e 1725 if (time_after(jiffies, t1 + 4))
1da177e4
LT		 1726 return 1;
1727 return 0;
1728}
1729
1730/*
1731 * In the SMP+IOAPIC case it might happen that there are an unspecified
1732 * number of pending IRQ events unhandled. These cases are very rare,
1733 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1734 * better to do it this way as thus we do not have to be aware of
1735 * 'pending' interrupts in the IRQ path, except at this point.
1736 */
1737/*
1738 * Edge triggered needs to resend any interrupt
1739 * that was delayed but this is now handled in the device
1740 * independent code.
1741 */
1742
1743/*
1744 * Starting up a edge-triggered IO-APIC interrupt is
1745 * nasty - we need to make sure that we get the edge.
1746 * If it is already asserted for some reason, we need
1747 * return 1 to indicate that is was pending.
1748 *
1749 * This is not complete - we should be able to fake
1750 * an edge even if it isn't on the 8259A...
1751 */
1752
f29bd1ba 1753static unsigned int startup_ioapic_irq(unsigned int irq)
1da177e4
LT		 1754{
1755 int was_pending = 0;
1756 unsigned long flags;
1757
1758 spin_lock_irqsave(&ioapic_lock, flags);
1759 if (irq < 16) {
1760 disable_8259A_irq(irq);
1761 if (i8259A_irq_pending(irq))
1762 was_pending = 1;
1763 }
1764 __unmask_IO_APIC_irq(irq);
1765 spin_unlock_irqrestore(&ioapic_lock, flags);
1766
1767 return was_pending;
1768}
1769
04b9267b 1770static int ioapic_retrigger_irq(unsigned int irq)
c0ad90a3 1771{
3ac2de48 1772 struct irq_cfg *cfg = irq_cfg(irq);
6bf2dafa 1773 unsigned long flags;
550f2299 1774
6bf2dafa 1775 spin_lock_irqsave(&vector_lock, flags);
cb6d2be6 1776 send_IPI_mask(cpumask_of_cpu(first_cpu(cfg->domain)), cfg->vector);
6bf2dafa 1777 spin_unlock_irqrestore(&vector_lock, flags);
c0ad90a3
IM		 1778
1779 return 1;
1780}
1781
1da177e4
LT		 1782/*
1783 * Level and edge triggered IO-APIC interrupts need different handling,
1784 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1785 * handled with the level-triggered descriptor, but that one has slightly
1786 * more overhead. Level-triggered interrupts cannot be handled with the
1787 * edge-triggered handler, without risking IRQ storms and other ugly
1788 * races.
1789 */
1790
61014292 1791#ifdef CONFIG_SMP
89027d35
SS		 1792
1793#ifdef CONFIG_INTR_REMAP
1794static void ir_irq_migration(struct work_struct *work);
1795
1796static DECLARE_DELAYED_WORK(ir_migration_work, ir_irq_migration);
1797
1798/*
1799 * Migrate the IO-APIC irq in the presence of intr-remapping.
1800 *
1801 * For edge triggered, irq migration is a simple atomic update(of vector
1802 * and cpu destination) of IRTE and flush the hardware cache.
1803 *
1804 * For level triggered, we need to modify the io-apic RTE aswell with the update
1805 * vector information, along with modifying IRTE with vector and destination.
1806 * So irq migration for level triggered is little bit more complex compared to
1807 * edge triggered migration. But the good news is, we use the same algorithm
1808 * for level triggered migration as we have today, only difference being,
1809 * we now initiate the irq migration from process context instead of the
1810 * interrupt context.
1811 *
1812 * In future, when we do a directed EOI (combined with cpu EOI broadcast
1813 * suppression) to the IO-APIC, level triggered irq migration will also be
1814 * as simple as edge triggered migration and we can do the irq migration
1815 * with a simple atomic update to IO-APIC RTE.
1816 */
1817static void migrate_ioapic_irq(int irq, cpumask_t mask)
1818{
3ac2de48 1819 struct irq_cfg *cfg;
08678b08 1820 struct irq_desc *desc;
89027d35
SS		 1821 cpumask_t tmp, cleanup_mask;
1822 struct irte irte;
08678b08 1823 int modify_ioapic_rte;
89027d35
SS		 1824 unsigned int dest;
1825 unsigned long flags;
1826
1827 cpus_and(tmp, mask, cpu_online_map);
1828 if (cpus_empty(tmp))
1829 return;
1830
1831 if (get_irte(irq, &irte))
1832 return;
1833
1834 if (assign_irq_vector(irq, mask))
1835 return;
1836
3ac2de48 1837 cfg = irq_cfg(irq);
89027d35
SS		 1838 cpus_and(tmp, cfg->domain, mask);
1839 dest = cpu_mask_to_apicid(tmp);
1840
08678b08
YL		 1841 desc = irq_to_desc(irq);
1842 modify_ioapic_rte = desc->status & IRQ_LEVEL;
89027d35
SS		 1843 if (modify_ioapic_rte) {
1844 spin_lock_irqsave(&ioapic_lock, flags);
1845 __target_IO_APIC_irq(irq, dest, cfg->vector);
1846 spin_unlock_irqrestore(&ioapic_lock, flags);
1847 }
1848
1849 irte.vector = cfg->vector;
1850 irte.dest_id = IRTE_DEST(dest);
1851
1852 /*
1853 * Modified the IRTE and flushes the Interrupt entry cache.
1854 */
1855 modify_irte(irq, &irte);
1856
1857 if (cfg->move_in_progress) {
1858 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
1859 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
1860 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
1861 cfg->move_in_progress = 0;
1862 }
1863
08678b08 1864 desc->affinity = mask;
89027d35
SS		 1865}
1866
1867static int migrate_irq_remapped_level(int irq)
1868{
1869 int ret = -1;
08678b08 1870 struct irq_desc *desc = irq_to_desc(irq);
89027d35
SS		 1871
1872 mask_IO_APIC_irq(irq);
1873
1874 if (io_apic_level_ack_pending(irq)) {
1875 /*
1876 * Interrupt in progress. Migrating irq now will change the
1877 * vector information in the IO-APIC RTE and that will confuse
1878 * the EOI broadcast performed by cpu.
1879 * So, delay the irq migration to the next instance.
1880 */
1881 schedule_delayed_work(&ir_migration_work, 1);
1882 goto unmask;
1883 }
1884
1885 /* everthing is clear. we have right of way */
08678b08 1886 migrate_ioapic_irq(irq, desc->pending_mask);
89027d35
SS		 1887
1888 ret = 0;
08678b08
YL		 1889 desc->status &= ~IRQ_MOVE_PENDING;
1890 cpus_clear(desc->pending_mask);
89027d35
SS		 1891
1892unmask:
1893 unmask_IO_APIC_irq(irq);
1894 return ret;
1895}
1896
1897static void ir_irq_migration(struct work_struct *work)
1898{
2c6927a3
YL		 1899 unsigned int irq;
1900 struct irq_desc *desc;
89027d35 1901
2c6927a3 1902 for_each_irq_desc(irq, desc) {
89027d35
SS		 1903 if (desc->status & IRQ_MOVE_PENDING) {
1904 unsigned long flags;
1905
1906 spin_lock_irqsave(&desc->lock, flags);
1907 if (!desc->chip->set_affinity ||
1908 !(desc->status & IRQ_MOVE_PENDING)) {
1909 desc->status &= ~IRQ_MOVE_PENDING;
1910 spin_unlock_irqrestore(&desc->lock, flags);
1911 continue;
1912 }
1913
08678b08 1914 desc->chip->set_affinity(irq, desc->pending_mask);
89027d35
SS		 1915 spin_unlock_irqrestore(&desc->lock, flags);
1916 }
1917 }
1918}
1919
1920/*
1921 * Migrates the IRQ destination in the process context.
1922 */
1923static void set_ir_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
1924{
08678b08
YL		 1925 struct irq_desc *desc = irq_to_desc(irq);
1926
1927 if (desc->status & IRQ_LEVEL) {
1928 desc->status |= IRQ_MOVE_PENDING;
1929 desc->pending_mask = mask;
89027d35
SS		 1930 migrate_irq_remapped_level(irq);
1931 return;
1932 }
1933
1934 migrate_ioapic_irq(irq, mask);
1935}
1936#endif
1937
61014292
EB		 1938asmlinkage void smp_irq_move_cleanup_interrupt(void)
1939{
1940 unsigned vector, me;
1941 ack_APIC_irq();
1942 exit_idle();
1943 irq_enter();
1944
1945 me = smp_processor_id();
1946 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
1947 unsigned int irq;
1948 struct irq_desc *desc;
1949 struct irq_cfg *cfg;
1950 irq = __get_cpu_var(vector_irq)[vector];
61014292 1951
08678b08 1952 desc = irq_to_desc(irq);
cb5bc832
YL		 1953 if (!desc)
1954 continue;
1955
3ac2de48 1956 cfg = irq_cfg(irq);
61014292
EB		 1957 spin_lock(&desc->lock);
1958 if (!cfg->move_cleanup_count)
1959 goto unlock;
1960
1961 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
1962 goto unlock;
1963
1964 __get_cpu_var(vector_irq)[vector] = -1;
1965 cfg->move_cleanup_count--;
1966unlock:
1967 spin_unlock(&desc->lock);
1968 }
1969
1970 irq_exit();
1971}
1972
1973static void irq_complete_move(unsigned int irq)
1974{
3ac2de48 1975 struct irq_cfg *cfg = irq_cfg(irq);
61014292
EB		 1976 unsigned vector, me;
1977
1978 if (likely(!cfg->move_in_progress))
1979 return;
1980
65ea5b03 1981 vector = ~get_irq_regs()->orig_ax;
61014292 1982 me = smp_processor_id();
f0e13ae7 1983 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
61014292
EB		 1984 cpumask_t cleanup_mask;
1985
1986 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
1987 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
1988 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
1989 cfg->move_in_progress = 0;
1990 }
1991}
1992#else
1993static inline void irq_complete_move(unsigned int irq) {}
1994#endif
89027d35
SS		 1995#ifdef CONFIG_INTR_REMAP
1996static void ack_x2apic_level(unsigned int irq)
1997{
1998 ack_x2APIC_irq();
1999}
2000
2001static void ack_x2apic_edge(unsigned int irq)
2002{
2003 ack_x2APIC_irq();
2004}
2005#endif
61014292 2006
0be6652f
EB		 2007static void ack_apic_edge(unsigned int irq)
2008{
61014292 2009 irq_complete_move(irq);
0be6652f
EB		 2010 move_native_irq(irq);
2011 ack_APIC_irq();
2012}
2013
2014static void ack_apic_level(unsigned int irq)
2015{
2016 int do_unmask_irq = 0;
2017
61014292 2018 irq_complete_move(irq);
52e3d90d 2019#ifdef CONFIG_GENERIC_PENDING_IRQ
0be6652f 2020 /* If we are moving the irq we need to mask it */
08678b08 2021 if (unlikely(irq_to_desc(irq)->status & IRQ_MOVE_PENDING)) {
0be6652f
EB		 2022 do_unmask_irq = 1;
2023 mask_IO_APIC_irq(irq);
2024 }
2025#endif
2026
2027 /*
2028 * We must acknowledge the irq before we move it or the acknowledge will
beb7dd86 2029 * not propagate properly.
0be6652f
EB		 2030 */
2031 ack_APIC_irq();
2032
2033 /* Now we can move and renable the irq */
ef3e28c5
EB		 2034 if (unlikely(do_unmask_irq)) {
2035 /* Only migrate the irq if the ack has been received.
2036 *
2037 * On rare occasions the broadcast level triggered ack gets
2038 * delayed going to ioapics, and if we reprogram the
2039 * vector while Remote IRR is still set the irq will never
2040 * fire again.
2041 *
2042 * To prevent this scenario we read the Remote IRR bit
2043 * of the ioapic. This has two effects.
2044 * - On any sane system the read of the ioapic will
2045 * flush writes (and acks) going to the ioapic from
2046 * this cpu.
2047 * - We get to see if the ACK has actually been delivered.
2048 *
2049 * Based on failed experiments of reprogramming the
2050 * ioapic entry from outside of irq context starting
2051 * with masking the ioapic entry and then polling until
2052 * Remote IRR was clear before reprogramming the
2053 * ioapic I don't trust the Remote IRR bit to be
2054 * completey accurate.
2055 *
2056 * However there appears to be no other way to plug
2057 * this race, so if the Remote IRR bit is not
2058 * accurate and is causing problems then it is a hardware bug
2059 * and you can go talk to the chipset vendor about it.
2060 */
2061 if (!io_apic_level_ack_pending(irq))
2062 move_masked_irq(irq);
0be6652f 2063 unmask_IO_APIC_irq(irq);
ef3e28c5 2064 }
0be6652f
EB		 2065}
2066
f29bd1ba
IM		 2067static struct irq_chip ioapic_chip __read_mostly = {
2068 .name = "IO-APIC",
04b9267b
EB		 2069 .startup = startup_ioapic_irq,
2070 .mask = mask_IO_APIC_irq,
2071 .unmask = unmask_IO_APIC_irq,
0be6652f
EB		 2072 .ack = ack_apic_edge,
2073 .eoi = ack_apic_level,
54d5d424 2074#ifdef CONFIG_SMP
04b9267b 2075 .set_affinity = set_ioapic_affinity_irq,
54d5d424 2076#endif
04b9267b 2077 .retrigger = ioapic_retrigger_irq,
1da177e4
LT		 2078};
2079
89027d35
SS		 2080#ifdef CONFIG_INTR_REMAP
2081static struct irq_chip ir_ioapic_chip __read_mostly = {
2082 .name = "IR-IO-APIC",
2083 .startup = startup_ioapic_irq,
2084 .mask = mask_IO_APIC_irq,
2085 .unmask = unmask_IO_APIC_irq,
2086 .ack = ack_x2apic_edge,
2087 .eoi = ack_x2apic_level,
2088#ifdef CONFIG_SMP
2089 .set_affinity = set_ir_ioapic_affinity_irq,
2090#endif
2091 .retrigger = ioapic_retrigger_irq,
2092};
2093#endif
2094
1da177e4
LT		 2095static inline void init_IO_APIC_traps(void)
2096{
2097 int irq;
08678b08 2098 struct irq_desc *desc;
46b8214d 2099 struct irq_cfg *cfg;
1da177e4
LT		 2100
2101 /*
2102 * NOTE! The local APIC isn't very good at handling
2103 * multiple interrupts at the same interrupt level.
2104 * As the interrupt level is determined by taking the
2105 * vector number and shifting that right by 4, we
2106 * want to spread these out a bit so that they don't
2107 * all fall in the same interrupt level.
2108 *
2109 * Also, we've got to be careful not to trash gate
2110 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2111 */
46b8214d
YL		 2112 for_each_irq_cfg(cfg) {
2113 irq = cfg->irq;
3ac2de48 2114 if (IO_APIC_IRQ(irq) && !cfg->vector) {
1da177e4
LT		 2115 /*
2116 * Hmm.. We don't have an entry for this,
2117 * so default to an old-fashioned 8259
2118 * interrupt if we can..
2119 */
2120 if (irq < 16)
2121 make_8259A_irq(irq);
08678b08
YL		 2122 else {
2123 desc = irq_to_desc(irq);
1da177e4 2124 /* Strange. Oh, well.. */
08678b08
YL		 2125 desc->chip = &no_irq_chip;
2126 }
1da177e4
LT		 2127 }
2128 }
2129}
2130
c88ac1df 2131static void unmask_lapic_irq(unsigned int irq)
1da177e4
LT		 2132{
2133 unsigned long v;
2134
2135 v = apic_read(APIC_LVT0);
11a8e778 2136 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1da177e4
LT		 2137}
2138
c88ac1df 2139static void mask_lapic_irq(unsigned int irq)
1da177e4
LT		 2140{
2141 unsigned long v;
2142
2143 v = apic_read(APIC_LVT0);
11a8e778 2144 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1da177e4
LT		 2145}
2146
2147static void ack_lapic_irq (unsigned int irq)
2148{
2149 ack_APIC_irq();
2150}
2151
c88ac1df
MR		 2152static struct irq_chip lapic_chip __read_mostly = {
2153 .name = "local-APIC",
2154 .mask = mask_lapic_irq,
2155 .unmask = unmask_lapic_irq,
2156 .ack = ack_lapic_irq,
1da177e4
LT		 2157};
2158
c88ac1df
MR		 2159static void lapic_register_intr(int irq)
2160{
08678b08
YL		 2161 struct irq_desc *desc;
2162
2163 desc = irq_to_desc(irq);
2164 desc->status &= ~IRQ_LEVEL;
c88ac1df
MR		 2165 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2166 "edge");
2167}
2168
e9427101 2169static void __init setup_nmi(void)
1da177e4
LT		 2170{
2171 /*
2172 * Dirty trick to enable the NMI watchdog ...
2173 * We put the 8259A master into AEOI mode and
2174 * unmask on all local APICs LVT0 as NMI.
2175 *
2176 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2177 * is from Maciej W. Rozycki - so we do not have to EOI from
2178 * the NMI handler or the timer interrupt.
2179 */
2180 printk(KERN_INFO "activating NMI Watchdog ...");
2181
e9427101 2182 enable_NMI_through_LVT0();
1da177e4
LT		 2183
2184 printk(" done.\n");
2185}
2186
2187/*
2188 * This looks a bit hackish but it's about the only one way of sending
2189 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2190 * not support the ExtINT mode, unfortunately. We need to send these
2191 * cycles as some i82489DX-based boards have glue logic that keeps the
2192 * 8259A interrupt line asserted until INTA. --macro
2193 */
5afca33a 2194static inline void __init unlock_ExtINT_logic(void)
1da177e4 2195{
1008fddc 2196 int apic, pin, i;
1da177e4
LT		 2197 struct IO_APIC_route_entry entry0, entry1;
2198 unsigned char save_control, save_freq_select;
1da177e4 2199
1008fddc
EB		 2200 pin = find_isa_irq_pin(8, mp_INT);
2201 apic = find_isa_irq_apic(8, mp_INT);
1da177e4
LT		 2202 if (pin == -1)
2203 return;
2204
a2249cba
AM		 2205 entry0 = ioapic_read_entry(apic, pin);
2206
1008fddc 2207 clear_IO_APIC_pin(apic, pin);
1da177e4
LT		 2208
2209 memset(&entry1, 0, sizeof(entry1));
2210
2211 entry1.dest_mode = 0; /* physical delivery */
2212 entry1.mask = 0; /* unmask IRQ now */
ee4eff6f 2213 entry1.dest = hard_smp_processor_id();
1da177e4
LT		 2214 entry1.delivery_mode = dest_ExtINT;
2215 entry1.polarity = entry0.polarity;
2216 entry1.trigger = 0;
2217 entry1.vector = 0;
2218
a2249cba 2219 ioapic_write_entry(apic, pin, entry1);
1da177e4
LT		 2220
2221 save_control = CMOS_READ(RTC_CONTROL);
2222 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2223 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2224 RTC_FREQ_SELECT);
2225 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2226
2227 i = 100;
2228 while (i-- > 0) {
2229 mdelay(10);
2230 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2231 i -= 10;
2232 }
2233
2234 CMOS_WRITE(save_control, RTC_CONTROL);
2235 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1008fddc 2236 clear_IO_APIC_pin(apic, pin);
1da177e4 2237
a2249cba 2238 ioapic_write_entry(apic, pin, entry0);
1da177e4
LT		 2239}
2240
2241/*
2242 * This code may look a bit paranoid, but it's supposed to cooperate with
2243 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2244 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2245 * fanatically on his truly buggy board.
fea5f1e1
LT		 2246 *
2247 * FIXME: really need to revamp this for modern platforms only.
1da177e4 2248 */
e9427101 2249static inline void __init check_timer(void)
1da177e4 2250{
3ac2de48 2251 struct irq_cfg *cfg = irq_cfg(0);
1008fddc 2252 int apic1, pin1, apic2, pin2;
4aae0702 2253 unsigned long flags;
691874fa 2254 int no_pin1 = 0;
4aae0702
IM		 2255
2256 local_irq_save(flags);
1da177e4
LT		 2257
2258 /*
2259 * get/set the timer IRQ vector:
2260 */
2261 disable_8259A_irq(0);
dfbffdd8 2262 assign_irq_vector(0, TARGET_CPUS);
1da177e4
LT		 2263
2264 /*
d11d5794
MR		 2265 * As IRQ0 is to be enabled in the 8259A, the virtual
2266 * wire has to be disabled in the local APIC.
1da177e4 2267 */
11a8e778 2268 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1da177e4 2269 init_8259A(1);
1da177e4 2270
1008fddc
EB		 2271 pin1 = find_isa_irq_pin(0, mp_INT);
2272 apic1 = find_isa_irq_apic(0, mp_INT);
2273 pin2 = ioapic_i8259.pin;
2274 apic2 = ioapic_i8259.apic;
1da177e4 2275
49a66a0b
MR		 2276 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2277 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2278 cfg->vector, apic1, pin1, apic2, pin2);
b0268726 2279
691874fa
MR		 2280 /*
2281 * Some BIOS writers are clueless and report the ExtINTA
2282 * I/O APIC input from the cascaded 8259A as the timer
2283 * interrupt input. So just in case, if only one pin
2284 * was found above, try it both directly and through the
2285 * 8259A.
2286 */
2287 if (pin1 == -1) {
89027d35
SS		 2288 if (intr_remapping_enabled)
2289 panic("BIOS bug: timer not connected to IO-APIC");
691874fa
MR		 2290 pin1 = pin2;
2291 apic1 = apic2;
2292 no_pin1 = 1;
2293 } else if (pin2 == -1) {
2294 pin2 = pin1;
2295 apic2 = apic1;
2296 }
2297
fea5f1e1
LT		 2298 if (pin1 != -1) {
2299 /*
2300 * Ok, does IRQ0 through the IOAPIC work?
2301 */
691874fa
MR		 2302 if (no_pin1) {
2303 add_pin_to_irq(0, apic1, pin1);
b1b57ee1 2304 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
691874fa 2305 }
fea5f1e1
LT		 2306 unmask_IO_APIC_irq(0);
2307 if (!no_timer_check && timer_irq_works()) {
fea5f1e1 2308 if (nmi_watchdog == NMI_IO_APIC) {
fea5f1e1
LT		 2309 setup_nmi();
2310 enable_8259A_irq(0);
2311 }
2312 if (disable_timer_pin_1 > 0)
2313 clear_IO_APIC_pin(0, pin1);
4aae0702 2314 goto out;
fea5f1e1 2315 }
89027d35
SS		 2316 if (intr_remapping_enabled)
2317 panic("timer doesn't work through Interrupt-remapped IO-APIC");
fea5f1e1 2318 clear_IO_APIC_pin(apic1, pin1);
691874fa 2319 if (!no_pin1)
49a66a0b 2320 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
691874fa 2321 "8254 timer not connected to IO-APIC\n");
1da177e4 2322
49a66a0b
MR		 2323 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2324 "(IRQ0) through the 8259A ...\n");
2325 apic_printk(APIC_QUIET, KERN_INFO
2326 "..... (found apic %d pin %d) ...\n", apic2, pin2);
fea5f1e1
LT		 2327 /*
2328 * legacy devices should be connected to IO APIC #0
2329 */
0b9f4f49 2330 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
f7633ce5 2331 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
24742ece 2332 unmask_IO_APIC_irq(0);
ecd29476 2333 enable_8259A_irq(0);
fea5f1e1 2334 if (timer_irq_works()) {
49a66a0b 2335 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
35542c5e 2336 timer_through_8259 = 1;
fea5f1e1 2337 if (nmi_watchdog == NMI_IO_APIC) {
60134ebe 2338 disable_8259A_irq(0);
fea5f1e1 2339 setup_nmi();
60134ebe 2340 enable_8259A_irq(0);
fea5f1e1 2341 }
4aae0702 2342 goto out;
fea5f1e1
LT		 2343 }
2344 /*
2345 * Cleanup, just in case ...
2346 */
ecd29476 2347 disable_8259A_irq(0);
fea5f1e1 2348 clear_IO_APIC_pin(apic2, pin2);
49a66a0b 2349 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
1da177e4 2350 }
1da177e4 2351
1f992153 2352 if (nmi_watchdog == NMI_IO_APIC) {
49a66a0b
MR		 2353 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2354 "through the IO-APIC - disabling NMI Watchdog!\n");
067fa0ff 2355 nmi_watchdog = NMI_NONE;
1da177e4
LT		 2356 }
2357
49a66a0b
MR		 2358 apic_printk(APIC_QUIET, KERN_INFO
2359 "...trying to set up timer as Virtual Wire IRQ...\n");
1da177e4 2360
c88ac1df 2361 lapic_register_intr(0);
dfbffdd8 2362 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
1da177e4
LT		 2363 enable_8259A_irq(0);
2364
2365 if (timer_irq_works()) {
49a66a0b 2366 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
4aae0702 2367 goto out;
1da177e4 2368 }
e67465f1 2369 disable_8259A_irq(0);
dfbffdd8 2370 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
49a66a0b 2371 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
1da177e4 2372
49a66a0b
MR		 2373 apic_printk(APIC_QUIET, KERN_INFO
2374 "...trying to set up timer as ExtINT IRQ...\n");
1da177e4
LT		 2375
2376 init_8259A(0);
2377 make_8259A_irq(0);
11a8e778 2378 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1da177e4
LT		 2379
2380 unlock_ExtINT_logic();
2381
2382 if (timer_irq_works()) {
49a66a0b 2383 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
4aae0702 2384 goto out;
1da177e4 2385 }
49a66a0b
MR		 2386 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2387 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2388 "report. Then try booting with the 'noapic' option.\n");
4aae0702
IM		 2389out:
2390 local_irq_restore(flags);
1da177e4
LT		 2391}
2392
14d98cad
AK		 2393static int __init notimercheck(char *s)
2394{
2395 no_timer_check = 1;
2396 return 1;
2397}
2398__setup("no_timer_check", notimercheck);
2399
1da177e4 2400/*
af174783
MR		 2401 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2402 * to devices. However there may be an I/O APIC pin available for
2403 * this interrupt regardless. The pin may be left unconnected, but
2404 * typically it will be reused as an ExtINT cascade interrupt for
2405 * the master 8259A. In the MPS case such a pin will normally be
2406 * reported as an ExtINT interrupt in the MP table. With ACPI
2407 * there is no provision for ExtINT interrupts, and in the absence
2408 * of an override it would be treated as an ordinary ISA I/O APIC
2409 * interrupt, that is edge-triggered and unmasked by default. We
2410 * used to do this, but it caused problems on some systems because
2411 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2412 * the same ExtINT cascade interrupt to drive the local APIC of the
2413 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2414 * the I/O APIC in all cases now. No actual device should request
2415 * it anyway. --macro
1da177e4
LT		 2416 */
2417#define PIC_IRQS (1<<2)
2418
2419void __init setup_IO_APIC(void)
2420{
1c69524c
YL		 2421
2422 /*
2423 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2424 */
1da177e4 2425
af174783 2426 io_apic_irqs = ~PIC_IRQS;
1da177e4
LT		 2427
2428 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2429
1da177e4
LT		 2430 sync_Arb_IDs();
2431 setup_IO_APIC_irqs();
2432 init_IO_APIC_traps();
2433 check_timer();
1da177e4
LT		 2434}
2435
2436struct sysfs_ioapic_data {
2437 struct sys_device dev;
2438 struct IO_APIC_route_entry entry[0];
2439};
2440static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2441
0b9c33a7 2442static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1da177e4
LT		 2443{
2444 struct IO_APIC_route_entry *entry;
2445 struct sysfs_ioapic_data *data;
1da177e4
LT		 2446 int i;
2447
2448 data = container_of(dev, struct sysfs_ioapic_data, dev);
2449 entry = data->entry;
eea0e11c
AK		 2450 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
2451 *entry = ioapic_read_entry(dev->id, i);
1da177e4
LT		 2452
2453 return 0;
2454}
2455
2456static int ioapic_resume(struct sys_device *dev)
2457{
2458 struct IO_APIC_route_entry *entry;
2459 struct sysfs_ioapic_data *data;
2460 unsigned long flags;
2461 union IO_APIC_reg_00 reg_00;
2462 int i;
2463
2464 data = container_of(dev, struct sysfs_ioapic_data, dev);
2465 entry = data->entry;
2466
2467 spin_lock_irqsave(&ioapic_lock, flags);
2468 reg_00.raw = io_apic_read(dev->id, 0);
ec2cd0a2
AS		 2469 if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) {
2470 reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid;
1da177e4
LT		 2471 io_apic_write(dev->id, 0, reg_00.raw);
2472 }
1da177e4 2473 spin_unlock_irqrestore(&ioapic_lock, flags);
eea0e11c
AK		 2474 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
2475 ioapic_write_entry(dev->id, i, entry[i]);
1da177e4
LT		 2476
2477 return 0;
2478}
2479
2480static struct sysdev_class ioapic_sysdev_class = {
af5ca3f4 2481 .name = "ioapic",
1da177e4
LT		 2482 .suspend = ioapic_suspend,
2483 .resume = ioapic_resume,
2484};
2485
2486static int __init ioapic_init_sysfs(void)
2487{
2488 struct sys_device * dev;
cddf7ff7 2489 int i, size, error;
1da177e4
LT		 2490
2491 error = sysdev_class_register(&ioapic_sysdev_class);
2492 if (error)
2493 return error;
2494
2495 for (i = 0; i < nr_ioapics; i++ ) {
2496 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2497 * sizeof(struct IO_APIC_route_entry);
cddf7ff7 2498 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
1da177e4
LT		 2499 if (!mp_ioapic_data[i]) {
2500 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2501 continue;
2502 }
1da177e4
LT		 2503 dev = &mp_ioapic_data[i]->dev;
2504 dev->id = i;
2505 dev->cls = &ioapic_sysdev_class;
2506 error = sysdev_register(dev);
2507 if (error) {
2508 kfree(mp_ioapic_data[i]);
2509 mp_ioapic_data[i] = NULL;
2510 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2511 continue;
2512 }
2513 }
2514
2515 return 0;
2516}
2517
2518device_initcall(ioapic_init_sysfs);
2519
c4fa0bbf 2520/*
04b9267b 2521 * Dynamic irq allocate and deallocation
c4fa0bbf 2522 */
6d50bc26 2523unsigned int create_irq_nr(unsigned int irq_want)
c4fa0bbf 2524{
04b9267b 2525 /* Allocate an unused irq */
6d50bc26
YL		 2526 unsigned int irq;
2527 unsigned int new;
c4fa0bbf 2528 unsigned long flags;
3ac2de48 2529 struct irq_cfg *cfg_new;
c4fa0bbf 2530
6d50bc26
YL		 2531#ifndef CONFIG_HAVE_SPARSE_IRQ
2532 irq_want = nr_irqs - 1;
2533#endif
2534
2535 irq = 0;
04b9267b 2536 spin_lock_irqsave(&vector_lock, flags);
6d50bc26 2537 for (new = irq_want; new > 0; new--) {
04b9267b
EB		 2538 if (platform_legacy_irq(new))
2539 continue;
3ac2de48
YL		 2540 cfg_new = irq_cfg(new);
2541 if (cfg_new && cfg_new->vector != 0)
04b9267b 2542 continue;
3ac2de48
YL		 2543 /* check if need to create one */
2544 if (!cfg_new)
2545 cfg_new = irq_cfg_alloc(new);
dfbffdd8 2546 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
04b9267b
EB		 2547 irq = new;
2548 break;
2549 }
2550 spin_unlock_irqrestore(&vector_lock, flags);
c4fa0bbf 2551
6d50bc26 2552 if (irq > 0) {
c4fa0bbf
EB		 2553 dynamic_irq_init(irq);
2554 }
2555 return irq;
2556}
2557
6d50bc26
YL		 2558int create_irq(void)
2559{
2560 int irq;
2561
2562 irq = create_irq_nr(nr_irqs - 1);
2563
2564 if (irq == 0)
2565 irq = -1;
2566
2567 return irq;
2568}
2569
c4fa0bbf
EB		 2570void destroy_irq(unsigned int irq)
2571{
2572 unsigned long flags;
c4fa0bbf
EB		 2573
2574 dynamic_irq_cleanup(irq);
2575
75c46fa6
SS		 2576#ifdef CONFIG_INTR_REMAP
2577 free_irte(irq);
2578#endif
c4fa0bbf 2579 spin_lock_irqsave(&vector_lock, flags);
5df0287e 2580 __clear_irq_vector(irq);
c4fa0bbf
EB		 2581 spin_unlock_irqrestore(&vector_lock, flags);
2582}
c4fa0bbf 2583
589e367f 2584/*
676b1855 2585 * MSI message composition
589e367f
EB		 2586 */
2587#ifdef CONFIG_PCI_MSI
3b7d1921 2588static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
589e367f 2589{
3ac2de48 2590 struct irq_cfg *cfg;
dfbffdd8 2591 int err;
589e367f 2592 unsigned dest;
c7111c13 2593 cpumask_t tmp;
589e367f 2594
dfbffdd8
EB		 2595 tmp = TARGET_CPUS;
2596 err = assign_irq_vector(irq, tmp);
75c46fa6
SS		 2597 if (err)
2598 return err;
2599
3ac2de48 2600 cfg = irq_cfg(irq);
75c46fa6
SS		 2601 cpus_and(tmp, cfg->domain, tmp);
2602 dest = cpu_mask_to_apicid(tmp);
2603
2604#ifdef CONFIG_INTR_REMAP
2605 if (irq_remapped(irq)) {
2606 struct irte irte;
2607 int ir_index;
2608 u16 sub_handle;
2609
2610 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
2611 BUG_ON(ir_index == -1);
2612
2613 memset (&irte, 0, sizeof(irte));
2614
2615 irte.present = 1;
2616 irte.dst_mode = INT_DEST_MODE;
2617 irte.trigger_mode = 0; /* edge */
2618 irte.dlvry_mode = INT_DELIVERY_MODE;
2619 irte.vector = cfg->vector;
2620 irte.dest_id = IRTE_DEST(dest);
2621
2622 modify_irte(irq, &irte);
589e367f 2623
75c46fa6
SS		 2624 msg->address_hi = MSI_ADDR_BASE_HI;
2625 msg->data = sub_handle;
2626 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
2627 MSI_ADDR_IR_SHV |
2628 MSI_ADDR_IR_INDEX1(ir_index) |
2629 MSI_ADDR_IR_INDEX2(ir_index);
2630 } else
2631#endif
2632 {
589e367f
EB		 2633 msg->address_hi = MSI_ADDR_BASE_HI;
2634 msg->address_lo =
2635 MSI_ADDR_BASE_LO |
2636 ((INT_DEST_MODE == 0) ?
2637 MSI_ADDR_DEST_MODE_PHYSICAL:
2638 MSI_ADDR_DEST_MODE_LOGICAL) |
2639 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2640 MSI_ADDR_REDIRECTION_CPU:
2641 MSI_ADDR_REDIRECTION_LOWPRI) |
2642 MSI_ADDR_DEST_ID(dest);
2643
2644 msg->data =
2645 MSI_DATA_TRIGGER_EDGE |
2646 MSI_DATA_LEVEL_ASSERT |
2647 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2648 MSI_DATA_DELIVERY_FIXED:
2649 MSI_DATA_DELIVERY_LOWPRI) |
dfbffdd8 2650 MSI_DATA_VECTOR(cfg->vector);
589e367f 2651 }
dfbffdd8 2652 return err;
589e367f
EB		 2653}
2654
3b7d1921
EB		 2655#ifdef CONFIG_SMP
2656static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
589e367f 2657{
3ac2de48 2658 struct irq_cfg *cfg;
3b7d1921
EB		 2659 struct msi_msg msg;
2660 unsigned int dest;
2661 cpumask_t tmp;
08678b08 2662 struct irq_desc *desc;
3b7d1921
EB		 2663
2664 cpus_and(tmp, mask, cpu_online_map);
2665 if (cpus_empty(tmp))
5ff5115e 2666 return;
589e367f 2667
dfbffdd8 2668 if (assign_irq_vector(irq, mask))
3b7d1921 2669 return;
550f2299 2670
3ac2de48 2671 cfg = irq_cfg(irq);
dfbffdd8 2672 cpus_and(tmp, cfg->domain, mask);
3b7d1921 2673 dest = cpu_mask_to_apicid(tmp);
589e367f 2674
3b7d1921
EB		 2675 read_msi_msg(irq, &msg);
2676
2677 msg.data &= ~MSI_DATA_VECTOR_MASK;
dfbffdd8 2678 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3b7d1921
EB		 2679 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2680 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2681
2682 write_msi_msg(irq, &msg);
08678b08
YL		 2683 desc = irq_to_desc(irq);
2684 desc->affinity = mask;
589e367f 2685}
75c46fa6
SS		 2686
2687#ifdef CONFIG_INTR_REMAP
2688/*
2689 * Migrate the MSI irq to another cpumask. This migration is
2690 * done in the process context using interrupt-remapping hardware.
2691 */
2692static void ir_set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2693{
3ac2de48 2694 struct irq_cfg *cfg;
75c46fa6
SS		 2695 unsigned int dest;
2696 cpumask_t tmp, cleanup_mask;
2697 struct irte irte;
08678b08 2698 struct irq_desc *desc;
75c46fa6
SS		 2699
2700 cpus_and(tmp, mask, cpu_online_map);
2701 if (cpus_empty(tmp))
2702 return;
2703
2704 if (get_irte(irq, &irte))
2705 return;
2706
2707 if (assign_irq_vector(irq, mask))
2708 return;
2709
3ac2de48 2710 cfg = irq_cfg(irq);
75c46fa6
SS		 2711 cpus_and(tmp, cfg->domain, mask);
2712 dest = cpu_mask_to_apicid(tmp);
2713
2714 irte.vector = cfg->vector;
2715 irte.dest_id = IRTE_DEST(dest);
2716
2717 /*
2718 * atomically update the IRTE with the new destination and vector.
2719 */
2720 modify_irte(irq, &irte);
2721
2722 /*
2723 * After this point, all the interrupts will start arriving
2724 * at the new destination. So, time to cleanup the previous
2725 * vector allocation.
2726 */
2727 if (cfg->move_in_progress) {
2728 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
2729 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
2730 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2731 cfg->move_in_progress = 0;
2732 }
2733
08678b08
YL		 2734 desc = irq_to_desc(irq);
2735 desc->affinity = mask;
75c46fa6
SS		 2736}
2737#endif
3b7d1921 2738#endif /* CONFIG_SMP */
589e367f 2739
3b7d1921
EB		 2740/*
2741 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2742 * which implement the MSI or MSI-X Capability Structure.
2743 */
2744static struct irq_chip msi_chip = {
2745 .name = "PCI-MSI",
2746 .unmask = unmask_msi_irq,
2747 .mask = mask_msi_irq,
2748 .ack = ack_apic_edge,
2749#ifdef CONFIG_SMP
2750 .set_affinity = set_msi_irq_affinity,
2751#endif
2752 .retrigger = ioapic_retrigger_irq,
589e367f
EB		 2753};
2754
75c46fa6
SS		 2755#ifdef CONFIG_INTR_REMAP
2756static struct irq_chip msi_ir_chip = {
2757 .name = "IR-PCI-MSI",
2758 .unmask = unmask_msi_irq,
2759 .mask = mask_msi_irq,
2760 .ack = ack_x2apic_edge,
2761#ifdef CONFIG_SMP
2762 .set_affinity = ir_set_msi_irq_affinity,
2763#endif
2764 .retrigger = ioapic_retrigger_irq,
2765};
2766
2767/*
2768 * Map the PCI dev to the corresponding remapping hardware unit
2769 * and allocate 'nvec' consecutive interrupt-remapping table entries
2770 * in it.
2771 */
2772static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3b7d1921 2773{
75c46fa6
SS		 2774 struct intel_iommu *iommu;
2775 int index;
2776
2777 iommu = map_dev_to_ir(dev);
2778 if (!iommu) {
2779 printk(KERN_ERR
2780 "Unable to map PCI %s to iommu\n", pci_name(dev));
2781 return -ENOENT;
2782 }
2783
2784 index = alloc_irte(iommu, irq, nvec);
2785 if (index < 0) {
2786 printk(KERN_ERR
2787 "Unable to allocate %d IRTE for PCI %s\n", nvec,
2788 pci_name(dev));
2789 return -ENOSPC;
2790 }
2791 return index;
2792}
2793#endif
2794
2795static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc, int irq)
2796{
2797 int ret;
3b7d1921 2798 struct msi_msg msg;
75c46fa6
SS		 2799
2800 ret = msi_compose_msg(dev, irq, &msg);
2801 if (ret < 0)
2802 return ret;
2803
2804 set_irq_msi(irq, desc);
2805 write_msi_msg(irq, &msg);
2806
2807#ifdef CONFIG_INTR_REMAP
2808 if (irq_remapped(irq)) {
08678b08 2809 struct irq_desc *desc = irq_to_desc(irq);
75c46fa6
SS		 2810 /*
2811 * irq migration in process context
2812 */
2813 desc->status |= IRQ_MOVE_PCNTXT;
2814 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
2815 } else
2816#endif
2817 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
2818
2819 return 0;
2820}
2821
6d50bc26
YL		 2822static unsigned int build_irq_for_pci_dev(struct pci_dev *dev)
2823{
2824 unsigned int irq;
2825
2826 irq = dev->bus->number;
2827 irq <<= 8;
2828 irq |= dev->devfn;
2829 irq <<= 12;
2830
2831 return irq;
2832}
2833
75c46fa6
SS		 2834int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2835{
6d50bc26
YL		 2836 unsigned int irq;
2837 int ret;
2838 unsigned int irq_want;
75c46fa6 2839
6d50bc26
YL		 2840 irq_want = build_irq_for_pci_dev(dev) + 0x100;
2841
2842 irq = create_irq_nr(irq_want);
2843 if (irq == 0)
2844 return -1;
f7feaca7 2845
75c46fa6
SS		 2846#ifdef CONFIG_INTR_REMAP
2847 if (!intr_remapping_enabled)
2848 goto no_ir;
2849
2850 ret = msi_alloc_irte(dev, irq, 1);
2851 if (ret < 0)
2852 goto error;
2853no_ir:
2854#endif
2855 ret = setup_msi_irq(dev, desc, irq);
f7feaca7
EB		 2856 if (ret < 0) {
2857 destroy_irq(irq);
3b7d1921 2858 return ret;
f7feaca7 2859 }
75c46fa6 2860 return 0;
3b7d1921 2861
75c46fa6
SS		 2862#ifdef CONFIG_INTR_REMAP
2863error:
2864 destroy_irq(irq);
2865 return ret;
2866#endif
2867}
3b7d1921 2868
75c46fa6
SS		 2869int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
2870{
6d50bc26
YL		 2871 unsigned int irq;
2872 int ret, sub_handle;
75c46fa6 2873 struct msi_desc *desc;
6d50bc26
YL		 2874 unsigned int irq_want;
2875
75c46fa6
SS		 2876#ifdef CONFIG_INTR_REMAP
2877 struct intel_iommu *iommu = 0;
2878 int index = 0;
2879#endif
2880
6d50bc26 2881 irq_want = build_irq_for_pci_dev(dev) + 0x100;
75c46fa6
SS		 2882 sub_handle = 0;
2883 list_for_each_entry(desc, &dev->msi_list, list) {
6d50bc26
YL		 2884 irq = create_irq_nr(irq_want--);
2885 if (irq == 0)
2886 return -1;
75c46fa6
SS		 2887#ifdef CONFIG_INTR_REMAP
2888 if (!intr_remapping_enabled)
2889 goto no_ir;
3b7d1921 2890
75c46fa6
SS		 2891 if (!sub_handle) {
2892 /*
2893 * allocate the consecutive block of IRTE's
2894 * for 'nvec'
2895 */
2896 index = msi_alloc_irte(dev, irq, nvec);
2897 if (index < 0) {
2898 ret = index;
2899 goto error;
2900 }
2901 } else {
2902 iommu = map_dev_to_ir(dev);
2903 if (!iommu) {
2904 ret = -ENOENT;
2905 goto error;
2906 }
2907 /*
2908 * setup the mapping between the irq and the IRTE
2909 * base index, the sub_handle pointing to the
2910 * appropriate interrupt remap table entry.
2911 */
2912 set_irte_irq(irq, iommu, index, sub_handle);
2913 }
2914no_ir:
2915#endif
2916 ret = setup_msi_irq(dev, desc, irq);
2917 if (ret < 0)
2918 goto error;
2919 sub_handle++;
2920 }
7fe3730d 2921 return 0;
75c46fa6
SS		 2922
2923error:
2924 destroy_irq(irq);
2925 return ret;
3b7d1921
EB		 2926}
2927
2928void arch_teardown_msi_irq(unsigned int irq)
2929{
f7feaca7 2930 destroy_irq(irq);
3b7d1921
EB		 2931}
2932
3460a6d9
KA		 2933#ifdef CONFIG_DMAR
2934#ifdef CONFIG_SMP
2935static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask)
2936{
3ac2de48 2937 struct irq_cfg *cfg;
3460a6d9
KA		 2938 struct msi_msg msg;
2939 unsigned int dest;
2940 cpumask_t tmp;
08678b08 2941 struct irq_desc *desc;
3460a6d9
KA		 2942
2943 cpus_and(tmp, mask, cpu_online_map);
2944 if (cpus_empty(tmp))
2945 return;
2946
2947 if (assign_irq_vector(irq, mask))
2948 return;
2949
3ac2de48 2950 cfg = irq_cfg(irq);
3460a6d9
KA		 2951 cpus_and(tmp, cfg->domain, mask);
2952 dest = cpu_mask_to_apicid(tmp);
2953
2954 dmar_msi_read(irq, &msg);
2955
2956 msg.data &= ~MSI_DATA_VECTOR_MASK;
2957 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2958 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2959 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2960
2961 dmar_msi_write(irq, &msg);
08678b08
YL		 2962 desc = irq_to_desc(irq);
2963 desc->affinity = mask;
3460a6d9
KA		 2964}
2965#endif /* CONFIG_SMP */
2966
2967struct irq_chip dmar_msi_type = {
2968 .name = "DMAR_MSI",
2969 .unmask = dmar_msi_unmask,
2970 .mask = dmar_msi_mask,
2971 .ack = ack_apic_edge,
2972#ifdef CONFIG_SMP
2973 .set_affinity = dmar_msi_set_affinity,
2974#endif
2975 .retrigger = ioapic_retrigger_irq,
2976};
2977
2978int arch_setup_dmar_msi(unsigned int irq)
2979{
2980 int ret;
2981 struct msi_msg msg;
2982
2983 ret = msi_compose_msg(NULL, irq, &msg);
2984 if (ret < 0)
2985 return ret;
2986 dmar_msi_write(irq, &msg);
2987 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
2988 "edge");
2989 return 0;
2990}
2991#endif
589e367f 2992
3460a6d9 2993#endif /* CONFIG_PCI_MSI */
8b955b0d
EB		 2994/*
2995 * Hypertransport interrupt support
2996 */
2997#ifdef CONFIG_HT_IRQ
2998
2999#ifdef CONFIG_SMP
3000
3001static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3002{
ec68307c
EB		 3003 struct ht_irq_msg msg;
3004 fetch_ht_irq_msg(irq, &msg);
8b955b0d 3005
ec68307c
EB		 3006 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3007 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
8b955b0d 3008
ec68307c
EB		 3009 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3010 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
8b955b0d 3011
ec68307c 3012 write_ht_irq_msg(irq, &msg);
8b955b0d
EB		 3013}
3014
3015static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
3016{
3ac2de48 3017 struct irq_cfg *cfg;
8b955b0d
EB		 3018 unsigned int dest;
3019 cpumask_t tmp;
08678b08 3020 struct irq_desc *desc;
8b955b0d
EB		 3021
3022 cpus_and(tmp, mask, cpu_online_map);
3023 if (cpus_empty(tmp))
5ff5115e 3024 return;
8b955b0d 3025
dfbffdd8 3026 if (assign_irq_vector(irq, mask))
8b955b0d
EB		 3027 return;
3028
3ac2de48 3029 cfg = irq_cfg(irq);
dfbffdd8 3030 cpus_and(tmp, cfg->domain, mask);
8b955b0d
EB		 3031 dest = cpu_mask_to_apicid(tmp);
3032
dfbffdd8 3033 target_ht_irq(irq, dest, cfg->vector);
08678b08
YL		 3034 desc = irq_to_desc(irq);
3035 desc->affinity = mask;
8b955b0d
EB		 3036}
3037#endif
3038
c37e108d 3039static struct irq_chip ht_irq_chip = {
8b955b0d
EB		 3040 .name = "PCI-HT",
3041 .mask = mask_ht_irq,
3042 .unmask = unmask_ht_irq,
3043 .ack = ack_apic_edge,
3044#ifdef CONFIG_SMP
3045 .set_affinity = set_ht_irq_affinity,
3046#endif
3047 .retrigger = ioapic_retrigger_irq,
3048};
3049
3050int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3051{
3ac2de48 3052 struct irq_cfg *cfg;
dfbffdd8 3053 int err;
c7111c13 3054 cpumask_t tmp;
8b955b0d 3055
dfbffdd8
EB		 3056 tmp = TARGET_CPUS;
3057 err = assign_irq_vector(irq, tmp);
3058 if (!err) {
ec68307c 3059 struct ht_irq_msg msg;
8b955b0d 3060 unsigned dest;
8b955b0d 3061
3ac2de48 3062 cfg = irq_cfg(irq);
dfbffdd8 3063 cpus_and(tmp, cfg->domain, tmp);
8b955b0d
EB		 3064 dest = cpu_mask_to_apicid(tmp);
3065
ec68307c 3066 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
8b955b0d 3067
ec68307c
EB		 3068 msg.address_lo =
3069 HT_IRQ_LOW_BASE |
8b955b0d 3070 HT_IRQ_LOW_DEST_ID(dest) |
dfbffdd8 3071 HT_IRQ_LOW_VECTOR(cfg->vector) |
8b955b0d
EB		 3072 ((INT_DEST_MODE == 0) ?
3073 HT_IRQ_LOW_DM_PHYSICAL :
3074 HT_IRQ_LOW_DM_LOGICAL) |
3075 HT_IRQ_LOW_RQEOI_EDGE |
3076 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3077 HT_IRQ_LOW_MT_FIXED :
ec68307c
EB		 3078 HT_IRQ_LOW_MT_ARBITRATED) |
3079 HT_IRQ_LOW_IRQ_MASKED;
8b955b0d 3080
ec68307c 3081 write_ht_irq_msg(irq, &msg);
8b955b0d 3082
a460e745
IM		 3083 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3084 handle_edge_irq, "edge");
8b955b0d 3085 }
dfbffdd8 3086 return err;
8b955b0d
EB		 3087}
3088#endif /* CONFIG_HT_IRQ */
3089
1da177e4
LT		 3090/* --------------------------------------------------------------------------
3091 ACPI-based IOAPIC Configuration
3092 -------------------------------------------------------------------------- */
3093
888ba6c6 3094#ifdef CONFIG_ACPI
1da177e4
LT		 3095
3096#define IO_APIC_MAX_ID 0xFE
3097
1da177e4
LT		 3098int __init io_apic_get_redir_entries (int ioapic)
3099{
3100 union IO_APIC_reg_01 reg_01;
3101 unsigned long flags;
3102
3103 spin_lock_irqsave(&ioapic_lock, flags);
3104 reg_01.raw = io_apic_read(ioapic, 1);
3105 spin_unlock_irqrestore(&ioapic_lock, flags);
3106
3107 return reg_01.bits.entries;
3108}
3109
3110
50eca3eb 3111int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
1da177e4 3112{
1da177e4
LT		 3113 if (!IO_APIC_IRQ(irq)) {
3114 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3115 ioapic);
3116 return -EINVAL;
3117 }
3118
550f2299
EB		 3119 /*
3120 * IRQs < 16 are already in the irq_2_pin[] map
3121 */
3122 if (irq >= 16)
3123 add_pin_to_irq(irq, ioapic, pin);
3124
a8c8a367 3125 setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
1da177e4
LT		 3126
3127 return 0;
3128}
3129
1da177e4 3130
61fd47e0
SL		 3131int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
3132{
3133 int i;
3134
3135 if (skip_ioapic_setup)
3136 return -1;
3137
3138 for (i = 0; i < mp_irq_entries; i++)
2fddb6e2
AS		 3139 if (mp_irqs[i].mp_irqtype == mp_INT &&
3140 mp_irqs[i].mp_srcbusirq == bus_irq)
61fd47e0
SL		 3141 break;
3142 if (i >= mp_irq_entries)
3143 return -1;
3144
3145 *trigger = irq_trigger(i);
3146 *polarity = irq_polarity(i);
3147 return 0;
3148}
3149
3150#endif /* CONFIG_ACPI */
1da177e4
LT		 3151
3152/*
3153 * This function currently is only a helper for the i386 smp boot process where
3154 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3155 * so mask in all cases should simply be TARGET_CPUS
3156 */
54d5d424 3157#ifdef CONFIG_SMP
1da177e4
LT		 3158void __init setup_ioapic_dest(void)
3159{
3160 int pin, ioapic, irq, irq_entry;
3ac2de48 3161 struct irq_cfg *cfg;
1da177e4
LT		 3162
3163 if (skip_ioapic_setup == 1)
3164 return;
3165
3166 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
3167 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
3168 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
3169 if (irq_entry == -1)
3170 continue;
3171 irq = pin_2_irq(irq_entry, ioapic, pin);
ad892f5e
YL		 3172
3173 /* setup_IO_APIC_irqs could fail to get vector for some device
3174 * when you have too many devices, because at that time only boot
3175 * cpu is online.
3176 */
3ac2de48
YL		 3177 cfg = irq_cfg(irq);
3178 if (!cfg->vector)
a8c8a367
EB		 3179 setup_IO_APIC_irq(ioapic, pin, irq,
3180 irq_trigger(irq_entry),
3181 irq_polarity(irq_entry));
89027d35
SS		 3182#ifdef CONFIG_INTR_REMAP
3183 else if (intr_remapping_enabled)
3184 set_ir_ioapic_affinity_irq(irq, TARGET_CPUS);
3185#endif
ad892f5e
YL		 3186 else
3187 set_ioapic_affinity_irq(irq, TARGET_CPUS);
1da177e4
LT		 3188 }
3189
3190 }
3191}
54d5d424 3192#endif
61fd47e0 3193
3e35a0e5
TG		 3194#define IOAPIC_RESOURCE_NAME_SIZE 11
3195
3196static struct resource *ioapic_resources;
3197
3198static struct resource * __init ioapic_setup_resources(void)
3199{
3200 unsigned long n;
3201 struct resource *res;
3202 char *mem;
3203 int i;
3204
3205 if (nr_ioapics <= 0)
3206 return NULL;
3207
3208 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
3209 n *= nr_ioapics;
3210
3211 mem = alloc_bootmem(n);
3212 res = (void *)mem;
3213
3214 if (mem != NULL) {
3e35a0e5
TG		 3215 mem += sizeof(struct resource) * nr_ioapics;
3216
3217 for (i = 0; i < nr_ioapics; i++) {
3218 res[i].name = mem;
3219 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
3220 sprintf(mem, "IOAPIC %u", i);
3221 mem += IOAPIC_RESOURCE_NAME_SIZE;
3222 }
3223 }
3224
3225 ioapic_resources = res;
3226
3227 return res;
3228}
3229
3230void __init ioapic_init_mappings(void)
3231{
3232 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
3233 struct resource *ioapic_res;
3234 int i;
3235
3236 ioapic_res = ioapic_setup_resources();
3237 for (i = 0; i < nr_ioapics; i++) {
3238 if (smp_found_config) {
ec2cd0a2 3239 ioapic_phys = mp_ioapics[i].mp_apicaddr;
3e35a0e5
TG		 3240 } else {
3241 ioapic_phys = (unsigned long)
3242 alloc_bootmem_pages(PAGE_SIZE);
3243 ioapic_phys = __pa(ioapic_phys);
3244 }
3245 set_fixmap_nocache(idx, ioapic_phys);
3246 apic_printk(APIC_VERBOSE,
3247 "mapped IOAPIC to %016lx (%016lx)\n",
3248 __fix_to_virt(idx), ioapic_phys);
3249 idx++;
3250
3251 if (ioapic_res != NULL) {
3252 ioapic_res->start = ioapic_phys;
3253 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
3254 ioapic_res++;
3255 }
3256 }
3257}
3258
3259static int __init ioapic_insert_resources(void)
3260{
3261 int i;
3262 struct resource *r = ioapic_resources;
3263
3264 if (!r) {
3265 printk(KERN_ERR
3266 "IO APIC resources could be not be allocated.\n");
3267 return -1;
3268 }
3269
3270 for (i = 0; i < nr_ioapics; i++) {
3271 insert_resource(&iomem_resource, r);
3272 r++;
3273 }
3274
3275 return 0;
3276}
3277
3278/* Insert the IO APIC resources after PCI initialization has occured to handle
3279 * IO APICS that are mapped in on a BAR in PCI space. */
3280late_initcall(ioapic_insert_resources);
3281
Linux kernel - Deliverables
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