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smp_call_function: get rid of the unused nonatomic/retry argument
[deliverable/linux.git] / arch / x86 / kernel / io_apic_64.c
CommitLineData
1da177e4
LT		 1/*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23#include <linux/mm.h>
1da177e4
LT		 24#include <linux/interrupt.h>
25#include <linux/init.h>
26#include <linux/delay.h>
27#include <linux/sched.h>
589e367f 28#include <linux/pci.h>
1da177e4
LT		 29#include <linux/mc146818rtc.h>
30#include <linux/acpi.h>
31#include <linux/sysdev.h>
3b7d1921 32#include <linux/msi.h>
95d77884 33#include <linux/htirq.h>
3460a6d9 34#include <linux/dmar.h>
1d16b53e 35#include <linux/jiffies.h>
ab688059
AK		 36#ifdef CONFIG_ACPI
37#include <acpi/acpi_bus.h>
38#endif
3e35a0e5 39#include <linux/bootmem.h>
1da177e4 40
61014292 41#include <asm/idle.h>
1da177e4
LT		 42#include <asm/io.h>
43#include <asm/smp.h>
44#include <asm/desc.h>
45#include <asm/proto.h>
8d916406 46#include <asm/acpi.h>
ca8642f6 47#include <asm/dma.h>
3e4ff115 48#include <asm/nmi.h>
589e367f 49#include <asm/msidef.h>
8b955b0d 50#include <asm/hypertransport.h>
1da177e4 51
5af5573e 52#include <mach_ipi.h>
dd46e3ca 53#include <mach_apic.h>
5af5573e 54
13a79503
EB		 55struct irq_cfg {
56 cpumask_t domain;
61014292
EB		 57 cpumask_t old_domain;
58 unsigned move_cleanup_count;
13a79503 59 u8 vector;
61014292 60 u8 move_in_progress : 1;
13a79503
EB		 61};
62
63/* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
64struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
bc5e81a1
EB		 65 [0] = { .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
66 [1] = { .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
67 [2] = { .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
68 [3] = { .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
69 [4] = { .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
70 [5] = { .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
71 [6] = { .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
72 [7] = { .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
73 [8] = { .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
74 [9] = { .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
75 [10] = { .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
76 [11] = { .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
77 [12] = { .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
78 [13] = { .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
79 [14] = { .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
80 [15] = { .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
13a79503
EB		 81};
82
dfbffdd8 83static int assign_irq_vector(int irq, cpumask_t mask);
04b9267b 84
1da177e4
LT		 85#define __apicdebuginit __init
86
87int sis_apic_bug; /* not actually supported, dummy for compile */
88
14d98cad
AK		 89static int no_timer_check;
90
fea5f1e1
LT		 91static int disable_timer_pin_1 __initdata;
92
93int timer_over_8254 __initdata = 1;
94
1008fddc
EB		 95/* Where if anywhere is the i8259 connect in external int mode */
96static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
97
1da177e4 98static DEFINE_SPINLOCK(ioapic_lock);
70a0a535 99DEFINE_SPINLOCK(vector_lock);
1da177e4
LT		 100
101/*
102 * # of IRQ routing registers
103 */
104int nr_ioapic_registers[MAX_IO_APICS];
105
9c7408f3
AS		 106/* I/O APIC entries */
107struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
108int nr_ioapics;
109
350bae1d
AS		 110/* MP IRQ source entries */
111struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
112
113/* # of MP IRQ source entries */
114int mp_irq_entries;
115
1da177e4
LT		 116/*
117 * Rough estimation of how many shared IRQs there are, can
118 * be changed anytime.
119 */
e273d140 120#define MAX_PLUS_SHARED_IRQS NR_IRQS
1da177e4
LT		 121#define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
122
123/*
124 * This is performance-critical, we want to do it O(1)
125 *
126 * the indexing order of this array favors 1:1 mappings
127 * between pins and IRQs.
128 */
129
130static struct irq_pin_list {
131 short apic, pin, next;
132} irq_2_pin[PIN_MAP_SIZE];
133
6c0ffb9d
LT		 134struct io_apic {
135 unsigned int index;
136 unsigned int unused[3];
137 unsigned int data;
138};
139
140static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
141{
142 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
143 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
144}
145
146static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
147{
148 struct io_apic __iomem *io_apic = io_apic_base(apic);
149 writel(reg, &io_apic->index);
150 return readl(&io_apic->data);
151}
152
153static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
154{
155 struct io_apic __iomem *io_apic = io_apic_base(apic);
156 writel(reg, &io_apic->index);
157 writel(value, &io_apic->data);
158}
159
160/*
161 * Re-write a value: to be used for read-modify-write
162 * cycles where the read already set up the index register.
163 */
164static inline void io_apic_modify(unsigned int apic, unsigned int value)
165{
166 struct io_apic __iomem *io_apic = io_apic_base(apic);
167 writel(value, &io_apic->data);
168}
169
9d25cb08 170static bool io_apic_level_ack_pending(unsigned int irq)
ef3e28c5
EB		 171{
172 struct irq_pin_list *entry;
173 unsigned long flags;
ef3e28c5
EB		 174
175 spin_lock_irqsave(&ioapic_lock, flags);
176 entry = irq_2_pin + irq;
177 for (;;) {
178 unsigned int reg;
179 int pin;
180
181 pin = entry->pin;
182 if (pin == -1)
183 break;
184 reg = io_apic_read(entry->apic, 0x10 + pin*2);
185 /* Is the remote IRR bit set? */
9d25cb08
AM		 186 if ((reg >> 14) & 1) {
187 spin_unlock_irqrestore(&ioapic_lock, flags);
188 return true;
189 }
ef3e28c5
EB		 190 if (!entry->next)
191 break;
192 entry = irq_2_pin + entry->next;
193 }
194 spin_unlock_irqrestore(&ioapic_lock, flags);
9d25cb08
AM		 195
196 return false;
ef3e28c5
EB		 197}
198
6c0ffb9d
LT		 199/*
200 * Synchronize the IO-APIC and the CPU by doing
201 * a dummy read from the IO-APIC
202 */
203static inline void io_apic_sync(unsigned int apic)
204{
205 struct io_apic __iomem *io_apic = io_apic_base(apic);
206 readl(&io_apic->data);
207}
208
54d5d424
AR		 209#define __DO_ACTION(R, ACTION, FINAL) \
210 \
211{ \
212 int pin; \
213 struct irq_pin_list *entry = irq_2_pin + irq; \
214 \
6004e1b7 215 BUG_ON(irq >= NR_IRQS); \
54d5d424
AR		 216 for (;;) { \
217 unsigned int reg; \
218 pin = entry->pin; \
219 if (pin == -1) \
220 break; \
221 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
222 reg ACTION; \
223 io_apic_modify(entry->apic, reg); \
f45bcd70 224 FINAL; \
54d5d424
AR		 225 if (!entry->next) \
226 break; \
227 entry = irq_2_pin + entry->next; \
228 } \
54d5d424
AR		 229}
230
eea0e11c
AK		 231union entry_union {
232 struct { u32 w1, w2; };
233 struct IO_APIC_route_entry entry;
234};
235
236static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
237{
238 union entry_union eu;
239 unsigned long flags;
240 spin_lock_irqsave(&ioapic_lock, flags);
241 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
242 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
243 spin_unlock_irqrestore(&ioapic_lock, flags);
244 return eu.entry;
245}
246
48797ebd
LT		 247/*
248 * When we write a new IO APIC routing entry, we need to write the high
249 * word first! If the mask bit in the low word is clear, we will enable
250 * the interrupt, and we need to make sure the entry is fully populated
251 * before that happens.
252 */
516d2836
AK		 253static void
254__ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
eea0e11c 255{
eea0e11c
AK		 256 union entry_union eu;
257 eu.entry = e;
48797ebd
LT		 258 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
259 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
516d2836
AK		 260}
261
262static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
263{
264 unsigned long flags;
265 spin_lock_irqsave(&ioapic_lock, flags);
266 __ioapic_write_entry(apic, pin, e);
48797ebd
LT		 267 spin_unlock_irqrestore(&ioapic_lock, flags);
268}
269
270/*
271 * When we mask an IO APIC routing entry, we need to write the low
272 * word first, in order to set the mask bit before we change the
273 * high bits!
274 */
275static void ioapic_mask_entry(int apic, int pin)
276{
277 unsigned long flags;
278 union entry_union eu = { .entry.mask = 1 };
279
eea0e11c
AK		 280 spin_lock_irqsave(&ioapic_lock, flags);
281 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
282 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
283 spin_unlock_irqrestore(&ioapic_lock, flags);
284}
285
54d5d424 286#ifdef CONFIG_SMP
550f2299
EB		 287static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
288{
289 int apic, pin;
290 struct irq_pin_list *entry = irq_2_pin + irq;
291
292 BUG_ON(irq >= NR_IRQS);
293 for (;;) {
294 unsigned int reg;
295 apic = entry->apic;
296 pin = entry->pin;
297 if (pin == -1)
298 break;
299 io_apic_write(apic, 0x11 + pin*2, dest);
300 reg = io_apic_read(apic, 0x10 + pin*2);
301 reg &= ~0x000000ff;
302 reg |= vector;
303 io_apic_modify(apic, reg);
304 if (!entry->next)
305 break;
306 entry = irq_2_pin + entry->next;
307 }
308}
309
54d5d424
AR		 310static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
311{
dfbffdd8 312 struct irq_cfg *cfg = irq_cfg + irq;
54d5d424
AR		 313 unsigned long flags;
314 unsigned int dest;
315 cpumask_t tmp;
316
317 cpus_and(tmp, mask, cpu_online_map);
318 if (cpus_empty(tmp))
5ff5115e 319 return;
54d5d424 320
dfbffdd8 321 if (assign_irq_vector(irq, mask))
550f2299
EB		 322 return;
323
dfbffdd8 324 cpus_and(tmp, cfg->domain, mask);
550f2299 325 dest = cpu_mask_to_apicid(tmp);
54d5d424
AR		 326
327 /*
328 * Only the high 8 bits are valid.
329 */
330 dest = SET_APIC_LOGICAL_ID(dest);
331
332 spin_lock_irqsave(&ioapic_lock, flags);
dfbffdd8 333 __target_IO_APIC_irq(irq, dest, cfg->vector);
9f0a5ba5 334 irq_desc[irq].affinity = mask;
54d5d424
AR		 335 spin_unlock_irqrestore(&ioapic_lock, flags);
336}
337#endif
338
1da177e4
LT		 339/*
340 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
341 * shared ISA-space IRQs, so we have to support them. We are super
342 * fast in the common case, and fast for shared ISA-space IRQs.
343 */
344static void add_pin_to_irq(unsigned int irq, int apic, int pin)
345{
346 static int first_free_entry = NR_IRQS;
347 struct irq_pin_list *entry = irq_2_pin + irq;
348
6004e1b7 349 BUG_ON(irq >= NR_IRQS);
1da177e4
LT		 350 while (entry->next)
351 entry = irq_2_pin + entry->next;
352
353 if (entry->pin != -1) {
354 entry->next = first_free_entry;
355 entry = irq_2_pin + entry->next;
356 if (++first_free_entry >= PIN_MAP_SIZE)
6004e1b7 357 panic("io_apic.c: ran out of irq_2_pin entries!");
1da177e4
LT		 358 }
359 entry->apic = apic;
360 entry->pin = pin;
361}
362
1da177e4
LT		 363
364#define DO_ACTION(name,R,ACTION, FINAL) \
365 \
366 static void name##_IO_APIC_irq (unsigned int irq) \
367 __DO_ACTION(R, ACTION, FINAL)
368
369DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
370 /* mask = 1 */
371DO_ACTION( __unmask, 0, &= 0xfffeffff, )
372 /* mask = 0 */
373
374static void mask_IO_APIC_irq (unsigned int irq)
375{
376 unsigned long flags;
377
378 spin_lock_irqsave(&ioapic_lock, flags);
379 __mask_IO_APIC_irq(irq);
380 spin_unlock_irqrestore(&ioapic_lock, flags);
381}
382
383static void unmask_IO_APIC_irq (unsigned int irq)
384{
385 unsigned long flags;
386
387 spin_lock_irqsave(&ioapic_lock, flags);
388 __unmask_IO_APIC_irq(irq);
389 spin_unlock_irqrestore(&ioapic_lock, flags);
390}
391
392static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
393{
394 struct IO_APIC_route_entry entry;
1da177e4
LT		 395
396 /* Check delivery_mode to be sure we're not clearing an SMI pin */
eea0e11c 397 entry = ioapic_read_entry(apic, pin);
1da177e4
LT		 398 if (entry.delivery_mode == dest_SMI)
399 return;
400 /*
401 * Disable it in the IO-APIC irq-routing table:
402 */
48797ebd 403 ioapic_mask_entry(apic, pin);
1da177e4
LT		 404}
405
406static void clear_IO_APIC (void)
407{
408 int apic, pin;
409
410 for (apic = 0; apic < nr_ioapics; apic++)
411 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
412 clear_IO_APIC_pin(apic, pin);
413}
414
1da177e4
LT		 415int skip_ioapic_setup;
416int ioapic_force;
417
61ec7567 418static int __init parse_noapic(char *str)
1da177e4 419{
61ec7567 420 disable_ioapic_setup();
2c8c0e6b 421 return 0;
1da177e4 422}
61ec7567 423early_param("noapic", parse_noapic);
1da177e4 424
fea5f1e1
LT		 425/* Actually the next is obsolete, but keep it for paranoid reasons -AK */
426static int __init disable_timer_pin_setup(char *arg)
427{
428 disable_timer_pin_1 = 1;
429 return 1;
430}
431__setup("disable_timer_pin_1", disable_timer_pin_setup);
432
433static int __init setup_disable_8254_timer(char *s)
434{
435 timer_over_8254 = -1;
436 return 1;
437}
438static int __init setup_enable_8254_timer(char *s)
439{
440 timer_over_8254 = 2;
441 return 1;
442}
443
444__setup("disable_8254_timer", setup_disable_8254_timer);
445__setup("enable_8254_timer", setup_enable_8254_timer);
446
447
1da177e4
LT		 448/*
449 * Find the IRQ entry number of a certain pin.
450 */
451static int find_irq_entry(int apic, int pin, int type)
452{
453 int i;
454
455 for (i = 0; i < mp_irq_entries; i++)
456 if (mp_irqs[i].mpc_irqtype == type &&
457 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
458 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
459 mp_irqs[i].mpc_dstirq == pin)
460 return i;
461
462 return -1;
463}
464
465/*
466 * Find the pin to which IRQ[irq] (ISA) is connected
467 */
1008fddc 468static int __init find_isa_irq_pin(int irq, int type)
1da177e4
LT		 469{
470 int i;
471
472 for (i = 0; i < mp_irq_entries; i++) {
473 int lbus = mp_irqs[i].mpc_srcbus;
474
55f05ffa 475 if (test_bit(lbus, mp_bus_not_pci) &&
1da177e4
LT		 476 (mp_irqs[i].mpc_irqtype == type) &&
477 (mp_irqs[i].mpc_srcbusirq == irq))
478
479 return mp_irqs[i].mpc_dstirq;
480 }
481 return -1;
482}
483
1008fddc
EB		 484static int __init find_isa_irq_apic(int irq, int type)
485{
486 int i;
487
488 for (i = 0; i < mp_irq_entries; i++) {
489 int lbus = mp_irqs[i].mpc_srcbus;
490
55f05ffa 491 if (test_bit(lbus, mp_bus_not_pci) &&
1008fddc
EB		 492 (mp_irqs[i].mpc_irqtype == type) &&
493 (mp_irqs[i].mpc_srcbusirq == irq))
494 break;
495 }
496 if (i < mp_irq_entries) {
497 int apic;
498 for(apic = 0; apic < nr_ioapics; apic++) {
499 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
500 return apic;
501 }
502 }
503
504 return -1;
505}
506
1da177e4
LT		 507/*
508 * Find a specific PCI IRQ entry.
509 * Not an __init, possibly needed by modules
510 */
511static int pin_2_irq(int idx, int apic, int pin);
512
513int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
514{
515 int apic, i, best_guess = -1;
516
517 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
518 bus, slot, pin);
519 if (mp_bus_id_to_pci_bus[bus] == -1) {
520 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
521 return -1;
522 }
523 for (i = 0; i < mp_irq_entries; i++) {
524 int lbus = mp_irqs[i].mpc_srcbus;
525
526 for (apic = 0; apic < nr_ioapics; apic++)
527 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
528 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
529 break;
530
55f05ffa 531 if (!test_bit(lbus, mp_bus_not_pci) &&
1da177e4
LT		 532 !mp_irqs[i].mpc_irqtype &&
533 (bus == lbus) &&
534 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
535 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
536
537 if (!(apic || IO_APIC_IRQ(irq)))
538 continue;
539
540 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
541 return irq;
542 /*
543 * Use the first all-but-pin matching entry as a
544 * best-guess fuzzy result for broken mptables.
545 */
546 if (best_guess < 0)
547 best_guess = irq;
548 }
549 }
6004e1b7 550 BUG_ON(best_guess >= NR_IRQS);
1da177e4
LT		 551 return best_guess;
552}
553
1da177e4
LT		 554/* ISA interrupts are always polarity zero edge triggered,
555 * when listed as conforming in the MP table. */
556
557#define default_ISA_trigger(idx) (0)
558#define default_ISA_polarity(idx) (0)
559
560/* PCI interrupts are always polarity one level triggered,
561 * when listed as conforming in the MP table. */
562
563#define default_PCI_trigger(idx) (1)
564#define default_PCI_polarity(idx) (1)
565
61fd47e0 566static int MPBIOS_polarity(int idx)
1da177e4
LT		 567{
568 int bus = mp_irqs[idx].mpc_srcbus;
569 int polarity;
570
571 /*
572 * Determine IRQ line polarity (high active or low active):
573 */
574 switch (mp_irqs[idx].mpc_irqflag & 3)
575 {
576 case 0: /* conforms, ie. bus-type dependent polarity */
55f05ffa
AK		 577 if (test_bit(bus, mp_bus_not_pci))
578 polarity = default_ISA_polarity(idx);
579 else
580 polarity = default_PCI_polarity(idx);
1da177e4 581 break;
1da177e4
LT		 582 case 1: /* high active */
583 {
584 polarity = 0;
585 break;
586 }
587 case 2: /* reserved */
588 {
589 printk(KERN_WARNING "broken BIOS!!\n");
590 polarity = 1;
591 break;
592 }
593 case 3: /* low active */
594 {
595 polarity = 1;
596 break;
597 }
598 default: /* invalid */
599 {
600 printk(KERN_WARNING "broken BIOS!!\n");
601 polarity = 1;
602 break;
603 }
604 }
605 return polarity;
606}
607
608static int MPBIOS_trigger(int idx)
609{
610 int bus = mp_irqs[idx].mpc_srcbus;
611 int trigger;
612
613 /*
614 * Determine IRQ trigger mode (edge or level sensitive):
615 */
616 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
617 {
618 case 0: /* conforms, ie. bus-type dependent */
55f05ffa
AK		 619 if (test_bit(bus, mp_bus_not_pci))
620 trigger = default_ISA_trigger(idx);
621 else
622 trigger = default_PCI_trigger(idx);
1da177e4 623 break;
1da177e4
LT		 624 case 1: /* edge */
625 {
626 trigger = 0;
627 break;
628 }
629 case 2: /* reserved */
630 {
631 printk(KERN_WARNING "broken BIOS!!\n");
632 trigger = 1;
633 break;
634 }
635 case 3: /* level */
636 {
637 trigger = 1;
638 break;
639 }
640 default: /* invalid */
641 {
642 printk(KERN_WARNING "broken BIOS!!\n");
643 trigger = 0;
644 break;
645 }
646 }
647 return trigger;
648}
649
650static inline int irq_polarity(int idx)
651{
652 return MPBIOS_polarity(idx);
653}
654
655static inline int irq_trigger(int idx)
656{
657 return MPBIOS_trigger(idx);
658}
659
660static int pin_2_irq(int idx, int apic, int pin)
661{
662 int irq, i;
663 int bus = mp_irqs[idx].mpc_srcbus;
664
665 /*
666 * Debugging check, we are in big trouble if this message pops up!
667 */
668 if (mp_irqs[idx].mpc_dstirq != pin)
669 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
670
55f05ffa
AK		 671 if (test_bit(bus, mp_bus_not_pci)) {
672 irq = mp_irqs[idx].mpc_srcbusirq;
673 } else {
674 /*
675 * PCI IRQs are mapped in order
676 */
677 i = irq = 0;
678 while (i < apic)
679 irq += nr_ioapic_registers[i++];
680 irq += pin;
1da177e4 681 }
6004e1b7 682 BUG_ON(irq >= NR_IRQS);
1da177e4
LT		 683 return irq;
684}
685
dfbffdd8 686static int __assign_irq_vector(int irq, cpumask_t mask)
1da177e4 687{
550f2299
EB		 688 /*
689 * NOTE! The local APIC isn't very good at handling
690 * multiple interrupts at the same interrupt level.
691 * As the interrupt level is determined by taking the
692 * vector number and shifting that right by 4, we
693 * want to spread these out a bit so that they don't
694 * all fall in the same interrupt level.
695 *
696 * Also, we've got to be careful not to trash gate
697 * 0x80, because int 0x80 is hm, kind of importantish. ;)
698 */
d1752aa8 699 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
dfbffdd8 700 unsigned int old_vector;
550f2299 701 int cpu;
13a79503 702 struct irq_cfg *cfg;
1da177e4 703
e273d140 704 BUG_ON((unsigned)irq >= NR_IRQS);
13a79503 705 cfg = &irq_cfg[irq];
0a1ad60d 706
70a0a535
EB		 707 /* Only try and allocate irqs on cpus that are present */
708 cpus_and(mask, mask, cpu_online_map);
709
61014292
EB		 710 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
711 return -EBUSY;
712
dfbffdd8
EB		 713 old_vector = cfg->vector;
714 if (old_vector) {
715 cpumask_t tmp;
716 cpus_and(tmp, cfg->domain, mask);
717 if (!cpus_empty(tmp))
718 return 0;
0a1ad60d 719 }
550f2299
EB		 720
721 for_each_cpu_mask(cpu, mask) {
70a0a535 722 cpumask_t domain, new_mask;
61014292 723 int new_cpu;
550f2299 724 int vector, offset;
c7111c13
EB		 725
726 domain = vector_allocation_domain(cpu);
70a0a535 727 cpus_and(new_mask, domain, cpu_online_map);
c7111c13 728
d1752aa8
EB		 729 vector = current_vector;
730 offset = current_offset;
1da177e4 731next:
550f2299
EB		 732 vector += 8;
733 if (vector >= FIRST_SYSTEM_VECTOR) {
734 /* If we run out of vectors on large boxen, must share them. */
735 offset = (offset + 1) % 8;
736 vector = FIRST_DEVICE_VECTOR + offset;
737 }
d1752aa8 738 if (unlikely(current_vector == vector))
550f2299
EB		 739 continue;
740 if (vector == IA32_SYSCALL_VECTOR)
741 goto next;
70a0a535 742 for_each_cpu_mask(new_cpu, new_mask)
45edfd1d 743 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
c7111c13 744 goto next;
550f2299 745 /* Found one! */
d1752aa8
EB		 746 current_vector = vector;
747 current_offset = offset;
61014292
EB		 748 if (old_vector) {
749 cfg->move_in_progress = 1;
750 cfg->old_domain = cfg->domain;
751 }
70a0a535 752 for_each_cpu_mask(new_cpu, new_mask)
c7111c13 753 per_cpu(vector_irq, new_cpu)[vector] = irq;
13a79503
EB		 754 cfg->vector = vector;
755 cfg->domain = domain;
dfbffdd8 756 return 0;
1da177e4 757 }
550f2299 758 return -ENOSPC;
04b9267b
EB		 759}
760
dfbffdd8 761static int assign_irq_vector(int irq, cpumask_t mask)
04b9267b 762{
dfbffdd8 763 int err;
04b9267b 764 unsigned long flags;
0a1ad60d 765
04b9267b 766 spin_lock_irqsave(&vector_lock, flags);
dfbffdd8 767 err = __assign_irq_vector(irq, mask);
26a3c49c 768 spin_unlock_irqrestore(&vector_lock, flags);
dfbffdd8 769 return err;
1da177e4
LT		 770}
771
5df0287e
YL		 772static void __clear_irq_vector(int irq)
773{
13a79503 774 struct irq_cfg *cfg;
5df0287e
YL		 775 cpumask_t mask;
776 int cpu, vector;
777
13a79503
EB		 778 BUG_ON((unsigned)irq >= NR_IRQS);
779 cfg = &irq_cfg[irq];
780 BUG_ON(!cfg->vector);
5df0287e 781
13a79503
EB		 782 vector = cfg->vector;
783 cpus_and(mask, cfg->domain, cpu_online_map);
5df0287e
YL		 784 for_each_cpu_mask(cpu, mask)
785 per_cpu(vector_irq, cpu)[vector] = -1;
786
13a79503 787 cfg->vector = 0;
d366f8cb 788 cpus_clear(cfg->domain);
5df0287e
YL		 789}
790
70a0a535
EB		 791void __setup_vector_irq(int cpu)
792{
793 /* Initialize vector_irq on a new cpu */
794 /* This function must be called with vector_lock held */
70a0a535
EB		 795 int irq, vector;
796
70a0a535 797 /* Mark the inuse vectors */
e273d140 798 for (irq = 0; irq < NR_IRQS; ++irq) {
13a79503 799 if (!cpu_isset(cpu, irq_cfg[irq].domain))
70a0a535 800 continue;
13a79503 801 vector = irq_cfg[irq].vector;
70a0a535
EB		 802 per_cpu(vector_irq, cpu)[vector] = irq;
803 }
804 /* Mark the free vectors */
805 for (vector = 0; vector < NR_VECTORS; ++vector) {
806 irq = per_cpu(vector_irq, cpu)[vector];
807 if (irq < 0)
808 continue;
13a79503 809 if (!cpu_isset(cpu, irq_cfg[irq].domain))
70a0a535
EB		 810 per_cpu(vector_irq, cpu)[vector] = -1;
811 }
812}
813
814
f29bd1ba 815static struct irq_chip ioapic_chip;
1da177e4 816
a27bc06d 817static void ioapic_register_intr(int irq, unsigned long trigger)
1da177e4 818{
cc75b92d
TG		 819 if (trigger) {
820 irq_desc[irq].status |= IRQ_LEVEL;
a460e745
IM		 821 set_irq_chip_and_handler_name(irq, &ioapic_chip,
822 handle_fasteoi_irq, "fasteoi");
cc75b92d
TG		 823 } else {
824 irq_desc[irq].status &= ~IRQ_LEVEL;
a460e745
IM		 825 set_irq_chip_and_handler_name(irq, &ioapic_chip,
826 handle_edge_irq, "edge");
cc75b92d 827 }
1da177e4 828}
a8c8a367
EB		 829
830static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
831 int trigger, int polarity)
1da177e4 832{
dfbffdd8 833 struct irq_cfg *cfg = irq_cfg + irq;
1da177e4 834 struct IO_APIC_route_entry entry;
a8c8a367 835 cpumask_t mask;
1da177e4 836
a8c8a367
EB		 837 if (!IO_APIC_IRQ(irq))
838 return;
839
dfbffdd8
EB		 840 mask = TARGET_CPUS;
841 if (assign_irq_vector(irq, mask))
a8c8a367
EB		 842 return;
843
dfbffdd8
EB		 844 cpus_and(mask, cfg->domain, mask);
845
a8c8a367
EB		 846 apic_printk(APIC_VERBOSE,KERN_DEBUG
847 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
848 "IRQ %d Mode:%i Active:%i)\n",
dfbffdd8 849 apic, mp_ioapics[apic].mpc_apicid, pin, cfg->vector,
a8c8a367 850 irq, trigger, polarity);
1da177e4 851
ad892f5e
YL		 852 /*
853 * add it to the IO-APIC irq-routing table:
854 */
855 memset(&entry,0,sizeof(entry));
1da177e4 856
ad892f5e
YL		 857 entry.delivery_mode = INT_DELIVERY_MODE;
858 entry.dest_mode = INT_DEST_MODE;
a8c8a367 859 entry.dest = cpu_mask_to_apicid(mask);
ad892f5e 860 entry.mask = 0; /* enable IRQ */
a8c8a367
EB		 861 entry.trigger = trigger;
862 entry.polarity = polarity;
dfbffdd8 863 entry.vector = cfg->vector;
1da177e4 864
a8c8a367
EB		 865 /* Mask level triggered irqs.
866 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
867 */
868 if (trigger)
ad892f5e 869 entry.mask = 1;
ad892f5e 870
a8c8a367
EB		 871 ioapic_register_intr(irq, trigger);
872 if (irq < 16)
873 disable_8259A_irq(irq);
ad892f5e
YL		 874
875 ioapic_write_entry(apic, pin, entry);
ad892f5e
YL		 876}
877
878static void __init setup_IO_APIC_irqs(void)
879{
880 int apic, pin, idx, irq, first_notcon = 1;
881
882 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
883
884 for (apic = 0; apic < nr_ioapics; apic++) {
885 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1da177e4
LT		 886
887 idx = find_irq_entry(apic,pin,mp_INT);
888 if (idx == -1) {
889 if (first_notcon) {
890 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
891 first_notcon = 0;
892 } else
893 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
894 continue;
895 }
20d225b9
YL		 896 if (!first_notcon) {
897 apic_printk(APIC_VERBOSE, " not connected.\n");
898 first_notcon = 1;
899 }
1da177e4 900
1da177e4
LT		 901 irq = pin_2_irq(idx, apic, pin);
902 add_pin_to_irq(irq, apic, pin);
903
a8c8a367
EB		 904 setup_IO_APIC_irq(apic, pin, irq,
905 irq_trigger(idx), irq_polarity(idx));
1da177e4
LT		 906 }
907 }
908
909 if (!first_notcon)
20d225b9 910 apic_printk(APIC_VERBOSE, " not connected.\n");
1da177e4
LT		 911}
912
913/*
914 * Set up the 8259A-master output pin as broadcast to all
915 * CPUs.
916 */
1008fddc 917static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1da177e4
LT		 918{
919 struct IO_APIC_route_entry entry;
1da177e4 920
a2249cba 921 memset(&entry, 0, sizeof(entry));
1da177e4
LT		 922
923 disable_8259A_irq(0);
924
925 /* mask LVT0 */
11a8e778 926 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1da177e4
LT		 927
928 /*
929 * We use logical delivery to get the timer IRQ
930 * to the first CPU.
931 */
932 entry.dest_mode = INT_DEST_MODE;
933 entry.mask = 0; /* unmask IRQ now */
ee4eff6f 934 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
1da177e4
LT		 935 entry.delivery_mode = INT_DELIVERY_MODE;
936 entry.polarity = 0;
937 entry.trigger = 0;
938 entry.vector = vector;
939
940 /*
941 * The timer IRQ doesn't have to know that behind the
942 * scene we have a 8259A-master in AEOI mode ...
943 */
a460e745 944 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1da177e4
LT		 945
946 /*
947 * Add it to the IO-APIC irq-routing table:
948 */
a2249cba 949 ioapic_write_entry(apic, pin, entry);
1da177e4
LT		 950
951 enable_8259A_irq(0);
952}
953
1da177e4
LT		 954void __apicdebuginit print_IO_APIC(void)
955{
956 int apic, i;
957 union IO_APIC_reg_00 reg_00;
958 union IO_APIC_reg_01 reg_01;
959 union IO_APIC_reg_02 reg_02;
960 unsigned long flags;
961
962 if (apic_verbosity == APIC_QUIET)
963 return;
964
965 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
966 for (i = 0; i < nr_ioapics; i++)
967 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
968 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
969
970 /*
971 * We are a bit conservative about what we expect. We have to
972 * know about every hardware change ASAP.
973 */
974 printk(KERN_INFO "testing the IO APIC.......................\n");
975
976 for (apic = 0; apic < nr_ioapics; apic++) {
977
978 spin_lock_irqsave(&ioapic_lock, flags);
979 reg_00.raw = io_apic_read(apic, 0);
980 reg_01.raw = io_apic_read(apic, 1);
981 if (reg_01.bits.version >= 0x10)
982 reg_02.raw = io_apic_read(apic, 2);
983 spin_unlock_irqrestore(&ioapic_lock, flags);
984
985 printk("\n");
986 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
987 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
988 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1da177e4
LT		 989
990 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
991 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1da177e4
LT		 992
993 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
994 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1da177e4
LT		 995
996 if (reg_01.bits.version >= 0x10) {
997 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
998 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1da177e4
LT		 999 }
1000
1001 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1002
ee4eff6f
BR		 1003 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1004 " Stat Dmod Deli Vect: \n");
1da177e4
LT		 1005
1006 for (i = 0; i <= reg_01.bits.entries; i++) {
1007 struct IO_APIC_route_entry entry;
1008
eea0e11c 1009 entry = ioapic_read_entry(apic, i);
1da177e4 1010
ee4eff6f 1011 printk(KERN_DEBUG " %02x %03X ",
1da177e4 1012 i,
ee4eff6f 1013 entry.dest
1da177e4
LT		 1014 );
1015
1016 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1017 entry.mask,
1018 entry.trigger,
1019 entry.irr,
1020 entry.polarity,
1021 entry.delivery_status,
1022 entry.dest_mode,
1023 entry.delivery_mode,
1024 entry.vector
1025 );
1026 }
1027 }
1da177e4
LT		 1028 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1029 for (i = 0; i < NR_IRQS; i++) {
1030 struct irq_pin_list *entry = irq_2_pin + i;
1031 if (entry->pin < 0)
1032 continue;
04b9267b 1033 printk(KERN_DEBUG "IRQ%d ", i);
1da177e4
LT		 1034 for (;;) {
1035 printk("-> %d:%d", entry->apic, entry->pin);
1036 if (!entry->next)
1037 break;
1038 entry = irq_2_pin + entry->next;
1039 }
1040 printk("\n");
1041 }
1042
1043 printk(KERN_INFO ".................................... done.\n");
1044
1045 return;
1046}
1047
1048#if 0
1049
1050static __apicdebuginit void print_APIC_bitfield (int base)
1051{
1052 unsigned int v;
1053 int i, j;
1054
1055 if (apic_verbosity == APIC_QUIET)
1056 return;
1057
1058 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1059 for (i = 0; i < 8; i++) {
1060 v = apic_read(base + i*0x10);
1061 for (j = 0; j < 32; j++) {
1062 if (v & (1<<j))
1063 printk("1");
1064 else
1065 printk("0");
1066 }
1067 printk("\n");
1068 }
1069}
1070
1071void __apicdebuginit print_local_APIC(void * dummy)
1072{
1073 unsigned int v, ver, maxlvt;
1074
1075 if (apic_verbosity == APIC_QUIET)
1076 return;
1077
1078 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1079 smp_processor_id(), hard_smp_processor_id());
05f2d12c 1080 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(read_apic_id()));
1da177e4
LT		 1081 v = apic_read(APIC_LVR);
1082 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1083 ver = GET_APIC_VERSION(v);
37e650c7 1084 maxlvt = lapic_get_maxlvt();
1da177e4
LT		 1085
1086 v = apic_read(APIC_TASKPRI);
1087 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1088
5a40b7c2
AK		 1089 v = apic_read(APIC_ARBPRI);
1090 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1091 v & APIC_ARBPRI_MASK);
1092 v = apic_read(APIC_PROCPRI);
1093 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1da177e4
LT		 1094
1095 v = apic_read(APIC_EOI);
1096 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1097 v = apic_read(APIC_RRR);
1098 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1099 v = apic_read(APIC_LDR);
1100 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1101 v = apic_read(APIC_DFR);
1102 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1103 v = apic_read(APIC_SPIV);
1104 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1105
1106 printk(KERN_DEBUG "... APIC ISR field:\n");
1107 print_APIC_bitfield(APIC_ISR);
1108 printk(KERN_DEBUG "... APIC TMR field:\n");
1109 print_APIC_bitfield(APIC_TMR);
1110 printk(KERN_DEBUG "... APIC IRR field:\n");
1111 print_APIC_bitfield(APIC_IRR);
1112
5a40b7c2
AK		 1113 v = apic_read(APIC_ESR);
1114 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1da177e4
LT		 1115
1116 v = apic_read(APIC_ICR);
1117 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1118 v = apic_read(APIC_ICR2);
1119 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1120
1121 v = apic_read(APIC_LVTT);
1122 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1123
1124 if (maxlvt > 3) { /* PC is LVT#4. */
1125 v = apic_read(APIC_LVTPC);
1126 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1127 }
1128 v = apic_read(APIC_LVT0);
1129 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1130 v = apic_read(APIC_LVT1);
1131 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1132
1133 if (maxlvt > 2) { /* ERR is LVT#3. */
1134 v = apic_read(APIC_LVTERR);
1135 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1136 }
1137
1138 v = apic_read(APIC_TMICT);
1139 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1140 v = apic_read(APIC_TMCCT);
1141 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1142 v = apic_read(APIC_TDCR);
1143 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1144 printk("\n");
1145}
1146
1147void print_all_local_APICs (void)
1148{
1149 on_each_cpu(print_local_APIC, NULL, 1, 1);
1150}
1151
1152void __apicdebuginit print_PIC(void)
1153{
1da177e4
LT		 1154 unsigned int v;
1155 unsigned long flags;
1156
1157 if (apic_verbosity == APIC_QUIET)
1158 return;
1159
1160 printk(KERN_DEBUG "\nprinting PIC contents\n");
1161
1162 spin_lock_irqsave(&i8259A_lock, flags);
1163
1164 v = inb(0xa1) << 8 | inb(0x21);
1165 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1166
1167 v = inb(0xa0) << 8 | inb(0x20);
1168 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1169
1170 outb(0x0b,0xa0);
1171 outb(0x0b,0x20);
1172 v = inb(0xa0) << 8 | inb(0x20);
1173 outb(0x0a,0xa0);
1174 outb(0x0a,0x20);
1175
1176 spin_unlock_irqrestore(&i8259A_lock, flags);
1177
1178 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1179
1180 v = inb(0x4d1) << 8 | inb(0x4d0);
1181 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1182}
1183
1184#endif /* 0 */
1185
1c69524c 1186void __init enable_IO_APIC(void)
1da177e4
LT		 1187{
1188 union IO_APIC_reg_01 reg_01;
1008fddc
EB		 1189 int i8259_apic, i8259_pin;
1190 int i, apic;
1da177e4
LT		 1191 unsigned long flags;
1192
1193 for (i = 0; i < PIN_MAP_SIZE; i++) {
1194 irq_2_pin[i].pin = -1;
1195 irq_2_pin[i].next = 0;
1196 }
1da177e4
LT		 1197
1198 /*
1199 * The number of IO-APIC IRQ registers (== #pins):
1200 */
1008fddc 1201 for (apic = 0; apic < nr_ioapics; apic++) {
1da177e4 1202 spin_lock_irqsave(&ioapic_lock, flags);
1008fddc 1203 reg_01.raw = io_apic_read(apic, 1);
1da177e4 1204 spin_unlock_irqrestore(&ioapic_lock, flags);
1008fddc
EB		 1205 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1206 }
1207 for(apic = 0; apic < nr_ioapics; apic++) {
1208 int pin;
1209 /* See if any of the pins is in ExtINT mode */
1210 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1211 struct IO_APIC_route_entry entry;
eea0e11c 1212 entry = ioapic_read_entry(apic, pin);
1008fddc
EB		 1213
1214 /* If the interrupt line is enabled and in ExtInt mode
1215 * I have found the pin where the i8259 is connected.
1216 */
1217 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1218 ioapic_i8259.apic = apic;
1219 ioapic_i8259.pin = pin;
1220 goto found_i8259;
1221 }
1222 }
1223 }
1224 found_i8259:
1225 /* Look to see what if the MP table has reported the ExtINT */
1226 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1227 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1228 /* Trust the MP table if nothing is setup in the hardware */
1229 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1230 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1231 ioapic_i8259.pin = i8259_pin;
1232 ioapic_i8259.apic = i8259_apic;
1233 }
1234 /* Complain if the MP table and the hardware disagree */
1235 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1236 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1237 {
1238 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1da177e4
LT		 1239 }
1240
1241 /*
1242 * Do not trust the IO-APIC being empty at bootup
1243 */
1244 clear_IO_APIC();
1245}
1246
1247/*
1248 * Not an __init, needed by the reboot code
1249 */
1250void disable_IO_APIC(void)
1251{
1252 /*
1253 * Clear the IO-APIC before rebooting:
1254 */
1255 clear_IO_APIC();
1256
208fb931 1257 /*
0b968d23 1258 * If the i8259 is routed through an IOAPIC
208fb931 1259 * Put that IOAPIC in virtual wire mode
0b968d23 1260 * so legacy interrupts can be delivered.
208fb931 1261 */
1008fddc 1262 if (ioapic_i8259.pin != -1) {
208fb931 1263 struct IO_APIC_route_entry entry;
208fb931
EB		 1264
1265 memset(&entry, 0, sizeof(entry));
1266 entry.mask = 0; /* Enabled */
1267 entry.trigger = 0; /* Edge */
1268 entry.irr = 0;
1269 entry.polarity = 0; /* High */
1270 entry.delivery_status = 0;
1271 entry.dest_mode = 0; /* Physical */
1008fddc 1272 entry.delivery_mode = dest_ExtINT; /* ExtInt */
208fb931 1273 entry.vector = 0;
05f2d12c 1274 entry.dest = GET_APIC_ID(read_apic_id());
208fb931 1275
208fb931
EB		 1276 /*
1277 * Add it to the IO-APIC irq-routing table:
1278 */
eea0e11c 1279 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
208fb931
EB		 1280 }
1281
1008fddc 1282 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1da177e4
LT		 1283}
1284
1da177e4
LT		 1285/*
1286 * There is a nasty bug in some older SMP boards, their mptable lies
1287 * about the timer IRQ. We do the following to work around the situation:
1288 *
1289 * - timer IRQ defaults to IO-APIC IRQ
1290 * - if this function detects that timer IRQs are defunct, then we fall
1291 * back to ISA timer IRQs
1292 */
1293static int __init timer_irq_works(void)
1294{
1295 unsigned long t1 = jiffies;
4aae0702 1296 unsigned long flags;
1da177e4 1297
4aae0702 1298 local_save_flags(flags);
1da177e4
LT		 1299 local_irq_enable();
1300 /* Let ten ticks pass... */
1301 mdelay((10 * 1000) / HZ);
4aae0702 1302 local_irq_restore(flags);
1da177e4
LT		 1303
1304 /*
1305 * Expect a few ticks at least, to be sure some possible
1306 * glue logic does not lock up after one or two first
1307 * ticks in a non-ExtINT mode. Also the local APIC
1308 * might have cached one ExtINT interrupt. Finally, at
1309 * least one tick may be lost due to delays.
1310 */
1311
1312 /* jiffies wrap? */
1d16b53e 1313 if (time_after(jiffies, t1 + 4))
1da177e4
LT		 1314 return 1;
1315 return 0;
1316}
1317
1318/*
1319 * In the SMP+IOAPIC case it might happen that there are an unspecified
1320 * number of pending IRQ events unhandled. These cases are very rare,
1321 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1322 * better to do it this way as thus we do not have to be aware of
1323 * 'pending' interrupts in the IRQ path, except at this point.
1324 */
1325/*
1326 * Edge triggered needs to resend any interrupt
1327 * that was delayed but this is now handled in the device
1328 * independent code.
1329 */
1330
1331/*
1332 * Starting up a edge-triggered IO-APIC interrupt is
1333 * nasty - we need to make sure that we get the edge.
1334 * If it is already asserted for some reason, we need
1335 * return 1 to indicate that is was pending.
1336 *
1337 * This is not complete - we should be able to fake
1338 * an edge even if it isn't on the 8259A...
1339 */
1340
f29bd1ba 1341static unsigned int startup_ioapic_irq(unsigned int irq)
1da177e4
LT		 1342{
1343 int was_pending = 0;
1344 unsigned long flags;
1345
1346 spin_lock_irqsave(&ioapic_lock, flags);
1347 if (irq < 16) {
1348 disable_8259A_irq(irq);
1349 if (i8259A_irq_pending(irq))
1350 was_pending = 1;
1351 }
1352 __unmask_IO_APIC_irq(irq);
1353 spin_unlock_irqrestore(&ioapic_lock, flags);
1354
1355 return was_pending;
1356}
1357
04b9267b 1358static int ioapic_retrigger_irq(unsigned int irq)
c0ad90a3 1359{
13a79503 1360 struct irq_cfg *cfg = &irq_cfg[irq];
550f2299 1361 cpumask_t mask;
6bf2dafa 1362 unsigned long flags;
550f2299 1363
6bf2dafa 1364 spin_lock_irqsave(&vector_lock, flags);
7281c96f 1365 mask = cpumask_of_cpu(first_cpu(cfg->domain));
13a79503 1366 send_IPI_mask(mask, cfg->vector);
6bf2dafa 1367 spin_unlock_irqrestore(&vector_lock, flags);
c0ad90a3
IM		 1368
1369 return 1;
1370}
1371
1da177e4
LT		 1372/*
1373 * Level and edge triggered IO-APIC interrupts need different handling,
1374 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1375 * handled with the level-triggered descriptor, but that one has slightly
1376 * more overhead. Level-triggered interrupts cannot be handled with the
1377 * edge-triggered handler, without risking IRQ storms and other ugly
1378 * races.
1379 */
1380
61014292
EB		 1381#ifdef CONFIG_SMP
1382asmlinkage void smp_irq_move_cleanup_interrupt(void)
1383{
1384 unsigned vector, me;
1385 ack_APIC_irq();
1386 exit_idle();
1387 irq_enter();
1388
1389 me = smp_processor_id();
1390 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
1391 unsigned int irq;
1392 struct irq_desc *desc;
1393 struct irq_cfg *cfg;
1394 irq = __get_cpu_var(vector_irq)[vector];
1395 if (irq >= NR_IRQS)
1396 continue;
1397
1398 desc = irq_desc + irq;
1399 cfg = irq_cfg + irq;
1400 spin_lock(&desc->lock);
1401 if (!cfg->move_cleanup_count)
1402 goto unlock;
1403
1404 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
1405 goto unlock;
1406
1407 __get_cpu_var(vector_irq)[vector] = -1;
1408 cfg->move_cleanup_count--;
1409unlock:
1410 spin_unlock(&desc->lock);
1411 }
1412
1413 irq_exit();
1414}
1415
1416static void irq_complete_move(unsigned int irq)
1417{
1418 struct irq_cfg *cfg = irq_cfg + irq;
1419 unsigned vector, me;
1420
1421 if (likely(!cfg->move_in_progress))
1422 return;
1423
65ea5b03 1424 vector = ~get_irq_regs()->orig_ax;
61014292 1425 me = smp_processor_id();
f0e13ae7 1426 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
61014292
EB		 1427 cpumask_t cleanup_mask;
1428
1429 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
1430 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
1431 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
1432 cfg->move_in_progress = 0;
1433 }
1434}
1435#else
1436static inline void irq_complete_move(unsigned int irq) {}
1437#endif
1438
0be6652f
EB		 1439static void ack_apic_edge(unsigned int irq)
1440{
61014292 1441 irq_complete_move(irq);
0be6652f
EB		 1442 move_native_irq(irq);
1443 ack_APIC_irq();
1444}
1445
1446static void ack_apic_level(unsigned int irq)
1447{
1448 int do_unmask_irq = 0;
1449
61014292 1450 irq_complete_move(irq);
52e3d90d 1451#ifdef CONFIG_GENERIC_PENDING_IRQ
0be6652f
EB		 1452 /* If we are moving the irq we need to mask it */
1453 if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1454 do_unmask_irq = 1;
1455 mask_IO_APIC_irq(irq);
1456 }
1457#endif
1458
1459 /*
1460 * We must acknowledge the irq before we move it or the acknowledge will
beb7dd86 1461 * not propagate properly.
0be6652f
EB		 1462 */
1463 ack_APIC_irq();
1464
1465 /* Now we can move and renable the irq */
ef3e28c5
EB		 1466 if (unlikely(do_unmask_irq)) {
1467 /* Only migrate the irq if the ack has been received.
1468 *
1469 * On rare occasions the broadcast level triggered ack gets
1470 * delayed going to ioapics, and if we reprogram the
1471 * vector while Remote IRR is still set the irq will never
1472 * fire again.
1473 *
1474 * To prevent this scenario we read the Remote IRR bit
1475 * of the ioapic. This has two effects.
1476 * - On any sane system the read of the ioapic will
1477 * flush writes (and acks) going to the ioapic from
1478 * this cpu.
1479 * - We get to see if the ACK has actually been delivered.
1480 *
1481 * Based on failed experiments of reprogramming the
1482 * ioapic entry from outside of irq context starting
1483 * with masking the ioapic entry and then polling until
1484 * Remote IRR was clear before reprogramming the
1485 * ioapic I don't trust the Remote IRR bit to be
1486 * completey accurate.
1487 *
1488 * However there appears to be no other way to plug
1489 * this race, so if the Remote IRR bit is not
1490 * accurate and is causing problems then it is a hardware bug
1491 * and you can go talk to the chipset vendor about it.
1492 */
1493 if (!io_apic_level_ack_pending(irq))
1494 move_masked_irq(irq);
0be6652f 1495 unmask_IO_APIC_irq(irq);
ef3e28c5 1496 }
0be6652f
EB		 1497}
1498
f29bd1ba
IM		 1499static struct irq_chip ioapic_chip __read_mostly = {
1500 .name = "IO-APIC",
04b9267b
EB		 1501 .startup = startup_ioapic_irq,
1502 .mask = mask_IO_APIC_irq,
1503 .unmask = unmask_IO_APIC_irq,
0be6652f
EB		 1504 .ack = ack_apic_edge,
1505 .eoi = ack_apic_level,
54d5d424 1506#ifdef CONFIG_SMP
04b9267b 1507 .set_affinity = set_ioapic_affinity_irq,
54d5d424 1508#endif
04b9267b 1509 .retrigger = ioapic_retrigger_irq,
1da177e4
LT		 1510};
1511
1512static inline void init_IO_APIC_traps(void)
1513{
1514 int irq;
1515
1516 /*
1517 * NOTE! The local APIC isn't very good at handling
1518 * multiple interrupts at the same interrupt level.
1519 * As the interrupt level is determined by taking the
1520 * vector number and shifting that right by 4, we
1521 * want to spread these out a bit so that they don't
1522 * all fall in the same interrupt level.
1523 *
1524 * Also, we've got to be careful not to trash gate
1525 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1526 */
1527 for (irq = 0; irq < NR_IRQS ; irq++) {
addfc66b 1528 if (IO_APIC_IRQ(irq) && !irq_cfg[irq].vector) {
1da177e4
LT		 1529 /*
1530 * Hmm.. We don't have an entry for this,
1531 * so default to an old-fashioned 8259
1532 * interrupt if we can..
1533 */
1534 if (irq < 16)
1535 make_8259A_irq(irq);
1536 else
1537 /* Strange. Oh, well.. */
f29bd1ba 1538 irq_desc[irq].chip = &no_irq_chip;
1da177e4
LT		 1539 }
1540 }
1541}
1542
1543static void enable_lapic_irq (unsigned int irq)
1544{
1545 unsigned long v;
1546
1547 v = apic_read(APIC_LVT0);
11a8e778 1548 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1da177e4
LT		 1549}
1550
1551static void disable_lapic_irq (unsigned int irq)
1552{
1553 unsigned long v;
1554
1555 v = apic_read(APIC_LVT0);
11a8e778 1556 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1da177e4
LT		 1557}
1558
1559static void ack_lapic_irq (unsigned int irq)
1560{
1561 ack_APIC_irq();
1562}
1563
1564static void end_lapic_irq (unsigned int i) { /* nothing */ }
1565
6c231b7b 1566static struct hw_interrupt_type lapic_irq_type __read_mostly = {
c47e285d 1567 .name = "local-APIC",
1da177e4
LT		 1568 .typename = "local-APIC-edge",
1569 .startup = NULL, /* startup_irq() not used for IRQ0 */
1570 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1571 .enable = enable_lapic_irq,
1572 .disable = disable_lapic_irq,
1573 .ack = ack_lapic_irq,
1574 .end = end_lapic_irq,
1575};
1576
e9427101 1577static void __init setup_nmi(void)
1da177e4
LT		 1578{
1579 /*
1580 * Dirty trick to enable the NMI watchdog ...
1581 * We put the 8259A master into AEOI mode and
1582 * unmask on all local APICs LVT0 as NMI.
1583 *
1584 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1585 * is from Maciej W. Rozycki - so we do not have to EOI from
1586 * the NMI handler or the timer interrupt.
1587 */
1588 printk(KERN_INFO "activating NMI Watchdog ...");
1589
e9427101 1590 enable_NMI_through_LVT0();
1da177e4
LT		 1591
1592 printk(" done.\n");
1593}
1594
1595/*
1596 * This looks a bit hackish but it's about the only one way of sending
1597 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1598 * not support the ExtINT mode, unfortunately. We need to send these
1599 * cycles as some i82489DX-based boards have glue logic that keeps the
1600 * 8259A interrupt line asserted until INTA. --macro
1601 */
5afca33a 1602static inline void __init unlock_ExtINT_logic(void)
1da177e4 1603{
1008fddc 1604 int apic, pin, i;
1da177e4
LT		 1605 struct IO_APIC_route_entry entry0, entry1;
1606 unsigned char save_control, save_freq_select;
1da177e4 1607
1008fddc
EB		 1608 pin = find_isa_irq_pin(8, mp_INT);
1609 apic = find_isa_irq_apic(8, mp_INT);
1da177e4
LT		 1610 if (pin == -1)
1611 return;
1612
a2249cba
AM		 1613 entry0 = ioapic_read_entry(apic, pin);
1614
1008fddc 1615 clear_IO_APIC_pin(apic, pin);
1da177e4
LT		 1616
1617 memset(&entry1, 0, sizeof(entry1));
1618
1619 entry1.dest_mode = 0; /* physical delivery */
1620 entry1.mask = 0; /* unmask IRQ now */
ee4eff6f 1621 entry1.dest = hard_smp_processor_id();
1da177e4
LT		 1622 entry1.delivery_mode = dest_ExtINT;
1623 entry1.polarity = entry0.polarity;
1624 entry1.trigger = 0;
1625 entry1.vector = 0;
1626
a2249cba 1627 ioapic_write_entry(apic, pin, entry1);
1da177e4
LT		 1628
1629 save_control = CMOS_READ(RTC_CONTROL);
1630 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1631 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1632 RTC_FREQ_SELECT);
1633 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1634
1635 i = 100;
1636 while (i-- > 0) {
1637 mdelay(10);
1638 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1639 i -= 10;
1640 }
1641
1642 CMOS_WRITE(save_control, RTC_CONTROL);
1643 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1008fddc 1644 clear_IO_APIC_pin(apic, pin);
1da177e4 1645
a2249cba 1646 ioapic_write_entry(apic, pin, entry0);
1da177e4
LT		 1647}
1648
1649/*
1650 * This code may look a bit paranoid, but it's supposed to cooperate with
1651 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1652 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1653 * fanatically on his truly buggy board.
fea5f1e1
LT		 1654 *
1655 * FIXME: really need to revamp this for modern platforms only.
1da177e4 1656 */
e9427101 1657static inline void __init check_timer(void)
1da177e4 1658{
dfbffdd8 1659 struct irq_cfg *cfg = irq_cfg + 0;
1008fddc 1660 int apic1, pin1, apic2, pin2;
4aae0702
IM		 1661 unsigned long flags;
1662
1663 local_irq_save(flags);
1da177e4
LT		 1664
1665 /*
1666 * get/set the timer IRQ vector:
1667 */
1668 disable_8259A_irq(0);
dfbffdd8 1669 assign_irq_vector(0, TARGET_CPUS);
1da177e4
LT		 1670
1671 /*
1672 * Subtle, code in do_timer_interrupt() expects an AEOI
1673 * mode for the 8259A whenever interrupts are routed
1674 * through I/O APICs. Also IRQ0 has to be enabled in
1675 * the 8259A which implies the virtual wire has to be
1676 * disabled in the local APIC.
1677 */
11a8e778 1678 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1da177e4 1679 init_8259A(1);
fea5f1e1
LT		 1680 if (timer_over_8254 > 0)
1681 enable_8259A_irq(0);
1da177e4 1682
1008fddc
EB		 1683 pin1 = find_isa_irq_pin(0, mp_INT);
1684 apic1 = find_isa_irq_apic(0, mp_INT);
1685 pin2 = ioapic_i8259.pin;
1686 apic2 = ioapic_i8259.apic;
1da177e4 1687
fea5f1e1 1688 apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
dfbffdd8 1689 cfg->vector, apic1, pin1, apic2, pin2);
b0268726 1690
fea5f1e1
LT		 1691 if (pin1 != -1) {
1692 /*
1693 * Ok, does IRQ0 through the IOAPIC work?
1694 */
1695 unmask_IO_APIC_irq(0);
1696 if (!no_timer_check && timer_irq_works()) {
1697 nmi_watchdog_default();
1698 if (nmi_watchdog == NMI_IO_APIC) {
1699 disable_8259A_irq(0);
1700 setup_nmi();
1701 enable_8259A_irq(0);
1702 }
1703 if (disable_timer_pin_1 > 0)
1704 clear_IO_APIC_pin(0, pin1);
4aae0702 1705 goto out;
fea5f1e1
LT		 1706 }
1707 clear_IO_APIC_pin(apic1, pin1);
1708 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1709 "connected to IO-APIC\n");
1710 }
1da177e4 1711
fea5f1e1
LT		 1712 apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1713 "through the 8259A ... ");
1da177e4 1714 if (pin2 != -1) {
fea5f1e1
LT		 1715 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1716 apic2, pin2);
1717 /*
1718 * legacy devices should be connected to IO APIC #0
1719 */
dfbffdd8 1720 setup_ExtINT_IRQ0_pin(apic2, pin2, cfg->vector);
fea5f1e1
LT		 1721 if (timer_irq_works()) {
1722 apic_printk(APIC_VERBOSE," works.\n");
1723 nmi_watchdog_default();
1724 if (nmi_watchdog == NMI_IO_APIC) {
1725 setup_nmi();
1726 }
4aae0702 1727 goto out;
fea5f1e1
LT		 1728 }
1729 /*
1730 * Cleanup, just in case ...
1731 */
1732 clear_IO_APIC_pin(apic2, pin2);
1da177e4 1733 }
fea5f1e1 1734 apic_printk(APIC_VERBOSE," failed.\n");
1da177e4 1735
1f992153 1736 if (nmi_watchdog == NMI_IO_APIC) {
1da177e4
LT		 1737 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1738 nmi_watchdog = 0;
1739 }
1740
1741 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1742
1743 disable_8259A_irq(0);
d1bef4ed 1744 irq_desc[0].chip = &lapic_irq_type;
dfbffdd8 1745 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
1da177e4
LT		 1746 enable_8259A_irq(0);
1747
1748 if (timer_irq_works()) {
5b922cd4 1749 apic_printk(APIC_VERBOSE," works.\n");
4aae0702 1750 goto out;
1da177e4 1751 }
dfbffdd8 1752 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
1da177e4
LT		 1753 apic_printk(APIC_VERBOSE," failed.\n");
1754
1755 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1756
1757 init_8259A(0);
1758 make_8259A_irq(0);
11a8e778 1759 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1da177e4
LT		 1760
1761 unlock_ExtINT_logic();
1762
1763 if (timer_irq_works()) {
1764 apic_printk(APIC_VERBOSE," works.\n");
4aae0702 1765 goto out;
1da177e4
LT		 1766 }
1767 apic_printk(APIC_VERBOSE," failed :(.\n");
1768 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
4aae0702
IM		 1769out:
1770 local_irq_restore(flags);
1da177e4
LT		 1771}
1772
14d98cad
AK		 1773static int __init notimercheck(char *s)
1774{
1775 no_timer_check = 1;
1776 return 1;
1777}
1778__setup("no_timer_check", notimercheck);
1779
1da177e4
LT		 1780/*
1781 *
676b1855 1782 * IRQs that are handled by the PIC in the MPS IOAPIC case.
1da177e4
LT		 1783 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1784 * Linux doesn't really care, as it's not actually used
1785 * for any interrupt handling anyway.
1786 */
1787#define PIC_IRQS (1<<2)
1788
1789void __init setup_IO_APIC(void)
1790{
1c69524c
YL		 1791
1792 /*
1793 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
1794 */
1da177e4
LT		 1795
1796 if (acpi_ioapic)
1797 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1798 else
1799 io_apic_irqs = ~PIC_IRQS;
1800
1801 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1802
1da177e4
LT		 1803 sync_Arb_IDs();
1804 setup_IO_APIC_irqs();
1805 init_IO_APIC_traps();
1806 check_timer();
1807 if (!acpi_ioapic)
1808 print_IO_APIC();
1809}
1810
1811struct sysfs_ioapic_data {
1812 struct sys_device dev;
1813 struct IO_APIC_route_entry entry[0];
1814};
1815static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1816
0b9c33a7 1817static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1da177e4
LT		 1818{
1819 struct IO_APIC_route_entry *entry;
1820 struct sysfs_ioapic_data *data;
1da177e4
LT		 1821 int i;
1822
1823 data = container_of(dev, struct sysfs_ioapic_data, dev);
1824 entry = data->entry;
eea0e11c
AK		 1825 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1826 *entry = ioapic_read_entry(dev->id, i);
1da177e4
LT		 1827
1828 return 0;
1829}
1830
1831static int ioapic_resume(struct sys_device *dev)
1832{
1833 struct IO_APIC_route_entry *entry;
1834 struct sysfs_ioapic_data *data;
1835 unsigned long flags;
1836 union IO_APIC_reg_00 reg_00;
1837 int i;
1838
1839 data = container_of(dev, struct sysfs_ioapic_data, dev);
1840 entry = data->entry;
1841
1842 spin_lock_irqsave(&ioapic_lock, flags);
1843 reg_00.raw = io_apic_read(dev->id, 0);
1844 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1845 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1846 io_apic_write(dev->id, 0, reg_00.raw);
1847 }
1da177e4 1848 spin_unlock_irqrestore(&ioapic_lock, flags);
eea0e11c
AK		 1849 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1850 ioapic_write_entry(dev->id, i, entry[i]);
1da177e4
LT		 1851
1852 return 0;
1853}
1854
1855static struct sysdev_class ioapic_sysdev_class = {
af5ca3f4 1856 .name = "ioapic",
1da177e4
LT		 1857 .suspend = ioapic_suspend,
1858 .resume = ioapic_resume,
1859};
1860
1861static int __init ioapic_init_sysfs(void)
1862{
1863 struct sys_device * dev;
cddf7ff7 1864 int i, size, error;
1da177e4
LT		 1865
1866 error = sysdev_class_register(&ioapic_sysdev_class);
1867 if (error)
1868 return error;
1869
1870 for (i = 0; i < nr_ioapics; i++ ) {
1871 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1872 * sizeof(struct IO_APIC_route_entry);
cddf7ff7 1873 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
1da177e4
LT		 1874 if (!mp_ioapic_data[i]) {
1875 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1876 continue;
1877 }
1da177e4
LT		 1878 dev = &mp_ioapic_data[i]->dev;
1879 dev->id = i;
1880 dev->cls = &ioapic_sysdev_class;
1881 error = sysdev_register(dev);
1882 if (error) {
1883 kfree(mp_ioapic_data[i]);
1884 mp_ioapic_data[i] = NULL;
1885 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1886 continue;
1887 }
1888 }
1889
1890 return 0;
1891}
1892
1893device_initcall(ioapic_init_sysfs);
1894
c4fa0bbf 1895/*
04b9267b 1896 * Dynamic irq allocate and deallocation
c4fa0bbf
EB		 1897 */
1898int create_irq(void)
1899{
04b9267b
EB		 1900 /* Allocate an unused irq */
1901 int irq;
1902 int new;
c4fa0bbf 1903 unsigned long flags;
c4fa0bbf 1904
04b9267b
EB		 1905 irq = -ENOSPC;
1906 spin_lock_irqsave(&vector_lock, flags);
1907 for (new = (NR_IRQS - 1); new >= 0; new--) {
1908 if (platform_legacy_irq(new))
1909 continue;
13a79503 1910 if (irq_cfg[new].vector != 0)
04b9267b 1911 continue;
dfbffdd8 1912 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
04b9267b
EB		 1913 irq = new;
1914 break;
1915 }
1916 spin_unlock_irqrestore(&vector_lock, flags);
c4fa0bbf 1917
04b9267b 1918 if (irq >= 0) {
c4fa0bbf
EB		 1919 dynamic_irq_init(irq);
1920 }
1921 return irq;
1922}
1923
1924void destroy_irq(unsigned int irq)
1925{
1926 unsigned long flags;
c4fa0bbf
EB		 1927
1928 dynamic_irq_cleanup(irq);
1929
1930 spin_lock_irqsave(&vector_lock, flags);
5df0287e 1931 __clear_irq_vector(irq);
c4fa0bbf
EB		 1932 spin_unlock_irqrestore(&vector_lock, flags);
1933}
c4fa0bbf 1934
589e367f 1935/*
676b1855 1936 * MSI message composition
589e367f
EB		 1937 */
1938#ifdef CONFIG_PCI_MSI
3b7d1921 1939static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
589e367f 1940{
dfbffdd8
EB		 1941 struct irq_cfg *cfg = irq_cfg + irq;
1942 int err;
589e367f 1943 unsigned dest;
c7111c13 1944 cpumask_t tmp;
589e367f 1945
dfbffdd8
EB		 1946 tmp = TARGET_CPUS;
1947 err = assign_irq_vector(irq, tmp);
1948 if (!err) {
1949 cpus_and(tmp, cfg->domain, tmp);
589e367f
EB		 1950 dest = cpu_mask_to_apicid(tmp);
1951
1952 msg->address_hi = MSI_ADDR_BASE_HI;
1953 msg->address_lo =
1954 MSI_ADDR_BASE_LO |
1955 ((INT_DEST_MODE == 0) ?
1956 MSI_ADDR_DEST_MODE_PHYSICAL:
1957 MSI_ADDR_DEST_MODE_LOGICAL) |
1958 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1959 MSI_ADDR_REDIRECTION_CPU:
1960 MSI_ADDR_REDIRECTION_LOWPRI) |
1961 MSI_ADDR_DEST_ID(dest);
1962
1963 msg->data =
1964 MSI_DATA_TRIGGER_EDGE |
1965 MSI_DATA_LEVEL_ASSERT |
1966 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1967 MSI_DATA_DELIVERY_FIXED:
1968 MSI_DATA_DELIVERY_LOWPRI) |
dfbffdd8 1969 MSI_DATA_VECTOR(cfg->vector);
589e367f 1970 }
dfbffdd8 1971 return err;
589e367f
EB		 1972}
1973
3b7d1921
EB		 1974#ifdef CONFIG_SMP
1975static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
589e367f 1976{
dfbffdd8 1977 struct irq_cfg *cfg = irq_cfg + irq;
3b7d1921
EB		 1978 struct msi_msg msg;
1979 unsigned int dest;
1980 cpumask_t tmp;
3b7d1921
EB		 1981
1982 cpus_and(tmp, mask, cpu_online_map);
1983 if (cpus_empty(tmp))
5ff5115e 1984 return;
589e367f 1985
dfbffdd8 1986 if (assign_irq_vector(irq, mask))
3b7d1921 1987 return;
550f2299 1988
dfbffdd8 1989 cpus_and(tmp, cfg->domain, mask);
3b7d1921 1990 dest = cpu_mask_to_apicid(tmp);
589e367f 1991
3b7d1921
EB		 1992 read_msi_msg(irq, &msg);
1993
1994 msg.data &= ~MSI_DATA_VECTOR_MASK;
dfbffdd8 1995 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3b7d1921
EB		 1996 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
1997 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
1998
1999 write_msi_msg(irq, &msg);
9f0a5ba5 2000 irq_desc[irq].affinity = mask;
589e367f 2001}
3b7d1921 2002#endif /* CONFIG_SMP */
589e367f 2003
3b7d1921
EB		 2004/*
2005 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2006 * which implement the MSI or MSI-X Capability Structure.
2007 */
2008static struct irq_chip msi_chip = {
2009 .name = "PCI-MSI",
2010 .unmask = unmask_msi_irq,
2011 .mask = mask_msi_irq,
2012 .ack = ack_apic_edge,
2013#ifdef CONFIG_SMP
2014 .set_affinity = set_msi_irq_affinity,
2015#endif
2016 .retrigger = ioapic_retrigger_irq,
589e367f
EB		 2017};
2018
f7feaca7 2019int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
3b7d1921
EB		 2020{
2021 struct msi_msg msg;
f7feaca7
EB		 2022 int irq, ret;
2023 irq = create_irq();
2024 if (irq < 0)
2025 return irq;
2026
3b7d1921 2027 ret = msi_compose_msg(dev, irq, &msg);
f7feaca7
EB		 2028 if (ret < 0) {
2029 destroy_irq(irq);
3b7d1921 2030 return ret;
f7feaca7 2031 }
3b7d1921 2032
7fe3730d 2033 set_irq_msi(irq, desc);
3b7d1921
EB		 2034 write_msi_msg(irq, &msg);
2035
a460e745 2036 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3b7d1921 2037
7fe3730d 2038 return 0;
3b7d1921
EB		 2039}
2040
2041void arch_teardown_msi_irq(unsigned int irq)
2042{
f7feaca7 2043 destroy_irq(irq);
3b7d1921
EB		 2044}
2045
3460a6d9
KA		 2046#ifdef CONFIG_DMAR
2047#ifdef CONFIG_SMP
2048static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask)
2049{
2050 struct irq_cfg *cfg = irq_cfg + irq;
2051 struct msi_msg msg;
2052 unsigned int dest;
2053 cpumask_t tmp;
2054
2055 cpus_and(tmp, mask, cpu_online_map);
2056 if (cpus_empty(tmp))
2057 return;
2058
2059 if (assign_irq_vector(irq, mask))
2060 return;
2061
2062 cpus_and(tmp, cfg->domain, mask);
2063 dest = cpu_mask_to_apicid(tmp);
2064
2065 dmar_msi_read(irq, &msg);
2066
2067 msg.data &= ~MSI_DATA_VECTOR_MASK;
2068 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2069 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2070 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2071
2072 dmar_msi_write(irq, &msg);
2073 irq_desc[irq].affinity = mask;
2074}
2075#endif /* CONFIG_SMP */
2076
2077struct irq_chip dmar_msi_type = {
2078 .name = "DMAR_MSI",
2079 .unmask = dmar_msi_unmask,
2080 .mask = dmar_msi_mask,
2081 .ack = ack_apic_edge,
2082#ifdef CONFIG_SMP
2083 .set_affinity = dmar_msi_set_affinity,
2084#endif
2085 .retrigger = ioapic_retrigger_irq,
2086};
2087
2088int arch_setup_dmar_msi(unsigned int irq)
2089{
2090 int ret;
2091 struct msi_msg msg;
2092
2093 ret = msi_compose_msg(NULL, irq, &msg);
2094 if (ret < 0)
2095 return ret;
2096 dmar_msi_write(irq, &msg);
2097 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
2098 "edge");
2099 return 0;
2100}
2101#endif
589e367f 2102
3460a6d9 2103#endif /* CONFIG_PCI_MSI */
8b955b0d
EB		 2104/*
2105 * Hypertransport interrupt support
2106 */
2107#ifdef CONFIG_HT_IRQ
2108
2109#ifdef CONFIG_SMP
2110
2111static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
2112{
ec68307c
EB		 2113 struct ht_irq_msg msg;
2114 fetch_ht_irq_msg(irq, &msg);
8b955b0d 2115
ec68307c
EB		 2116 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
2117 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
8b955b0d 2118
ec68307c
EB		 2119 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
2120 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
8b955b0d 2121
ec68307c 2122 write_ht_irq_msg(irq, &msg);
8b955b0d
EB		 2123}
2124
2125static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2126{
dfbffdd8 2127 struct irq_cfg *cfg = irq_cfg + irq;
8b955b0d
EB		 2128 unsigned int dest;
2129 cpumask_t tmp;
8b955b0d
EB		 2130
2131 cpus_and(tmp, mask, cpu_online_map);
2132 if (cpus_empty(tmp))
5ff5115e 2133 return;
8b955b0d 2134
dfbffdd8 2135 if (assign_irq_vector(irq, mask))
8b955b0d
EB		 2136 return;
2137
dfbffdd8 2138 cpus_and(tmp, cfg->domain, mask);
8b955b0d
EB		 2139 dest = cpu_mask_to_apicid(tmp);
2140
dfbffdd8 2141 target_ht_irq(irq, dest, cfg->vector);
9f0a5ba5 2142 irq_desc[irq].affinity = mask;
8b955b0d
EB		 2143}
2144#endif
2145
c37e108d 2146static struct irq_chip ht_irq_chip = {
8b955b0d
EB		 2147 .name = "PCI-HT",
2148 .mask = mask_ht_irq,
2149 .unmask = unmask_ht_irq,
2150 .ack = ack_apic_edge,
2151#ifdef CONFIG_SMP
2152 .set_affinity = set_ht_irq_affinity,
2153#endif
2154 .retrigger = ioapic_retrigger_irq,
2155};
2156
2157int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2158{
dfbffdd8
EB		 2159 struct irq_cfg *cfg = irq_cfg + irq;
2160 int err;
c7111c13 2161 cpumask_t tmp;
8b955b0d 2162
dfbffdd8
EB		 2163 tmp = TARGET_CPUS;
2164 err = assign_irq_vector(irq, tmp);
2165 if (!err) {
ec68307c 2166 struct ht_irq_msg msg;
8b955b0d 2167 unsigned dest;
8b955b0d 2168
dfbffdd8 2169 cpus_and(tmp, cfg->domain, tmp);
8b955b0d
EB		 2170 dest = cpu_mask_to_apicid(tmp);
2171
ec68307c 2172 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
8b955b0d 2173
ec68307c
EB		 2174 msg.address_lo =
2175 HT_IRQ_LOW_BASE |
8b955b0d 2176 HT_IRQ_LOW_DEST_ID(dest) |
dfbffdd8 2177 HT_IRQ_LOW_VECTOR(cfg->vector) |
8b955b0d
EB		 2178 ((INT_DEST_MODE == 0) ?
2179 HT_IRQ_LOW_DM_PHYSICAL :
2180 HT_IRQ_LOW_DM_LOGICAL) |
2181 HT_IRQ_LOW_RQEOI_EDGE |
2182 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2183 HT_IRQ_LOW_MT_FIXED :
ec68307c
EB		 2184 HT_IRQ_LOW_MT_ARBITRATED) |
2185 HT_IRQ_LOW_IRQ_MASKED;
8b955b0d 2186
ec68307c 2187 write_ht_irq_msg(irq, &msg);
8b955b0d 2188
a460e745
IM		 2189 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2190 handle_edge_irq, "edge");
8b955b0d 2191 }
dfbffdd8 2192 return err;
8b955b0d
EB		 2193}
2194#endif /* CONFIG_HT_IRQ */
2195
1da177e4
LT		 2196/* --------------------------------------------------------------------------
2197 ACPI-based IOAPIC Configuration
2198 -------------------------------------------------------------------------- */
2199
888ba6c6 2200#ifdef CONFIG_ACPI
1da177e4
LT		 2201
2202#define IO_APIC_MAX_ID 0xFE
2203
1da177e4
LT		 2204int __init io_apic_get_redir_entries (int ioapic)
2205{
2206 union IO_APIC_reg_01 reg_01;
2207 unsigned long flags;
2208
2209 spin_lock_irqsave(&ioapic_lock, flags);
2210 reg_01.raw = io_apic_read(ioapic, 1);
2211 spin_unlock_irqrestore(&ioapic_lock, flags);
2212
2213 return reg_01.bits.entries;
2214}
2215
2216
50eca3eb 2217int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
1da177e4 2218{
1da177e4
LT		 2219 if (!IO_APIC_IRQ(irq)) {
2220 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2221 ioapic);
2222 return -EINVAL;
2223 }
2224
550f2299
EB		 2225 /*
2226 * IRQs < 16 are already in the irq_2_pin[] map
2227 */
2228 if (irq >= 16)
2229 add_pin_to_irq(irq, ioapic, pin);
2230
a8c8a367 2231 setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
1da177e4
LT		 2232
2233 return 0;
2234}
2235
1da177e4 2236
61fd47e0
SL		 2237int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
2238{
2239 int i;
2240
2241 if (skip_ioapic_setup)
2242 return -1;
2243
2244 for (i = 0; i < mp_irq_entries; i++)
2245 if (mp_irqs[i].mpc_irqtype == mp_INT &&
2246 mp_irqs[i].mpc_srcbusirq == bus_irq)
2247 break;
2248 if (i >= mp_irq_entries)
2249 return -1;
2250
2251 *trigger = irq_trigger(i);
2252 *polarity = irq_polarity(i);
2253 return 0;
2254}
2255
2256#endif /* CONFIG_ACPI */
1da177e4
LT		 2257
2258/*
2259 * This function currently is only a helper for the i386 smp boot process where
2260 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2261 * so mask in all cases should simply be TARGET_CPUS
2262 */
54d5d424 2263#ifdef CONFIG_SMP
1da177e4
LT		 2264void __init setup_ioapic_dest(void)
2265{
2266 int pin, ioapic, irq, irq_entry;
2267
2268 if (skip_ioapic_setup == 1)
2269 return;
2270
2271 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2272 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2273 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2274 if (irq_entry == -1)
2275 continue;
2276 irq = pin_2_irq(irq_entry, ioapic, pin);
ad892f5e
YL		 2277
2278 /* setup_IO_APIC_irqs could fail to get vector for some device
2279 * when you have too many devices, because at that time only boot
2280 * cpu is online.
2281 */
13a79503 2282 if (!irq_cfg[irq].vector)
a8c8a367
EB		 2283 setup_IO_APIC_irq(ioapic, pin, irq,
2284 irq_trigger(irq_entry),
2285 irq_polarity(irq_entry));
ad892f5e
YL		 2286 else
2287 set_ioapic_affinity_irq(irq, TARGET_CPUS);
1da177e4
LT		 2288 }
2289
2290 }
2291}
54d5d424 2292#endif
61fd47e0 2293
3e35a0e5
TG		 2294#define IOAPIC_RESOURCE_NAME_SIZE 11
2295
2296static struct resource *ioapic_resources;
2297
2298static struct resource * __init ioapic_setup_resources(void)
2299{
2300 unsigned long n;
2301 struct resource *res;
2302 char *mem;
2303 int i;
2304
2305 if (nr_ioapics <= 0)
2306 return NULL;
2307
2308 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
2309 n *= nr_ioapics;
2310
2311 mem = alloc_bootmem(n);
2312 res = (void *)mem;
2313
2314 if (mem != NULL) {
3e35a0e5
TG		 2315 mem += sizeof(struct resource) * nr_ioapics;
2316
2317 for (i = 0; i < nr_ioapics; i++) {
2318 res[i].name = mem;
2319 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
2320 sprintf(mem, "IOAPIC %u", i);
2321 mem += IOAPIC_RESOURCE_NAME_SIZE;
2322 }
2323 }
2324
2325 ioapic_resources = res;
2326
2327 return res;
2328}
2329
2330void __init ioapic_init_mappings(void)
2331{
2332 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2333 struct resource *ioapic_res;
2334 int i;
2335
2336 ioapic_res = ioapic_setup_resources();
2337 for (i = 0; i < nr_ioapics; i++) {
2338 if (smp_found_config) {
2339 ioapic_phys = mp_ioapics[i].mpc_apicaddr;
2340 } else {
2341 ioapic_phys = (unsigned long)
2342 alloc_bootmem_pages(PAGE_SIZE);
2343 ioapic_phys = __pa(ioapic_phys);
2344 }
2345 set_fixmap_nocache(idx, ioapic_phys);
2346 apic_printk(APIC_VERBOSE,
2347 "mapped IOAPIC to %016lx (%016lx)\n",
2348 __fix_to_virt(idx), ioapic_phys);
2349 idx++;
2350
2351 if (ioapic_res != NULL) {
2352 ioapic_res->start = ioapic_phys;
2353 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
2354 ioapic_res++;
2355 }
2356 }
2357}
2358
2359static int __init ioapic_insert_resources(void)
2360{
2361 int i;
2362 struct resource *r = ioapic_resources;
2363
2364 if (!r) {
2365 printk(KERN_ERR
2366 "IO APIC resources could be not be allocated.\n");
2367 return -1;
2368 }
2369
2370 for (i = 0; i < nr_ioapics; i++) {
2371 insert_resource(&iomem_resource, r);
2372 r++;
2373 }
2374
2375 return 0;
2376}
2377
2378/* Insert the IO APIC resources after PCI initialization has occured to handle
2379 * IO APICS that are mapped in on a BAR in PCI space. */
2380late_initcall(ioapic_insert_resources);
2381
Linux kernel - Deliverables
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