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x86: replace most VM86 flags with flags from processor-flags.h
[deliverable/linux.git] / arch / x86 / kernel / io_apic_64.c
CommitLineData
1da177e4
LT		 1/*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23#include <linux/mm.h>
1da177e4
LT		 24#include <linux/interrupt.h>
25#include <linux/init.h>
26#include <linux/delay.h>
27#include <linux/sched.h>
589e367f 28#include <linux/pci.h>
1da177e4
LT		 29#include <linux/mc146818rtc.h>
30#include <linux/acpi.h>
31#include <linux/sysdev.h>
3b7d1921 32#include <linux/msi.h>
95d77884 33#include <linux/htirq.h>
3460a6d9 34#include <linux/dmar.h>
1d16b53e 35#include <linux/jiffies.h>
ab688059
AK		 36#ifdef CONFIG_ACPI
37#include <acpi/acpi_bus.h>
38#endif
3e35a0e5 39#include <linux/bootmem.h>
1da177e4 40
61014292 41#include <asm/idle.h>
1da177e4
LT		 42#include <asm/io.h>
43#include <asm/smp.h>
44#include <asm/desc.h>
45#include <asm/proto.h>
8d916406 46#include <asm/acpi.h>
ca8642f6 47#include <asm/dma.h>
3e4ff115 48#include <asm/nmi.h>
589e367f 49#include <asm/msidef.h>
8b955b0d 50#include <asm/hypertransport.h>
1da177e4 51
5af5573e 52#include <mach_ipi.h>
dd46e3ca 53#include <mach_apic.h>
5af5573e 54
13a79503
EB		 55struct irq_cfg {
56 cpumask_t domain;
61014292
EB		 57 cpumask_t old_domain;
58 unsigned move_cleanup_count;
13a79503 59 u8 vector;
61014292 60 u8 move_in_progress : 1;
13a79503
EB		 61};
62
63/* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
64struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
bc5e81a1
EB		 65 [0] = { .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
66 [1] = { .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
67 [2] = { .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
68 [3] = { .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
69 [4] = { .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
70 [5] = { .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
71 [6] = { .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
72 [7] = { .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
73 [8] = { .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
74 [9] = { .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
75 [10] = { .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
76 [11] = { .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
77 [12] = { .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
78 [13] = { .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
79 [14] = { .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
80 [15] = { .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
13a79503
EB		 81};
82
dfbffdd8 83static int assign_irq_vector(int irq, cpumask_t mask);
04b9267b 84
1da177e4
LT		 85#define __apicdebuginit __init
86
87int sis_apic_bug; /* not actually supported, dummy for compile */
88
14d98cad
AK		 89static int no_timer_check;
90
fea5f1e1
LT		 91static int disable_timer_pin_1 __initdata;
92
93int timer_over_8254 __initdata = 1;
94
1008fddc
EB		 95/* Where if anywhere is the i8259 connect in external int mode */
96static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
97
1da177e4 98static DEFINE_SPINLOCK(ioapic_lock);
70a0a535 99DEFINE_SPINLOCK(vector_lock);
1da177e4
LT		 100
101/*
102 * # of IRQ routing registers
103 */
104int nr_ioapic_registers[MAX_IO_APICS];
105
106/*
107 * Rough estimation of how many shared IRQs there are, can
108 * be changed anytime.
109 */
e273d140 110#define MAX_PLUS_SHARED_IRQS NR_IRQS
1da177e4
LT		 111#define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
112
113/*
114 * This is performance-critical, we want to do it O(1)
115 *
116 * the indexing order of this array favors 1:1 mappings
117 * between pins and IRQs.
118 */
119
120static struct irq_pin_list {
121 short apic, pin, next;
122} irq_2_pin[PIN_MAP_SIZE];
123
6c0ffb9d
LT		 124struct io_apic {
125 unsigned int index;
126 unsigned int unused[3];
127 unsigned int data;
128};
129
130static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
131{
132 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
133 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
134}
135
136static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
137{
138 struct io_apic __iomem *io_apic = io_apic_base(apic);
139 writel(reg, &io_apic->index);
140 return readl(&io_apic->data);
141}
142
143static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
144{
145 struct io_apic __iomem *io_apic = io_apic_base(apic);
146 writel(reg, &io_apic->index);
147 writel(value, &io_apic->data);
148}
149
150/*
151 * Re-write a value: to be used for read-modify-write
152 * cycles where the read already set up the index register.
153 */
154static inline void io_apic_modify(unsigned int apic, unsigned int value)
155{
156 struct io_apic __iomem *io_apic = io_apic_base(apic);
157 writel(value, &io_apic->data);
158}
159
ef3e28c5
EB		 160static int io_apic_level_ack_pending(unsigned int irq)
161{
162 struct irq_pin_list *entry;
163 unsigned long flags;
164 int pending = 0;
165
166 spin_lock_irqsave(&ioapic_lock, flags);
167 entry = irq_2_pin + irq;
168 for (;;) {
169 unsigned int reg;
170 int pin;
171
172 pin = entry->pin;
173 if (pin == -1)
174 break;
175 reg = io_apic_read(entry->apic, 0x10 + pin*2);
176 /* Is the remote IRR bit set? */
177 pending |= (reg >> 14) & 1;
178 if (!entry->next)
179 break;
180 entry = irq_2_pin + entry->next;
181 }
182 spin_unlock_irqrestore(&ioapic_lock, flags);
183 return pending;
184}
185
6c0ffb9d
LT		 186/*
187 * Synchronize the IO-APIC and the CPU by doing
188 * a dummy read from the IO-APIC
189 */
190static inline void io_apic_sync(unsigned int apic)
191{
192 struct io_apic __iomem *io_apic = io_apic_base(apic);
193 readl(&io_apic->data);
194}
195
54d5d424
AR		 196#define __DO_ACTION(R, ACTION, FINAL) \
197 \
198{ \
199 int pin; \
200 struct irq_pin_list *entry = irq_2_pin + irq; \
201 \
6004e1b7 202 BUG_ON(irq >= NR_IRQS); \
54d5d424
AR		 203 for (;;) { \
204 unsigned int reg; \
205 pin = entry->pin; \
206 if (pin == -1) \
207 break; \
208 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
209 reg ACTION; \
210 io_apic_modify(entry->apic, reg); \
f45bcd70 211 FINAL; \
54d5d424
AR		 212 if (!entry->next) \
213 break; \
214 entry = irq_2_pin + entry->next; \
215 } \
54d5d424
AR		 216}
217
eea0e11c
AK		 218union entry_union {
219 struct { u32 w1, w2; };
220 struct IO_APIC_route_entry entry;
221};
222
223static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
224{
225 union entry_union eu;
226 unsigned long flags;
227 spin_lock_irqsave(&ioapic_lock, flags);
228 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
229 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
230 spin_unlock_irqrestore(&ioapic_lock, flags);
231 return eu.entry;
232}
233
48797ebd
LT		 234/*
235 * When we write a new IO APIC routing entry, we need to write the high
236 * word first! If the mask bit in the low word is clear, we will enable
237 * the interrupt, and we need to make sure the entry is fully populated
238 * before that happens.
239 */
516d2836
AK		 240static void
241__ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
eea0e11c 242{
eea0e11c
AK		 243 union entry_union eu;
244 eu.entry = e;
48797ebd
LT		 245 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
246 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
516d2836
AK		 247}
248
249static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
250{
251 unsigned long flags;
252 spin_lock_irqsave(&ioapic_lock, flags);
253 __ioapic_write_entry(apic, pin, e);
48797ebd
LT		 254 spin_unlock_irqrestore(&ioapic_lock, flags);
255}
256
257/*
258 * When we mask an IO APIC routing entry, we need to write the low
259 * word first, in order to set the mask bit before we change the
260 * high bits!
261 */
262static void ioapic_mask_entry(int apic, int pin)
263{
264 unsigned long flags;
265 union entry_union eu = { .entry.mask = 1 };
266
eea0e11c
AK		 267 spin_lock_irqsave(&ioapic_lock, flags);
268 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
269 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
270 spin_unlock_irqrestore(&ioapic_lock, flags);
271}
272
54d5d424 273#ifdef CONFIG_SMP
550f2299
EB		 274static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
275{
276 int apic, pin;
277 struct irq_pin_list *entry = irq_2_pin + irq;
278
279 BUG_ON(irq >= NR_IRQS);
280 for (;;) {
281 unsigned int reg;
282 apic = entry->apic;
283 pin = entry->pin;
284 if (pin == -1)
285 break;
286 io_apic_write(apic, 0x11 + pin*2, dest);
287 reg = io_apic_read(apic, 0x10 + pin*2);
288 reg &= ~0x000000ff;
289 reg |= vector;
290 io_apic_modify(apic, reg);
291 if (!entry->next)
292 break;
293 entry = irq_2_pin + entry->next;
294 }
295}
296
54d5d424
AR		 297static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
298{
dfbffdd8 299 struct irq_cfg *cfg = irq_cfg + irq;
54d5d424
AR		 300 unsigned long flags;
301 unsigned int dest;
302 cpumask_t tmp;
303
304 cpus_and(tmp, mask, cpu_online_map);
305 if (cpus_empty(tmp))
5ff5115e 306 return;
54d5d424 307
dfbffdd8 308 if (assign_irq_vector(irq, mask))
550f2299
EB		 309 return;
310
dfbffdd8 311 cpus_and(tmp, cfg->domain, mask);
550f2299 312 dest = cpu_mask_to_apicid(tmp);
54d5d424
AR		 313
314 /*
315 * Only the high 8 bits are valid.
316 */
317 dest = SET_APIC_LOGICAL_ID(dest);
318
319 spin_lock_irqsave(&ioapic_lock, flags);
dfbffdd8 320 __target_IO_APIC_irq(irq, dest, cfg->vector);
9f0a5ba5 321 irq_desc[irq].affinity = mask;
54d5d424
AR		 322 spin_unlock_irqrestore(&ioapic_lock, flags);
323}
324#endif
325
1da177e4
LT		 326/*
327 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
328 * shared ISA-space IRQs, so we have to support them. We are super
329 * fast in the common case, and fast for shared ISA-space IRQs.
330 */
331static void add_pin_to_irq(unsigned int irq, int apic, int pin)
332{
333 static int first_free_entry = NR_IRQS;
334 struct irq_pin_list *entry = irq_2_pin + irq;
335
6004e1b7 336 BUG_ON(irq >= NR_IRQS);
1da177e4
LT		 337 while (entry->next)
338 entry = irq_2_pin + entry->next;
339
340 if (entry->pin != -1) {
341 entry->next = first_free_entry;
342 entry = irq_2_pin + entry->next;
343 if (++first_free_entry >= PIN_MAP_SIZE)
6004e1b7 344 panic("io_apic.c: ran out of irq_2_pin entries!");
1da177e4
LT		 345 }
346 entry->apic = apic;
347 entry->pin = pin;
348}
349
1da177e4
LT		 350
351#define DO_ACTION(name,R,ACTION, FINAL) \
352 \
353 static void name##_IO_APIC_irq (unsigned int irq) \
354 __DO_ACTION(R, ACTION, FINAL)
355
356DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
357 /* mask = 1 */
358DO_ACTION( __unmask, 0, &= 0xfffeffff, )
359 /* mask = 0 */
360
361static void mask_IO_APIC_irq (unsigned int irq)
362{
363 unsigned long flags;
364
365 spin_lock_irqsave(&ioapic_lock, flags);
366 __mask_IO_APIC_irq(irq);
367 spin_unlock_irqrestore(&ioapic_lock, flags);
368}
369
370static void unmask_IO_APIC_irq (unsigned int irq)
371{
372 unsigned long flags;
373
374 spin_lock_irqsave(&ioapic_lock, flags);
375 __unmask_IO_APIC_irq(irq);
376 spin_unlock_irqrestore(&ioapic_lock, flags);
377}
378
379static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
380{
381 struct IO_APIC_route_entry entry;
1da177e4
LT		 382
383 /* Check delivery_mode to be sure we're not clearing an SMI pin */
eea0e11c 384 entry = ioapic_read_entry(apic, pin);
1da177e4
LT		 385 if (entry.delivery_mode == dest_SMI)
386 return;
387 /*
388 * Disable it in the IO-APIC irq-routing table:
389 */
48797ebd 390 ioapic_mask_entry(apic, pin);
1da177e4
LT		 391}
392
393static void clear_IO_APIC (void)
394{
395 int apic, pin;
396
397 for (apic = 0; apic < nr_ioapics; apic++)
398 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
399 clear_IO_APIC_pin(apic, pin);
400}
401
1da177e4
LT		 402int skip_ioapic_setup;
403int ioapic_force;
404
61ec7567 405static int __init parse_noapic(char *str)
1da177e4 406{
61ec7567 407 disable_ioapic_setup();
2c8c0e6b 408 return 0;
1da177e4 409}
61ec7567 410early_param("noapic", parse_noapic);
1da177e4 411
fea5f1e1
LT		 412/* Actually the next is obsolete, but keep it for paranoid reasons -AK */
413static int __init disable_timer_pin_setup(char *arg)
414{
415 disable_timer_pin_1 = 1;
416 return 1;
417}
418__setup("disable_timer_pin_1", disable_timer_pin_setup);
419
420static int __init setup_disable_8254_timer(char *s)
421{
422 timer_over_8254 = -1;
423 return 1;
424}
425static int __init setup_enable_8254_timer(char *s)
426{
427 timer_over_8254 = 2;
428 return 1;
429}
430
431__setup("disable_8254_timer", setup_disable_8254_timer);
432__setup("enable_8254_timer", setup_enable_8254_timer);
433
434
1da177e4
LT		 435/*
436 * Find the IRQ entry number of a certain pin.
437 */
438static int find_irq_entry(int apic, int pin, int type)
439{
440 int i;
441
442 for (i = 0; i < mp_irq_entries; i++)
443 if (mp_irqs[i].mpc_irqtype == type &&
444 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
445 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
446 mp_irqs[i].mpc_dstirq == pin)
447 return i;
448
449 return -1;
450}
451
452/*
453 * Find the pin to which IRQ[irq] (ISA) is connected
454 */
1008fddc 455static int __init find_isa_irq_pin(int irq, int type)
1da177e4
LT		 456{
457 int i;
458
459 for (i = 0; i < mp_irq_entries; i++) {
460 int lbus = mp_irqs[i].mpc_srcbus;
461
55f05ffa 462 if (test_bit(lbus, mp_bus_not_pci) &&
1da177e4
LT		 463 (mp_irqs[i].mpc_irqtype == type) &&
464 (mp_irqs[i].mpc_srcbusirq == irq))
465
466 return mp_irqs[i].mpc_dstirq;
467 }
468 return -1;
469}
470
1008fddc
EB		 471static int __init find_isa_irq_apic(int irq, int type)
472{
473 int i;
474
475 for (i = 0; i < mp_irq_entries; i++) {
476 int lbus = mp_irqs[i].mpc_srcbus;
477
55f05ffa 478 if (test_bit(lbus, mp_bus_not_pci) &&
1008fddc
EB		 479 (mp_irqs[i].mpc_irqtype == type) &&
480 (mp_irqs[i].mpc_srcbusirq == irq))
481 break;
482 }
483 if (i < mp_irq_entries) {
484 int apic;
485 for(apic = 0; apic < nr_ioapics; apic++) {
486 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
487 return apic;
488 }
489 }
490
491 return -1;
492}
493
1da177e4
LT		 494/*
495 * Find a specific PCI IRQ entry.
496 * Not an __init, possibly needed by modules
497 */
498static int pin_2_irq(int idx, int apic, int pin);
499
500int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
501{
502 int apic, i, best_guess = -1;
503
504 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
505 bus, slot, pin);
506 if (mp_bus_id_to_pci_bus[bus] == -1) {
507 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
508 return -1;
509 }
510 for (i = 0; i < mp_irq_entries; i++) {
511 int lbus = mp_irqs[i].mpc_srcbus;
512
513 for (apic = 0; apic < nr_ioapics; apic++)
514 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
515 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
516 break;
517
55f05ffa 518 if (!test_bit(lbus, mp_bus_not_pci) &&
1da177e4
LT		 519 !mp_irqs[i].mpc_irqtype &&
520 (bus == lbus) &&
521 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
522 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
523
524 if (!(apic || IO_APIC_IRQ(irq)))
525 continue;
526
527 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
528 return irq;
529 /*
530 * Use the first all-but-pin matching entry as a
531 * best-guess fuzzy result for broken mptables.
532 */
533 if (best_guess < 0)
534 best_guess = irq;
535 }
536 }
6004e1b7 537 BUG_ON(best_guess >= NR_IRQS);
1da177e4
LT		 538 return best_guess;
539}
540
1da177e4
LT		 541/* ISA interrupts are always polarity zero edge triggered,
542 * when listed as conforming in the MP table. */
543
544#define default_ISA_trigger(idx) (0)
545#define default_ISA_polarity(idx) (0)
546
547/* PCI interrupts are always polarity one level triggered,
548 * when listed as conforming in the MP table. */
549
550#define default_PCI_trigger(idx) (1)
551#define default_PCI_polarity(idx) (1)
552
61fd47e0 553static int MPBIOS_polarity(int idx)
1da177e4
LT		 554{
555 int bus = mp_irqs[idx].mpc_srcbus;
556 int polarity;
557
558 /*
559 * Determine IRQ line polarity (high active or low active):
560 */
561 switch (mp_irqs[idx].mpc_irqflag & 3)
562 {
563 case 0: /* conforms, ie. bus-type dependent polarity */
55f05ffa
AK		 564 if (test_bit(bus, mp_bus_not_pci))
565 polarity = default_ISA_polarity(idx);
566 else
567 polarity = default_PCI_polarity(idx);
1da177e4 568 break;
1da177e4
LT		 569 case 1: /* high active */
570 {
571 polarity = 0;
572 break;
573 }
574 case 2: /* reserved */
575 {
576 printk(KERN_WARNING "broken BIOS!!\n");
577 polarity = 1;
578 break;
579 }
580 case 3: /* low active */
581 {
582 polarity = 1;
583 break;
584 }
585 default: /* invalid */
586 {
587 printk(KERN_WARNING "broken BIOS!!\n");
588 polarity = 1;
589 break;
590 }
591 }
592 return polarity;
593}
594
595static int MPBIOS_trigger(int idx)
596{
597 int bus = mp_irqs[idx].mpc_srcbus;
598 int trigger;
599
600 /*
601 * Determine IRQ trigger mode (edge or level sensitive):
602 */
603 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
604 {
605 case 0: /* conforms, ie. bus-type dependent */
55f05ffa
AK		 606 if (test_bit(bus, mp_bus_not_pci))
607 trigger = default_ISA_trigger(idx);
608 else
609 trigger = default_PCI_trigger(idx);
1da177e4 610 break;
1da177e4
LT		 611 case 1: /* edge */
612 {
613 trigger = 0;
614 break;
615 }
616 case 2: /* reserved */
617 {
618 printk(KERN_WARNING "broken BIOS!!\n");
619 trigger = 1;
620 break;
621 }
622 case 3: /* level */
623 {
624 trigger = 1;
625 break;
626 }
627 default: /* invalid */
628 {
629 printk(KERN_WARNING "broken BIOS!!\n");
630 trigger = 0;
631 break;
632 }
633 }
634 return trigger;
635}
636
637static inline int irq_polarity(int idx)
638{
639 return MPBIOS_polarity(idx);
640}
641
642static inline int irq_trigger(int idx)
643{
644 return MPBIOS_trigger(idx);
645}
646
647static int pin_2_irq(int idx, int apic, int pin)
648{
649 int irq, i;
650 int bus = mp_irqs[idx].mpc_srcbus;
651
652 /*
653 * Debugging check, we are in big trouble if this message pops up!
654 */
655 if (mp_irqs[idx].mpc_dstirq != pin)
656 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
657
55f05ffa
AK		 658 if (test_bit(bus, mp_bus_not_pci)) {
659 irq = mp_irqs[idx].mpc_srcbusirq;
660 } else {
661 /*
662 * PCI IRQs are mapped in order
663 */
664 i = irq = 0;
665 while (i < apic)
666 irq += nr_ioapic_registers[i++];
667 irq += pin;
1da177e4 668 }
6004e1b7 669 BUG_ON(irq >= NR_IRQS);
1da177e4
LT		 670 return irq;
671}
672
dfbffdd8 673static int __assign_irq_vector(int irq, cpumask_t mask)
1da177e4 674{
550f2299
EB		 675 /*
676 * NOTE! The local APIC isn't very good at handling
677 * multiple interrupts at the same interrupt level.
678 * As the interrupt level is determined by taking the
679 * vector number and shifting that right by 4, we
680 * want to spread these out a bit so that they don't
681 * all fall in the same interrupt level.
682 *
683 * Also, we've got to be careful not to trash gate
684 * 0x80, because int 0x80 is hm, kind of importantish. ;)
685 */
d1752aa8 686 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
dfbffdd8 687 unsigned int old_vector;
550f2299 688 int cpu;
13a79503 689 struct irq_cfg *cfg;
1da177e4 690
e273d140 691 BUG_ON((unsigned)irq >= NR_IRQS);
13a79503 692 cfg = &irq_cfg[irq];
0a1ad60d 693
70a0a535
EB		 694 /* Only try and allocate irqs on cpus that are present */
695 cpus_and(mask, mask, cpu_online_map);
696
61014292
EB		 697 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
698 return -EBUSY;
699
dfbffdd8
EB		 700 old_vector = cfg->vector;
701 if (old_vector) {
702 cpumask_t tmp;
703 cpus_and(tmp, cfg->domain, mask);
704 if (!cpus_empty(tmp))
705 return 0;
0a1ad60d 706 }
550f2299
EB		 707
708 for_each_cpu_mask(cpu, mask) {
70a0a535 709 cpumask_t domain, new_mask;
61014292 710 int new_cpu;
550f2299 711 int vector, offset;
c7111c13
EB		 712
713 domain = vector_allocation_domain(cpu);
70a0a535 714 cpus_and(new_mask, domain, cpu_online_map);
c7111c13 715
d1752aa8
EB		 716 vector = current_vector;
717 offset = current_offset;
1da177e4 718next:
550f2299
EB		 719 vector += 8;
720 if (vector >= FIRST_SYSTEM_VECTOR) {
721 /* If we run out of vectors on large boxen, must share them. */
722 offset = (offset + 1) % 8;
723 vector = FIRST_DEVICE_VECTOR + offset;
724 }
d1752aa8 725 if (unlikely(current_vector == vector))
550f2299
EB		 726 continue;
727 if (vector == IA32_SYSCALL_VECTOR)
728 goto next;
70a0a535 729 for_each_cpu_mask(new_cpu, new_mask)
45edfd1d 730 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
c7111c13 731 goto next;
550f2299 732 /* Found one! */
d1752aa8
EB		 733 current_vector = vector;
734 current_offset = offset;
61014292
EB		 735 if (old_vector) {
736 cfg->move_in_progress = 1;
737 cfg->old_domain = cfg->domain;
738 }
70a0a535 739 for_each_cpu_mask(new_cpu, new_mask)
c7111c13 740 per_cpu(vector_irq, new_cpu)[vector] = irq;
13a79503
EB		 741 cfg->vector = vector;
742 cfg->domain = domain;
dfbffdd8 743 return 0;
1da177e4 744 }
550f2299 745 return -ENOSPC;
04b9267b
EB		 746}
747
dfbffdd8 748static int assign_irq_vector(int irq, cpumask_t mask)
04b9267b 749{
dfbffdd8 750 int err;
04b9267b 751 unsigned long flags;
0a1ad60d 752
04b9267b 753 spin_lock_irqsave(&vector_lock, flags);
dfbffdd8 754 err = __assign_irq_vector(irq, mask);
26a3c49c 755 spin_unlock_irqrestore(&vector_lock, flags);
dfbffdd8 756 return err;
1da177e4
LT		 757}
758
5df0287e
YL		 759static void __clear_irq_vector(int irq)
760{
13a79503 761 struct irq_cfg *cfg;
5df0287e
YL		 762 cpumask_t mask;
763 int cpu, vector;
764
13a79503
EB		 765 BUG_ON((unsigned)irq >= NR_IRQS);
766 cfg = &irq_cfg[irq];
767 BUG_ON(!cfg->vector);
5df0287e 768
13a79503
EB		 769 vector = cfg->vector;
770 cpus_and(mask, cfg->domain, cpu_online_map);
5df0287e
YL		 771 for_each_cpu_mask(cpu, mask)
772 per_cpu(vector_irq, cpu)[vector] = -1;
773
13a79503
EB		 774 cfg->vector = 0;
775 cfg->domain = CPU_MASK_NONE;
5df0287e
YL		 776}
777
70a0a535
EB		 778void __setup_vector_irq(int cpu)
779{
780 /* Initialize vector_irq on a new cpu */
781 /* This function must be called with vector_lock held */
70a0a535
EB		 782 int irq, vector;
783
70a0a535 784 /* Mark the inuse vectors */
e273d140 785 for (irq = 0; irq < NR_IRQS; ++irq) {
13a79503 786 if (!cpu_isset(cpu, irq_cfg[irq].domain))
70a0a535 787 continue;
13a79503 788 vector = irq_cfg[irq].vector;
70a0a535
EB		 789 per_cpu(vector_irq, cpu)[vector] = irq;
790 }
791 /* Mark the free vectors */
792 for (vector = 0; vector < NR_VECTORS; ++vector) {
793 irq = per_cpu(vector_irq, cpu)[vector];
794 if (irq < 0)
795 continue;
13a79503 796 if (!cpu_isset(cpu, irq_cfg[irq].domain))
70a0a535
EB		 797 per_cpu(vector_irq, cpu)[vector] = -1;
798 }
799}
800
801
f29bd1ba 802static struct irq_chip ioapic_chip;
1da177e4 803
a27bc06d 804static void ioapic_register_intr(int irq, unsigned long trigger)
1da177e4 805{
cc75b92d
TG		 806 if (trigger) {
807 irq_desc[irq].status |= IRQ_LEVEL;
a460e745
IM		 808 set_irq_chip_and_handler_name(irq, &ioapic_chip,
809 handle_fasteoi_irq, "fasteoi");
cc75b92d
TG		 810 } else {
811 irq_desc[irq].status &= ~IRQ_LEVEL;
a460e745
IM		 812 set_irq_chip_and_handler_name(irq, &ioapic_chip,
813 handle_edge_irq, "edge");
cc75b92d 814 }
1da177e4 815}
a8c8a367
EB		 816
817static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
818 int trigger, int polarity)
1da177e4 819{
dfbffdd8 820 struct irq_cfg *cfg = irq_cfg + irq;
1da177e4 821 struct IO_APIC_route_entry entry;
a8c8a367 822 cpumask_t mask;
1da177e4 823
a8c8a367
EB		 824 if (!IO_APIC_IRQ(irq))
825 return;
826
dfbffdd8
EB		 827 mask = TARGET_CPUS;
828 if (assign_irq_vector(irq, mask))
a8c8a367
EB		 829 return;
830
dfbffdd8
EB		 831 cpus_and(mask, cfg->domain, mask);
832
a8c8a367
EB		 833 apic_printk(APIC_VERBOSE,KERN_DEBUG
834 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
835 "IRQ %d Mode:%i Active:%i)\n",
dfbffdd8 836 apic, mp_ioapics[apic].mpc_apicid, pin, cfg->vector,
a8c8a367 837 irq, trigger, polarity);
1da177e4 838
ad892f5e
YL		 839 /*
840 * add it to the IO-APIC irq-routing table:
841 */
842 memset(&entry,0,sizeof(entry));
1da177e4 843
ad892f5e
YL		 844 entry.delivery_mode = INT_DELIVERY_MODE;
845 entry.dest_mode = INT_DEST_MODE;
a8c8a367 846 entry.dest = cpu_mask_to_apicid(mask);
ad892f5e 847 entry.mask = 0; /* enable IRQ */
a8c8a367
EB		 848 entry.trigger = trigger;
849 entry.polarity = polarity;
dfbffdd8 850 entry.vector = cfg->vector;
1da177e4 851
a8c8a367
EB		 852 /* Mask level triggered irqs.
853 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
854 */
855 if (trigger)
ad892f5e 856 entry.mask = 1;
ad892f5e 857
a8c8a367
EB		 858 ioapic_register_intr(irq, trigger);
859 if (irq < 16)
860 disable_8259A_irq(irq);
ad892f5e
YL		 861
862 ioapic_write_entry(apic, pin, entry);
ad892f5e
YL		 863}
864
865static void __init setup_IO_APIC_irqs(void)
866{
867 int apic, pin, idx, irq, first_notcon = 1;
868
869 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
870
871 for (apic = 0; apic < nr_ioapics; apic++) {
872 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1da177e4
LT		 873
874 idx = find_irq_entry(apic,pin,mp_INT);
875 if (idx == -1) {
876 if (first_notcon) {
877 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
878 first_notcon = 0;
879 } else
880 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
881 continue;
882 }
20d225b9
YL		 883 if (!first_notcon) {
884 apic_printk(APIC_VERBOSE, " not connected.\n");
885 first_notcon = 1;
886 }
1da177e4 887
1da177e4
LT		 888 irq = pin_2_irq(idx, apic, pin);
889 add_pin_to_irq(irq, apic, pin);
890
a8c8a367
EB		 891 setup_IO_APIC_irq(apic, pin, irq,
892 irq_trigger(idx), irq_polarity(idx));
1da177e4
LT		 893 }
894 }
895
896 if (!first_notcon)
20d225b9 897 apic_printk(APIC_VERBOSE, " not connected.\n");
1da177e4
LT		 898}
899
900/*
901 * Set up the 8259A-master output pin as broadcast to all
902 * CPUs.
903 */
1008fddc 904static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1da177e4
LT		 905{
906 struct IO_APIC_route_entry entry;
907 unsigned long flags;
908
909 memset(&entry,0,sizeof(entry));
910
911 disable_8259A_irq(0);
912
913 /* mask LVT0 */
11a8e778 914 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1da177e4
LT		 915
916 /*
917 * We use logical delivery to get the timer IRQ
918 * to the first CPU.
919 */
920 entry.dest_mode = INT_DEST_MODE;
921 entry.mask = 0; /* unmask IRQ now */
ee4eff6f 922 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
1da177e4
LT		 923 entry.delivery_mode = INT_DELIVERY_MODE;
924 entry.polarity = 0;
925 entry.trigger = 0;
926 entry.vector = vector;
927
928 /*
929 * The timer IRQ doesn't have to know that behind the
930 * scene we have a 8259A-master in AEOI mode ...
931 */
a460e745 932 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1da177e4
LT		 933
934 /*
935 * Add it to the IO-APIC irq-routing table:
936 */
937 spin_lock_irqsave(&ioapic_lock, flags);
1008fddc
EB		 938 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
939 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1da177e4
LT		 940 spin_unlock_irqrestore(&ioapic_lock, flags);
941
942 enable_8259A_irq(0);
943}
944
1da177e4
LT		 945void __apicdebuginit print_IO_APIC(void)
946{
947 int apic, i;
948 union IO_APIC_reg_00 reg_00;
949 union IO_APIC_reg_01 reg_01;
950 union IO_APIC_reg_02 reg_02;
951 unsigned long flags;
952
953 if (apic_verbosity == APIC_QUIET)
954 return;
955
956 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
957 for (i = 0; i < nr_ioapics; i++)
958 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
959 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
960
961 /*
962 * We are a bit conservative about what we expect. We have to
963 * know about every hardware change ASAP.
964 */
965 printk(KERN_INFO "testing the IO APIC.......................\n");
966
967 for (apic = 0; apic < nr_ioapics; apic++) {
968
969 spin_lock_irqsave(&ioapic_lock, flags);
970 reg_00.raw = io_apic_read(apic, 0);
971 reg_01.raw = io_apic_read(apic, 1);
972 if (reg_01.bits.version >= 0x10)
973 reg_02.raw = io_apic_read(apic, 2);
974 spin_unlock_irqrestore(&ioapic_lock, flags);
975
976 printk("\n");
977 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
978 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
979 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1da177e4
LT		 980
981 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
982 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1da177e4
LT		 983
984 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
985 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1da177e4
LT		 986
987 if (reg_01.bits.version >= 0x10) {
988 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
989 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1da177e4
LT		 990 }
991
992 printk(KERN_DEBUG ".... IRQ redirection table:\n");
993
ee4eff6f
BR		 994 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
995 " Stat Dmod Deli Vect: \n");
1da177e4
LT		 996
997 for (i = 0; i <= reg_01.bits.entries; i++) {
998 struct IO_APIC_route_entry entry;
999
eea0e11c 1000 entry = ioapic_read_entry(apic, i);
1da177e4 1001
ee4eff6f 1002 printk(KERN_DEBUG " %02x %03X ",
1da177e4 1003 i,
ee4eff6f 1004 entry.dest
1da177e4
LT		 1005 );
1006
1007 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1008 entry.mask,
1009 entry.trigger,
1010 entry.irr,
1011 entry.polarity,
1012 entry.delivery_status,
1013 entry.dest_mode,
1014 entry.delivery_mode,
1015 entry.vector
1016 );
1017 }
1018 }
1da177e4
LT		 1019 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1020 for (i = 0; i < NR_IRQS; i++) {
1021 struct irq_pin_list *entry = irq_2_pin + i;
1022 if (entry->pin < 0)
1023 continue;
04b9267b 1024 printk(KERN_DEBUG "IRQ%d ", i);
1da177e4
LT		 1025 for (;;) {
1026 printk("-> %d:%d", entry->apic, entry->pin);
1027 if (!entry->next)
1028 break;
1029 entry = irq_2_pin + entry->next;
1030 }
1031 printk("\n");
1032 }
1033
1034 printk(KERN_INFO ".................................... done.\n");
1035
1036 return;
1037}
1038
1039#if 0
1040
1041static __apicdebuginit void print_APIC_bitfield (int base)
1042{
1043 unsigned int v;
1044 int i, j;
1045
1046 if (apic_verbosity == APIC_QUIET)
1047 return;
1048
1049 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1050 for (i = 0; i < 8; i++) {
1051 v = apic_read(base + i*0x10);
1052 for (j = 0; j < 32; j++) {
1053 if (v & (1<<j))
1054 printk("1");
1055 else
1056 printk("0");
1057 }
1058 printk("\n");
1059 }
1060}
1061
1062void __apicdebuginit print_local_APIC(void * dummy)
1063{
1064 unsigned int v, ver, maxlvt;
1065
1066 if (apic_verbosity == APIC_QUIET)
1067 return;
1068
1069 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1070 smp_processor_id(), hard_smp_processor_id());
1071 v = apic_read(APIC_ID);
1072 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
1073 v = apic_read(APIC_LVR);
1074 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1075 ver = GET_APIC_VERSION(v);
37e650c7 1076 maxlvt = lapic_get_maxlvt();
1da177e4
LT		 1077
1078 v = apic_read(APIC_TASKPRI);
1079 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1080
5a40b7c2
AK		 1081 v = apic_read(APIC_ARBPRI);
1082 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1083 v & APIC_ARBPRI_MASK);
1084 v = apic_read(APIC_PROCPRI);
1085 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1da177e4
LT		 1086
1087 v = apic_read(APIC_EOI);
1088 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1089 v = apic_read(APIC_RRR);
1090 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1091 v = apic_read(APIC_LDR);
1092 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1093 v = apic_read(APIC_DFR);
1094 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1095 v = apic_read(APIC_SPIV);
1096 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1097
1098 printk(KERN_DEBUG "... APIC ISR field:\n");
1099 print_APIC_bitfield(APIC_ISR);
1100 printk(KERN_DEBUG "... APIC TMR field:\n");
1101 print_APIC_bitfield(APIC_TMR);
1102 printk(KERN_DEBUG "... APIC IRR field:\n");
1103 print_APIC_bitfield(APIC_IRR);
1104
5a40b7c2
AK		 1105 v = apic_read(APIC_ESR);
1106 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1da177e4
LT		 1107
1108 v = apic_read(APIC_ICR);
1109 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1110 v = apic_read(APIC_ICR2);
1111 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1112
1113 v = apic_read(APIC_LVTT);
1114 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1115
1116 if (maxlvt > 3) { /* PC is LVT#4. */
1117 v = apic_read(APIC_LVTPC);
1118 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1119 }
1120 v = apic_read(APIC_LVT0);
1121 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1122 v = apic_read(APIC_LVT1);
1123 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1124
1125 if (maxlvt > 2) { /* ERR is LVT#3. */
1126 v = apic_read(APIC_LVTERR);
1127 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1128 }
1129
1130 v = apic_read(APIC_TMICT);
1131 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1132 v = apic_read(APIC_TMCCT);
1133 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1134 v = apic_read(APIC_TDCR);
1135 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1136 printk("\n");
1137}
1138
1139void print_all_local_APICs (void)
1140{
1141 on_each_cpu(print_local_APIC, NULL, 1, 1);
1142}
1143
1144void __apicdebuginit print_PIC(void)
1145{
1da177e4
LT		 1146 unsigned int v;
1147 unsigned long flags;
1148
1149 if (apic_verbosity == APIC_QUIET)
1150 return;
1151
1152 printk(KERN_DEBUG "\nprinting PIC contents\n");
1153
1154 spin_lock_irqsave(&i8259A_lock, flags);
1155
1156 v = inb(0xa1) << 8 | inb(0x21);
1157 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1158
1159 v = inb(0xa0) << 8 | inb(0x20);
1160 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1161
1162 outb(0x0b,0xa0);
1163 outb(0x0b,0x20);
1164 v = inb(0xa0) << 8 | inb(0x20);
1165 outb(0x0a,0xa0);
1166 outb(0x0a,0x20);
1167
1168 spin_unlock_irqrestore(&i8259A_lock, flags);
1169
1170 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1171
1172 v = inb(0x4d1) << 8 | inb(0x4d0);
1173 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1174}
1175
1176#endif /* 0 */
1177
1c69524c 1178void __init enable_IO_APIC(void)
1da177e4
LT		 1179{
1180 union IO_APIC_reg_01 reg_01;
1008fddc
EB		 1181 int i8259_apic, i8259_pin;
1182 int i, apic;
1da177e4
LT		 1183 unsigned long flags;
1184
1185 for (i = 0; i < PIN_MAP_SIZE; i++) {
1186 irq_2_pin[i].pin = -1;
1187 irq_2_pin[i].next = 0;
1188 }
1da177e4
LT		 1189
1190 /*
1191 * The number of IO-APIC IRQ registers (== #pins):
1192 */
1008fddc 1193 for (apic = 0; apic < nr_ioapics; apic++) {
1da177e4 1194 spin_lock_irqsave(&ioapic_lock, flags);
1008fddc 1195 reg_01.raw = io_apic_read(apic, 1);
1da177e4 1196 spin_unlock_irqrestore(&ioapic_lock, flags);
1008fddc
EB		 1197 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1198 }
1199 for(apic = 0; apic < nr_ioapics; apic++) {
1200 int pin;
1201 /* See if any of the pins is in ExtINT mode */
1202 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1203 struct IO_APIC_route_entry entry;
eea0e11c 1204 entry = ioapic_read_entry(apic, pin);
1008fddc
EB		 1205
1206 /* If the interrupt line is enabled and in ExtInt mode
1207 * I have found the pin where the i8259 is connected.
1208 */
1209 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1210 ioapic_i8259.apic = apic;
1211 ioapic_i8259.pin = pin;
1212 goto found_i8259;
1213 }
1214 }
1215 }
1216 found_i8259:
1217 /* Look to see what if the MP table has reported the ExtINT */
1218 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1219 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1220 /* Trust the MP table if nothing is setup in the hardware */
1221 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1222 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1223 ioapic_i8259.pin = i8259_pin;
1224 ioapic_i8259.apic = i8259_apic;
1225 }
1226 /* Complain if the MP table and the hardware disagree */
1227 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1228 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1229 {
1230 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1da177e4
LT		 1231 }
1232
1233 /*
1234 * Do not trust the IO-APIC being empty at bootup
1235 */
1236 clear_IO_APIC();
1237}
1238
1239/*
1240 * Not an __init, needed by the reboot code
1241 */
1242void disable_IO_APIC(void)
1243{
1244 /*
1245 * Clear the IO-APIC before rebooting:
1246 */
1247 clear_IO_APIC();
1248
208fb931 1249 /*
0b968d23 1250 * If the i8259 is routed through an IOAPIC
208fb931 1251 * Put that IOAPIC in virtual wire mode
0b968d23 1252 * so legacy interrupts can be delivered.
208fb931 1253 */
1008fddc 1254 if (ioapic_i8259.pin != -1) {
208fb931 1255 struct IO_APIC_route_entry entry;
208fb931
EB		 1256
1257 memset(&entry, 0, sizeof(entry));
1258 entry.mask = 0; /* Enabled */
1259 entry.trigger = 0; /* Edge */
1260 entry.irr = 0;
1261 entry.polarity = 0; /* High */
1262 entry.delivery_status = 0;
1263 entry.dest_mode = 0; /* Physical */
1008fddc 1264 entry.delivery_mode = dest_ExtINT; /* ExtInt */
208fb931 1265 entry.vector = 0;
ee4eff6f 1266 entry.dest = GET_APIC_ID(apic_read(APIC_ID));
208fb931 1267
208fb931
EB		 1268 /*
1269 * Add it to the IO-APIC irq-routing table:
1270 */
eea0e11c 1271 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
208fb931
EB		 1272 }
1273
1008fddc 1274 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1da177e4
LT		 1275}
1276
1da177e4
LT		 1277/*
1278 * There is a nasty bug in some older SMP boards, their mptable lies
1279 * about the timer IRQ. We do the following to work around the situation:
1280 *
1281 * - timer IRQ defaults to IO-APIC IRQ
1282 * - if this function detects that timer IRQs are defunct, then we fall
1283 * back to ISA timer IRQs
1284 */
1285static int __init timer_irq_works(void)
1286{
1287 unsigned long t1 = jiffies;
4aae0702 1288 unsigned long flags;
1da177e4 1289
4aae0702 1290 local_save_flags(flags);
1da177e4
LT		 1291 local_irq_enable();
1292 /* Let ten ticks pass... */
1293 mdelay((10 * 1000) / HZ);
4aae0702 1294 local_irq_restore(flags);
1da177e4
LT		 1295
1296 /*
1297 * Expect a few ticks at least, to be sure some possible
1298 * glue logic does not lock up after one or two first
1299 * ticks in a non-ExtINT mode. Also the local APIC
1300 * might have cached one ExtINT interrupt. Finally, at
1301 * least one tick may be lost due to delays.
1302 */
1303
1304 /* jiffies wrap? */
1d16b53e 1305 if (time_after(jiffies, t1 + 4))
1da177e4
LT		 1306 return 1;
1307 return 0;
1308}
1309
1310/*
1311 * In the SMP+IOAPIC case it might happen that there are an unspecified
1312 * number of pending IRQ events unhandled. These cases are very rare,
1313 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1314 * better to do it this way as thus we do not have to be aware of
1315 * 'pending' interrupts in the IRQ path, except at this point.
1316 */
1317/*
1318 * Edge triggered needs to resend any interrupt
1319 * that was delayed but this is now handled in the device
1320 * independent code.
1321 */
1322
1323/*
1324 * Starting up a edge-triggered IO-APIC interrupt is
1325 * nasty - we need to make sure that we get the edge.
1326 * If it is already asserted for some reason, we need
1327 * return 1 to indicate that is was pending.
1328 *
1329 * This is not complete - we should be able to fake
1330 * an edge even if it isn't on the 8259A...
1331 */
1332
f29bd1ba 1333static unsigned int startup_ioapic_irq(unsigned int irq)
1da177e4
LT		 1334{
1335 int was_pending = 0;
1336 unsigned long flags;
1337
1338 spin_lock_irqsave(&ioapic_lock, flags);
1339 if (irq < 16) {
1340 disable_8259A_irq(irq);
1341 if (i8259A_irq_pending(irq))
1342 was_pending = 1;
1343 }
1344 __unmask_IO_APIC_irq(irq);
1345 spin_unlock_irqrestore(&ioapic_lock, flags);
1346
1347 return was_pending;
1348}
1349
04b9267b 1350static int ioapic_retrigger_irq(unsigned int irq)
c0ad90a3 1351{
13a79503 1352 struct irq_cfg *cfg = &irq_cfg[irq];
550f2299 1353 cpumask_t mask;
6bf2dafa 1354 unsigned long flags;
550f2299 1355
6bf2dafa 1356 spin_lock_irqsave(&vector_lock, flags);
550f2299 1357 cpus_clear(mask);
13a79503 1358 cpu_set(first_cpu(cfg->domain), mask);
550f2299 1359
13a79503 1360 send_IPI_mask(mask, cfg->vector);
6bf2dafa 1361 spin_unlock_irqrestore(&vector_lock, flags);
c0ad90a3
IM		 1362
1363 return 1;
1364}
1365
1da177e4
LT		 1366/*
1367 * Level and edge triggered IO-APIC interrupts need different handling,
1368 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1369 * handled with the level-triggered descriptor, but that one has slightly
1370 * more overhead. Level-triggered interrupts cannot be handled with the
1371 * edge-triggered handler, without risking IRQ storms and other ugly
1372 * races.
1373 */
1374
61014292
EB		 1375#ifdef CONFIG_SMP
1376asmlinkage void smp_irq_move_cleanup_interrupt(void)
1377{
1378 unsigned vector, me;
1379 ack_APIC_irq();
1380 exit_idle();
1381 irq_enter();
1382
1383 me = smp_processor_id();
1384 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
1385 unsigned int irq;
1386 struct irq_desc *desc;
1387 struct irq_cfg *cfg;
1388 irq = __get_cpu_var(vector_irq)[vector];
1389 if (irq >= NR_IRQS)
1390 continue;
1391
1392 desc = irq_desc + irq;
1393 cfg = irq_cfg + irq;
1394 spin_lock(&desc->lock);
1395 if (!cfg->move_cleanup_count)
1396 goto unlock;
1397
1398 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
1399 goto unlock;
1400
1401 __get_cpu_var(vector_irq)[vector] = -1;
1402 cfg->move_cleanup_count--;
1403unlock:
1404 spin_unlock(&desc->lock);
1405 }
1406
1407 irq_exit();
1408}
1409
1410static void irq_complete_move(unsigned int irq)
1411{
1412 struct irq_cfg *cfg = irq_cfg + irq;
1413 unsigned vector, me;
1414
1415 if (likely(!cfg->move_in_progress))
1416 return;
1417
65ea5b03 1418 vector = ~get_irq_regs()->orig_ax;
61014292 1419 me = smp_processor_id();
f0e13ae7 1420 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
61014292
EB		 1421 cpumask_t cleanup_mask;
1422
1423 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
1424 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
1425 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
1426 cfg->move_in_progress = 0;
1427 }
1428}
1429#else
1430static inline void irq_complete_move(unsigned int irq) {}
1431#endif
1432
0be6652f
EB		 1433static void ack_apic_edge(unsigned int irq)
1434{
61014292 1435 irq_complete_move(irq);
0be6652f
EB		 1436 move_native_irq(irq);
1437 ack_APIC_irq();
1438}
1439
1440static void ack_apic_level(unsigned int irq)
1441{
1442 int do_unmask_irq = 0;
1443
61014292 1444 irq_complete_move(irq);
52e3d90d 1445#ifdef CONFIG_GENERIC_PENDING_IRQ
0be6652f
EB		 1446 /* If we are moving the irq we need to mask it */
1447 if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1448 do_unmask_irq = 1;
1449 mask_IO_APIC_irq(irq);
1450 }
1451#endif
1452
1453 /*
1454 * We must acknowledge the irq before we move it or the acknowledge will
beb7dd86 1455 * not propagate properly.
0be6652f
EB		 1456 */
1457 ack_APIC_irq();
1458
1459 /* Now we can move and renable the irq */
ef3e28c5
EB		 1460 if (unlikely(do_unmask_irq)) {
1461 /* Only migrate the irq if the ack has been received.
1462 *
1463 * On rare occasions the broadcast level triggered ack gets
1464 * delayed going to ioapics, and if we reprogram the
1465 * vector while Remote IRR is still set the irq will never
1466 * fire again.
1467 *
1468 * To prevent this scenario we read the Remote IRR bit
1469 * of the ioapic. This has two effects.
1470 * - On any sane system the read of the ioapic will
1471 * flush writes (and acks) going to the ioapic from
1472 * this cpu.
1473 * - We get to see if the ACK has actually been delivered.
1474 *
1475 * Based on failed experiments of reprogramming the
1476 * ioapic entry from outside of irq context starting
1477 * with masking the ioapic entry and then polling until
1478 * Remote IRR was clear before reprogramming the
1479 * ioapic I don't trust the Remote IRR bit to be
1480 * completey accurate.
1481 *
1482 * However there appears to be no other way to plug
1483 * this race, so if the Remote IRR bit is not
1484 * accurate and is causing problems then it is a hardware bug
1485 * and you can go talk to the chipset vendor about it.
1486 */
1487 if (!io_apic_level_ack_pending(irq))
1488 move_masked_irq(irq);
0be6652f 1489 unmask_IO_APIC_irq(irq);
ef3e28c5 1490 }
0be6652f
EB		 1491}
1492
f29bd1ba
IM		 1493static struct irq_chip ioapic_chip __read_mostly = {
1494 .name = "IO-APIC",
04b9267b
EB		 1495 .startup = startup_ioapic_irq,
1496 .mask = mask_IO_APIC_irq,
1497 .unmask = unmask_IO_APIC_irq,
0be6652f
EB		 1498 .ack = ack_apic_edge,
1499 .eoi = ack_apic_level,
54d5d424 1500#ifdef CONFIG_SMP
04b9267b 1501 .set_affinity = set_ioapic_affinity_irq,
54d5d424 1502#endif
04b9267b 1503 .retrigger = ioapic_retrigger_irq,
1da177e4
LT		 1504};
1505
1506static inline void init_IO_APIC_traps(void)
1507{
1508 int irq;
1509
1510 /*
1511 * NOTE! The local APIC isn't very good at handling
1512 * multiple interrupts at the same interrupt level.
1513 * As the interrupt level is determined by taking the
1514 * vector number and shifting that right by 4, we
1515 * want to spread these out a bit so that they don't
1516 * all fall in the same interrupt level.
1517 *
1518 * Also, we've got to be careful not to trash gate
1519 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1520 */
1521 for (irq = 0; irq < NR_IRQS ; irq++) {
1522 int tmp = irq;
13a79503 1523 if (IO_APIC_IRQ(tmp) && !irq_cfg[tmp].vector) {
1da177e4
LT		 1524 /*
1525 * Hmm.. We don't have an entry for this,
1526 * so default to an old-fashioned 8259
1527 * interrupt if we can..
1528 */
1529 if (irq < 16)
1530 make_8259A_irq(irq);
1531 else
1532 /* Strange. Oh, well.. */
f29bd1ba 1533 irq_desc[irq].chip = &no_irq_chip;
1da177e4
LT		 1534 }
1535 }
1536}
1537
1538static void enable_lapic_irq (unsigned int irq)
1539{
1540 unsigned long v;
1541
1542 v = apic_read(APIC_LVT0);
11a8e778 1543 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1da177e4
LT		 1544}
1545
1546static void disable_lapic_irq (unsigned int irq)
1547{
1548 unsigned long v;
1549
1550 v = apic_read(APIC_LVT0);
11a8e778 1551 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1da177e4
LT		 1552}
1553
1554static void ack_lapic_irq (unsigned int irq)
1555{
1556 ack_APIC_irq();
1557}
1558
1559static void end_lapic_irq (unsigned int i) { /* nothing */ }
1560
6c231b7b 1561static struct hw_interrupt_type lapic_irq_type __read_mostly = {
c47e285d 1562 .name = "local-APIC",
1da177e4
LT		 1563 .typename = "local-APIC-edge",
1564 .startup = NULL, /* startup_irq() not used for IRQ0 */
1565 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1566 .enable = enable_lapic_irq,
1567 .disable = disable_lapic_irq,
1568 .ack = ack_lapic_irq,
1569 .end = end_lapic_irq,
1570};
1571
e9427101 1572static void __init setup_nmi(void)
1da177e4
LT		 1573{
1574 /*
1575 * Dirty trick to enable the NMI watchdog ...
1576 * We put the 8259A master into AEOI mode and
1577 * unmask on all local APICs LVT0 as NMI.
1578 *
1579 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1580 * is from Maciej W. Rozycki - so we do not have to EOI from
1581 * the NMI handler or the timer interrupt.
1582 */
1583 printk(KERN_INFO "activating NMI Watchdog ...");
1584
e9427101 1585 enable_NMI_through_LVT0();
1da177e4
LT		 1586
1587 printk(" done.\n");
1588}
1589
1590/*
1591 * This looks a bit hackish but it's about the only one way of sending
1592 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1593 * not support the ExtINT mode, unfortunately. We need to send these
1594 * cycles as some i82489DX-based boards have glue logic that keeps the
1595 * 8259A interrupt line asserted until INTA. --macro
1596 */
1597static inline void unlock_ExtINT_logic(void)
1598{
1008fddc 1599 int apic, pin, i;
1da177e4
LT		 1600 struct IO_APIC_route_entry entry0, entry1;
1601 unsigned char save_control, save_freq_select;
1602 unsigned long flags;
1603
1008fddc
EB		 1604 pin = find_isa_irq_pin(8, mp_INT);
1605 apic = find_isa_irq_apic(8, mp_INT);
1da177e4
LT		 1606 if (pin == -1)
1607 return;
1608
1609 spin_lock_irqsave(&ioapic_lock, flags);
1008fddc
EB		 1610 *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1611 *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1da177e4 1612 spin_unlock_irqrestore(&ioapic_lock, flags);
1008fddc 1613 clear_IO_APIC_pin(apic, pin);
1da177e4
LT		 1614
1615 memset(&entry1, 0, sizeof(entry1));
1616
1617 entry1.dest_mode = 0; /* physical delivery */
1618 entry1.mask = 0; /* unmask IRQ now */
ee4eff6f 1619 entry1.dest = hard_smp_processor_id();
1da177e4
LT		 1620 entry1.delivery_mode = dest_ExtINT;
1621 entry1.polarity = entry0.polarity;
1622 entry1.trigger = 0;
1623 entry1.vector = 0;
1624
1625 spin_lock_irqsave(&ioapic_lock, flags);
1008fddc
EB		 1626 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1627 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1da177e4
LT		 1628 spin_unlock_irqrestore(&ioapic_lock, flags);
1629
1630 save_control = CMOS_READ(RTC_CONTROL);
1631 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1632 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1633 RTC_FREQ_SELECT);
1634 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1635
1636 i = 100;
1637 while (i-- > 0) {
1638 mdelay(10);
1639 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1640 i -= 10;
1641 }
1642
1643 CMOS_WRITE(save_control, RTC_CONTROL);
1644 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1008fddc 1645 clear_IO_APIC_pin(apic, pin);
1da177e4
LT		 1646
1647 spin_lock_irqsave(&ioapic_lock, flags);
1008fddc
EB		 1648 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1649 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1da177e4
LT		 1650 spin_unlock_irqrestore(&ioapic_lock, flags);
1651}
1652
1653/*
1654 * This code may look a bit paranoid, but it's supposed to cooperate with
1655 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1656 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1657 * fanatically on his truly buggy board.
fea5f1e1
LT		 1658 *
1659 * FIXME: really need to revamp this for modern platforms only.
1da177e4 1660 */
e9427101 1661static inline void __init check_timer(void)
1da177e4 1662{
dfbffdd8 1663 struct irq_cfg *cfg = irq_cfg + 0;
1008fddc 1664 int apic1, pin1, apic2, pin2;
4aae0702
IM		 1665 unsigned long flags;
1666
1667 local_irq_save(flags);
1da177e4
LT		 1668
1669 /*
1670 * get/set the timer IRQ vector:
1671 */
1672 disable_8259A_irq(0);
dfbffdd8 1673 assign_irq_vector(0, TARGET_CPUS);
1da177e4
LT		 1674
1675 /*
1676 * Subtle, code in do_timer_interrupt() expects an AEOI
1677 * mode for the 8259A whenever interrupts are routed
1678 * through I/O APICs. Also IRQ0 has to be enabled in
1679 * the 8259A which implies the virtual wire has to be
1680 * disabled in the local APIC.
1681 */
11a8e778 1682 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1da177e4 1683 init_8259A(1);
fea5f1e1
LT		 1684 if (timer_over_8254 > 0)
1685 enable_8259A_irq(0);
1da177e4 1686
1008fddc
EB		 1687 pin1 = find_isa_irq_pin(0, mp_INT);
1688 apic1 = find_isa_irq_apic(0, mp_INT);
1689 pin2 = ioapic_i8259.pin;
1690 apic2 = ioapic_i8259.apic;
1da177e4 1691
fea5f1e1 1692 apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
dfbffdd8 1693 cfg->vector, apic1, pin1, apic2, pin2);
b0268726 1694
fea5f1e1
LT		 1695 if (pin1 != -1) {
1696 /*
1697 * Ok, does IRQ0 through the IOAPIC work?
1698 */
1699 unmask_IO_APIC_irq(0);
1700 if (!no_timer_check && timer_irq_works()) {
1701 nmi_watchdog_default();
1702 if (nmi_watchdog == NMI_IO_APIC) {
1703 disable_8259A_irq(0);
1704 setup_nmi();
1705 enable_8259A_irq(0);
1706 }
1707 if (disable_timer_pin_1 > 0)
1708 clear_IO_APIC_pin(0, pin1);
4aae0702 1709 goto out;
fea5f1e1
LT		 1710 }
1711 clear_IO_APIC_pin(apic1, pin1);
1712 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1713 "connected to IO-APIC\n");
1714 }
1da177e4 1715
fea5f1e1
LT		 1716 apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1717 "through the 8259A ... ");
1da177e4 1718 if (pin2 != -1) {
fea5f1e1
LT		 1719 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1720 apic2, pin2);
1721 /*
1722 * legacy devices should be connected to IO APIC #0
1723 */
dfbffdd8 1724 setup_ExtINT_IRQ0_pin(apic2, pin2, cfg->vector);
fea5f1e1
LT		 1725 if (timer_irq_works()) {
1726 apic_printk(APIC_VERBOSE," works.\n");
1727 nmi_watchdog_default();
1728 if (nmi_watchdog == NMI_IO_APIC) {
1729 setup_nmi();
1730 }
4aae0702 1731 goto out;
fea5f1e1
LT		 1732 }
1733 /*
1734 * Cleanup, just in case ...
1735 */
1736 clear_IO_APIC_pin(apic2, pin2);
1da177e4 1737 }
fea5f1e1 1738 apic_printk(APIC_VERBOSE," failed.\n");
1da177e4 1739
1f992153 1740 if (nmi_watchdog == NMI_IO_APIC) {
1da177e4
LT		 1741 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1742 nmi_watchdog = 0;
1743 }
1744
1745 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1746
1747 disable_8259A_irq(0);
d1bef4ed 1748 irq_desc[0].chip = &lapic_irq_type;
dfbffdd8 1749 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
1da177e4
LT		 1750 enable_8259A_irq(0);
1751
1752 if (timer_irq_works()) {
5b922cd4 1753 apic_printk(APIC_VERBOSE," works.\n");
4aae0702 1754 goto out;
1da177e4 1755 }
dfbffdd8 1756 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
1da177e4
LT		 1757 apic_printk(APIC_VERBOSE," failed.\n");
1758
1759 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1760
1761 init_8259A(0);
1762 make_8259A_irq(0);
11a8e778 1763 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1da177e4
LT		 1764
1765 unlock_ExtINT_logic();
1766
1767 if (timer_irq_works()) {
1768 apic_printk(APIC_VERBOSE," works.\n");
4aae0702 1769 goto out;
1da177e4
LT		 1770 }
1771 apic_printk(APIC_VERBOSE," failed :(.\n");
1772 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
4aae0702
IM		 1773out:
1774 local_irq_restore(flags);
1da177e4
LT		 1775}
1776
14d98cad
AK		 1777static int __init notimercheck(char *s)
1778{
1779 no_timer_check = 1;
1780 return 1;
1781}
1782__setup("no_timer_check", notimercheck);
1783
1da177e4
LT		 1784/*
1785 *
676b1855 1786 * IRQs that are handled by the PIC in the MPS IOAPIC case.
1da177e4
LT		 1787 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1788 * Linux doesn't really care, as it's not actually used
1789 * for any interrupt handling anyway.
1790 */
1791#define PIC_IRQS (1<<2)
1792
1793void __init setup_IO_APIC(void)
1794{
1c69524c
YL		 1795
1796 /*
1797 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
1798 */
1da177e4
LT		 1799
1800 if (acpi_ioapic)
1801 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1802 else
1803 io_apic_irqs = ~PIC_IRQS;
1804
1805 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1806
1da177e4
LT		 1807 sync_Arb_IDs();
1808 setup_IO_APIC_irqs();
1809 init_IO_APIC_traps();
1810 check_timer();
1811 if (!acpi_ioapic)
1812 print_IO_APIC();
1813}
1814
1815struct sysfs_ioapic_data {
1816 struct sys_device dev;
1817 struct IO_APIC_route_entry entry[0];
1818};
1819static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1820
0b9c33a7 1821static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1da177e4
LT		 1822{
1823 struct IO_APIC_route_entry *entry;
1824 struct sysfs_ioapic_data *data;
1da177e4
LT		 1825 int i;
1826
1827 data = container_of(dev, struct sysfs_ioapic_data, dev);
1828 entry = data->entry;
eea0e11c
AK		 1829 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1830 *entry = ioapic_read_entry(dev->id, i);
1da177e4
LT		 1831
1832 return 0;
1833}
1834
1835static int ioapic_resume(struct sys_device *dev)
1836{
1837 struct IO_APIC_route_entry *entry;
1838 struct sysfs_ioapic_data *data;
1839 unsigned long flags;
1840 union IO_APIC_reg_00 reg_00;
1841 int i;
1842
1843 data = container_of(dev, struct sysfs_ioapic_data, dev);
1844 entry = data->entry;
1845
1846 spin_lock_irqsave(&ioapic_lock, flags);
1847 reg_00.raw = io_apic_read(dev->id, 0);
1848 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1849 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1850 io_apic_write(dev->id, 0, reg_00.raw);
1851 }
1da177e4 1852 spin_unlock_irqrestore(&ioapic_lock, flags);
eea0e11c
AK		 1853 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1854 ioapic_write_entry(dev->id, i, entry[i]);
1da177e4
LT		 1855
1856 return 0;
1857}
1858
1859static struct sysdev_class ioapic_sysdev_class = {
af5ca3f4 1860 .name = "ioapic",
1da177e4
LT		 1861 .suspend = ioapic_suspend,
1862 .resume = ioapic_resume,
1863};
1864
1865static int __init ioapic_init_sysfs(void)
1866{
1867 struct sys_device * dev;
cddf7ff7 1868 int i, size, error;
1da177e4
LT		 1869
1870 error = sysdev_class_register(&ioapic_sysdev_class);
1871 if (error)
1872 return error;
1873
1874 for (i = 0; i < nr_ioapics; i++ ) {
1875 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1876 * sizeof(struct IO_APIC_route_entry);
cddf7ff7 1877 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
1da177e4
LT		 1878 if (!mp_ioapic_data[i]) {
1879 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1880 continue;
1881 }
1da177e4
LT		 1882 dev = &mp_ioapic_data[i]->dev;
1883 dev->id = i;
1884 dev->cls = &ioapic_sysdev_class;
1885 error = sysdev_register(dev);
1886 if (error) {
1887 kfree(mp_ioapic_data[i]);
1888 mp_ioapic_data[i] = NULL;
1889 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1890 continue;
1891 }
1892 }
1893
1894 return 0;
1895}
1896
1897device_initcall(ioapic_init_sysfs);
1898
c4fa0bbf 1899/*
04b9267b 1900 * Dynamic irq allocate and deallocation
c4fa0bbf
EB		 1901 */
1902int create_irq(void)
1903{
04b9267b
EB		 1904 /* Allocate an unused irq */
1905 int irq;
1906 int new;
c4fa0bbf 1907 unsigned long flags;
c4fa0bbf 1908
04b9267b
EB		 1909 irq = -ENOSPC;
1910 spin_lock_irqsave(&vector_lock, flags);
1911 for (new = (NR_IRQS - 1); new >= 0; new--) {
1912 if (platform_legacy_irq(new))
1913 continue;
13a79503 1914 if (irq_cfg[new].vector != 0)
04b9267b 1915 continue;
dfbffdd8 1916 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
04b9267b
EB		 1917 irq = new;
1918 break;
1919 }
1920 spin_unlock_irqrestore(&vector_lock, flags);
c4fa0bbf 1921
04b9267b 1922 if (irq >= 0) {
c4fa0bbf
EB		 1923 dynamic_irq_init(irq);
1924 }
1925 return irq;
1926}
1927
1928void destroy_irq(unsigned int irq)
1929{
1930 unsigned long flags;
c4fa0bbf
EB		 1931
1932 dynamic_irq_cleanup(irq);
1933
1934 spin_lock_irqsave(&vector_lock, flags);
5df0287e 1935 __clear_irq_vector(irq);
c4fa0bbf
EB		 1936 spin_unlock_irqrestore(&vector_lock, flags);
1937}
c4fa0bbf 1938
589e367f 1939/*
676b1855 1940 * MSI message composition
589e367f
EB		 1941 */
1942#ifdef CONFIG_PCI_MSI
3b7d1921 1943static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
589e367f 1944{
dfbffdd8
EB		 1945 struct irq_cfg *cfg = irq_cfg + irq;
1946 int err;
589e367f 1947 unsigned dest;
c7111c13 1948 cpumask_t tmp;
589e367f 1949
dfbffdd8
EB		 1950 tmp = TARGET_CPUS;
1951 err = assign_irq_vector(irq, tmp);
1952 if (!err) {
1953 cpus_and(tmp, cfg->domain, tmp);
589e367f
EB		 1954 dest = cpu_mask_to_apicid(tmp);
1955
1956 msg->address_hi = MSI_ADDR_BASE_HI;
1957 msg->address_lo =
1958 MSI_ADDR_BASE_LO |
1959 ((INT_DEST_MODE == 0) ?
1960 MSI_ADDR_DEST_MODE_PHYSICAL:
1961 MSI_ADDR_DEST_MODE_LOGICAL) |
1962 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1963 MSI_ADDR_REDIRECTION_CPU:
1964 MSI_ADDR_REDIRECTION_LOWPRI) |
1965 MSI_ADDR_DEST_ID(dest);
1966
1967 msg->data =
1968 MSI_DATA_TRIGGER_EDGE |
1969 MSI_DATA_LEVEL_ASSERT |
1970 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1971 MSI_DATA_DELIVERY_FIXED:
1972 MSI_DATA_DELIVERY_LOWPRI) |
dfbffdd8 1973 MSI_DATA_VECTOR(cfg->vector);
589e367f 1974 }
dfbffdd8 1975 return err;
589e367f
EB		 1976}
1977
3b7d1921
EB		 1978#ifdef CONFIG_SMP
1979static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
589e367f 1980{
dfbffdd8 1981 struct irq_cfg *cfg = irq_cfg + irq;
3b7d1921
EB		 1982 struct msi_msg msg;
1983 unsigned int dest;
1984 cpumask_t tmp;
3b7d1921
EB		 1985
1986 cpus_and(tmp, mask, cpu_online_map);
1987 if (cpus_empty(tmp))
5ff5115e 1988 return;
589e367f 1989
dfbffdd8 1990 if (assign_irq_vector(irq, mask))
3b7d1921 1991 return;
550f2299 1992
dfbffdd8 1993 cpus_and(tmp, cfg->domain, mask);
3b7d1921 1994 dest = cpu_mask_to_apicid(tmp);
589e367f 1995
3b7d1921
EB		 1996 read_msi_msg(irq, &msg);
1997
1998 msg.data &= ~MSI_DATA_VECTOR_MASK;
dfbffdd8 1999 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3b7d1921
EB		 2000 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2001 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2002
2003 write_msi_msg(irq, &msg);
9f0a5ba5 2004 irq_desc[irq].affinity = mask;
589e367f 2005}
3b7d1921 2006#endif /* CONFIG_SMP */
589e367f 2007
3b7d1921
EB		 2008/*
2009 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2010 * which implement the MSI or MSI-X Capability Structure.
2011 */
2012static struct irq_chip msi_chip = {
2013 .name = "PCI-MSI",
2014 .unmask = unmask_msi_irq,
2015 .mask = mask_msi_irq,
2016 .ack = ack_apic_edge,
2017#ifdef CONFIG_SMP
2018 .set_affinity = set_msi_irq_affinity,
2019#endif
2020 .retrigger = ioapic_retrigger_irq,
589e367f
EB		 2021};
2022
f7feaca7 2023int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
3b7d1921
EB		 2024{
2025 struct msi_msg msg;
f7feaca7
EB		 2026 int irq, ret;
2027 irq = create_irq();
2028 if (irq < 0)
2029 return irq;
2030
3b7d1921 2031 ret = msi_compose_msg(dev, irq, &msg);
f7feaca7
EB		 2032 if (ret < 0) {
2033 destroy_irq(irq);
3b7d1921 2034 return ret;
f7feaca7 2035 }
3b7d1921 2036
7fe3730d 2037 set_irq_msi(irq, desc);
3b7d1921
EB		 2038 write_msi_msg(irq, &msg);
2039
a460e745 2040 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3b7d1921 2041
7fe3730d 2042 return 0;
3b7d1921
EB		 2043}
2044
2045void arch_teardown_msi_irq(unsigned int irq)
2046{
f7feaca7 2047 destroy_irq(irq);
3b7d1921
EB		 2048}
2049
3460a6d9
KA		 2050#ifdef CONFIG_DMAR
2051#ifdef CONFIG_SMP
2052static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask)
2053{
2054 struct irq_cfg *cfg = irq_cfg + irq;
2055 struct msi_msg msg;
2056 unsigned int dest;
2057 cpumask_t tmp;
2058
2059 cpus_and(tmp, mask, cpu_online_map);
2060 if (cpus_empty(tmp))
2061 return;
2062
2063 if (assign_irq_vector(irq, mask))
2064 return;
2065
2066 cpus_and(tmp, cfg->domain, mask);
2067 dest = cpu_mask_to_apicid(tmp);
2068
2069 dmar_msi_read(irq, &msg);
2070
2071 msg.data &= ~MSI_DATA_VECTOR_MASK;
2072 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2073 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2074 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2075
2076 dmar_msi_write(irq, &msg);
2077 irq_desc[irq].affinity = mask;
2078}
2079#endif /* CONFIG_SMP */
2080
2081struct irq_chip dmar_msi_type = {
2082 .name = "DMAR_MSI",
2083 .unmask = dmar_msi_unmask,
2084 .mask = dmar_msi_mask,
2085 .ack = ack_apic_edge,
2086#ifdef CONFIG_SMP
2087 .set_affinity = dmar_msi_set_affinity,
2088#endif
2089 .retrigger = ioapic_retrigger_irq,
2090};
2091
2092int arch_setup_dmar_msi(unsigned int irq)
2093{
2094 int ret;
2095 struct msi_msg msg;
2096
2097 ret = msi_compose_msg(NULL, irq, &msg);
2098 if (ret < 0)
2099 return ret;
2100 dmar_msi_write(irq, &msg);
2101 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
2102 "edge");
2103 return 0;
2104}
2105#endif
589e367f 2106
3460a6d9 2107#endif /* CONFIG_PCI_MSI */
8b955b0d
EB		 2108/*
2109 * Hypertransport interrupt support
2110 */
2111#ifdef CONFIG_HT_IRQ
2112
2113#ifdef CONFIG_SMP
2114
2115static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
2116{
ec68307c
EB		 2117 struct ht_irq_msg msg;
2118 fetch_ht_irq_msg(irq, &msg);
8b955b0d 2119
ec68307c
EB		 2120 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
2121 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
8b955b0d 2122
ec68307c
EB		 2123 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
2124 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
8b955b0d 2125
ec68307c 2126 write_ht_irq_msg(irq, &msg);
8b955b0d
EB		 2127}
2128
2129static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2130{
dfbffdd8 2131 struct irq_cfg *cfg = irq_cfg + irq;
8b955b0d
EB		 2132 unsigned int dest;
2133 cpumask_t tmp;
8b955b0d
EB		 2134
2135 cpus_and(tmp, mask, cpu_online_map);
2136 if (cpus_empty(tmp))
5ff5115e 2137 return;
8b955b0d 2138
dfbffdd8 2139 if (assign_irq_vector(irq, mask))
8b955b0d
EB		 2140 return;
2141
dfbffdd8 2142 cpus_and(tmp, cfg->domain, mask);
8b955b0d
EB		 2143 dest = cpu_mask_to_apicid(tmp);
2144
dfbffdd8 2145 target_ht_irq(irq, dest, cfg->vector);
9f0a5ba5 2146 irq_desc[irq].affinity = mask;
8b955b0d
EB		 2147}
2148#endif
2149
c37e108d 2150static struct irq_chip ht_irq_chip = {
8b955b0d
EB		 2151 .name = "PCI-HT",
2152 .mask = mask_ht_irq,
2153 .unmask = unmask_ht_irq,
2154 .ack = ack_apic_edge,
2155#ifdef CONFIG_SMP
2156 .set_affinity = set_ht_irq_affinity,
2157#endif
2158 .retrigger = ioapic_retrigger_irq,
2159};
2160
2161int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2162{
dfbffdd8
EB		 2163 struct irq_cfg *cfg = irq_cfg + irq;
2164 int err;
c7111c13 2165 cpumask_t tmp;
8b955b0d 2166
dfbffdd8
EB		 2167 tmp = TARGET_CPUS;
2168 err = assign_irq_vector(irq, tmp);
2169 if (!err) {
ec68307c 2170 struct ht_irq_msg msg;
8b955b0d 2171 unsigned dest;
8b955b0d 2172
dfbffdd8 2173 cpus_and(tmp, cfg->domain, tmp);
8b955b0d
EB		 2174 dest = cpu_mask_to_apicid(tmp);
2175
ec68307c 2176 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
8b955b0d 2177
ec68307c
EB		 2178 msg.address_lo =
2179 HT_IRQ_LOW_BASE |
8b955b0d 2180 HT_IRQ_LOW_DEST_ID(dest) |
dfbffdd8 2181 HT_IRQ_LOW_VECTOR(cfg->vector) |
8b955b0d
EB		 2182 ((INT_DEST_MODE == 0) ?
2183 HT_IRQ_LOW_DM_PHYSICAL :
2184 HT_IRQ_LOW_DM_LOGICAL) |
2185 HT_IRQ_LOW_RQEOI_EDGE |
2186 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2187 HT_IRQ_LOW_MT_FIXED :
ec68307c
EB		 2188 HT_IRQ_LOW_MT_ARBITRATED) |
2189 HT_IRQ_LOW_IRQ_MASKED;
8b955b0d 2190
ec68307c 2191 write_ht_irq_msg(irq, &msg);
8b955b0d 2192
a460e745
IM		 2193 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2194 handle_edge_irq, "edge");
8b955b0d 2195 }
dfbffdd8 2196 return err;
8b955b0d
EB		 2197}
2198#endif /* CONFIG_HT_IRQ */
2199
1da177e4
LT		 2200/* --------------------------------------------------------------------------
2201 ACPI-based IOAPIC Configuration
2202 -------------------------------------------------------------------------- */
2203
888ba6c6 2204#ifdef CONFIG_ACPI
1da177e4
LT		 2205
2206#define IO_APIC_MAX_ID 0xFE
2207
1da177e4
LT		 2208int __init io_apic_get_redir_entries (int ioapic)
2209{
2210 union IO_APIC_reg_01 reg_01;
2211 unsigned long flags;
2212
2213 spin_lock_irqsave(&ioapic_lock, flags);
2214 reg_01.raw = io_apic_read(ioapic, 1);
2215 spin_unlock_irqrestore(&ioapic_lock, flags);
2216
2217 return reg_01.bits.entries;
2218}
2219
2220
50eca3eb 2221int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
1da177e4 2222{
1da177e4
LT		 2223 if (!IO_APIC_IRQ(irq)) {
2224 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2225 ioapic);
2226 return -EINVAL;
2227 }
2228
550f2299
EB		 2229 /*
2230 * IRQs < 16 are already in the irq_2_pin[] map
2231 */
2232 if (irq >= 16)
2233 add_pin_to_irq(irq, ioapic, pin);
2234
a8c8a367 2235 setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
1da177e4
LT		 2236
2237 return 0;
2238}
2239
1da177e4 2240
61fd47e0
SL		 2241int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
2242{
2243 int i;
2244
2245 if (skip_ioapic_setup)
2246 return -1;
2247
2248 for (i = 0; i < mp_irq_entries; i++)
2249 if (mp_irqs[i].mpc_irqtype == mp_INT &&
2250 mp_irqs[i].mpc_srcbusirq == bus_irq)
2251 break;
2252 if (i >= mp_irq_entries)
2253 return -1;
2254
2255 *trigger = irq_trigger(i);
2256 *polarity = irq_polarity(i);
2257 return 0;
2258}
2259
2260#endif /* CONFIG_ACPI */
1da177e4
LT		 2261
2262/*
2263 * This function currently is only a helper for the i386 smp boot process where
2264 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2265 * so mask in all cases should simply be TARGET_CPUS
2266 */
54d5d424 2267#ifdef CONFIG_SMP
1da177e4
LT		 2268void __init setup_ioapic_dest(void)
2269{
2270 int pin, ioapic, irq, irq_entry;
2271
2272 if (skip_ioapic_setup == 1)
2273 return;
2274
2275 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2276 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2277 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2278 if (irq_entry == -1)
2279 continue;
2280 irq = pin_2_irq(irq_entry, ioapic, pin);
ad892f5e
YL		 2281
2282 /* setup_IO_APIC_irqs could fail to get vector for some device
2283 * when you have too many devices, because at that time only boot
2284 * cpu is online.
2285 */
13a79503 2286 if (!irq_cfg[irq].vector)
a8c8a367
EB		 2287 setup_IO_APIC_irq(ioapic, pin, irq,
2288 irq_trigger(irq_entry),
2289 irq_polarity(irq_entry));
ad892f5e
YL		 2290 else
2291 set_ioapic_affinity_irq(irq, TARGET_CPUS);
1da177e4
LT		 2292 }
2293
2294 }
2295}
54d5d424 2296#endif
61fd47e0 2297
3e35a0e5
TG		 2298#define IOAPIC_RESOURCE_NAME_SIZE 11
2299
2300static struct resource *ioapic_resources;
2301
2302static struct resource * __init ioapic_setup_resources(void)
2303{
2304 unsigned long n;
2305 struct resource *res;
2306 char *mem;
2307 int i;
2308
2309 if (nr_ioapics <= 0)
2310 return NULL;
2311
2312 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
2313 n *= nr_ioapics;
2314
2315 mem = alloc_bootmem(n);
2316 res = (void *)mem;
2317
2318 if (mem != NULL) {
2319 memset(mem, 0, n);
2320 mem += sizeof(struct resource) * nr_ioapics;
2321
2322 for (i = 0; i < nr_ioapics; i++) {
2323 res[i].name = mem;
2324 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
2325 sprintf(mem, "IOAPIC %u", i);
2326 mem += IOAPIC_RESOURCE_NAME_SIZE;
2327 }
2328 }
2329
2330 ioapic_resources = res;
2331
2332 return res;
2333}
2334
2335void __init ioapic_init_mappings(void)
2336{
2337 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2338 struct resource *ioapic_res;
2339 int i;
2340
2341 ioapic_res = ioapic_setup_resources();
2342 for (i = 0; i < nr_ioapics; i++) {
2343 if (smp_found_config) {
2344 ioapic_phys = mp_ioapics[i].mpc_apicaddr;
2345 } else {
2346 ioapic_phys = (unsigned long)
2347 alloc_bootmem_pages(PAGE_SIZE);
2348 ioapic_phys = __pa(ioapic_phys);
2349 }
2350 set_fixmap_nocache(idx, ioapic_phys);
2351 apic_printk(APIC_VERBOSE,
2352 "mapped IOAPIC to %016lx (%016lx)\n",
2353 __fix_to_virt(idx), ioapic_phys);
2354 idx++;
2355
2356 if (ioapic_res != NULL) {
2357 ioapic_res->start = ioapic_phys;
2358 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
2359 ioapic_res++;
2360 }
2361 }
2362}
2363
2364static int __init ioapic_insert_resources(void)
2365{
2366 int i;
2367 struct resource *r = ioapic_resources;
2368
2369 if (!r) {
2370 printk(KERN_ERR
2371 "IO APIC resources could be not be allocated.\n");
2372 return -1;
2373 }
2374
2375 for (i = 0; i < nr_ioapics; i++) {
2376 insert_resource(&iomem_resource, r);
2377 r++;
2378 }
2379
2380 return 0;
2381}
2382
2383/* Insert the IO APIC resources after PCI initialization has occured to handle
2384 * IO APICS that are mapped in on a BAR in PCI space. */
2385late_initcall(ioapic_insert_resources);
2386
Linux kernel - Deliverables
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