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x86: remove ioapic_force
[deliverable/linux.git] / arch / x86 / kernel / io_apic_64.c
CommitLineData
1da177e4
LT		 1/*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23#include <linux/mm.h>
1da177e4
LT		 24#include <linux/interrupt.h>
25#include <linux/init.h>
26#include <linux/delay.h>
27#include <linux/sched.h>
589e367f 28#include <linux/pci.h>
1da177e4 29#include <linux/mc146818rtc.h>
d4057bdb 30#include <linux/compiler.h>
1da177e4 31#include <linux/acpi.h>
d4057bdb 32#include <linux/module.h>
1da177e4 33#include <linux/sysdev.h>
3b7d1921 34#include <linux/msi.h>
95d77884 35#include <linux/htirq.h>
d4057bdb
YL		 36#include <linux/freezer.h>
37#include <linux/kthread.h>
38#include <linux/jiffies.h> /* time_after() */
ab688059
AK		 39#ifdef CONFIG_ACPI
40#include <acpi/acpi_bus.h>
41#endif
3e35a0e5 42#include <linux/bootmem.h>
89027d35 43#include <linux/dmar.h>
1da177e4 44
61014292 45#include <asm/idle.h>
1da177e4
LT		 46#include <asm/io.h>
47#include <asm/smp.h>
48#include <asm/desc.h>
49#include <asm/proto.h>
8d916406 50#include <asm/acpi.h>
ca8642f6 51#include <asm/dma.h>
d4057bdb 52#include <asm/timer.h>
17c44697 53#include <asm/i8259.h>
3e4ff115 54#include <asm/nmi.h>
589e367f 55#include <asm/msidef.h>
8b955b0d 56#include <asm/hypertransport.h>
d4057bdb 57#include <asm/setup.h>
89027d35 58#include <asm/irq_remapping.h>
1da177e4 59
5af5573e 60#include <mach_ipi.h>
dd46e3ca 61#include <mach_apic.h>
d4057bdb 62#include <mach_apicdef.h>
5af5573e 63
32f71aff
MR		 64#define __apicdebuginit(type) static type __init
65
f876d213
YL		 66/*
67 * Is the SiS APIC rmw bug present ?
68 * -1 = don't know, 0 = no, 1 = yes
69 */
70int sis_apic_bug = -1;
efa2559f
YL		 71
72static DEFINE_SPINLOCK(ioapic_lock);
73static DEFINE_SPINLOCK(vector_lock);
74
75int first_free_entry;
76/*
77 * Rough estimation of how many shared IRQs there are, can
78 * be changed anytime.
79 */
80int pin_map_size;
81
82/*
83 * # of IRQ routing registers
84 */
85int nr_ioapic_registers[MAX_IO_APICS];
86
87/* I/O APIC entries */
88struct mp_config_ioapic mp_ioapics[MAX_IO_APICS];
89int nr_ioapics;
90
91/* MP IRQ source entries */
92struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
93
94/* # of MP IRQ source entries */
95int mp_irq_entries;
96
97DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
98
99int skip_ioapic_setup;
100
101static int __init parse_noapic(char *str)
102{
103 disable_ioapic_setup();
104 return 0;
105}
106early_param("noapic", parse_noapic);
107
108
3ac2de48 109struct irq_cfg;
e5a53714 110struct irq_pin_list;
13a79503 111struct irq_cfg {
3ac2de48
YL		 112 unsigned int irq;
113 struct irq_cfg *next;
e5a53714 114 struct irq_pin_list *irq_2_pin;
13a79503 115 cpumask_t domain;
61014292
EB		 116 cpumask_t old_domain;
117 unsigned move_cleanup_count;
13a79503 118 u8 vector;
61014292 119 u8 move_in_progress : 1;
13a79503
EB		 120};
121
122/* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
301e6190 123static struct irq_cfg irq_cfg_legacy[] __initdata = {
3ac2de48
YL		 124 [0] = { .irq = 0, .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
125 [1] = { .irq = 1, .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
126 [2] = { .irq = 2, .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
127 [3] = { .irq = 3, .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
128 [4] = { .irq = 4, .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
129 [5] = { .irq = 5, .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
130 [6] = { .irq = 6, .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
131 [7] = { .irq = 7, .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
132 [8] = { .irq = 8, .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
133 [9] = { .irq = 9, .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
134 [10] = { .irq = 10, .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
135 [11] = { .irq = 11, .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
136 [12] = { .irq = 12, .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
137 [13] = { .irq = 13, .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
138 [14] = { .irq = 14, .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
139 [15] = { .irq = 15, .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
13a79503
EB		 140};
141
3ac2de48
YL		 142static struct irq_cfg irq_cfg_init = { .irq = -1U, };
143/* need to be biger than size of irq_cfg_legacy */
144static int nr_irq_cfg = 32;
145
146static int __init parse_nr_irq_cfg(char *arg)
147{
148 if (arg) {
149 nr_irq_cfg = simple_strtoul(arg, NULL, 0);
150 if (nr_irq_cfg < 32)
151 nr_irq_cfg = 32;
152 }
153 return 0;
154}
155
156early_param("nr_irq_cfg", parse_nr_irq_cfg);
157
158static void init_one_irq_cfg(struct irq_cfg *cfg)
159{
160 memcpy(cfg, &irq_cfg_init, sizeof(struct irq_cfg));
161}
301e6190 162
a2f9f438
YL		 163static struct irq_cfg *irq_cfgx;
164static struct irq_cfg *irq_cfgx_free;
301e6190
YL		 165static void __init init_work(void *data)
166{
167 struct dyn_array *da = data;
3ac2de48 168 struct irq_cfg *cfg;
a2f9f438 169 int legacy_count;
3ac2de48 170 int i;
301e6190 171
3ac2de48
YL		 172 cfg = *da->name;
173
174 memcpy(cfg, irq_cfg_legacy, sizeof(irq_cfg_legacy));
175
a2f9f438
YL		 176 legacy_count = sizeof(irq_cfg_legacy)/sizeof(irq_cfg_legacy[0]);
177 for (i = legacy_count; i < *da->nr; i++)
3ac2de48
YL		 178 init_one_irq_cfg(&cfg[i]);
179
180 for (i = 1; i < *da->nr; i++)
181 cfg[i-1].next = &cfg[i];
a2f9f438
YL		 182
183 irq_cfgx_free = &irq_cfgx[legacy_count];
184 irq_cfgx[legacy_count - 1].next = NULL;
301e6190
YL		 185}
186
46b8214d 187#define for_each_irq_cfg(cfg) \
a2f9f438 188 for (cfg = irq_cfgx; cfg; cfg = cfg->next)
46b8214d 189
3ac2de48
YL		 190DEFINE_DYN_ARRAY(irq_cfgx, sizeof(struct irq_cfg), nr_irq_cfg, PAGE_SIZE, init_work);
191
192static struct irq_cfg *irq_cfg(unsigned int irq)
193{
194 struct irq_cfg *cfg;
195
a2f9f438 196 cfg = irq_cfgx;
3ac2de48
YL		 197 while (cfg) {
198 if (cfg->irq == irq)
199 return cfg;
200
3ac2de48
YL		 201 cfg = cfg->next;
202 }
203
204 return NULL;
205}
206
207static struct irq_cfg *irq_cfg_alloc(unsigned int irq)
208{
209 struct irq_cfg *cfg, *cfg_pri;
210 int i;
211 int count = 0;
212
a2f9f438 213 cfg_pri = cfg = irq_cfgx;
3ac2de48
YL		 214 while (cfg) {
215 if (cfg->irq == irq)
216 return cfg;
217
3ac2de48
YL		 218 cfg_pri = cfg;
219 cfg = cfg->next;
220 count++;
221 }
222
a2f9f438
YL		 223 if (!irq_cfgx_free) {
224 unsigned long phys;
225 unsigned long total_bytes;
226 /*
227 * we run out of pre-allocate ones, allocate more
228 */
229 printk(KERN_DEBUG "try to get more irq_cfg %d\n", nr_irq_cfg);
3ac2de48 230
a2f9f438
YL		 231 total_bytes = sizeof(struct irq_cfg) * nr_irq_cfg;
232 if (after_bootmem)
233 cfg = kzalloc(total_bytes, GFP_ATOMIC);
234 else
235 cfg = __alloc_bootmem_nopanic(total_bytes, PAGE_SIZE, 0);
3ac2de48 236
a2f9f438
YL		 237 if (!cfg)
238 panic("please boot with nr_irq_cfg= %d\n", count * 2);
3ac2de48 239
a2f9f438
YL		 240 phys = __pa(cfg);
241 printk(KERN_DEBUG "irq_irq ==> [%#lx - %#lx]\n", phys, phys + total_bytes);
3ac2de48 242
a2f9f438
YL		 243 for (i = 0; i < nr_irq_cfg; i++)
244 init_one_irq_cfg(&cfg[i]);
3ac2de48 245
a2f9f438
YL		 246 for (i = 1; i < nr_irq_cfg; i++)
247 cfg[i-1].next = &cfg[i];
3ac2de48 248
a2f9f438
YL		 249 irq_cfgx_free = cfg;
250 }
251
252 cfg = irq_cfgx_free;
253 irq_cfgx_free = irq_cfgx_free->next;
254 cfg->next = NULL;
255 if (cfg_pri)
256 cfg_pri->next = cfg;
257 else
258 irq_cfgx = cfg;
259 cfg->irq = irq;
260 printk(KERN_DEBUG "found new irq_cfg for irq %d\n", cfg->irq);
261#ifdef CONFIG_HAVE_SPARSE_IRQ_DEBUG
262 {
263 /* dump the results */
264 struct irq_cfg *cfg;
265 unsigned long phys;
266 unsigned long bytes = sizeof(struct irq_cfg);
267
268 printk(KERN_DEBUG "=========================== %d\n", irq);
269 printk(KERN_DEBUG "irq_cfg dump after get that for %d\n", irq);
270 for_each_irq_cfg(cfg) {
271 phys = __pa(cfg);
272 printk(KERN_DEBUG "irq_cfg %d ==> [%#lx - %#lx]\n", cfg->irq, phys, phys + bytes);
273 }
274 printk(KERN_DEBUG "===========================\n");
275 }
276#endif
3ac2de48
YL		 277 return cfg;
278}
301e6190 279
1da177e4
LT		 280/*
281 * This is performance-critical, we want to do it O(1)
282 *
283 * the indexing order of this array favors 1:1 mappings
284 * between pins and IRQs.
285 */
286
e5a53714
YL		 287struct irq_pin_list {
288 int apic, pin;
289 struct irq_pin_list *next;
290};
291
292static struct irq_pin_list *irq_2_pin_head;
293/* fill one page ? */
294static int nr_irq_2_pin = 0x100;
295static struct irq_pin_list *irq_2_pin_ptr;
296static void __init irq_2_pin_init_work(void *data)
297{
298 struct dyn_array *da = data;
299 struct irq_pin_list *pin;
300 int i;
301
302 pin = *da->name;
303
304 for (i = 1; i < *da->nr; i++)
305 pin[i-1].next = &pin[i];
306
307 irq_2_pin_ptr = &pin[0];
308}
309DEFINE_DYN_ARRAY(irq_2_pin_head, sizeof(struct irq_pin_list), nr_irq_2_pin, PAGE_SIZE, irq_2_pin_init_work);
310
311static struct irq_pin_list *get_one_free_irq_2_pin(void)
312{
313 struct irq_pin_list *pin;
314 int i;
315
316 pin = irq_2_pin_ptr;
317
318 if (pin) {
319 irq_2_pin_ptr = pin->next;
320 pin->next = NULL;
321 return pin;
322 }
323
324 /*
325 * we run out of pre-allocate ones, allocate more
326 */
327 printk(KERN_DEBUG "try to get more irq_2_pin %d\n", nr_irq_2_pin);
328
329 if (after_bootmem)
330 pin = kzalloc(sizeof(struct irq_pin_list)*nr_irq_2_pin,
331 GFP_ATOMIC);
332 else
333 pin = __alloc_bootmem_nopanic(sizeof(struct irq_pin_list) *
334 nr_irq_2_pin, PAGE_SIZE, 0);
335
336 if (!pin)
337 panic("can not get more irq_2_pin\n");
301e6190 338
e5a53714
YL		 339 for (i = 1; i < nr_irq_2_pin; i++)
340 pin[i-1].next = &pin[i];
301e6190 341
e5a53714
YL		 342 irq_2_pin_ptr = pin->next;
343 pin->next = NULL;
344
345 return pin;
346}
1da177e4 347
6c0ffb9d
LT		 348struct io_apic {
349 unsigned int index;
350 unsigned int unused[3];
351 unsigned int data;
352};
353
354static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
355{
356 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
ec2cd0a2 357 + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK);
6c0ffb9d
LT		 358}
359
360static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
361{
362 struct io_apic __iomem *io_apic = io_apic_base(apic);
363 writel(reg, &io_apic->index);
364 return readl(&io_apic->data);
365}
366
367static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
368{
369 struct io_apic __iomem *io_apic = io_apic_base(apic);
370 writel(reg, &io_apic->index);
371 writel(value, &io_apic->data);
372}
373
374/*
375 * Re-write a value: to be used for read-modify-write
376 * cycles where the read already set up the index register.
377 */
f876d213 378static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
6c0ffb9d
LT		 379{
380 struct io_apic __iomem *io_apic = io_apic_base(apic);
f876d213
YL		 381 if (sis_apic_bug)
382 writel(reg, &io_apic->index);
6c0ffb9d
LT		 383 writel(value, &io_apic->data);
384}
385
9d25cb08 386static bool io_apic_level_ack_pending(unsigned int irq)
ef3e28c5
EB		 387{
388 struct irq_pin_list *entry;
389 unsigned long flags;
e5a53714 390 struct irq_cfg *cfg = irq_cfg(irq);
ef3e28c5
EB		 391
392 spin_lock_irqsave(&ioapic_lock, flags);
e5a53714 393 entry = cfg->irq_2_pin;
ef3e28c5
EB		 394 for (;;) {
395 unsigned int reg;
396 int pin;
397
e5a53714 398 if (!entry)
ef3e28c5 399 break;
e5a53714 400 pin = entry->pin;
ef3e28c5
EB		 401 reg = io_apic_read(entry->apic, 0x10 + pin*2);
402 /* Is the remote IRR bit set? */
46b3b4ef 403 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
9d25cb08
AM		 404 spin_unlock_irqrestore(&ioapic_lock, flags);
405 return true;
406 }
ef3e28c5
EB		 407 if (!entry->next)
408 break;
e5a53714 409 entry = entry->next;
ef3e28c5
EB		 410 }
411 spin_unlock_irqrestore(&ioapic_lock, flags);
9d25cb08
AM		 412
413 return false;
ef3e28c5
EB		 414}
415
eea0e11c
AK		 416union entry_union {
417 struct { u32 w1, w2; };
418 struct IO_APIC_route_entry entry;
419};
420
421static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
422{
423 union entry_union eu;
424 unsigned long flags;
425 spin_lock_irqsave(&ioapic_lock, flags);
426 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
427 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
428 spin_unlock_irqrestore(&ioapic_lock, flags);
429 return eu.entry;
430}
431
48797ebd
LT		 432/*
433 * When we write a new IO APIC routing entry, we need to write the high
434 * word first! If the mask bit in the low word is clear, we will enable
435 * the interrupt, and we need to make sure the entry is fully populated
436 * before that happens.
437 */
516d2836
AK		 438static void
439__ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
eea0e11c 440{
eea0e11c
AK		 441 union entry_union eu;
442 eu.entry = e;
48797ebd
LT		 443 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
444 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
516d2836
AK		 445}
446
447static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
448{
449 unsigned long flags;
450 spin_lock_irqsave(&ioapic_lock, flags);
451 __ioapic_write_entry(apic, pin, e);
48797ebd
LT		 452 spin_unlock_irqrestore(&ioapic_lock, flags);
453}
454
455/*
456 * When we mask an IO APIC routing entry, we need to write the low
457 * word first, in order to set the mask bit before we change the
458 * high bits!
459 */
460static void ioapic_mask_entry(int apic, int pin)
461{
462 unsigned long flags;
463 union entry_union eu = { .entry.mask = 1 };
464
eea0e11c
AK		 465 spin_lock_irqsave(&ioapic_lock, flags);
466 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
467 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
468 spin_unlock_irqrestore(&ioapic_lock, flags);
469}
470
54d5d424 471#ifdef CONFIG_SMP
550f2299
EB		 472static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
473{
474 int apic, pin;
e5a53714
YL		 475 struct irq_cfg *cfg;
476 struct irq_pin_list *entry;
550f2299 477
e5a53714
YL		 478 cfg = irq_cfg(irq);
479 entry = cfg->irq_2_pin;
550f2299
EB		 480 for (;;) {
481 unsigned int reg;
e5a53714
YL		 482
483 if (!entry)
484 break;
485
550f2299
EB		 486 apic = entry->apic;
487 pin = entry->pin;
efa2559f 488#ifdef CONFIG_INTR_REMAP
89027d35
SS		 489 /*
490 * With interrupt-remapping, destination information comes
491 * from interrupt-remapping table entry.
492 */
493 if (!irq_remapped(irq))
494 io_apic_write(apic, 0x11 + pin*2, dest);
efa2559f
YL		 495#else
496 io_apic_write(apic, 0x11 + pin*2, dest);
497#endif
550f2299 498 reg = io_apic_read(apic, 0x10 + pin*2);
46b3b4ef 499 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
550f2299 500 reg |= vector;
f876d213 501 io_apic_modify(apic, 0x10 + pin*2, reg);
550f2299
EB		 502 if (!entry->next)
503 break;
e5a53714 504 entry = entry->next;
550f2299
EB		 505 }
506}
507
efa2559f
YL		 508static int assign_irq_vector(int irq, cpumask_t mask);
509
54d5d424
AR		 510static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
511{
3ac2de48 512 struct irq_cfg *cfg = irq_cfg(irq);
54d5d424
AR		 513 unsigned long flags;
514 unsigned int dest;
515 cpumask_t tmp;
08678b08 516 struct irq_desc *desc;
54d5d424
AR		 517
518 cpus_and(tmp, mask, cpu_online_map);
519 if (cpus_empty(tmp))
5ff5115e 520 return;
54d5d424 521
dfbffdd8 522 if (assign_irq_vector(irq, mask))
550f2299
EB		 523 return;
524
dfbffdd8 525 cpus_and(tmp, cfg->domain, mask);
550f2299 526 dest = cpu_mask_to_apicid(tmp);
54d5d424
AR		 527
528 /*
529 * Only the high 8 bits are valid.
530 */
531 dest = SET_APIC_LOGICAL_ID(dest);
532
08678b08 533 desc = irq_to_desc(irq);
54d5d424 534 spin_lock_irqsave(&ioapic_lock, flags);
dfbffdd8 535 __target_IO_APIC_irq(irq, dest, cfg->vector);
08678b08 536 desc->affinity = mask;
54d5d424
AR		 537 spin_unlock_irqrestore(&ioapic_lock, flags);
538}
539#endif
540
1da177e4
LT		 541/*
542 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
543 * shared ISA-space IRQs, so we have to support them. We are super
544 * fast in the common case, and fast for shared ISA-space IRQs.
545 */
546static void add_pin_to_irq(unsigned int irq, int apic, int pin)
547{
e5a53714
YL		 548 struct irq_cfg *cfg;
549 struct irq_pin_list *entry;
1da177e4 550
e5a53714
YL		 551 /* first time to refer irq_cfg, so with new */
552 cfg = irq_cfg_alloc(irq);
553 entry = cfg->irq_2_pin;
554 if (!entry) {
555 entry = get_one_free_irq_2_pin();
556 cfg->irq_2_pin = entry;
557 entry->apic = apic;
558 entry->pin = pin;
559 printk(KERN_DEBUG " 0 add_pin_to_irq: irq %d --> apic %d pin %d\n", irq, apic, pin);
560 return;
561 }
3ac2de48 562
e5a53714
YL		 563 while (entry->next) {
564 /* not again, please */
565 if (entry->apic == apic && entry->pin == pin)
566 return;
1da177e4 567
e5a53714 568 entry = entry->next;
1da177e4 569 }
e5a53714
YL		 570
571 entry->next = get_one_free_irq_2_pin();
572 entry = entry->next;
1da177e4
LT		 573 entry->apic = apic;
574 entry->pin = pin;
e5a53714 575 printk(KERN_DEBUG " x add_pin_to_irq: irq %d --> apic %d pin %d\n", irq, apic, pin);
1da177e4
LT		 576}
577
0b9f4f49
MR		 578/*
579 * Reroute an IRQ to a different pin.
580 */
581static void __init replace_pin_at_irq(unsigned int irq,
582 int oldapic, int oldpin,
583 int newapic, int newpin)
584{
e5a53714
YL		 585 struct irq_cfg *cfg = irq_cfg(irq);
586 struct irq_pin_list *entry = cfg->irq_2_pin;
587 int replaced = 0;
0b9f4f49 588
e5a53714 589 while (entry) {
0b9f4f49
MR		 590 if (entry->apic == oldapic && entry->pin == oldpin) {
591 entry->apic = newapic;
592 entry->pin = newpin;
e5a53714
YL		 593 replaced = 1;
594 /* every one is different, right? */
0b9f4f49 595 break;
e5a53714
YL		 596 }
597 entry = entry->next;
0b9f4f49 598 }
e5a53714
YL		 599
600 /* why? call replace before add? */
601 if (!replaced)
602 add_pin_to_irq(irq, newapic, newpin);
0b9f4f49
MR		 603}
604
8ea5371b
YL		 605/*
606 * Synchronize the IO-APIC and the CPU by doing
607 * a dummy read from the IO-APIC
608 */
609static inline void io_apic_sync(unsigned int apic)
610{
611 struct io_apic __iomem *io_apic = io_apic_base(apic);
612 readl(&io_apic->data);
613}
614
615#define __DO_ACTION(R, ACTION, FINAL) \
616 \
617{ \
618 int pin; \
619 struct irq_cfg *cfg; \
620 struct irq_pin_list *entry; \
621 \
622 cfg = irq_cfg(irq); \
623 entry = cfg->irq_2_pin; \
624 for (;;) { \
625 unsigned int reg; \
626 if (!entry) \
627 break; \
628 pin = entry->pin; \
629 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
630 reg ACTION; \
f876d213 631 io_apic_modify(entry->apic, 0x10 + R + pin*2, reg); \
8ea5371b
YL		 632 FINAL; \
633 if (!entry->next) \
634 break; \
635 entry = entry->next; \
636 } \
637}
1da177e4
LT		 638
639#define DO_ACTION(name,R,ACTION, FINAL) \
640 \
641 static void name##_IO_APIC_irq (unsigned int irq) \
642 __DO_ACTION(R, ACTION, FINAL)
643
46b3b4ef
CG		 644/* mask = 1 */
645DO_ACTION(__mask, 0, |= IO_APIC_REDIR_MASKED, io_apic_sync(entry->apic))
646
647/* mask = 0 */
648DO_ACTION(__unmask, 0, &= ~IO_APIC_REDIR_MASKED, )
1da177e4
LT		 649
650static void mask_IO_APIC_irq (unsigned int irq)
651{
652 unsigned long flags;
653
654 spin_lock_irqsave(&ioapic_lock, flags);
655 __mask_IO_APIC_irq(irq);
656 spin_unlock_irqrestore(&ioapic_lock, flags);
657}
658
659static void unmask_IO_APIC_irq (unsigned int irq)
660{
661 unsigned long flags;
662
663 spin_lock_irqsave(&ioapic_lock, flags);
664 __unmask_IO_APIC_irq(irq);
665 spin_unlock_irqrestore(&ioapic_lock, flags);
666}
667
668static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
669{
670 struct IO_APIC_route_entry entry;
1da177e4
LT		 671
672 /* Check delivery_mode to be sure we're not clearing an SMI pin */
eea0e11c 673 entry = ioapic_read_entry(apic, pin);
1da177e4
LT		 674 if (entry.delivery_mode == dest_SMI)
675 return;
676 /*
677 * Disable it in the IO-APIC irq-routing table:
678 */
48797ebd 679 ioapic_mask_entry(apic, pin);
1da177e4
LT		 680}
681
682static void clear_IO_APIC (void)
683{
684 int apic, pin;
685
686 for (apic = 0; apic < nr_ioapics; apic++)
687 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
688 clear_IO_APIC_pin(apic, pin);
689}
690
efa2559f
YL		 691#ifdef CONFIG_INTR_REMAP
692/* I/O APIC RTE contents at the OS boot up */
693static struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS];
694
4dc2f96c
SS		 695/*
696 * Saves and masks all the unmasked IO-APIC RTE's
697 */
698int save_mask_IO_APIC_setup(void)
699{
700 union IO_APIC_reg_01 reg_01;
701 unsigned long flags;
702 int apic, pin;
703
704 /*
705 * The number of IO-APIC IRQ registers (== #pins):
706 */
707 for (apic = 0; apic < nr_ioapics; apic++) {
708 spin_lock_irqsave(&ioapic_lock, flags);
709 reg_01.raw = io_apic_read(apic, 1);
710 spin_unlock_irqrestore(&ioapic_lock, flags);
711 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
712 }
713
714 for (apic = 0; apic < nr_ioapics; apic++) {
715 early_ioapic_entries[apic] =
716 kzalloc(sizeof(struct IO_APIC_route_entry) *
717 nr_ioapic_registers[apic], GFP_KERNEL);
718 if (!early_ioapic_entries[apic])
719 return -ENOMEM;
720 }
721
722 for (apic = 0; apic < nr_ioapics; apic++)
723 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
724 struct IO_APIC_route_entry entry;
725
726 entry = early_ioapic_entries[apic][pin] =
727 ioapic_read_entry(apic, pin);
728 if (!entry.mask) {
729 entry.mask = 1;
730 ioapic_write_entry(apic, pin, entry);
731 }
732 }
733 return 0;
734}
735
736void restore_IO_APIC_setup(void)
737{
738 int apic, pin;
739
740 for (apic = 0; apic < nr_ioapics; apic++)
741 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
742 ioapic_write_entry(apic, pin,
743 early_ioapic_entries[apic][pin]);
744}
745
746void reinit_intr_remapped_IO_APIC(int intr_remapping)
747{
748 /*
749 * for now plain restore of previous settings.
750 * TBD: In the case of OS enabling interrupt-remapping,
751 * IO-APIC RTE's need to be setup to point to interrupt-remapping
752 * table entries. for now, do a plain restore, and wait for
753 * the setup_IO_APIC_irqs() to do proper initialization.
754 */
755 restore_IO_APIC_setup();
756}
efa2559f 757#endif
fea5f1e1 758
1da177e4
LT		 759/*
760 * Find the IRQ entry number of a certain pin.
761 */
762static int find_irq_entry(int apic, int pin, int type)
763{
764 int i;
765
766 for (i = 0; i < mp_irq_entries; i++)
2fddb6e2
AS		 767 if (mp_irqs[i].mp_irqtype == type &&
768 (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid ||
769 mp_irqs[i].mp_dstapic == MP_APIC_ALL) &&
770 mp_irqs[i].mp_dstirq == pin)
1da177e4
LT		 771 return i;
772
773 return -1;
774}
775
776/*
777 * Find the pin to which IRQ[irq] (ISA) is connected
778 */
1008fddc 779static int __init find_isa_irq_pin(int irq, int type)
1da177e4
LT		 780{
781 int i;
782
783 for (i = 0; i < mp_irq_entries; i++) {
2fddb6e2 784 int lbus = mp_irqs[i].mp_srcbus;
1da177e4 785
55f05ffa 786 if (test_bit(lbus, mp_bus_not_pci) &&
2fddb6e2
AS		 787 (mp_irqs[i].mp_irqtype == type) &&
788 (mp_irqs[i].mp_srcbusirq == irq))
1da177e4 789
2fddb6e2 790 return mp_irqs[i].mp_dstirq;
1da177e4
LT		 791 }
792 return -1;
793}
794
1008fddc
EB		 795static int __init find_isa_irq_apic(int irq, int type)
796{
797 int i;
798
799 for (i = 0; i < mp_irq_entries; i++) {
2fddb6e2 800 int lbus = mp_irqs[i].mp_srcbus;
1008fddc 801
55f05ffa 802 if (test_bit(lbus, mp_bus_not_pci) &&
2fddb6e2
AS		 803 (mp_irqs[i].mp_irqtype == type) &&
804 (mp_irqs[i].mp_srcbusirq == irq))
1008fddc
EB		 805 break;
806 }
807 if (i < mp_irq_entries) {
808 int apic;
809 for(apic = 0; apic < nr_ioapics; apic++) {
2fddb6e2 810 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic)
1008fddc
EB		 811 return apic;
812 }
813 }
814
815 return -1;
816}
817
1da177e4
LT		 818/*
819 * Find a specific PCI IRQ entry.
820 * Not an __init, possibly needed by modules
821 */
822static int pin_2_irq(int idx, int apic, int pin);
823
824int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
825{
826 int apic, i, best_guess = -1;
827
828 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
829 bus, slot, pin);
ce6444d3 830 if (test_bit(bus, mp_bus_not_pci)) {
1da177e4
LT		 831 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
832 return -1;
833 }
834 for (i = 0; i < mp_irq_entries; i++) {
2fddb6e2 835 int lbus = mp_irqs[i].mp_srcbus;
1da177e4
LT		 836
837 for (apic = 0; apic < nr_ioapics; apic++)
2fddb6e2
AS		 838 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic ||
839 mp_irqs[i].mp_dstapic == MP_APIC_ALL)
1da177e4
LT		 840 break;
841
55f05ffa 842 if (!test_bit(lbus, mp_bus_not_pci) &&
2fddb6e2 843 !mp_irqs[i].mp_irqtype &&
1da177e4 844 (bus == lbus) &&
2fddb6e2
AS		 845 (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) {
846 int irq = pin_2_irq(i,apic,mp_irqs[i].mp_dstirq);
1da177e4
LT		 847
848 if (!(apic || IO_APIC_IRQ(irq)))
849 continue;
850
2fddb6e2 851 if (pin == (mp_irqs[i].mp_srcbusirq & 3))
1da177e4
LT		 852 return irq;
853 /*
854 * Use the first all-but-pin matching entry as a
855 * best-guess fuzzy result for broken mptables.
856 */
857 if (best_guess < 0)
858 best_guess = irq;
859 }
860 }
861 return best_guess;
862}
863
1da177e4
LT		 864/* ISA interrupts are always polarity zero edge triggered,
865 * when listed as conforming in the MP table. */
866
867#define default_ISA_trigger(idx) (0)
868#define default_ISA_polarity(idx) (0)
869
870/* PCI interrupts are always polarity one level triggered,
871 * when listed as conforming in the MP table. */
872
873#define default_PCI_trigger(idx) (1)
874#define default_PCI_polarity(idx) (1)
875
61fd47e0 876static int MPBIOS_polarity(int idx)
1da177e4 877{
2fddb6e2 878 int bus = mp_irqs[idx].mp_srcbus;
1da177e4
LT		 879 int polarity;
880
881 /*
882 * Determine IRQ line polarity (high active or low active):
883 */
2fddb6e2 884 switch (mp_irqs[idx].mp_irqflag & 3)
1da177e4
LT		 885 {
886 case 0: /* conforms, ie. bus-type dependent polarity */
55f05ffa
AK		 887 if (test_bit(bus, mp_bus_not_pci))
888 polarity = default_ISA_polarity(idx);
889 else
890 polarity = default_PCI_polarity(idx);
1da177e4 891 break;
1da177e4
LT		 892 case 1: /* high active */
893 {
894 polarity = 0;
895 break;
896 }
897 case 2: /* reserved */
898 {
899 printk(KERN_WARNING "broken BIOS!!\n");
900 polarity = 1;
901 break;
902 }
903 case 3: /* low active */
904 {
905 polarity = 1;
906 break;
907 }
908 default: /* invalid */
909 {
910 printk(KERN_WARNING "broken BIOS!!\n");
911 polarity = 1;
912 break;
913 }
914 }
915 return polarity;
916}
917
918static int MPBIOS_trigger(int idx)
919{
2fddb6e2 920 int bus = mp_irqs[idx].mp_srcbus;
1da177e4
LT		 921 int trigger;
922
923 /*
924 * Determine IRQ trigger mode (edge or level sensitive):
925 */
2fddb6e2 926 switch ((mp_irqs[idx].mp_irqflag>>2) & 3)
1da177e4
LT		 927 {
928 case 0: /* conforms, ie. bus-type dependent */
55f05ffa
AK		 929 if (test_bit(bus, mp_bus_not_pci))
930 trigger = default_ISA_trigger(idx);
931 else
932 trigger = default_PCI_trigger(idx);
1da177e4 933 break;
1da177e4
LT		 934 case 1: /* edge */
935 {
936 trigger = 0;
937 break;
938 }
939 case 2: /* reserved */
940 {
941 printk(KERN_WARNING "broken BIOS!!\n");
942 trigger = 1;
943 break;
944 }
945 case 3: /* level */
946 {
947 trigger = 1;
948 break;
949 }
950 default: /* invalid */
951 {
952 printk(KERN_WARNING "broken BIOS!!\n");
953 trigger = 0;
954 break;
955 }
956 }
957 return trigger;
958}
959
960static inline int irq_polarity(int idx)
961{
962 return MPBIOS_polarity(idx);
963}
964
965static inline int irq_trigger(int idx)
966{
967 return MPBIOS_trigger(idx);
968}
969
970static int pin_2_irq(int idx, int apic, int pin)
971{
972 int irq, i;
2fddb6e2 973 int bus = mp_irqs[idx].mp_srcbus;
1da177e4
LT		 974
975 /*
976 * Debugging check, we are in big trouble if this message pops up!
977 */
2fddb6e2 978 if (mp_irqs[idx].mp_dstirq != pin)
1da177e4
LT		 979 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
980
55f05ffa 981 if (test_bit(bus, mp_bus_not_pci)) {
2fddb6e2 982 irq = mp_irqs[idx].mp_srcbusirq;
55f05ffa
AK		 983 } else {
984 /*
985 * PCI IRQs are mapped in order
986 */
987 i = irq = 0;
988 while (i < apic)
989 irq += nr_ioapic_registers[i++];
990 irq += pin;
1da177e4 991 }
1da177e4
LT		 992 return irq;
993}
994
d388e5fd
EB		 995void lock_vector_lock(void)
996{
997 /* Used to the online set of cpus does not change
998 * during assign_irq_vector.
999 */
1000 spin_lock(&vector_lock);
1001}
1002
1003void unlock_vector_lock(void)
1004{
1005 spin_unlock(&vector_lock);
1006}
1007
dfbffdd8 1008static int __assign_irq_vector(int irq, cpumask_t mask)
1da177e4 1009{
550f2299
EB		 1010 /*
1011 * NOTE! The local APIC isn't very good at handling
1012 * multiple interrupts at the same interrupt level.
1013 * As the interrupt level is determined by taking the
1014 * vector number and shifting that right by 4, we
1015 * want to spread these out a bit so that they don't
1016 * all fall in the same interrupt level.
1017 *
1018 * Also, we've got to be careful not to trash gate
1019 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1020 */
d1752aa8 1021 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
dfbffdd8 1022 unsigned int old_vector;
550f2299 1023 int cpu;
13a79503 1024 struct irq_cfg *cfg;
1da177e4 1025
3ac2de48 1026 cfg = irq_cfg(irq);
0a1ad60d 1027
70a0a535
EB		 1028 /* Only try and allocate irqs on cpus that are present */
1029 cpus_and(mask, mask, cpu_online_map);
1030
61014292
EB		 1031 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1032 return -EBUSY;
1033
dfbffdd8
EB		 1034 old_vector = cfg->vector;
1035 if (old_vector) {
1036 cpumask_t tmp;
1037 cpus_and(tmp, cfg->domain, mask);
1038 if (!cpus_empty(tmp))
1039 return 0;
0a1ad60d 1040 }
550f2299 1041
334ef7a7 1042 for_each_cpu_mask_nr(cpu, mask) {
70a0a535 1043 cpumask_t domain, new_mask;
61014292 1044 int new_cpu;
550f2299 1045 int vector, offset;
c7111c13
EB		 1046
1047 domain = vector_allocation_domain(cpu);
70a0a535 1048 cpus_and(new_mask, domain, cpu_online_map);
c7111c13 1049
d1752aa8
EB		 1050 vector = current_vector;
1051 offset = current_offset;
1da177e4 1052next:
550f2299 1053 vector += 8;
305b92a2 1054 if (vector >= first_system_vector) {
550f2299
EB		 1055 /* If we run out of vectors on large boxen, must share them. */
1056 offset = (offset + 1) % 8;
1057 vector = FIRST_DEVICE_VECTOR + offset;
1058 }
d1752aa8 1059 if (unlikely(current_vector == vector))
550f2299
EB		 1060 continue;
1061 if (vector == IA32_SYSCALL_VECTOR)
1062 goto next;
334ef7a7 1063 for_each_cpu_mask_nr(new_cpu, new_mask)
45edfd1d 1064 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
c7111c13 1065 goto next;
550f2299 1066 /* Found one! */
d1752aa8
EB		 1067 current_vector = vector;
1068 current_offset = offset;
61014292
EB		 1069 if (old_vector) {
1070 cfg->move_in_progress = 1;
1071 cfg->old_domain = cfg->domain;
1072 }
334ef7a7 1073 for_each_cpu_mask_nr(new_cpu, new_mask)
c7111c13 1074 per_cpu(vector_irq, new_cpu)[vector] = irq;
13a79503
EB		 1075 cfg->vector = vector;
1076 cfg->domain = domain;
dfbffdd8 1077 return 0;
1da177e4 1078 }
550f2299 1079 return -ENOSPC;
04b9267b
EB		 1080}
1081
dfbffdd8 1082static int assign_irq_vector(int irq, cpumask_t mask)
04b9267b 1083{
dfbffdd8 1084 int err;
04b9267b 1085 unsigned long flags;
0a1ad60d 1086
04b9267b 1087 spin_lock_irqsave(&vector_lock, flags);
dfbffdd8 1088 err = __assign_irq_vector(irq, mask);
26a3c49c 1089 spin_unlock_irqrestore(&vector_lock, flags);
dfbffdd8 1090 return err;
1da177e4
LT		 1091}
1092
5df0287e
YL		 1093static void __clear_irq_vector(int irq)
1094{
13a79503 1095 struct irq_cfg *cfg;
5df0287e
YL		 1096 cpumask_t mask;
1097 int cpu, vector;
1098
3ac2de48 1099 cfg = irq_cfg(irq);
13a79503 1100 BUG_ON(!cfg->vector);
5df0287e 1101
13a79503
EB		 1102 vector = cfg->vector;
1103 cpus_and(mask, cfg->domain, cpu_online_map);
334ef7a7 1104 for_each_cpu_mask_nr(cpu, mask)
5df0287e
YL		 1105 per_cpu(vector_irq, cpu)[vector] = -1;
1106
13a79503 1107 cfg->vector = 0;
d366f8cb 1108 cpus_clear(cfg->domain);
5df0287e
YL		 1109}
1110
d388e5fd 1111void __setup_vector_irq(int cpu)
70a0a535
EB		 1112{
1113 /* Initialize vector_irq on a new cpu */
1114 /* This function must be called with vector_lock held */
70a0a535 1115 int irq, vector;
46b8214d 1116 struct irq_cfg *cfg;
70a0a535 1117
70a0a535 1118 /* Mark the inuse vectors */
46b8214d 1119 for_each_irq_cfg(cfg) {
3ac2de48 1120 if (!cpu_isset(cpu, cfg->domain))
70a0a535 1121 continue;
3ac2de48 1122 vector = cfg->vector;
46b8214d 1123 irq = cfg->irq;
70a0a535
EB		 1124 per_cpu(vector_irq, cpu)[vector] = irq;
1125 }
1126 /* Mark the free vectors */
1127 for (vector = 0; vector < NR_VECTORS; ++vector) {
1128 irq = per_cpu(vector_irq, cpu)[vector];
1129 if (irq < 0)
1130 continue;
3ac2de48
YL		 1131
1132 cfg = irq_cfg(irq);
1133 if (!cpu_isset(cpu, cfg->domain))
70a0a535
EB		 1134 per_cpu(vector_irq, cpu)[vector] = -1;
1135 }
1136}
1137
f29bd1ba 1138static struct irq_chip ioapic_chip;
89027d35
SS		 1139#ifdef CONFIG_INTR_REMAP
1140static struct irq_chip ir_ioapic_chip;
1141#endif
1da177e4 1142
a27bc06d 1143static void ioapic_register_intr(int irq, unsigned long trigger)
1da177e4 1144{
08678b08
YL		 1145 struct irq_desc *desc;
1146
cb5bc832
YL		 1147 /* first time to use this irq_desc */
1148 if (irq < 16)
1149 desc = irq_to_desc(irq);
1150 else
1151 desc = irq_to_desc_alloc(irq);
1152
89027d35 1153 if (trigger)
08678b08 1154 desc->status |= IRQ_LEVEL;
89027d35 1155 else
08678b08 1156 desc->status &= ~IRQ_LEVEL;
89027d35
SS		 1157
1158#ifdef CONFIG_INTR_REMAP
1159 if (irq_remapped(irq)) {
08678b08 1160 desc->status |= IRQ_MOVE_PCNTXT;
89027d35
SS		 1161 if (trigger)
1162 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1163 handle_fasteoi_irq,
1164 "fasteoi");
1165 else
1166 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1167 handle_edge_irq, "edge");
1168 return;
1169 }
1170#endif
1171 if (trigger)
1172 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1173 handle_fasteoi_irq,
1174 "fasteoi");
1175 else
a460e745
IM		 1176 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1177 handle_edge_irq, "edge");
89027d35
SS		 1178}
1179
1180static int setup_ioapic_entry(int apic, int irq,
1181 struct IO_APIC_route_entry *entry,
1182 unsigned int destination, int trigger,
1183 int polarity, int vector)
1184{
1185 /*
1186 * add it to the IO-APIC irq-routing table:
1187 */
1188 memset(entry,0,sizeof(*entry));
1189
1190#ifdef CONFIG_INTR_REMAP
1191 if (intr_remapping_enabled) {
1192 struct intel_iommu *iommu = map_ioapic_to_ir(apic);
1193 struct irte irte;
1194 struct IR_IO_APIC_route_entry *ir_entry =
1195 (struct IR_IO_APIC_route_entry *) entry;
1196 int index;
1197
1198 if (!iommu)
1199 panic("No mapping iommu for ioapic %d\n", apic);
1200
1201 index = alloc_irte(iommu, irq, 1);
1202 if (index < 0)
1203 panic("Failed to allocate IRTE for ioapic %d\n", apic);
1204
1205 memset(&irte, 0, sizeof(irte));
1206
1207 irte.present = 1;
1208 irte.dst_mode = INT_DEST_MODE;
1209 irte.trigger_mode = trigger;
1210 irte.dlvry_mode = INT_DELIVERY_MODE;
1211 irte.vector = vector;
1212 irte.dest_id = IRTE_DEST(destination);
1213
1214 modify_irte(irq, &irte);
1215
1216 ir_entry->index2 = (index >> 15) & 0x1;
1217 ir_entry->zero = 0;
1218 ir_entry->format = 1;
1219 ir_entry->index = (index & 0x7fff);
1220 } else
1221#endif
1222 {
1223 entry->delivery_mode = INT_DELIVERY_MODE;
1224 entry->dest_mode = INT_DEST_MODE;
1225 entry->dest = destination;
cc75b92d 1226 }
89027d35
SS		 1227
1228 entry->mask = 0; /* enable IRQ */
1229 entry->trigger = trigger;
1230 entry->polarity = polarity;
1231 entry->vector = vector;
1232
1233 /* Mask level triggered irqs.
1234 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1235 */
1236 if (trigger)
1237 entry->mask = 1;
1238 return 0;
1da177e4 1239}
a8c8a367
EB		 1240
1241static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
1242 int trigger, int polarity)
1da177e4 1243{
3ac2de48 1244 struct irq_cfg *cfg;
1da177e4 1245 struct IO_APIC_route_entry entry;
a8c8a367 1246 cpumask_t mask;
1da177e4 1247
a8c8a367
EB		 1248 if (!IO_APIC_IRQ(irq))
1249 return;
1250
3ac2de48
YL		 1251 cfg = irq_cfg(irq);
1252
dfbffdd8
EB		 1253 mask = TARGET_CPUS;
1254 if (assign_irq_vector(irq, mask))
a8c8a367
EB		 1255 return;
1256
dfbffdd8
EB		 1257 cpus_and(mask, cfg->domain, mask);
1258
a8c8a367
EB		 1259 apic_printk(APIC_VERBOSE,KERN_DEBUG
1260 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1261 "IRQ %d Mode:%i Active:%i)\n",
ec2cd0a2 1262 apic, mp_ioapics[apic].mp_apicid, pin, cfg->vector,
a8c8a367 1263 irq, trigger, polarity);
1da177e4 1264
1da177e4 1265
89027d35
SS		 1266 if (setup_ioapic_entry(mp_ioapics[apic].mp_apicid, irq, &entry,
1267 cpu_mask_to_apicid(mask), trigger, polarity,
1268 cfg->vector)) {
1269 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1270 mp_ioapics[apic].mp_apicid, pin);
1271 __clear_irq_vector(irq);
1272 return;
1273 }
ad892f5e 1274
a8c8a367
EB		 1275 ioapic_register_intr(irq, trigger);
1276 if (irq < 16)
1277 disable_8259A_irq(irq);
ad892f5e
YL		 1278
1279 ioapic_write_entry(apic, pin, entry);
ad892f5e
YL		 1280}
1281
1282static void __init setup_IO_APIC_irqs(void)
1283{
1284 int apic, pin, idx, irq, first_notcon = 1;
1285
1286 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1287
1288 for (apic = 0; apic < nr_ioapics; apic++) {
1289 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1da177e4
LT		 1290
1291 idx = find_irq_entry(apic,pin,mp_INT);
1292 if (idx == -1) {
1293 if (first_notcon) {
ec2cd0a2 1294 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mp_apicid, pin);
1da177e4
LT		 1295 first_notcon = 0;
1296 } else
ec2cd0a2 1297 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mp_apicid, pin);
1da177e4
LT		 1298 continue;
1299 }
20d225b9
YL		 1300 if (!first_notcon) {
1301 apic_printk(APIC_VERBOSE, " not connected.\n");
1302 first_notcon = 1;
1303 }
1da177e4 1304
1da177e4
LT		 1305 irq = pin_2_irq(idx, apic, pin);
1306 add_pin_to_irq(irq, apic, pin);
1307
a8c8a367
EB		 1308 setup_IO_APIC_irq(apic, pin, irq,
1309 irq_trigger(idx), irq_polarity(idx));
1da177e4
LT		 1310 }
1311 }
1312
1313 if (!first_notcon)
20d225b9 1314 apic_printk(APIC_VERBOSE, " not connected.\n");
1da177e4
LT		 1315}
1316
1317/*
f7633ce5 1318 * Set up the timer pin, possibly with the 8259A-master behind.
1da177e4 1319 */
f7633ce5
MR		 1320static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
1321 int vector)
1da177e4
LT		 1322{
1323 struct IO_APIC_route_entry entry;
1da177e4 1324
efa2559f 1325#ifdef CONFIG_INTR_REMAP
89027d35
SS		 1326 if (intr_remapping_enabled)
1327 return;
efa2559f 1328#endif
89027d35 1329
a2249cba 1330 memset(&entry, 0, sizeof(entry));
1da177e4 1331
1da177e4
LT		 1332 /*
1333 * We use logical delivery to get the timer IRQ
1334 * to the first CPU.
1335 */
1336 entry.dest_mode = INT_DEST_MODE;
03be7505 1337 entry.mask = 1; /* mask IRQ now */
ee4eff6f 1338 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
1da177e4
LT		 1339 entry.delivery_mode = INT_DELIVERY_MODE;
1340 entry.polarity = 0;
1341 entry.trigger = 0;
1342 entry.vector = vector;
1343
1344 /*
1345 * The timer IRQ doesn't have to know that behind the
f7633ce5 1346 * scene we may have a 8259A-master in AEOI mode ...
1da177e4 1347 */
a460e745 1348 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1da177e4
LT		 1349
1350 /*
1351 * Add it to the IO-APIC irq-routing table:
1352 */
a2249cba 1353 ioapic_write_entry(apic, pin, entry);
1da177e4
LT		 1354}
1355
32f71aff
MR		 1356
1357__apicdebuginit(void) print_IO_APIC(void)
1da177e4
LT		 1358{
1359 int apic, i;
1360 union IO_APIC_reg_00 reg_00;
1361 union IO_APIC_reg_01 reg_01;
1362 union IO_APIC_reg_02 reg_02;
1363 unsigned long flags;
46b8214d 1364 struct irq_cfg *cfg;
1da177e4
LT		 1365
1366 if (apic_verbosity == APIC_QUIET)
1367 return;
1368
1369 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1370 for (i = 0; i < nr_ioapics; i++)
1371 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
ec2cd0a2 1372 mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]);
1da177e4
LT		 1373
1374 /*
1375 * We are a bit conservative about what we expect. We have to
1376 * know about every hardware change ASAP.
1377 */
1378 printk(KERN_INFO "testing the IO APIC.......................\n");
1379
1380 for (apic = 0; apic < nr_ioapics; apic++) {
1381
1382 spin_lock_irqsave(&ioapic_lock, flags);
1383 reg_00.raw = io_apic_read(apic, 0);
1384 reg_01.raw = io_apic_read(apic, 1);
1385 if (reg_01.bits.version >= 0x10)
1386 reg_02.raw = io_apic_read(apic, 2);
1387 spin_unlock_irqrestore(&ioapic_lock, flags);
1388
1389 printk("\n");
ec2cd0a2 1390 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid);
1da177e4
LT		 1391 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1392 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
7a959cff
YL		 1393 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1394 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1da177e4
LT		 1395
1396 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1397 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1da177e4
LT		 1398
1399 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1400 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1da177e4
LT		 1401
1402 if (reg_01.bits.version >= 0x10) {
1403 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1404 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1da177e4
LT		 1405 }
1406
1407 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1408
ee4eff6f
BR		 1409 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1410 " Stat Dmod Deli Vect: \n");
1da177e4
LT		 1411
1412 for (i = 0; i <= reg_01.bits.entries; i++) {
1413 struct IO_APIC_route_entry entry;
1414
eea0e11c 1415 entry = ioapic_read_entry(apic, i);
1da177e4 1416
ee4eff6f 1417 printk(KERN_DEBUG " %02x %03X ",
1da177e4 1418 i,
ee4eff6f 1419 entry.dest
1da177e4
LT		 1420 );
1421
1422 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1423 entry.mask,
1424 entry.trigger,
1425 entry.irr,
1426 entry.polarity,
1427 entry.delivery_status,
1428 entry.dest_mode,
1429 entry.delivery_mode,
1430 entry.vector
1431 );
1432 }
1433 }
1da177e4 1434 printk(KERN_DEBUG "IRQ to pin mappings:\n");
46b8214d 1435 for_each_irq_cfg(cfg) {
e5a53714
YL		 1436 struct irq_pin_list *entry = cfg->irq_2_pin;
1437 if (!entry)
1da177e4 1438 continue;
46b8214d 1439 printk(KERN_DEBUG "IRQ%d ", cfg->irq);
1da177e4
LT		 1440 for (;;) {
1441 printk("-> %d:%d", entry->apic, entry->pin);
1442 if (!entry->next)
1443 break;
e5a53714 1444 entry = entry->next;
1da177e4
LT		 1445 }
1446 printk("\n");
1447 }
1448
1449 printk(KERN_INFO ".................................... done.\n");
1450
1451 return;
1452}
1453
32f71aff 1454__apicdebuginit(void) print_APIC_bitfield(int base)
1da177e4
LT		 1455{
1456 unsigned int v;
1457 int i, j;
1458
1459 if (apic_verbosity == APIC_QUIET)
1460 return;
1461
1462 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1463 for (i = 0; i < 8; i++) {
1464 v = apic_read(base + i*0x10);
1465 for (j = 0; j < 32; j++) {
1466 if (v & (1<<j))
1467 printk("1");
1468 else
1469 printk("0");
1470 }
1471 printk("\n");
1472 }
1473}
1474
32f71aff 1475__apicdebuginit(void) print_local_APIC(void *dummy)
1da177e4
LT		 1476{
1477 unsigned int v, ver, maxlvt;
1b374e4d 1478 unsigned long icr;
1da177e4
LT		 1479
1480 if (apic_verbosity == APIC_QUIET)
1481 return;
1482
1483 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1484 smp_processor_id(), hard_smp_processor_id());
66823114 1485 v = apic_read(APIC_ID);
4c9961d5 1486 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1da177e4
LT		 1487 v = apic_read(APIC_LVR);
1488 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1489 ver = GET_APIC_VERSION(v);
37e650c7 1490 maxlvt = lapic_get_maxlvt();
1da177e4
LT		 1491
1492 v = apic_read(APIC_TASKPRI);
1493 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1494
5a40b7c2
AK		 1495 v = apic_read(APIC_ARBPRI);
1496 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1497 v & APIC_ARBPRI_MASK);
1498 v = apic_read(APIC_PROCPRI);
1499 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1da177e4
LT		 1500
1501 v = apic_read(APIC_EOI);
1502 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1503 v = apic_read(APIC_RRR);
1504 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1505 v = apic_read(APIC_LDR);
1506 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1507 v = apic_read(APIC_DFR);
1508 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1509 v = apic_read(APIC_SPIV);
1510 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1511
1512 printk(KERN_DEBUG "... APIC ISR field:\n");
1513 print_APIC_bitfield(APIC_ISR);
1514 printk(KERN_DEBUG "... APIC TMR field:\n");
1515 print_APIC_bitfield(APIC_TMR);
1516 printk(KERN_DEBUG "... APIC IRR field:\n");
1517 print_APIC_bitfield(APIC_IRR);
1518
5a40b7c2
AK		 1519 v = apic_read(APIC_ESR);
1520 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1da177e4 1521
1b374e4d 1522 icr = apic_icr_read();
d562353a
IM		 1523 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1524 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1da177e4
LT		 1525
1526 v = apic_read(APIC_LVTT);
1527 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1528
1529 if (maxlvt > 3) { /* PC is LVT#4. */
1530 v = apic_read(APIC_LVTPC);
1531 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1532 }
1533 v = apic_read(APIC_LVT0);
1534 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1535 v = apic_read(APIC_LVT1);
1536 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1537
1538 if (maxlvt > 2) { /* ERR is LVT#3. */
1539 v = apic_read(APIC_LVTERR);
1540 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1541 }
1542
1543 v = apic_read(APIC_TMICT);
1544 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1545 v = apic_read(APIC_TMCCT);
1546 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1547 v = apic_read(APIC_TDCR);
1548 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1549 printk("\n");
1550}
1551
32f71aff 1552__apicdebuginit(void) print_all_local_APICs(void)
1da177e4 1553{
15c8b6c1 1554 on_each_cpu(print_local_APIC, NULL, 1);
1da177e4
LT		 1555}
1556
32f71aff 1557__apicdebuginit(void) print_PIC(void)
1da177e4 1558{
1da177e4
LT		 1559 unsigned int v;
1560 unsigned long flags;
1561
1562 if (apic_verbosity == APIC_QUIET)
1563 return;
1564
1565 printk(KERN_DEBUG "\nprinting PIC contents\n");
1566
1567 spin_lock_irqsave(&i8259A_lock, flags);
1568
1569 v = inb(0xa1) << 8 | inb(0x21);
1570 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1571
1572 v = inb(0xa0) << 8 | inb(0x20);
1573 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1574
1575 outb(0x0b,0xa0);
1576 outb(0x0b,0x20);
1577 v = inb(0xa0) << 8 | inb(0x20);
1578 outb(0x0a,0xa0);
1579 outb(0x0a,0x20);
1580
1581 spin_unlock_irqrestore(&i8259A_lock, flags);
1582
1583 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1584
1585 v = inb(0x4d1) << 8 | inb(0x4d0);
1586 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1587}
1588
32f71aff
MR		 1589__apicdebuginit(int) print_all_ICs(void)
1590{
1591 print_PIC();
1592 print_all_local_APICs();
1593 print_IO_APIC();
1594
1595 return 0;
1596}
1597
1598fs_initcall(print_all_ICs);
1599
1da177e4 1600
efa2559f
YL		 1601/* Where if anywhere is the i8259 connect in external int mode */
1602static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1603
1c69524c 1604void __init enable_IO_APIC(void)
1da177e4
LT		 1605{
1606 union IO_APIC_reg_01 reg_01;
1008fddc 1607 int i8259_apic, i8259_pin;
e5a53714 1608 int apic;
1da177e4
LT		 1609 unsigned long flags;
1610
1da177e4
LT		 1611 /*
1612 * The number of IO-APIC IRQ registers (== #pins):
1613 */
1008fddc 1614 for (apic = 0; apic < nr_ioapics; apic++) {
1da177e4 1615 spin_lock_irqsave(&ioapic_lock, flags);
1008fddc 1616 reg_01.raw = io_apic_read(apic, 1);
1da177e4 1617 spin_unlock_irqrestore(&ioapic_lock, flags);
1008fddc
EB		 1618 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1619 }
1620 for(apic = 0; apic < nr_ioapics; apic++) {
1621 int pin;
1622 /* See if any of the pins is in ExtINT mode */
1623 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1624 struct IO_APIC_route_entry entry;
eea0e11c 1625 entry = ioapic_read_entry(apic, pin);
1008fddc
EB		 1626
1627 /* If the interrupt line is enabled and in ExtInt mode
1628 * I have found the pin where the i8259 is connected.
1629 */
1630 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1631 ioapic_i8259.apic = apic;
1632 ioapic_i8259.pin = pin;
1633 goto found_i8259;
1634 }
1635 }
1636 }
1637 found_i8259:
1638 /* Look to see what if the MP table has reported the ExtINT */
1639 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1640 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1641 /* Trust the MP table if nothing is setup in the hardware */
1642 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1643 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1644 ioapic_i8259.pin = i8259_pin;
1645 ioapic_i8259.apic = i8259_apic;
1646 }
1647 /* Complain if the MP table and the hardware disagree */
1648 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1649 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1650 {
1651 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1da177e4
LT		 1652 }
1653
1654 /*
1655 * Do not trust the IO-APIC being empty at bootup
1656 */
1657 clear_IO_APIC();
1658}
1659
1660/*
1661 * Not an __init, needed by the reboot code
1662 */
1663void disable_IO_APIC(void)
1664{
1665 /*
1666 * Clear the IO-APIC before rebooting:
1667 */
1668 clear_IO_APIC();
1669
208fb931 1670 /*
0b968d23 1671 * If the i8259 is routed through an IOAPIC
208fb931 1672 * Put that IOAPIC in virtual wire mode
0b968d23 1673 * so legacy interrupts can be delivered.
208fb931 1674 */
1008fddc 1675 if (ioapic_i8259.pin != -1) {
208fb931 1676 struct IO_APIC_route_entry entry;
208fb931
EB		 1677
1678 memset(&entry, 0, sizeof(entry));
1679 entry.mask = 0; /* Enabled */
1680 entry.trigger = 0; /* Edge */
1681 entry.irr = 0;
1682 entry.polarity = 0; /* High */
1683 entry.delivery_status = 0;
1684 entry.dest_mode = 0; /* Physical */
1008fddc 1685 entry.delivery_mode = dest_ExtINT; /* ExtInt */
208fb931 1686 entry.vector = 0;
4c9961d5 1687 entry.dest = read_apic_id();
208fb931 1688
208fb931
EB		 1689 /*
1690 * Add it to the IO-APIC irq-routing table:
1691 */
eea0e11c 1692 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
208fb931
EB		 1693 }
1694
1008fddc 1695 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1da177e4
LT		 1696}
1697
d4057bdb 1698int no_timer_check __initdata;
efa2559f
YL		 1699
1700static int __init notimercheck(char *s)
1701{
1702 no_timer_check = 1;
1703 return 1;
1704}
1705__setup("no_timer_check", notimercheck);
1706
1da177e4
LT		 1707/*
1708 * There is a nasty bug in some older SMP boards, their mptable lies
1709 * about the timer IRQ. We do the following to work around the situation:
1710 *
1711 * - timer IRQ defaults to IO-APIC IRQ
1712 * - if this function detects that timer IRQs are defunct, then we fall
1713 * back to ISA timer IRQs
1714 */
1715static int __init timer_irq_works(void)
1716{
1717 unsigned long t1 = jiffies;
4aae0702 1718 unsigned long flags;
1da177e4 1719
efa2559f
YL		 1720 if (no_timer_check)
1721 return 1;
1722
4aae0702 1723 local_save_flags(flags);
1da177e4
LT		 1724 local_irq_enable();
1725 /* Let ten ticks pass... */
1726 mdelay((10 * 1000) / HZ);
4aae0702 1727 local_irq_restore(flags);
1da177e4
LT		 1728
1729 /*
1730 * Expect a few ticks at least, to be sure some possible
1731 * glue logic does not lock up after one or two first
1732 * ticks in a non-ExtINT mode. Also the local APIC
1733 * might have cached one ExtINT interrupt. Finally, at
1734 * least one tick may be lost due to delays.
1735 */
1736
1737 /* jiffies wrap? */
1d16b53e 1738 if (time_after(jiffies, t1 + 4))
1da177e4
LT		 1739 return 1;
1740 return 0;
1741}
1742
1743/*
1744 * In the SMP+IOAPIC case it might happen that there are an unspecified
1745 * number of pending IRQ events unhandled. These cases are very rare,
1746 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1747 * better to do it this way as thus we do not have to be aware of
1748 * 'pending' interrupts in the IRQ path, except at this point.
1749 */
1750/*
1751 * Edge triggered needs to resend any interrupt
1752 * that was delayed but this is now handled in the device
1753 * independent code.
1754 */
1755
1756/*
1757 * Starting up a edge-triggered IO-APIC interrupt is
1758 * nasty - we need to make sure that we get the edge.
1759 * If it is already asserted for some reason, we need
1760 * return 1 to indicate that is was pending.
1761 *
1762 * This is not complete - we should be able to fake
1763 * an edge even if it isn't on the 8259A...
1764 */
1765
f29bd1ba 1766static unsigned int startup_ioapic_irq(unsigned int irq)
1da177e4
LT		 1767{
1768 int was_pending = 0;
1769 unsigned long flags;
1770
1771 spin_lock_irqsave(&ioapic_lock, flags);
1772 if (irq < 16) {
1773 disable_8259A_irq(irq);
1774 if (i8259A_irq_pending(irq))
1775 was_pending = 1;
1776 }
1777 __unmask_IO_APIC_irq(irq);
1778 spin_unlock_irqrestore(&ioapic_lock, flags);
1779
1780 return was_pending;
1781}
1782
04b9267b 1783static int ioapic_retrigger_irq(unsigned int irq)
c0ad90a3 1784{
3ac2de48 1785 struct irq_cfg *cfg = irq_cfg(irq);
6bf2dafa 1786 unsigned long flags;
550f2299 1787
6bf2dafa 1788 spin_lock_irqsave(&vector_lock, flags);
cb6d2be6 1789 send_IPI_mask(cpumask_of_cpu(first_cpu(cfg->domain)), cfg->vector);
6bf2dafa 1790 spin_unlock_irqrestore(&vector_lock, flags);
c0ad90a3
IM		 1791
1792 return 1;
1793}
1794
1da177e4
LT		 1795/*
1796 * Level and edge triggered IO-APIC interrupts need different handling,
1797 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1798 * handled with the level-triggered descriptor, but that one has slightly
1799 * more overhead. Level-triggered interrupts cannot be handled with the
1800 * edge-triggered handler, without risking IRQ storms and other ugly
1801 * races.
1802 */
1803
61014292 1804#ifdef CONFIG_SMP
89027d35
SS		 1805
1806#ifdef CONFIG_INTR_REMAP
1807static void ir_irq_migration(struct work_struct *work);
1808
1809static DECLARE_DELAYED_WORK(ir_migration_work, ir_irq_migration);
1810
1811/*
1812 * Migrate the IO-APIC irq in the presence of intr-remapping.
1813 *
1814 * For edge triggered, irq migration is a simple atomic update(of vector
1815 * and cpu destination) of IRTE and flush the hardware cache.
1816 *
1817 * For level triggered, we need to modify the io-apic RTE aswell with the update
1818 * vector information, along with modifying IRTE with vector and destination.
1819 * So irq migration for level triggered is little bit more complex compared to
1820 * edge triggered migration. But the good news is, we use the same algorithm
1821 * for level triggered migration as we have today, only difference being,
1822 * we now initiate the irq migration from process context instead of the
1823 * interrupt context.
1824 *
1825 * In future, when we do a directed EOI (combined with cpu EOI broadcast
1826 * suppression) to the IO-APIC, level triggered irq migration will also be
1827 * as simple as edge triggered migration and we can do the irq migration
1828 * with a simple atomic update to IO-APIC RTE.
1829 */
1830static void migrate_ioapic_irq(int irq, cpumask_t mask)
1831{
3ac2de48 1832 struct irq_cfg *cfg;
08678b08 1833 struct irq_desc *desc;
89027d35
SS		 1834 cpumask_t tmp, cleanup_mask;
1835 struct irte irte;
08678b08 1836 int modify_ioapic_rte;
89027d35
SS		 1837 unsigned int dest;
1838 unsigned long flags;
1839
1840 cpus_and(tmp, mask, cpu_online_map);
1841 if (cpus_empty(tmp))
1842 return;
1843
1844 if (get_irte(irq, &irte))
1845 return;
1846
1847 if (assign_irq_vector(irq, mask))
1848 return;
1849
3ac2de48 1850 cfg = irq_cfg(irq);
89027d35
SS		 1851 cpus_and(tmp, cfg->domain, mask);
1852 dest = cpu_mask_to_apicid(tmp);
1853
08678b08
YL		 1854 desc = irq_to_desc(irq);
1855 modify_ioapic_rte = desc->status & IRQ_LEVEL;
89027d35
SS		 1856 if (modify_ioapic_rte) {
1857 spin_lock_irqsave(&ioapic_lock, flags);
1858 __target_IO_APIC_irq(irq, dest, cfg->vector);
1859 spin_unlock_irqrestore(&ioapic_lock, flags);
1860 }
1861
1862 irte.vector = cfg->vector;
1863 irte.dest_id = IRTE_DEST(dest);
1864
1865 /*
1866 * Modified the IRTE and flushes the Interrupt entry cache.
1867 */
1868 modify_irte(irq, &irte);
1869
1870 if (cfg->move_in_progress) {
1871 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
1872 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
1873 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
1874 cfg->move_in_progress = 0;
1875 }
1876
08678b08 1877 desc->affinity = mask;
89027d35
SS		 1878}
1879
1880static int migrate_irq_remapped_level(int irq)
1881{
1882 int ret = -1;
08678b08 1883 struct irq_desc *desc = irq_to_desc(irq);
89027d35
SS		 1884
1885 mask_IO_APIC_irq(irq);
1886
1887 if (io_apic_level_ack_pending(irq)) {
1888 /*
1889 * Interrupt in progress. Migrating irq now will change the
1890 * vector information in the IO-APIC RTE and that will confuse
1891 * the EOI broadcast performed by cpu.
1892 * So, delay the irq migration to the next instance.
1893 */
1894 schedule_delayed_work(&ir_migration_work, 1);
1895 goto unmask;
1896 }
1897
1898 /* everthing is clear. we have right of way */
08678b08 1899 migrate_ioapic_irq(irq, desc->pending_mask);
89027d35
SS		 1900
1901 ret = 0;
08678b08
YL		 1902 desc->status &= ~IRQ_MOVE_PENDING;
1903 cpus_clear(desc->pending_mask);
89027d35
SS		 1904
1905unmask:
1906 unmask_IO_APIC_irq(irq);
1907 return ret;
1908}
1909
1910static void ir_irq_migration(struct work_struct *work)
1911{
2c6927a3
YL		 1912 unsigned int irq;
1913 struct irq_desc *desc;
89027d35 1914
2c6927a3 1915 for_each_irq_desc(irq, desc) {
89027d35
SS		 1916 if (desc->status & IRQ_MOVE_PENDING) {
1917 unsigned long flags;
1918
1919 spin_lock_irqsave(&desc->lock, flags);
1920 if (!desc->chip->set_affinity ||
1921 !(desc->status & IRQ_MOVE_PENDING)) {
1922 desc->status &= ~IRQ_MOVE_PENDING;
1923 spin_unlock_irqrestore(&desc->lock, flags);
1924 continue;
1925 }
1926
08678b08 1927 desc->chip->set_affinity(irq, desc->pending_mask);
89027d35
SS		 1928 spin_unlock_irqrestore(&desc->lock, flags);
1929 }
1930 }
1931}
1932
1933/*
1934 * Migrates the IRQ destination in the process context.
1935 */
1936static void set_ir_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
1937{
08678b08
YL		 1938 struct irq_desc *desc = irq_to_desc(irq);
1939
1940 if (desc->status & IRQ_LEVEL) {
1941 desc->status |= IRQ_MOVE_PENDING;
1942 desc->pending_mask = mask;
89027d35
SS		 1943 migrate_irq_remapped_level(irq);
1944 return;
1945 }
1946
1947 migrate_ioapic_irq(irq, mask);
1948}
1949#endif
1950
61014292
EB		 1951asmlinkage void smp_irq_move_cleanup_interrupt(void)
1952{
1953 unsigned vector, me;
1954 ack_APIC_irq();
1955 exit_idle();
1956 irq_enter();
1957
1958 me = smp_processor_id();
1959 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
1960 unsigned int irq;
1961 struct irq_desc *desc;
1962 struct irq_cfg *cfg;
1963 irq = __get_cpu_var(vector_irq)[vector];
61014292 1964
08678b08 1965 desc = irq_to_desc(irq);
cb5bc832
YL		 1966 if (!desc)
1967 continue;
1968
3ac2de48 1969 cfg = irq_cfg(irq);
61014292
EB		 1970 spin_lock(&desc->lock);
1971 if (!cfg->move_cleanup_count)
1972 goto unlock;
1973
1974 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
1975 goto unlock;
1976
1977 __get_cpu_var(vector_irq)[vector] = -1;
1978 cfg->move_cleanup_count--;
1979unlock:
1980 spin_unlock(&desc->lock);
1981 }
1982
1983 irq_exit();
1984}
1985
1986static void irq_complete_move(unsigned int irq)
1987{
3ac2de48 1988 struct irq_cfg *cfg = irq_cfg(irq);
61014292
EB		 1989 unsigned vector, me;
1990
1991 if (likely(!cfg->move_in_progress))
1992 return;
1993
65ea5b03 1994 vector = ~get_irq_regs()->orig_ax;
61014292 1995 me = smp_processor_id();
f0e13ae7 1996 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
61014292
EB		 1997 cpumask_t cleanup_mask;
1998
1999 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
2000 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
2001 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2002 cfg->move_in_progress = 0;
2003 }
2004}
2005#else
2006static inline void irq_complete_move(unsigned int irq) {}
2007#endif
89027d35
SS		 2008#ifdef CONFIG_INTR_REMAP
2009static void ack_x2apic_level(unsigned int irq)
2010{
2011 ack_x2APIC_irq();
2012}
2013
2014static void ack_x2apic_edge(unsigned int irq)
2015{
2016 ack_x2APIC_irq();
2017}
2018#endif
61014292 2019
0be6652f
EB		 2020static void ack_apic_edge(unsigned int irq)
2021{
61014292 2022 irq_complete_move(irq);
0be6652f
EB		 2023 move_native_irq(irq);
2024 ack_APIC_irq();
2025}
2026
2027static void ack_apic_level(unsigned int irq)
2028{
2029 int do_unmask_irq = 0;
2030
61014292 2031 irq_complete_move(irq);
52e3d90d 2032#ifdef CONFIG_GENERIC_PENDING_IRQ
0be6652f 2033 /* If we are moving the irq we need to mask it */
08678b08 2034 if (unlikely(irq_to_desc(irq)->status & IRQ_MOVE_PENDING)) {
0be6652f
EB		 2035 do_unmask_irq = 1;
2036 mask_IO_APIC_irq(irq);
2037 }
2038#endif
2039
2040 /*
2041 * We must acknowledge the irq before we move it or the acknowledge will
beb7dd86 2042 * not propagate properly.
0be6652f
EB		 2043 */
2044 ack_APIC_irq();
2045
2046 /* Now we can move and renable the irq */
ef3e28c5
EB		 2047 if (unlikely(do_unmask_irq)) {
2048 /* Only migrate the irq if the ack has been received.
2049 *
2050 * On rare occasions the broadcast level triggered ack gets
2051 * delayed going to ioapics, and if we reprogram the
2052 * vector while Remote IRR is still set the irq will never
2053 * fire again.
2054 *
2055 * To prevent this scenario we read the Remote IRR bit
2056 * of the ioapic. This has two effects.
2057 * - On any sane system the read of the ioapic will
2058 * flush writes (and acks) going to the ioapic from
2059 * this cpu.
2060 * - We get to see if the ACK has actually been delivered.
2061 *
2062 * Based on failed experiments of reprogramming the
2063 * ioapic entry from outside of irq context starting
2064 * with masking the ioapic entry and then polling until
2065 * Remote IRR was clear before reprogramming the
2066 * ioapic I don't trust the Remote IRR bit to be
2067 * completey accurate.
2068 *
2069 * However there appears to be no other way to plug
2070 * this race, so if the Remote IRR bit is not
2071 * accurate and is causing problems then it is a hardware bug
2072 * and you can go talk to the chipset vendor about it.
2073 */
2074 if (!io_apic_level_ack_pending(irq))
2075 move_masked_irq(irq);
0be6652f 2076 unmask_IO_APIC_irq(irq);
ef3e28c5 2077 }
0be6652f
EB		 2078}
2079
f29bd1ba
IM		 2080static struct irq_chip ioapic_chip __read_mostly = {
2081 .name = "IO-APIC",
04b9267b
EB		 2082 .startup = startup_ioapic_irq,
2083 .mask = mask_IO_APIC_irq,
2084 .unmask = unmask_IO_APIC_irq,
0be6652f
EB		 2085 .ack = ack_apic_edge,
2086 .eoi = ack_apic_level,
54d5d424 2087#ifdef CONFIG_SMP
04b9267b 2088 .set_affinity = set_ioapic_affinity_irq,
54d5d424 2089#endif
04b9267b 2090 .retrigger = ioapic_retrigger_irq,
1da177e4
LT		 2091};
2092
89027d35
SS		 2093#ifdef CONFIG_INTR_REMAP
2094static struct irq_chip ir_ioapic_chip __read_mostly = {
2095 .name = "IR-IO-APIC",
2096 .startup = startup_ioapic_irq,
2097 .mask = mask_IO_APIC_irq,
2098 .unmask = unmask_IO_APIC_irq,
2099 .ack = ack_x2apic_edge,
2100 .eoi = ack_x2apic_level,
2101#ifdef CONFIG_SMP
2102 .set_affinity = set_ir_ioapic_affinity_irq,
2103#endif
2104 .retrigger = ioapic_retrigger_irq,
2105};
2106#endif
2107
1da177e4
LT		 2108static inline void init_IO_APIC_traps(void)
2109{
2110 int irq;
08678b08 2111 struct irq_desc *desc;
46b8214d 2112 struct irq_cfg *cfg;
1da177e4
LT		 2113
2114 /*
2115 * NOTE! The local APIC isn't very good at handling
2116 * multiple interrupts at the same interrupt level.
2117 * As the interrupt level is determined by taking the
2118 * vector number and shifting that right by 4, we
2119 * want to spread these out a bit so that they don't
2120 * all fall in the same interrupt level.
2121 *
2122 * Also, we've got to be careful not to trash gate
2123 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2124 */
46b8214d
YL		 2125 for_each_irq_cfg(cfg) {
2126 irq = cfg->irq;
3ac2de48 2127 if (IO_APIC_IRQ(irq) && !cfg->vector) {
1da177e4
LT		 2128 /*
2129 * Hmm.. We don't have an entry for this,
2130 * so default to an old-fashioned 8259
2131 * interrupt if we can..
2132 */
2133 if (irq < 16)
2134 make_8259A_irq(irq);
08678b08
YL		 2135 else {
2136 desc = irq_to_desc(irq);
1da177e4 2137 /* Strange. Oh, well.. */
08678b08
YL		 2138 desc->chip = &no_irq_chip;
2139 }
1da177e4
LT		 2140 }
2141 }
2142}
2143
c88ac1df 2144static void unmask_lapic_irq(unsigned int irq)
1da177e4
LT		 2145{
2146 unsigned long v;
2147
2148 v = apic_read(APIC_LVT0);
11a8e778 2149 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1da177e4
LT		 2150}
2151
c88ac1df 2152static void mask_lapic_irq(unsigned int irq)
1da177e4
LT		 2153{
2154 unsigned long v;
2155
2156 v = apic_read(APIC_LVT0);
11a8e778 2157 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1da177e4
LT		 2158}
2159
2160static void ack_lapic_irq (unsigned int irq)
2161{
2162 ack_APIC_irq();
2163}
2164
c88ac1df
MR		 2165static struct irq_chip lapic_chip __read_mostly = {
2166 .name = "local-APIC",
2167 .mask = mask_lapic_irq,
2168 .unmask = unmask_lapic_irq,
2169 .ack = ack_lapic_irq,
1da177e4
LT		 2170};
2171
c88ac1df
MR		 2172static void lapic_register_intr(int irq)
2173{
08678b08
YL		 2174 struct irq_desc *desc;
2175
2176 desc = irq_to_desc(irq);
2177 desc->status &= ~IRQ_LEVEL;
c88ac1df
MR		 2178 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2179 "edge");
2180}
2181
e9427101 2182static void __init setup_nmi(void)
1da177e4
LT		 2183{
2184 /*
2185 * Dirty trick to enable the NMI watchdog ...
2186 * We put the 8259A master into AEOI mode and
2187 * unmask on all local APICs LVT0 as NMI.
2188 *
2189 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2190 * is from Maciej W. Rozycki - so we do not have to EOI from
2191 * the NMI handler or the timer interrupt.
2192 */
2193 printk(KERN_INFO "activating NMI Watchdog ...");
2194
e9427101 2195 enable_NMI_through_LVT0();
1da177e4
LT		 2196
2197 printk(" done.\n");
2198}
2199
2200/*
2201 * This looks a bit hackish but it's about the only one way of sending
2202 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2203 * not support the ExtINT mode, unfortunately. We need to send these
2204 * cycles as some i82489DX-based boards have glue logic that keeps the
2205 * 8259A interrupt line asserted until INTA. --macro
2206 */
5afca33a 2207static inline void __init unlock_ExtINT_logic(void)
1da177e4 2208{
1008fddc 2209 int apic, pin, i;
1da177e4
LT		 2210 struct IO_APIC_route_entry entry0, entry1;
2211 unsigned char save_control, save_freq_select;
1da177e4 2212
1008fddc
EB		 2213 pin = find_isa_irq_pin(8, mp_INT);
2214 apic = find_isa_irq_apic(8, mp_INT);
1da177e4
LT		 2215 if (pin == -1)
2216 return;
2217
a2249cba
AM		 2218 entry0 = ioapic_read_entry(apic, pin);
2219
1008fddc 2220 clear_IO_APIC_pin(apic, pin);
1da177e4
LT		 2221
2222 memset(&entry1, 0, sizeof(entry1));
2223
2224 entry1.dest_mode = 0; /* physical delivery */
2225 entry1.mask = 0; /* unmask IRQ now */
ee4eff6f 2226 entry1.dest = hard_smp_processor_id();
1da177e4
LT		 2227 entry1.delivery_mode = dest_ExtINT;
2228 entry1.polarity = entry0.polarity;
2229 entry1.trigger = 0;
2230 entry1.vector = 0;
2231
a2249cba 2232 ioapic_write_entry(apic, pin, entry1);
1da177e4
LT		 2233
2234 save_control = CMOS_READ(RTC_CONTROL);
2235 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2236 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2237 RTC_FREQ_SELECT);
2238 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2239
2240 i = 100;
2241 while (i-- > 0) {
2242 mdelay(10);
2243 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2244 i -= 10;
2245 }
2246
2247 CMOS_WRITE(save_control, RTC_CONTROL);
2248 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1008fddc 2249 clear_IO_APIC_pin(apic, pin);
1da177e4 2250
a2249cba 2251 ioapic_write_entry(apic, pin, entry0);
1da177e4
LT		 2252}
2253
efa2559f
YL		 2254static int disable_timer_pin_1 __initdata;
2255/* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2256static int __init disable_timer_pin_setup(char *arg)
2257{
2258 disable_timer_pin_1 = 1;
2259 return 0;
2260}
2261early_param("disable_timer_pin_1", disable_timer_pin_setup);
2262
2263int timer_through_8259 __initdata;
2264
1da177e4
LT		 2265/*
2266 * This code may look a bit paranoid, but it's supposed to cooperate with
2267 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2268 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2269 * fanatically on his truly buggy board.
fea5f1e1
LT		 2270 *
2271 * FIXME: really need to revamp this for modern platforms only.
1da177e4 2272 */
e9427101 2273static inline void __init check_timer(void)
1da177e4 2274{
3ac2de48 2275 struct irq_cfg *cfg = irq_cfg(0);
1008fddc 2276 int apic1, pin1, apic2, pin2;
4aae0702 2277 unsigned long flags;
691874fa 2278 int no_pin1 = 0;
4aae0702
IM		 2279
2280 local_irq_save(flags);
1da177e4
LT		 2281
2282 /*
2283 * get/set the timer IRQ vector:
2284 */
2285 disable_8259A_irq(0);
dfbffdd8 2286 assign_irq_vector(0, TARGET_CPUS);
1da177e4
LT		 2287
2288 /*
d11d5794
MR		 2289 * As IRQ0 is to be enabled in the 8259A, the virtual
2290 * wire has to be disabled in the local APIC.
1da177e4 2291 */
11a8e778 2292 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1da177e4 2293 init_8259A(1);
1da177e4 2294
1008fddc
EB		 2295 pin1 = find_isa_irq_pin(0, mp_INT);
2296 apic1 = find_isa_irq_apic(0, mp_INT);
2297 pin2 = ioapic_i8259.pin;
2298 apic2 = ioapic_i8259.apic;
1da177e4 2299
49a66a0b
MR		 2300 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2301 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2302 cfg->vector, apic1, pin1, apic2, pin2);
b0268726 2303
691874fa
MR		 2304 /*
2305 * Some BIOS writers are clueless and report the ExtINTA
2306 * I/O APIC input from the cascaded 8259A as the timer
2307 * interrupt input. So just in case, if only one pin
2308 * was found above, try it both directly and through the
2309 * 8259A.
2310 */
2311 if (pin1 == -1) {
efa2559f 2312#ifdef CONFIG_INTR_REMAP
89027d35
SS		 2313 if (intr_remapping_enabled)
2314 panic("BIOS bug: timer not connected to IO-APIC");
efa2559f 2315#endif
691874fa
MR		 2316 pin1 = pin2;
2317 apic1 = apic2;
2318 no_pin1 = 1;
2319 } else if (pin2 == -1) {
2320 pin2 = pin1;
2321 apic2 = apic1;
2322 }
2323
fea5f1e1
LT		 2324 if (pin1 != -1) {
2325 /*
2326 * Ok, does IRQ0 through the IOAPIC work?
2327 */
691874fa
MR		 2328 if (no_pin1) {
2329 add_pin_to_irq(0, apic1, pin1);
b1b57ee1 2330 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
691874fa 2331 }
fea5f1e1 2332 unmask_IO_APIC_irq(0);
efa2559f 2333 if (timer_irq_works()) {
fea5f1e1 2334 if (nmi_watchdog == NMI_IO_APIC) {
fea5f1e1
LT		 2335 setup_nmi();
2336 enable_8259A_irq(0);
2337 }
2338 if (disable_timer_pin_1 > 0)
2339 clear_IO_APIC_pin(0, pin1);
4aae0702 2340 goto out;
fea5f1e1 2341 }
efa2559f 2342#ifdef CONFIG_INTR_REMAP
89027d35
SS		 2343 if (intr_remapping_enabled)
2344 panic("timer doesn't work through Interrupt-remapped IO-APIC");
efa2559f 2345#endif
fea5f1e1 2346 clear_IO_APIC_pin(apic1, pin1);
691874fa 2347 if (!no_pin1)
49a66a0b 2348 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
691874fa 2349 "8254 timer not connected to IO-APIC\n");
1da177e4 2350
49a66a0b
MR		 2351 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2352 "(IRQ0) through the 8259A ...\n");
2353 apic_printk(APIC_QUIET, KERN_INFO
2354 "..... (found apic %d pin %d) ...\n", apic2, pin2);
fea5f1e1
LT		 2355 /*
2356 * legacy devices should be connected to IO APIC #0
2357 */
0b9f4f49 2358 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
f7633ce5 2359 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
24742ece 2360 unmask_IO_APIC_irq(0);
ecd29476 2361 enable_8259A_irq(0);
fea5f1e1 2362 if (timer_irq_works()) {
49a66a0b 2363 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
35542c5e 2364 timer_through_8259 = 1;
fea5f1e1 2365 if (nmi_watchdog == NMI_IO_APIC) {
60134ebe 2366 disable_8259A_irq(0);
fea5f1e1 2367 setup_nmi();
60134ebe 2368 enable_8259A_irq(0);
fea5f1e1 2369 }
4aae0702 2370 goto out;
fea5f1e1
LT		 2371 }
2372 /*
2373 * Cleanup, just in case ...
2374 */
ecd29476 2375 disable_8259A_irq(0);
fea5f1e1 2376 clear_IO_APIC_pin(apic2, pin2);
49a66a0b 2377 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
1da177e4 2378 }
1da177e4 2379
1f992153 2380 if (nmi_watchdog == NMI_IO_APIC) {
49a66a0b
MR		 2381 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2382 "through the IO-APIC - disabling NMI Watchdog!\n");
067fa0ff 2383 nmi_watchdog = NMI_NONE;
1da177e4
LT		 2384 }
2385
49a66a0b
MR		 2386 apic_printk(APIC_QUIET, KERN_INFO
2387 "...trying to set up timer as Virtual Wire IRQ...\n");
1da177e4 2388
c88ac1df 2389 lapic_register_intr(0);
dfbffdd8 2390 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
1da177e4
LT		 2391 enable_8259A_irq(0);
2392
2393 if (timer_irq_works()) {
49a66a0b 2394 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
4aae0702 2395 goto out;
1da177e4 2396 }
e67465f1 2397 disable_8259A_irq(0);
dfbffdd8 2398 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
49a66a0b 2399 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
1da177e4 2400
49a66a0b
MR		 2401 apic_printk(APIC_QUIET, KERN_INFO
2402 "...trying to set up timer as ExtINT IRQ...\n");
1da177e4
LT		 2403
2404 init_8259A(0);
2405 make_8259A_irq(0);
11a8e778 2406 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1da177e4
LT		 2407
2408 unlock_ExtINT_logic();
2409
2410 if (timer_irq_works()) {
49a66a0b 2411 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
4aae0702 2412 goto out;
1da177e4 2413 }
49a66a0b
MR		 2414 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2415 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2416 "report. Then try booting with the 'noapic' option.\n");
4aae0702
IM		 2417out:
2418 local_irq_restore(flags);
1da177e4
LT		 2419}
2420
2421/*
af174783
MR		 2422 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2423 * to devices. However there may be an I/O APIC pin available for
2424 * this interrupt regardless. The pin may be left unconnected, but
2425 * typically it will be reused as an ExtINT cascade interrupt for
2426 * the master 8259A. In the MPS case such a pin will normally be
2427 * reported as an ExtINT interrupt in the MP table. With ACPI
2428 * there is no provision for ExtINT interrupts, and in the absence
2429 * of an override it would be treated as an ordinary ISA I/O APIC
2430 * interrupt, that is edge-triggered and unmasked by default. We
2431 * used to do this, but it caused problems on some systems because
2432 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2433 * the same ExtINT cascade interrupt to drive the local APIC of the
2434 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2435 * the I/O APIC in all cases now. No actual device should request
2436 * it anyway. --macro
1da177e4
LT		 2437 */
2438#define PIC_IRQS (1<<2)
2439
2440void __init setup_IO_APIC(void)
2441{
1c69524c
YL		 2442
2443 /*
2444 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2445 */
1da177e4 2446
af174783 2447 io_apic_irqs = ~PIC_IRQS;
1da177e4
LT		 2448
2449 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2450
1da177e4
LT		 2451 sync_Arb_IDs();
2452 setup_IO_APIC_irqs();
2453 init_IO_APIC_traps();
2454 check_timer();
1da177e4
LT		 2455}
2456
f876d213
YL		 2457/*
2458 * Called after all the initialization is done. If we didnt find any
2459 * APIC bugs then we can allow the modify fast path
2460 */
2461
2462static int __init io_apic_bug_finalize(void)
2463{
2464 if (sis_apic_bug == -1)
2465 sis_apic_bug = 0;
2466 return 0;
2467}
2468
2469late_initcall(io_apic_bug_finalize);
2470
1da177e4
LT		 2471struct sysfs_ioapic_data {
2472 struct sys_device dev;
2473 struct IO_APIC_route_entry entry[0];
2474};
2475static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2476
0b9c33a7 2477static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1da177e4
LT		 2478{
2479 struct IO_APIC_route_entry *entry;
2480 struct sysfs_ioapic_data *data;
1da177e4
LT		 2481 int i;
2482
2483 data = container_of(dev, struct sysfs_ioapic_data, dev);
2484 entry = data->entry;
eea0e11c
AK		 2485 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
2486 *entry = ioapic_read_entry(dev->id, i);
1da177e4
LT		 2487
2488 return 0;
2489}
2490
2491static int ioapic_resume(struct sys_device *dev)
2492{
2493 struct IO_APIC_route_entry *entry;
2494 struct sysfs_ioapic_data *data;
2495 unsigned long flags;
2496 union IO_APIC_reg_00 reg_00;
2497 int i;
2498
2499 data = container_of(dev, struct sysfs_ioapic_data, dev);
2500 entry = data->entry;
2501
2502 spin_lock_irqsave(&ioapic_lock, flags);
2503 reg_00.raw = io_apic_read(dev->id, 0);
ec2cd0a2
AS		 2504 if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) {
2505 reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid;
1da177e4
LT		 2506 io_apic_write(dev->id, 0, reg_00.raw);
2507 }
1da177e4 2508 spin_unlock_irqrestore(&ioapic_lock, flags);
eea0e11c
AK		 2509 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
2510 ioapic_write_entry(dev->id, i, entry[i]);
1da177e4
LT		 2511
2512 return 0;
2513}
2514
2515static struct sysdev_class ioapic_sysdev_class = {
af5ca3f4 2516 .name = "ioapic",
1da177e4
LT		 2517 .suspend = ioapic_suspend,
2518 .resume = ioapic_resume,
2519};
2520
2521static int __init ioapic_init_sysfs(void)
2522{
2523 struct sys_device * dev;
cddf7ff7 2524 int i, size, error;
1da177e4
LT		 2525
2526 error = sysdev_class_register(&ioapic_sysdev_class);
2527 if (error)
2528 return error;
2529
2530 for (i = 0; i < nr_ioapics; i++ ) {
2531 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2532 * sizeof(struct IO_APIC_route_entry);
cddf7ff7 2533 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
1da177e4
LT		 2534 if (!mp_ioapic_data[i]) {
2535 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2536 continue;
2537 }
1da177e4
LT		 2538 dev = &mp_ioapic_data[i]->dev;
2539 dev->id = i;
2540 dev->cls = &ioapic_sysdev_class;
2541 error = sysdev_register(dev);
2542 if (error) {
2543 kfree(mp_ioapic_data[i]);
2544 mp_ioapic_data[i] = NULL;
2545 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2546 continue;
2547 }
2548 }
2549
2550 return 0;
2551}
2552
2553device_initcall(ioapic_init_sysfs);
2554
c4fa0bbf 2555/*
04b9267b 2556 * Dynamic irq allocate and deallocation
c4fa0bbf 2557 */
6d50bc26 2558unsigned int create_irq_nr(unsigned int irq_want)
c4fa0bbf 2559{
04b9267b 2560 /* Allocate an unused irq */
6d50bc26
YL		 2561 unsigned int irq;
2562 unsigned int new;
c4fa0bbf 2563 unsigned long flags;
3ac2de48 2564 struct irq_cfg *cfg_new;
c4fa0bbf 2565
6d50bc26
YL		 2566#ifndef CONFIG_HAVE_SPARSE_IRQ
2567 irq_want = nr_irqs - 1;
2568#endif
2569
2570 irq = 0;
04b9267b 2571 spin_lock_irqsave(&vector_lock, flags);
6d50bc26 2572 for (new = irq_want; new > 0; new--) {
04b9267b
EB		 2573 if (platform_legacy_irq(new))
2574 continue;
3ac2de48
YL		 2575 cfg_new = irq_cfg(new);
2576 if (cfg_new && cfg_new->vector != 0)
04b9267b 2577 continue;
3ac2de48
YL		 2578 /* check if need to create one */
2579 if (!cfg_new)
2580 cfg_new = irq_cfg_alloc(new);
dfbffdd8 2581 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
04b9267b
EB		 2582 irq = new;
2583 break;
2584 }
2585 spin_unlock_irqrestore(&vector_lock, flags);
c4fa0bbf 2586
6d50bc26 2587 if (irq > 0) {
c4fa0bbf
EB		 2588 dynamic_irq_init(irq);
2589 }
2590 return irq;
2591}
2592
6d50bc26
YL		 2593int create_irq(void)
2594{
2595 int irq;
2596
2597 irq = create_irq_nr(nr_irqs - 1);
2598
2599 if (irq == 0)
2600 irq = -1;
2601
2602 return irq;
2603}
2604
c4fa0bbf
EB		 2605void destroy_irq(unsigned int irq)
2606{
2607 unsigned long flags;
c4fa0bbf
EB		 2608
2609 dynamic_irq_cleanup(irq);
2610
75c46fa6
SS		 2611#ifdef CONFIG_INTR_REMAP
2612 free_irte(irq);
2613#endif
c4fa0bbf 2614 spin_lock_irqsave(&vector_lock, flags);
5df0287e 2615 __clear_irq_vector(irq);
c4fa0bbf
EB		 2616 spin_unlock_irqrestore(&vector_lock, flags);
2617}
c4fa0bbf 2618
589e367f 2619/*
676b1855 2620 * MSI message composition
589e367f
EB		 2621 */
2622#ifdef CONFIG_PCI_MSI
3b7d1921 2623static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
589e367f 2624{
3ac2de48 2625 struct irq_cfg *cfg;
dfbffdd8 2626 int err;
589e367f 2627 unsigned dest;
c7111c13 2628 cpumask_t tmp;
589e367f 2629
dfbffdd8
EB		 2630 tmp = TARGET_CPUS;
2631 err = assign_irq_vector(irq, tmp);
75c46fa6
SS		 2632 if (err)
2633 return err;
2634
3ac2de48 2635 cfg = irq_cfg(irq);
75c46fa6
SS		 2636 cpus_and(tmp, cfg->domain, tmp);
2637 dest = cpu_mask_to_apicid(tmp);
2638
2639#ifdef CONFIG_INTR_REMAP
2640 if (irq_remapped(irq)) {
2641 struct irte irte;
2642 int ir_index;
2643 u16 sub_handle;
2644
2645 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
2646 BUG_ON(ir_index == -1);
2647
2648 memset (&irte, 0, sizeof(irte));
2649
2650 irte.present = 1;
2651 irte.dst_mode = INT_DEST_MODE;
2652 irte.trigger_mode = 0; /* edge */
2653 irte.dlvry_mode = INT_DELIVERY_MODE;
2654 irte.vector = cfg->vector;
2655 irte.dest_id = IRTE_DEST(dest);
2656
2657 modify_irte(irq, &irte);
589e367f 2658
75c46fa6
SS		 2659 msg->address_hi = MSI_ADDR_BASE_HI;
2660 msg->data = sub_handle;
2661 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
2662 MSI_ADDR_IR_SHV |
2663 MSI_ADDR_IR_INDEX1(ir_index) |
2664 MSI_ADDR_IR_INDEX2(ir_index);
2665 } else
2666#endif
2667 {
589e367f
EB		 2668 msg->address_hi = MSI_ADDR_BASE_HI;
2669 msg->address_lo =
2670 MSI_ADDR_BASE_LO |
2671 ((INT_DEST_MODE == 0) ?
2672 MSI_ADDR_DEST_MODE_PHYSICAL:
2673 MSI_ADDR_DEST_MODE_LOGICAL) |
2674 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2675 MSI_ADDR_REDIRECTION_CPU:
2676 MSI_ADDR_REDIRECTION_LOWPRI) |
2677 MSI_ADDR_DEST_ID(dest);
2678
2679 msg->data =
2680 MSI_DATA_TRIGGER_EDGE |
2681 MSI_DATA_LEVEL_ASSERT |
2682 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2683 MSI_DATA_DELIVERY_FIXED:
2684 MSI_DATA_DELIVERY_LOWPRI) |
dfbffdd8 2685 MSI_DATA_VECTOR(cfg->vector);
589e367f 2686 }
dfbffdd8 2687 return err;
589e367f
EB		 2688}
2689
3b7d1921
EB		 2690#ifdef CONFIG_SMP
2691static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
589e367f 2692{
3ac2de48 2693 struct irq_cfg *cfg;
3b7d1921
EB		 2694 struct msi_msg msg;
2695 unsigned int dest;
2696 cpumask_t tmp;
08678b08 2697 struct irq_desc *desc;
3b7d1921
EB		 2698
2699 cpus_and(tmp, mask, cpu_online_map);
2700 if (cpus_empty(tmp))
5ff5115e 2701 return;
589e367f 2702
dfbffdd8 2703 if (assign_irq_vector(irq, mask))
3b7d1921 2704 return;
550f2299 2705
3ac2de48 2706 cfg = irq_cfg(irq);
dfbffdd8 2707 cpus_and(tmp, cfg->domain, mask);
3b7d1921 2708 dest = cpu_mask_to_apicid(tmp);
589e367f 2709
3b7d1921
EB		 2710 read_msi_msg(irq, &msg);
2711
2712 msg.data &= ~MSI_DATA_VECTOR_MASK;
dfbffdd8 2713 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3b7d1921
EB		 2714 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2715 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2716
2717 write_msi_msg(irq, &msg);
08678b08
YL		 2718 desc = irq_to_desc(irq);
2719 desc->affinity = mask;
589e367f 2720}
75c46fa6
SS		 2721
2722#ifdef CONFIG_INTR_REMAP
2723/*
2724 * Migrate the MSI irq to another cpumask. This migration is
2725 * done in the process context using interrupt-remapping hardware.
2726 */
2727static void ir_set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2728{
3ac2de48 2729 struct irq_cfg *cfg;
75c46fa6
SS		 2730 unsigned int dest;
2731 cpumask_t tmp, cleanup_mask;
2732 struct irte irte;
08678b08 2733 struct irq_desc *desc;
75c46fa6
SS		 2734
2735 cpus_and(tmp, mask, cpu_online_map);
2736 if (cpus_empty(tmp))
2737 return;
2738
2739 if (get_irte(irq, &irte))
2740 return;
2741
2742 if (assign_irq_vector(irq, mask))
2743 return;
2744
3ac2de48 2745 cfg = irq_cfg(irq);
75c46fa6
SS		 2746 cpus_and(tmp, cfg->domain, mask);
2747 dest = cpu_mask_to_apicid(tmp);
2748
2749 irte.vector = cfg->vector;
2750 irte.dest_id = IRTE_DEST(dest);
2751
2752 /*
2753 * atomically update the IRTE with the new destination and vector.
2754 */
2755 modify_irte(irq, &irte);
2756
2757 /*
2758 * After this point, all the interrupts will start arriving
2759 * at the new destination. So, time to cleanup the previous
2760 * vector allocation.
2761 */
2762 if (cfg->move_in_progress) {
2763 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
2764 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
2765 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2766 cfg->move_in_progress = 0;
2767 }
2768
08678b08
YL		 2769 desc = irq_to_desc(irq);
2770 desc->affinity = mask;
75c46fa6
SS		 2771}
2772#endif
3b7d1921 2773#endif /* CONFIG_SMP */
589e367f 2774
3b7d1921
EB		 2775/*
2776 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2777 * which implement the MSI or MSI-X Capability Structure.
2778 */
2779static struct irq_chip msi_chip = {
2780 .name = "PCI-MSI",
2781 .unmask = unmask_msi_irq,
2782 .mask = mask_msi_irq,
2783 .ack = ack_apic_edge,
2784#ifdef CONFIG_SMP
2785 .set_affinity = set_msi_irq_affinity,
2786#endif
2787 .retrigger = ioapic_retrigger_irq,
589e367f
EB		 2788};
2789
75c46fa6
SS		 2790#ifdef CONFIG_INTR_REMAP
2791static struct irq_chip msi_ir_chip = {
2792 .name = "IR-PCI-MSI",
2793 .unmask = unmask_msi_irq,
2794 .mask = mask_msi_irq,
2795 .ack = ack_x2apic_edge,
2796#ifdef CONFIG_SMP
2797 .set_affinity = ir_set_msi_irq_affinity,
2798#endif
2799 .retrigger = ioapic_retrigger_irq,
2800};
2801
2802/*
2803 * Map the PCI dev to the corresponding remapping hardware unit
2804 * and allocate 'nvec' consecutive interrupt-remapping table entries
2805 * in it.
2806 */
2807static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3b7d1921 2808{
75c46fa6
SS		 2809 struct intel_iommu *iommu;
2810 int index;
2811
2812 iommu = map_dev_to_ir(dev);
2813 if (!iommu) {
2814 printk(KERN_ERR
2815 "Unable to map PCI %s to iommu\n", pci_name(dev));
2816 return -ENOENT;
2817 }
2818
2819 index = alloc_irte(iommu, irq, nvec);
2820 if (index < 0) {
2821 printk(KERN_ERR
2822 "Unable to allocate %d IRTE for PCI %s\n", nvec,
2823 pci_name(dev));
2824 return -ENOSPC;
2825 }
2826 return index;
2827}
2828#endif
2829
2830static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc, int irq)
2831{
2832 int ret;
3b7d1921 2833 struct msi_msg msg;
75c46fa6
SS		 2834
2835 ret = msi_compose_msg(dev, irq, &msg);
2836 if (ret < 0)
2837 return ret;
2838
2839 set_irq_msi(irq, desc);
2840 write_msi_msg(irq, &msg);
2841
2842#ifdef CONFIG_INTR_REMAP
2843 if (irq_remapped(irq)) {
08678b08 2844 struct irq_desc *desc = irq_to_desc(irq);
75c46fa6
SS		 2845 /*
2846 * irq migration in process context
2847 */
2848 desc->status |= IRQ_MOVE_PCNTXT;
2849 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
2850 } else
2851#endif
2852 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
2853
2854 return 0;
2855}
2856
6d50bc26
YL		 2857static unsigned int build_irq_for_pci_dev(struct pci_dev *dev)
2858{
2859 unsigned int irq;
2860
2861 irq = dev->bus->number;
2862 irq <<= 8;
2863 irq |= dev->devfn;
2864 irq <<= 12;
2865
2866 return irq;
2867}
2868
75c46fa6
SS		 2869int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2870{
6d50bc26
YL		 2871 unsigned int irq;
2872 int ret;
2873 unsigned int irq_want;
75c46fa6 2874
6d50bc26
YL		 2875 irq_want = build_irq_for_pci_dev(dev) + 0x100;
2876
2877 irq = create_irq_nr(irq_want);
2878 if (irq == 0)
2879 return -1;
f7feaca7 2880
75c46fa6
SS		 2881#ifdef CONFIG_INTR_REMAP
2882 if (!intr_remapping_enabled)
2883 goto no_ir;
2884
2885 ret = msi_alloc_irte(dev, irq, 1);
2886 if (ret < 0)
2887 goto error;
2888no_ir:
2889#endif
2890 ret = setup_msi_irq(dev, desc, irq);
f7feaca7
EB		 2891 if (ret < 0) {
2892 destroy_irq(irq);
3b7d1921 2893 return ret;
f7feaca7 2894 }
75c46fa6 2895 return 0;
3b7d1921 2896
75c46fa6
SS		 2897#ifdef CONFIG_INTR_REMAP
2898error:
2899 destroy_irq(irq);
2900 return ret;
2901#endif
2902}
3b7d1921 2903
75c46fa6
SS		 2904int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
2905{
6d50bc26
YL		 2906 unsigned int irq;
2907 int ret, sub_handle;
75c46fa6 2908 struct msi_desc *desc;
6d50bc26
YL		 2909 unsigned int irq_want;
2910
75c46fa6
SS		 2911#ifdef CONFIG_INTR_REMAP
2912 struct intel_iommu *iommu = 0;
2913 int index = 0;
2914#endif
2915
6d50bc26 2916 irq_want = build_irq_for_pci_dev(dev) + 0x100;
75c46fa6
SS		 2917 sub_handle = 0;
2918 list_for_each_entry(desc, &dev->msi_list, list) {
6d50bc26
YL		 2919 irq = create_irq_nr(irq_want--);
2920 if (irq == 0)
2921 return -1;
75c46fa6
SS		 2922#ifdef CONFIG_INTR_REMAP
2923 if (!intr_remapping_enabled)
2924 goto no_ir;
3b7d1921 2925
75c46fa6
SS		 2926 if (!sub_handle) {
2927 /*
2928 * allocate the consecutive block of IRTE's
2929 * for 'nvec'
2930 */
2931 index = msi_alloc_irte(dev, irq, nvec);
2932 if (index < 0) {
2933 ret = index;
2934 goto error;
2935 }
2936 } else {
2937 iommu = map_dev_to_ir(dev);
2938 if (!iommu) {
2939 ret = -ENOENT;
2940 goto error;
2941 }
2942 /*
2943 * setup the mapping between the irq and the IRTE
2944 * base index, the sub_handle pointing to the
2945 * appropriate interrupt remap table entry.
2946 */
2947 set_irte_irq(irq, iommu, index, sub_handle);
2948 }
2949no_ir:
2950#endif
2951 ret = setup_msi_irq(dev, desc, irq);
2952 if (ret < 0)
2953 goto error;
2954 sub_handle++;
2955 }
7fe3730d 2956 return 0;
75c46fa6
SS		 2957
2958error:
2959 destroy_irq(irq);
2960 return ret;
3b7d1921
EB		 2961}
2962
2963void arch_teardown_msi_irq(unsigned int irq)
2964{
f7feaca7 2965 destroy_irq(irq);
3b7d1921
EB		 2966}
2967
3460a6d9
KA		 2968#ifdef CONFIG_DMAR
2969#ifdef CONFIG_SMP
2970static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask)
2971{
3ac2de48 2972 struct irq_cfg *cfg;
3460a6d9
KA		 2973 struct msi_msg msg;
2974 unsigned int dest;
2975 cpumask_t tmp;
08678b08 2976 struct irq_desc *desc;
3460a6d9
KA		 2977
2978 cpus_and(tmp, mask, cpu_online_map);
2979 if (cpus_empty(tmp))
2980 return;
2981
2982 if (assign_irq_vector(irq, mask))
2983 return;
2984
3ac2de48 2985 cfg = irq_cfg(irq);
3460a6d9
KA		 2986 cpus_and(tmp, cfg->domain, mask);
2987 dest = cpu_mask_to_apicid(tmp);
2988
2989 dmar_msi_read(irq, &msg);
2990
2991 msg.data &= ~MSI_DATA_VECTOR_MASK;
2992 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2993 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2994 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2995
2996 dmar_msi_write(irq, &msg);
08678b08
YL		 2997 desc = irq_to_desc(irq);
2998 desc->affinity = mask;
3460a6d9
KA		 2999}
3000#endif /* CONFIG_SMP */
3001
3002struct irq_chip dmar_msi_type = {
3003 .name = "DMAR_MSI",
3004 .unmask = dmar_msi_unmask,
3005 .mask = dmar_msi_mask,
3006 .ack = ack_apic_edge,
3007#ifdef CONFIG_SMP
3008 .set_affinity = dmar_msi_set_affinity,
3009#endif
3010 .retrigger = ioapic_retrigger_irq,
3011};
3012
3013int arch_setup_dmar_msi(unsigned int irq)
3014{
3015 int ret;
3016 struct msi_msg msg;
3017
3018 ret = msi_compose_msg(NULL, irq, &msg);
3019 if (ret < 0)
3020 return ret;
3021 dmar_msi_write(irq, &msg);
3022 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3023 "edge");
3024 return 0;
3025}
3026#endif
589e367f 3027
3460a6d9 3028#endif /* CONFIG_PCI_MSI */
8b955b0d
EB		 3029/*
3030 * Hypertransport interrupt support
3031 */
3032#ifdef CONFIG_HT_IRQ
3033
3034#ifdef CONFIG_SMP
3035
3036static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3037{
ec68307c
EB		 3038 struct ht_irq_msg msg;
3039 fetch_ht_irq_msg(irq, &msg);
8b955b0d 3040
ec68307c
EB		 3041 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3042 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
8b955b0d 3043
ec68307c
EB		 3044 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3045 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
8b955b0d 3046
ec68307c 3047 write_ht_irq_msg(irq, &msg);
8b955b0d
EB		 3048}
3049
3050static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
3051{
3ac2de48 3052 struct irq_cfg *cfg;
8b955b0d
EB		 3053 unsigned int dest;
3054 cpumask_t tmp;
08678b08 3055 struct irq_desc *desc;
8b955b0d
EB		 3056
3057 cpus_and(tmp, mask, cpu_online_map);
3058 if (cpus_empty(tmp))
5ff5115e 3059 return;
8b955b0d 3060
dfbffdd8 3061 if (assign_irq_vector(irq, mask))
8b955b0d
EB		 3062 return;
3063
3ac2de48 3064 cfg = irq_cfg(irq);
dfbffdd8 3065 cpus_and(tmp, cfg->domain, mask);
8b955b0d
EB		 3066 dest = cpu_mask_to_apicid(tmp);
3067
dfbffdd8 3068 target_ht_irq(irq, dest, cfg->vector);
08678b08
YL		 3069 desc = irq_to_desc(irq);
3070 desc->affinity = mask;
8b955b0d
EB		 3071}
3072#endif
3073
c37e108d 3074static struct irq_chip ht_irq_chip = {
8b955b0d
EB		 3075 .name = "PCI-HT",
3076 .mask = mask_ht_irq,
3077 .unmask = unmask_ht_irq,
3078 .ack = ack_apic_edge,
3079#ifdef CONFIG_SMP
3080 .set_affinity = set_ht_irq_affinity,
3081#endif
3082 .retrigger = ioapic_retrigger_irq,
3083};
3084
3085int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3086{
3ac2de48 3087 struct irq_cfg *cfg;
dfbffdd8 3088 int err;
c7111c13 3089 cpumask_t tmp;
8b955b0d 3090
dfbffdd8
EB		 3091 tmp = TARGET_CPUS;
3092 err = assign_irq_vector(irq, tmp);
3093 if (!err) {
ec68307c 3094 struct ht_irq_msg msg;
8b955b0d 3095 unsigned dest;
8b955b0d 3096
3ac2de48 3097 cfg = irq_cfg(irq);
dfbffdd8 3098 cpus_and(tmp, cfg->domain, tmp);
8b955b0d
EB		 3099 dest = cpu_mask_to_apicid(tmp);
3100
ec68307c 3101 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
8b955b0d 3102
ec68307c
EB		 3103 msg.address_lo =
3104 HT_IRQ_LOW_BASE |
8b955b0d 3105 HT_IRQ_LOW_DEST_ID(dest) |
dfbffdd8 3106 HT_IRQ_LOW_VECTOR(cfg->vector) |
8b955b0d
EB		 3107 ((INT_DEST_MODE == 0) ?
3108 HT_IRQ_LOW_DM_PHYSICAL :
3109 HT_IRQ_LOW_DM_LOGICAL) |
3110 HT_IRQ_LOW_RQEOI_EDGE |
3111 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3112 HT_IRQ_LOW_MT_FIXED :
ec68307c
EB		 3113 HT_IRQ_LOW_MT_ARBITRATED) |
3114 HT_IRQ_LOW_IRQ_MASKED;
8b955b0d 3115
ec68307c 3116 write_ht_irq_msg(irq, &msg);
8b955b0d 3117
a460e745
IM		 3118 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3119 handle_edge_irq, "edge");
8b955b0d 3120 }
dfbffdd8 3121 return err;
8b955b0d
EB		 3122}
3123#endif /* CONFIG_HT_IRQ */
3124
1da177e4
LT		 3125/* --------------------------------------------------------------------------
3126 ACPI-based IOAPIC Configuration
3127 -------------------------------------------------------------------------- */
3128
888ba6c6 3129#ifdef CONFIG_ACPI
1da177e4
LT		 3130
3131#define IO_APIC_MAX_ID 0xFE
3132
1da177e4
LT		 3133int __init io_apic_get_redir_entries (int ioapic)
3134{
3135 union IO_APIC_reg_01 reg_01;
3136 unsigned long flags;
3137
3138 spin_lock_irqsave(&ioapic_lock, flags);
3139 reg_01.raw = io_apic_read(ioapic, 1);
3140 spin_unlock_irqrestore(&ioapic_lock, flags);
3141
3142 return reg_01.bits.entries;
3143}
3144
3145
50eca3eb 3146int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
1da177e4 3147{
1da177e4
LT		 3148 if (!IO_APIC_IRQ(irq)) {
3149 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3150 ioapic);
3151 return -EINVAL;
3152 }
3153
550f2299
EB		 3154 /*
3155 * IRQs < 16 are already in the irq_2_pin[] map
3156 */
3157 if (irq >= 16)
3158 add_pin_to_irq(irq, ioapic, pin);
3159
a8c8a367 3160 setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
1da177e4
LT		 3161
3162 return 0;
3163}
3164
1da177e4 3165
61fd47e0
SL		 3166int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
3167{
3168 int i;
3169
3170 if (skip_ioapic_setup)
3171 return -1;
3172
3173 for (i = 0; i < mp_irq_entries; i++)
2fddb6e2
AS		 3174 if (mp_irqs[i].mp_irqtype == mp_INT &&
3175 mp_irqs[i].mp_srcbusirq == bus_irq)
61fd47e0
SL		 3176 break;
3177 if (i >= mp_irq_entries)
3178 return -1;
3179
3180 *trigger = irq_trigger(i);
3181 *polarity = irq_polarity(i);
3182 return 0;
3183}
3184
3185#endif /* CONFIG_ACPI */
1da177e4
LT		 3186
3187/*
3188 * This function currently is only a helper for the i386 smp boot process where
3189 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3190 * so mask in all cases should simply be TARGET_CPUS
3191 */
54d5d424 3192#ifdef CONFIG_SMP
1da177e4
LT		 3193void __init setup_ioapic_dest(void)
3194{
3195 int pin, ioapic, irq, irq_entry;
3ac2de48 3196 struct irq_cfg *cfg;
1da177e4
LT		 3197
3198 if (skip_ioapic_setup == 1)
3199 return;
3200
3201 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
3202 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
3203 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
3204 if (irq_entry == -1)
3205 continue;
3206 irq = pin_2_irq(irq_entry, ioapic, pin);
ad892f5e
YL		 3207
3208 /* setup_IO_APIC_irqs could fail to get vector for some device
3209 * when you have too many devices, because at that time only boot
3210 * cpu is online.
3211 */
3ac2de48
YL		 3212 cfg = irq_cfg(irq);
3213 if (!cfg->vector)
a8c8a367
EB		 3214 setup_IO_APIC_irq(ioapic, pin, irq,
3215 irq_trigger(irq_entry),
3216 irq_polarity(irq_entry));
89027d35
SS		 3217#ifdef CONFIG_INTR_REMAP
3218 else if (intr_remapping_enabled)
3219 set_ir_ioapic_affinity_irq(irq, TARGET_CPUS);
3220#endif
ad892f5e
YL		 3221 else
3222 set_ioapic_affinity_irq(irq, TARGET_CPUS);
1da177e4
LT		 3223 }
3224
3225 }
3226}
54d5d424 3227#endif
61fd47e0 3228
3e35a0e5
TG		 3229#define IOAPIC_RESOURCE_NAME_SIZE 11
3230
3231static struct resource *ioapic_resources;
3232
3233static struct resource * __init ioapic_setup_resources(void)
3234{
3235 unsigned long n;
3236 struct resource *res;
3237 char *mem;
3238 int i;
3239
3240 if (nr_ioapics <= 0)
3241 return NULL;
3242
3243 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
3244 n *= nr_ioapics;
3245
3246 mem = alloc_bootmem(n);
3247 res = (void *)mem;
3248
3249 if (mem != NULL) {
3e35a0e5
TG		 3250 mem += sizeof(struct resource) * nr_ioapics;
3251
3252 for (i = 0; i < nr_ioapics; i++) {
3253 res[i].name = mem;
3254 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
3255 sprintf(mem, "IOAPIC %u", i);
3256 mem += IOAPIC_RESOURCE_NAME_SIZE;
3257 }
3258 }
3259
3260 ioapic_resources = res;
3261
3262 return res;
3263}
3264
3265void __init ioapic_init_mappings(void)
3266{
3267 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
3268 struct resource *ioapic_res;
3269 int i;
3270
3271 ioapic_res = ioapic_setup_resources();
3272 for (i = 0; i < nr_ioapics; i++) {
3273 if (smp_found_config) {
ec2cd0a2 3274 ioapic_phys = mp_ioapics[i].mp_apicaddr;
3e35a0e5
TG		 3275 } else {
3276 ioapic_phys = (unsigned long)
3277 alloc_bootmem_pages(PAGE_SIZE);
3278 ioapic_phys = __pa(ioapic_phys);
3279 }
3280 set_fixmap_nocache(idx, ioapic_phys);
3281 apic_printk(APIC_VERBOSE,
3282 "mapped IOAPIC to %016lx (%016lx)\n",
3283 __fix_to_virt(idx), ioapic_phys);
3284 idx++;
3285
3286 if (ioapic_res != NULL) {
3287 ioapic_res->start = ioapic_phys;
3288 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
3289 ioapic_res++;
3290 }
3291 }
3292}
3293
3294static int __init ioapic_insert_resources(void)
3295{
3296 int i;
3297 struct resource *r = ioapic_resources;
3298
3299 if (!r) {
3300 printk(KERN_ERR
3301 "IO APIC resources could be not be allocated.\n");
3302 return -1;
3303 }
3304
3305 for (i = 0; i < nr_ioapics; i++) {
3306 insert_resource(&iomem_resource, r);
3307 r++;
3308 }
3309
3310 return 0;
3311}
3312
3313/* Insert the IO APIC resources after PCI initialization has occured to handle
3314 * IO APICS that are mapped in on a BAR in PCI space. */
3315late_initcall(ioapic_insert_resources);
3316
Linux kernel - Deliverables
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