Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
4 | * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo | |
5 | * | |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
589e367f | 28 | #include <linux/pci.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/acpi.h> | |
31 | #include <linux/sysdev.h> | |
3b7d1921 | 32 | #include <linux/msi.h> |
95d77884 | 33 | #include <linux/htirq.h> |
3460a6d9 | 34 | #include <linux/dmar.h> |
1d16b53e | 35 | #include <linux/jiffies.h> |
ab688059 AK |
36 | #ifdef CONFIG_ACPI |
37 | #include <acpi/acpi_bus.h> | |
38 | #endif | |
3e35a0e5 | 39 | #include <linux/bootmem.h> |
1da177e4 | 40 | |
61014292 | 41 | #include <asm/idle.h> |
1da177e4 LT |
42 | #include <asm/io.h> |
43 | #include <asm/smp.h> | |
44 | #include <asm/desc.h> | |
45 | #include <asm/proto.h> | |
8d916406 | 46 | #include <asm/acpi.h> |
ca8642f6 | 47 | #include <asm/dma.h> |
3e4ff115 | 48 | #include <asm/nmi.h> |
589e367f | 49 | #include <asm/msidef.h> |
8b955b0d | 50 | #include <asm/hypertransport.h> |
1da177e4 | 51 | |
5af5573e | 52 | #include <mach_ipi.h> |
dd46e3ca | 53 | #include <mach_apic.h> |
5af5573e | 54 | |
13a79503 EB |
55 | struct irq_cfg { |
56 | cpumask_t domain; | |
61014292 EB |
57 | cpumask_t old_domain; |
58 | unsigned move_cleanup_count; | |
13a79503 | 59 | u8 vector; |
61014292 | 60 | u8 move_in_progress : 1; |
13a79503 EB |
61 | }; |
62 | ||
63 | /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */ | |
7223daf5 | 64 | static struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = { |
bc5e81a1 EB |
65 | [0] = { .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, }, |
66 | [1] = { .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, }, | |
67 | [2] = { .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, }, | |
68 | [3] = { .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, }, | |
69 | [4] = { .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, }, | |
70 | [5] = { .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, }, | |
71 | [6] = { .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, }, | |
72 | [7] = { .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, }, | |
73 | [8] = { .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, }, | |
74 | [9] = { .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, }, | |
75 | [10] = { .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, }, | |
76 | [11] = { .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, }, | |
77 | [12] = { .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, }, | |
78 | [13] = { .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, }, | |
79 | [14] = { .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, }, | |
80 | [15] = { .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, }, | |
13a79503 EB |
81 | }; |
82 | ||
dfbffdd8 | 83 | static int assign_irq_vector(int irq, cpumask_t mask); |
04b9267b | 84 | |
305b92a2 AM |
85 | int first_system_vector = 0xfe; |
86 | ||
87 | char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE}; | |
88 | ||
1da177e4 LT |
89 | #define __apicdebuginit __init |
90 | ||
91 | int sis_apic_bug; /* not actually supported, dummy for compile */ | |
92 | ||
14d98cad AK |
93 | static int no_timer_check; |
94 | ||
fea5f1e1 LT |
95 | static int disable_timer_pin_1 __initdata; |
96 | ||
e2079c43 RW |
97 | static bool mask_ioapic_irq_2 __initdata; |
98 | ||
99 | void __init force_mask_ioapic_irq_2(void) | |
100 | { | |
101 | mask_ioapic_irq_2 = true; | |
102 | } | |
103 | ||
35542c5e | 104 | int timer_through_8259 __initdata; |
fea5f1e1 | 105 | |
1008fddc EB |
106 | /* Where if anywhere is the i8259 connect in external int mode */ |
107 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
108 | ||
1da177e4 | 109 | static DEFINE_SPINLOCK(ioapic_lock); |
70a0a535 | 110 | DEFINE_SPINLOCK(vector_lock); |
1da177e4 LT |
111 | |
112 | /* | |
113 | * # of IRQ routing registers | |
114 | */ | |
115 | int nr_ioapic_registers[MAX_IO_APICS]; | |
116 | ||
9c7408f3 | 117 | /* I/O APIC entries */ |
ec2cd0a2 | 118 | struct mp_config_ioapic mp_ioapics[MAX_IO_APICS]; |
9c7408f3 AS |
119 | int nr_ioapics; |
120 | ||
350bae1d | 121 | /* MP IRQ source entries */ |
2fddb6e2 | 122 | struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
350bae1d AS |
123 | |
124 | /* # of MP IRQ source entries */ | |
125 | int mp_irq_entries; | |
126 | ||
8732fc4b AS |
127 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); |
128 | ||
1da177e4 LT |
129 | /* |
130 | * Rough estimation of how many shared IRQs there are, can | |
131 | * be changed anytime. | |
132 | */ | |
e273d140 | 133 | #define MAX_PLUS_SHARED_IRQS NR_IRQS |
1da177e4 LT |
134 | #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS) |
135 | ||
136 | /* | |
137 | * This is performance-critical, we want to do it O(1) | |
138 | * | |
139 | * the indexing order of this array favors 1:1 mappings | |
140 | * between pins and IRQs. | |
141 | */ | |
142 | ||
143 | static struct irq_pin_list { | |
144 | short apic, pin, next; | |
145 | } irq_2_pin[PIN_MAP_SIZE]; | |
146 | ||
6c0ffb9d LT |
147 | struct io_apic { |
148 | unsigned int index; | |
149 | unsigned int unused[3]; | |
150 | unsigned int data; | |
151 | }; | |
152 | ||
153 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
154 | { | |
155 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
ec2cd0a2 | 156 | + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK); |
6c0ffb9d LT |
157 | } |
158 | ||
159 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) | |
160 | { | |
161 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
162 | writel(reg, &io_apic->index); | |
163 | return readl(&io_apic->data); | |
164 | } | |
165 | ||
166 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) | |
167 | { | |
168 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
169 | writel(reg, &io_apic->index); | |
170 | writel(value, &io_apic->data); | |
171 | } | |
172 | ||
173 | /* | |
174 | * Re-write a value: to be used for read-modify-write | |
175 | * cycles where the read already set up the index register. | |
176 | */ | |
177 | static inline void io_apic_modify(unsigned int apic, unsigned int value) | |
178 | { | |
179 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
180 | writel(value, &io_apic->data); | |
181 | } | |
182 | ||
9d25cb08 | 183 | static bool io_apic_level_ack_pending(unsigned int irq) |
ef3e28c5 EB |
184 | { |
185 | struct irq_pin_list *entry; | |
186 | unsigned long flags; | |
ef3e28c5 EB |
187 | |
188 | spin_lock_irqsave(&ioapic_lock, flags); | |
189 | entry = irq_2_pin + irq; | |
190 | for (;;) { | |
191 | unsigned int reg; | |
192 | int pin; | |
193 | ||
194 | pin = entry->pin; | |
195 | if (pin == -1) | |
196 | break; | |
197 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
198 | /* Is the remote IRR bit set? */ | |
46b3b4ef | 199 | if (reg & IO_APIC_REDIR_REMOTE_IRR) { |
9d25cb08 AM |
200 | spin_unlock_irqrestore(&ioapic_lock, flags); |
201 | return true; | |
202 | } | |
ef3e28c5 EB |
203 | if (!entry->next) |
204 | break; | |
205 | entry = irq_2_pin + entry->next; | |
206 | } | |
207 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
9d25cb08 AM |
208 | |
209 | return false; | |
ef3e28c5 EB |
210 | } |
211 | ||
6c0ffb9d LT |
212 | /* |
213 | * Synchronize the IO-APIC and the CPU by doing | |
214 | * a dummy read from the IO-APIC | |
215 | */ | |
216 | static inline void io_apic_sync(unsigned int apic) | |
217 | { | |
218 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
219 | readl(&io_apic->data); | |
220 | } | |
221 | ||
54d5d424 AR |
222 | #define __DO_ACTION(R, ACTION, FINAL) \ |
223 | \ | |
224 | { \ | |
225 | int pin; \ | |
226 | struct irq_pin_list *entry = irq_2_pin + irq; \ | |
227 | \ | |
6004e1b7 | 228 | BUG_ON(irq >= NR_IRQS); \ |
54d5d424 AR |
229 | for (;;) { \ |
230 | unsigned int reg; \ | |
231 | pin = entry->pin; \ | |
232 | if (pin == -1) \ | |
233 | break; \ | |
234 | reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \ | |
235 | reg ACTION; \ | |
236 | io_apic_modify(entry->apic, reg); \ | |
f45bcd70 | 237 | FINAL; \ |
54d5d424 AR |
238 | if (!entry->next) \ |
239 | break; \ | |
240 | entry = irq_2_pin + entry->next; \ | |
241 | } \ | |
54d5d424 AR |
242 | } |
243 | ||
eea0e11c AK |
244 | union entry_union { |
245 | struct { u32 w1, w2; }; | |
246 | struct IO_APIC_route_entry entry; | |
247 | }; | |
248 | ||
249 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) | |
250 | { | |
251 | union entry_union eu; | |
252 | unsigned long flags; | |
253 | spin_lock_irqsave(&ioapic_lock, flags); | |
254 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); | |
255 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
256 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
257 | return eu.entry; | |
258 | } | |
259 | ||
48797ebd LT |
260 | /* |
261 | * When we write a new IO APIC routing entry, we need to write the high | |
262 | * word first! If the mask bit in the low word is clear, we will enable | |
263 | * the interrupt, and we need to make sure the entry is fully populated | |
264 | * before that happens. | |
265 | */ | |
516d2836 AK |
266 | static void |
267 | __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
eea0e11c | 268 | { |
eea0e11c AK |
269 | union entry_union eu; |
270 | eu.entry = e; | |
48797ebd LT |
271 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
272 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
516d2836 AK |
273 | } |
274 | ||
275 | static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
276 | { | |
277 | unsigned long flags; | |
278 | spin_lock_irqsave(&ioapic_lock, flags); | |
279 | __ioapic_write_entry(apic, pin, e); | |
48797ebd LT |
280 | spin_unlock_irqrestore(&ioapic_lock, flags); |
281 | } | |
282 | ||
283 | /* | |
284 | * When we mask an IO APIC routing entry, we need to write the low | |
285 | * word first, in order to set the mask bit before we change the | |
286 | * high bits! | |
287 | */ | |
288 | static void ioapic_mask_entry(int apic, int pin) | |
289 | { | |
290 | unsigned long flags; | |
291 | union entry_union eu = { .entry.mask = 1 }; | |
292 | ||
eea0e11c AK |
293 | spin_lock_irqsave(&ioapic_lock, flags); |
294 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
295 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
296 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
297 | } | |
298 | ||
54d5d424 | 299 | #ifdef CONFIG_SMP |
550f2299 EB |
300 | static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector) |
301 | { | |
302 | int apic, pin; | |
303 | struct irq_pin_list *entry = irq_2_pin + irq; | |
304 | ||
305 | BUG_ON(irq >= NR_IRQS); | |
306 | for (;;) { | |
307 | unsigned int reg; | |
308 | apic = entry->apic; | |
309 | pin = entry->pin; | |
310 | if (pin == -1) | |
311 | break; | |
312 | io_apic_write(apic, 0x11 + pin*2, dest); | |
313 | reg = io_apic_read(apic, 0x10 + pin*2); | |
46b3b4ef | 314 | reg &= ~IO_APIC_REDIR_VECTOR_MASK; |
550f2299 EB |
315 | reg |= vector; |
316 | io_apic_modify(apic, reg); | |
317 | if (!entry->next) | |
318 | break; | |
319 | entry = irq_2_pin + entry->next; | |
320 | } | |
321 | } | |
322 | ||
54d5d424 AR |
323 | static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask) |
324 | { | |
dfbffdd8 | 325 | struct irq_cfg *cfg = irq_cfg + irq; |
54d5d424 AR |
326 | unsigned long flags; |
327 | unsigned int dest; | |
328 | cpumask_t tmp; | |
329 | ||
330 | cpus_and(tmp, mask, cpu_online_map); | |
331 | if (cpus_empty(tmp)) | |
5ff5115e | 332 | return; |
54d5d424 | 333 | |
dfbffdd8 | 334 | if (assign_irq_vector(irq, mask)) |
550f2299 EB |
335 | return; |
336 | ||
dfbffdd8 | 337 | cpus_and(tmp, cfg->domain, mask); |
550f2299 | 338 | dest = cpu_mask_to_apicid(tmp); |
54d5d424 AR |
339 | |
340 | /* | |
341 | * Only the high 8 bits are valid. | |
342 | */ | |
343 | dest = SET_APIC_LOGICAL_ID(dest); | |
344 | ||
345 | spin_lock_irqsave(&ioapic_lock, flags); | |
dfbffdd8 | 346 | __target_IO_APIC_irq(irq, dest, cfg->vector); |
9f0a5ba5 | 347 | irq_desc[irq].affinity = mask; |
54d5d424 AR |
348 | spin_unlock_irqrestore(&ioapic_lock, flags); |
349 | } | |
350 | #endif | |
351 | ||
1da177e4 LT |
352 | /* |
353 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
354 | * shared ISA-space IRQs, so we have to support them. We are super | |
355 | * fast in the common case, and fast for shared ISA-space IRQs. | |
356 | */ | |
357 | static void add_pin_to_irq(unsigned int irq, int apic, int pin) | |
358 | { | |
359 | static int first_free_entry = NR_IRQS; | |
360 | struct irq_pin_list *entry = irq_2_pin + irq; | |
361 | ||
6004e1b7 | 362 | BUG_ON(irq >= NR_IRQS); |
1da177e4 LT |
363 | while (entry->next) |
364 | entry = irq_2_pin + entry->next; | |
365 | ||
366 | if (entry->pin != -1) { | |
367 | entry->next = first_free_entry; | |
368 | entry = irq_2_pin + entry->next; | |
369 | if (++first_free_entry >= PIN_MAP_SIZE) | |
6004e1b7 | 370 | panic("io_apic.c: ran out of irq_2_pin entries!"); |
1da177e4 LT |
371 | } |
372 | entry->apic = apic; | |
373 | entry->pin = pin; | |
374 | } | |
375 | ||
0b9f4f49 MR |
376 | /* |
377 | * Reroute an IRQ to a different pin. | |
378 | */ | |
379 | static void __init replace_pin_at_irq(unsigned int irq, | |
380 | int oldapic, int oldpin, | |
381 | int newapic, int newpin) | |
382 | { | |
383 | struct irq_pin_list *entry = irq_2_pin + irq; | |
384 | ||
385 | while (1) { | |
386 | if (entry->apic == oldapic && entry->pin == oldpin) { | |
387 | entry->apic = newapic; | |
388 | entry->pin = newpin; | |
389 | } | |
390 | if (!entry->next) | |
391 | break; | |
392 | entry = irq_2_pin + entry->next; | |
393 | } | |
394 | } | |
395 | ||
1da177e4 LT |
396 | |
397 | #define DO_ACTION(name,R,ACTION, FINAL) \ | |
398 | \ | |
399 | static void name##_IO_APIC_irq (unsigned int irq) \ | |
400 | __DO_ACTION(R, ACTION, FINAL) | |
401 | ||
46b3b4ef CG |
402 | /* mask = 1 */ |
403 | DO_ACTION(__mask, 0, |= IO_APIC_REDIR_MASKED, io_apic_sync(entry->apic)) | |
404 | ||
405 | /* mask = 0 */ | |
406 | DO_ACTION(__unmask, 0, &= ~IO_APIC_REDIR_MASKED, ) | |
1da177e4 LT |
407 | |
408 | static void mask_IO_APIC_irq (unsigned int irq) | |
409 | { | |
410 | unsigned long flags; | |
411 | ||
412 | spin_lock_irqsave(&ioapic_lock, flags); | |
413 | __mask_IO_APIC_irq(irq); | |
414 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
415 | } | |
416 | ||
417 | static void unmask_IO_APIC_irq (unsigned int irq) | |
418 | { | |
419 | unsigned long flags; | |
420 | ||
421 | spin_lock_irqsave(&ioapic_lock, flags); | |
422 | __unmask_IO_APIC_irq(irq); | |
423 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
424 | } | |
425 | ||
426 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) | |
427 | { | |
428 | struct IO_APIC_route_entry entry; | |
1da177e4 LT |
429 | |
430 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ | |
eea0e11c | 431 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
432 | if (entry.delivery_mode == dest_SMI) |
433 | return; | |
434 | /* | |
435 | * Disable it in the IO-APIC irq-routing table: | |
436 | */ | |
48797ebd | 437 | ioapic_mask_entry(apic, pin); |
1da177e4 LT |
438 | } |
439 | ||
440 | static void clear_IO_APIC (void) | |
441 | { | |
442 | int apic, pin; | |
443 | ||
444 | for (apic = 0; apic < nr_ioapics; apic++) | |
445 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) | |
446 | clear_IO_APIC_pin(apic, pin); | |
447 | } | |
448 | ||
1da177e4 LT |
449 | int skip_ioapic_setup; |
450 | int ioapic_force; | |
451 | ||
61ec7567 | 452 | static int __init parse_noapic(char *str) |
1da177e4 | 453 | { |
61ec7567 | 454 | disable_ioapic_setup(); |
2c8c0e6b | 455 | return 0; |
1da177e4 | 456 | } |
61ec7567 | 457 | early_param("noapic", parse_noapic); |
1da177e4 | 458 | |
fea5f1e1 LT |
459 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
460 | static int __init disable_timer_pin_setup(char *arg) | |
461 | { | |
462 | disable_timer_pin_1 = 1; | |
463 | return 1; | |
464 | } | |
465 | __setup("disable_timer_pin_1", disable_timer_pin_setup); | |
466 | ||
fea5f1e1 | 467 | |
1da177e4 LT |
468 | /* |
469 | * Find the IRQ entry number of a certain pin. | |
470 | */ | |
471 | static int find_irq_entry(int apic, int pin, int type) | |
472 | { | |
473 | int i; | |
474 | ||
475 | for (i = 0; i < mp_irq_entries; i++) | |
2fddb6e2 AS |
476 | if (mp_irqs[i].mp_irqtype == type && |
477 | (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid || | |
478 | mp_irqs[i].mp_dstapic == MP_APIC_ALL) && | |
479 | mp_irqs[i].mp_dstirq == pin) | |
1da177e4 LT |
480 | return i; |
481 | ||
482 | return -1; | |
483 | } | |
484 | ||
485 | /* | |
486 | * Find the pin to which IRQ[irq] (ISA) is connected | |
487 | */ | |
1008fddc | 488 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
489 | { |
490 | int i; | |
491 | ||
492 | for (i = 0; i < mp_irq_entries; i++) { | |
2fddb6e2 | 493 | int lbus = mp_irqs[i].mp_srcbus; |
1da177e4 | 494 | |
55f05ffa | 495 | if (test_bit(lbus, mp_bus_not_pci) && |
2fddb6e2 AS |
496 | (mp_irqs[i].mp_irqtype == type) && |
497 | (mp_irqs[i].mp_srcbusirq == irq)) | |
1da177e4 | 498 | |
2fddb6e2 | 499 | return mp_irqs[i].mp_dstirq; |
1da177e4 LT |
500 | } |
501 | return -1; | |
502 | } | |
503 | ||
1008fddc EB |
504 | static int __init find_isa_irq_apic(int irq, int type) |
505 | { | |
506 | int i; | |
507 | ||
508 | for (i = 0; i < mp_irq_entries; i++) { | |
2fddb6e2 | 509 | int lbus = mp_irqs[i].mp_srcbus; |
1008fddc | 510 | |
55f05ffa | 511 | if (test_bit(lbus, mp_bus_not_pci) && |
2fddb6e2 AS |
512 | (mp_irqs[i].mp_irqtype == type) && |
513 | (mp_irqs[i].mp_srcbusirq == irq)) | |
1008fddc EB |
514 | break; |
515 | } | |
516 | if (i < mp_irq_entries) { | |
517 | int apic; | |
518 | for(apic = 0; apic < nr_ioapics; apic++) { | |
2fddb6e2 | 519 | if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic) |
1008fddc EB |
520 | return apic; |
521 | } | |
522 | } | |
523 | ||
524 | return -1; | |
525 | } | |
526 | ||
1da177e4 LT |
527 | /* |
528 | * Find a specific PCI IRQ entry. | |
529 | * Not an __init, possibly needed by modules | |
530 | */ | |
531 | static int pin_2_irq(int idx, int apic, int pin); | |
532 | ||
533 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin) | |
534 | { | |
535 | int apic, i, best_guess = -1; | |
536 | ||
537 | apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", | |
538 | bus, slot, pin); | |
ce6444d3 | 539 | if (test_bit(bus, mp_bus_not_pci)) { |
1da177e4 LT |
540 | apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus); |
541 | return -1; | |
542 | } | |
543 | for (i = 0; i < mp_irq_entries; i++) { | |
2fddb6e2 | 544 | int lbus = mp_irqs[i].mp_srcbus; |
1da177e4 LT |
545 | |
546 | for (apic = 0; apic < nr_ioapics; apic++) | |
2fddb6e2 AS |
547 | if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic || |
548 | mp_irqs[i].mp_dstapic == MP_APIC_ALL) | |
1da177e4 LT |
549 | break; |
550 | ||
55f05ffa | 551 | if (!test_bit(lbus, mp_bus_not_pci) && |
2fddb6e2 | 552 | !mp_irqs[i].mp_irqtype && |
1da177e4 | 553 | (bus == lbus) && |
2fddb6e2 AS |
554 | (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) { |
555 | int irq = pin_2_irq(i,apic,mp_irqs[i].mp_dstirq); | |
1da177e4 LT |
556 | |
557 | if (!(apic || IO_APIC_IRQ(irq))) | |
558 | continue; | |
559 | ||
2fddb6e2 | 560 | if (pin == (mp_irqs[i].mp_srcbusirq & 3)) |
1da177e4 LT |
561 | return irq; |
562 | /* | |
563 | * Use the first all-but-pin matching entry as a | |
564 | * best-guess fuzzy result for broken mptables. | |
565 | */ | |
566 | if (best_guess < 0) | |
567 | best_guess = irq; | |
568 | } | |
569 | } | |
6004e1b7 | 570 | BUG_ON(best_guess >= NR_IRQS); |
1da177e4 LT |
571 | return best_guess; |
572 | } | |
573 | ||
1da177e4 LT |
574 | /* ISA interrupts are always polarity zero edge triggered, |
575 | * when listed as conforming in the MP table. */ | |
576 | ||
577 | #define default_ISA_trigger(idx) (0) | |
578 | #define default_ISA_polarity(idx) (0) | |
579 | ||
580 | /* PCI interrupts are always polarity one level triggered, | |
581 | * when listed as conforming in the MP table. */ | |
582 | ||
583 | #define default_PCI_trigger(idx) (1) | |
584 | #define default_PCI_polarity(idx) (1) | |
585 | ||
61fd47e0 | 586 | static int MPBIOS_polarity(int idx) |
1da177e4 | 587 | { |
2fddb6e2 | 588 | int bus = mp_irqs[idx].mp_srcbus; |
1da177e4 LT |
589 | int polarity; |
590 | ||
591 | /* | |
592 | * Determine IRQ line polarity (high active or low active): | |
593 | */ | |
2fddb6e2 | 594 | switch (mp_irqs[idx].mp_irqflag & 3) |
1da177e4 LT |
595 | { |
596 | case 0: /* conforms, ie. bus-type dependent polarity */ | |
55f05ffa AK |
597 | if (test_bit(bus, mp_bus_not_pci)) |
598 | polarity = default_ISA_polarity(idx); | |
599 | else | |
600 | polarity = default_PCI_polarity(idx); | |
1da177e4 | 601 | break; |
1da177e4 LT |
602 | case 1: /* high active */ |
603 | { | |
604 | polarity = 0; | |
605 | break; | |
606 | } | |
607 | case 2: /* reserved */ | |
608 | { | |
609 | printk(KERN_WARNING "broken BIOS!!\n"); | |
610 | polarity = 1; | |
611 | break; | |
612 | } | |
613 | case 3: /* low active */ | |
614 | { | |
615 | polarity = 1; | |
616 | break; | |
617 | } | |
618 | default: /* invalid */ | |
619 | { | |
620 | printk(KERN_WARNING "broken BIOS!!\n"); | |
621 | polarity = 1; | |
622 | break; | |
623 | } | |
624 | } | |
625 | return polarity; | |
626 | } | |
627 | ||
628 | static int MPBIOS_trigger(int idx) | |
629 | { | |
2fddb6e2 | 630 | int bus = mp_irqs[idx].mp_srcbus; |
1da177e4 LT |
631 | int trigger; |
632 | ||
633 | /* | |
634 | * Determine IRQ trigger mode (edge or level sensitive): | |
635 | */ | |
2fddb6e2 | 636 | switch ((mp_irqs[idx].mp_irqflag>>2) & 3) |
1da177e4 LT |
637 | { |
638 | case 0: /* conforms, ie. bus-type dependent */ | |
55f05ffa AK |
639 | if (test_bit(bus, mp_bus_not_pci)) |
640 | trigger = default_ISA_trigger(idx); | |
641 | else | |
642 | trigger = default_PCI_trigger(idx); | |
1da177e4 | 643 | break; |
1da177e4 LT |
644 | case 1: /* edge */ |
645 | { | |
646 | trigger = 0; | |
647 | break; | |
648 | } | |
649 | case 2: /* reserved */ | |
650 | { | |
651 | printk(KERN_WARNING "broken BIOS!!\n"); | |
652 | trigger = 1; | |
653 | break; | |
654 | } | |
655 | case 3: /* level */ | |
656 | { | |
657 | trigger = 1; | |
658 | break; | |
659 | } | |
660 | default: /* invalid */ | |
661 | { | |
662 | printk(KERN_WARNING "broken BIOS!!\n"); | |
663 | trigger = 0; | |
664 | break; | |
665 | } | |
666 | } | |
667 | return trigger; | |
668 | } | |
669 | ||
670 | static inline int irq_polarity(int idx) | |
671 | { | |
672 | return MPBIOS_polarity(idx); | |
673 | } | |
674 | ||
675 | static inline int irq_trigger(int idx) | |
676 | { | |
677 | return MPBIOS_trigger(idx); | |
678 | } | |
679 | ||
680 | static int pin_2_irq(int idx, int apic, int pin) | |
681 | { | |
682 | int irq, i; | |
2fddb6e2 | 683 | int bus = mp_irqs[idx].mp_srcbus; |
1da177e4 LT |
684 | |
685 | /* | |
686 | * Debugging check, we are in big trouble if this message pops up! | |
687 | */ | |
2fddb6e2 | 688 | if (mp_irqs[idx].mp_dstirq != pin) |
1da177e4 LT |
689 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); |
690 | ||
55f05ffa | 691 | if (test_bit(bus, mp_bus_not_pci)) { |
2fddb6e2 | 692 | irq = mp_irqs[idx].mp_srcbusirq; |
55f05ffa AK |
693 | } else { |
694 | /* | |
695 | * PCI IRQs are mapped in order | |
696 | */ | |
697 | i = irq = 0; | |
698 | while (i < apic) | |
699 | irq += nr_ioapic_registers[i++]; | |
700 | irq += pin; | |
1da177e4 | 701 | } |
6004e1b7 | 702 | BUG_ON(irq >= NR_IRQS); |
1da177e4 LT |
703 | return irq; |
704 | } | |
705 | ||
dfbffdd8 | 706 | static int __assign_irq_vector(int irq, cpumask_t mask) |
1da177e4 | 707 | { |
550f2299 EB |
708 | /* |
709 | * NOTE! The local APIC isn't very good at handling | |
710 | * multiple interrupts at the same interrupt level. | |
711 | * As the interrupt level is determined by taking the | |
712 | * vector number and shifting that right by 4, we | |
713 | * want to spread these out a bit so that they don't | |
714 | * all fall in the same interrupt level. | |
715 | * | |
716 | * Also, we've got to be careful not to trash gate | |
717 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
718 | */ | |
d1752aa8 | 719 | static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0; |
dfbffdd8 | 720 | unsigned int old_vector; |
550f2299 | 721 | int cpu; |
13a79503 | 722 | struct irq_cfg *cfg; |
1da177e4 | 723 | |
e273d140 | 724 | BUG_ON((unsigned)irq >= NR_IRQS); |
13a79503 | 725 | cfg = &irq_cfg[irq]; |
0a1ad60d | 726 | |
70a0a535 EB |
727 | /* Only try and allocate irqs on cpus that are present */ |
728 | cpus_and(mask, mask, cpu_online_map); | |
729 | ||
61014292 EB |
730 | if ((cfg->move_in_progress) || cfg->move_cleanup_count) |
731 | return -EBUSY; | |
732 | ||
dfbffdd8 EB |
733 | old_vector = cfg->vector; |
734 | if (old_vector) { | |
735 | cpumask_t tmp; | |
736 | cpus_and(tmp, cfg->domain, mask); | |
737 | if (!cpus_empty(tmp)) | |
738 | return 0; | |
0a1ad60d | 739 | } |
550f2299 EB |
740 | |
741 | for_each_cpu_mask(cpu, mask) { | |
70a0a535 | 742 | cpumask_t domain, new_mask; |
61014292 | 743 | int new_cpu; |
550f2299 | 744 | int vector, offset; |
c7111c13 EB |
745 | |
746 | domain = vector_allocation_domain(cpu); | |
70a0a535 | 747 | cpus_and(new_mask, domain, cpu_online_map); |
c7111c13 | 748 | |
d1752aa8 EB |
749 | vector = current_vector; |
750 | offset = current_offset; | |
1da177e4 | 751 | next: |
550f2299 | 752 | vector += 8; |
305b92a2 | 753 | if (vector >= first_system_vector) { |
550f2299 EB |
754 | /* If we run out of vectors on large boxen, must share them. */ |
755 | offset = (offset + 1) % 8; | |
756 | vector = FIRST_DEVICE_VECTOR + offset; | |
757 | } | |
d1752aa8 | 758 | if (unlikely(current_vector == vector)) |
550f2299 EB |
759 | continue; |
760 | if (vector == IA32_SYSCALL_VECTOR) | |
761 | goto next; | |
70a0a535 | 762 | for_each_cpu_mask(new_cpu, new_mask) |
45edfd1d | 763 | if (per_cpu(vector_irq, new_cpu)[vector] != -1) |
c7111c13 | 764 | goto next; |
550f2299 | 765 | /* Found one! */ |
d1752aa8 EB |
766 | current_vector = vector; |
767 | current_offset = offset; | |
61014292 EB |
768 | if (old_vector) { |
769 | cfg->move_in_progress = 1; | |
770 | cfg->old_domain = cfg->domain; | |
771 | } | |
70a0a535 | 772 | for_each_cpu_mask(new_cpu, new_mask) |
c7111c13 | 773 | per_cpu(vector_irq, new_cpu)[vector] = irq; |
13a79503 EB |
774 | cfg->vector = vector; |
775 | cfg->domain = domain; | |
dfbffdd8 | 776 | return 0; |
1da177e4 | 777 | } |
550f2299 | 778 | return -ENOSPC; |
04b9267b EB |
779 | } |
780 | ||
dfbffdd8 | 781 | static int assign_irq_vector(int irq, cpumask_t mask) |
04b9267b | 782 | { |
dfbffdd8 | 783 | int err; |
04b9267b | 784 | unsigned long flags; |
0a1ad60d | 785 | |
04b9267b | 786 | spin_lock_irqsave(&vector_lock, flags); |
dfbffdd8 | 787 | err = __assign_irq_vector(irq, mask); |
26a3c49c | 788 | spin_unlock_irqrestore(&vector_lock, flags); |
dfbffdd8 | 789 | return err; |
1da177e4 LT |
790 | } |
791 | ||
5df0287e YL |
792 | static void __clear_irq_vector(int irq) |
793 | { | |
13a79503 | 794 | struct irq_cfg *cfg; |
5df0287e YL |
795 | cpumask_t mask; |
796 | int cpu, vector; | |
797 | ||
13a79503 EB |
798 | BUG_ON((unsigned)irq >= NR_IRQS); |
799 | cfg = &irq_cfg[irq]; | |
800 | BUG_ON(!cfg->vector); | |
5df0287e | 801 | |
13a79503 EB |
802 | vector = cfg->vector; |
803 | cpus_and(mask, cfg->domain, cpu_online_map); | |
5df0287e YL |
804 | for_each_cpu_mask(cpu, mask) |
805 | per_cpu(vector_irq, cpu)[vector] = -1; | |
806 | ||
13a79503 | 807 | cfg->vector = 0; |
d366f8cb | 808 | cpus_clear(cfg->domain); |
5df0287e YL |
809 | } |
810 | ||
3fde6900 | 811 | static void __setup_vector_irq(int cpu) |
70a0a535 EB |
812 | { |
813 | /* Initialize vector_irq on a new cpu */ | |
814 | /* This function must be called with vector_lock held */ | |
70a0a535 EB |
815 | int irq, vector; |
816 | ||
70a0a535 | 817 | /* Mark the inuse vectors */ |
e273d140 | 818 | for (irq = 0; irq < NR_IRQS; ++irq) { |
13a79503 | 819 | if (!cpu_isset(cpu, irq_cfg[irq].domain)) |
70a0a535 | 820 | continue; |
13a79503 | 821 | vector = irq_cfg[irq].vector; |
70a0a535 EB |
822 | per_cpu(vector_irq, cpu)[vector] = irq; |
823 | } | |
824 | /* Mark the free vectors */ | |
825 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
826 | irq = per_cpu(vector_irq, cpu)[vector]; | |
827 | if (irq < 0) | |
828 | continue; | |
13a79503 | 829 | if (!cpu_isset(cpu, irq_cfg[irq].domain)) |
70a0a535 EB |
830 | per_cpu(vector_irq, cpu)[vector] = -1; |
831 | } | |
832 | } | |
833 | ||
3fde6900 GC |
834 | void setup_vector_irq(int cpu) |
835 | { | |
836 | spin_lock(&vector_lock); | |
837 | __setup_vector_irq(smp_processor_id()); | |
838 | spin_unlock(&vector_lock); | |
839 | } | |
840 | ||
70a0a535 | 841 | |
f29bd1ba | 842 | static struct irq_chip ioapic_chip; |
1da177e4 | 843 | |
a27bc06d | 844 | static void ioapic_register_intr(int irq, unsigned long trigger) |
1da177e4 | 845 | { |
cc75b92d TG |
846 | if (trigger) { |
847 | irq_desc[irq].status |= IRQ_LEVEL; | |
a460e745 IM |
848 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
849 | handle_fasteoi_irq, "fasteoi"); | |
cc75b92d TG |
850 | } else { |
851 | irq_desc[irq].status &= ~IRQ_LEVEL; | |
a460e745 IM |
852 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
853 | handle_edge_irq, "edge"); | |
cc75b92d | 854 | } |
1da177e4 | 855 | } |
a8c8a367 EB |
856 | |
857 | static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq, | |
858 | int trigger, int polarity) | |
1da177e4 | 859 | { |
dfbffdd8 | 860 | struct irq_cfg *cfg = irq_cfg + irq; |
1da177e4 | 861 | struct IO_APIC_route_entry entry; |
a8c8a367 | 862 | cpumask_t mask; |
1da177e4 | 863 | |
a8c8a367 EB |
864 | if (!IO_APIC_IRQ(irq)) |
865 | return; | |
866 | ||
dfbffdd8 EB |
867 | mask = TARGET_CPUS; |
868 | if (assign_irq_vector(irq, mask)) | |
a8c8a367 EB |
869 | return; |
870 | ||
dfbffdd8 EB |
871 | cpus_and(mask, cfg->domain, mask); |
872 | ||
a8c8a367 EB |
873 | apic_printk(APIC_VERBOSE,KERN_DEBUG |
874 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " | |
875 | "IRQ %d Mode:%i Active:%i)\n", | |
ec2cd0a2 | 876 | apic, mp_ioapics[apic].mp_apicid, pin, cfg->vector, |
a8c8a367 | 877 | irq, trigger, polarity); |
1da177e4 | 878 | |
ad892f5e YL |
879 | /* |
880 | * add it to the IO-APIC irq-routing table: | |
881 | */ | |
882 | memset(&entry,0,sizeof(entry)); | |
1da177e4 | 883 | |
ad892f5e YL |
884 | entry.delivery_mode = INT_DELIVERY_MODE; |
885 | entry.dest_mode = INT_DEST_MODE; | |
a8c8a367 | 886 | entry.dest = cpu_mask_to_apicid(mask); |
ad892f5e | 887 | entry.mask = 0; /* enable IRQ */ |
a8c8a367 EB |
888 | entry.trigger = trigger; |
889 | entry.polarity = polarity; | |
dfbffdd8 | 890 | entry.vector = cfg->vector; |
1da177e4 | 891 | |
a8c8a367 EB |
892 | /* Mask level triggered irqs. |
893 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. | |
894 | */ | |
895 | if (trigger) | |
ad892f5e | 896 | entry.mask = 1; |
ad892f5e | 897 | |
a8c8a367 EB |
898 | ioapic_register_intr(irq, trigger); |
899 | if (irq < 16) | |
900 | disable_8259A_irq(irq); | |
ad892f5e YL |
901 | |
902 | ioapic_write_entry(apic, pin, entry); | |
ad892f5e YL |
903 | } |
904 | ||
905 | static void __init setup_IO_APIC_irqs(void) | |
906 | { | |
907 | int apic, pin, idx, irq, first_notcon = 1; | |
908 | ||
909 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
910 | ||
911 | for (apic = 0; apic < nr_ioapics; apic++) { | |
912 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1da177e4 LT |
913 | |
914 | idx = find_irq_entry(apic,pin,mp_INT); | |
915 | if (idx == -1) { | |
916 | if (first_notcon) { | |
ec2cd0a2 | 917 | apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mp_apicid, pin); |
1da177e4 LT |
918 | first_notcon = 0; |
919 | } else | |
ec2cd0a2 | 920 | apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mp_apicid, pin); |
1da177e4 LT |
921 | continue; |
922 | } | |
20d225b9 YL |
923 | if (!first_notcon) { |
924 | apic_printk(APIC_VERBOSE, " not connected.\n"); | |
925 | first_notcon = 1; | |
926 | } | |
1da177e4 | 927 | |
1da177e4 LT |
928 | irq = pin_2_irq(idx, apic, pin); |
929 | add_pin_to_irq(irq, apic, pin); | |
930 | ||
a8c8a367 EB |
931 | setup_IO_APIC_irq(apic, pin, irq, |
932 | irq_trigger(idx), irq_polarity(idx)); | |
1da177e4 LT |
933 | } |
934 | } | |
935 | ||
936 | if (!first_notcon) | |
20d225b9 | 937 | apic_printk(APIC_VERBOSE, " not connected.\n"); |
1da177e4 LT |
938 | } |
939 | ||
940 | /* | |
f7633ce5 | 941 | * Set up the timer pin, possibly with the 8259A-master behind. |
1da177e4 | 942 | */ |
f7633ce5 MR |
943 | static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin, |
944 | int vector) | |
1da177e4 LT |
945 | { |
946 | struct IO_APIC_route_entry entry; | |
1da177e4 | 947 | |
a2249cba | 948 | memset(&entry, 0, sizeof(entry)); |
1da177e4 | 949 | |
1da177e4 LT |
950 | /* |
951 | * We use logical delivery to get the timer IRQ | |
952 | * to the first CPU. | |
953 | */ | |
954 | entry.dest_mode = INT_DEST_MODE; | |
03be7505 | 955 | entry.mask = 1; /* mask IRQ now */ |
ee4eff6f | 956 | entry.dest = cpu_mask_to_apicid(TARGET_CPUS); |
1da177e4 LT |
957 | entry.delivery_mode = INT_DELIVERY_MODE; |
958 | entry.polarity = 0; | |
959 | entry.trigger = 0; | |
960 | entry.vector = vector; | |
961 | ||
962 | /* | |
963 | * The timer IRQ doesn't have to know that behind the | |
f7633ce5 | 964 | * scene we may have a 8259A-master in AEOI mode ... |
1da177e4 | 965 | */ |
a460e745 | 966 | set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge"); |
1da177e4 LT |
967 | |
968 | /* | |
969 | * Add it to the IO-APIC irq-routing table: | |
970 | */ | |
a2249cba | 971 | ioapic_write_entry(apic, pin, entry); |
1da177e4 LT |
972 | } |
973 | ||
1da177e4 LT |
974 | void __apicdebuginit print_IO_APIC(void) |
975 | { | |
976 | int apic, i; | |
977 | union IO_APIC_reg_00 reg_00; | |
978 | union IO_APIC_reg_01 reg_01; | |
979 | union IO_APIC_reg_02 reg_02; | |
980 | unsigned long flags; | |
981 | ||
982 | if (apic_verbosity == APIC_QUIET) | |
983 | return; | |
984 | ||
985 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); | |
986 | for (i = 0; i < nr_ioapics; i++) | |
987 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", | |
ec2cd0a2 | 988 | mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]); |
1da177e4 LT |
989 | |
990 | /* | |
991 | * We are a bit conservative about what we expect. We have to | |
992 | * know about every hardware change ASAP. | |
993 | */ | |
994 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
995 | ||
996 | for (apic = 0; apic < nr_ioapics; apic++) { | |
997 | ||
998 | spin_lock_irqsave(&ioapic_lock, flags); | |
999 | reg_00.raw = io_apic_read(apic, 0); | |
1000 | reg_01.raw = io_apic_read(apic, 1); | |
1001 | if (reg_01.bits.version >= 0x10) | |
1002 | reg_02.raw = io_apic_read(apic, 2); | |
1003 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1004 | ||
1005 | printk("\n"); | |
ec2cd0a2 | 1006 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
1007 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1008 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1da177e4 LT |
1009 | |
1010 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); | |
1011 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); | |
1da177e4 LT |
1012 | |
1013 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
1014 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); | |
1da177e4 LT |
1015 | |
1016 | if (reg_01.bits.version >= 0x10) { | |
1017 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1018 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1019 | } |
1020 | ||
1021 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1022 | ||
ee4eff6f BR |
1023 | printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol" |
1024 | " Stat Dmod Deli Vect: \n"); | |
1da177e4 LT |
1025 | |
1026 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
1027 | struct IO_APIC_route_entry entry; | |
1028 | ||
eea0e11c | 1029 | entry = ioapic_read_entry(apic, i); |
1da177e4 | 1030 | |
ee4eff6f | 1031 | printk(KERN_DEBUG " %02x %03X ", |
1da177e4 | 1032 | i, |
ee4eff6f | 1033 | entry.dest |
1da177e4 LT |
1034 | ); |
1035 | ||
1036 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", | |
1037 | entry.mask, | |
1038 | entry.trigger, | |
1039 | entry.irr, | |
1040 | entry.polarity, | |
1041 | entry.delivery_status, | |
1042 | entry.dest_mode, | |
1043 | entry.delivery_mode, | |
1044 | entry.vector | |
1045 | ); | |
1046 | } | |
1047 | } | |
1da177e4 LT |
1048 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
1049 | for (i = 0; i < NR_IRQS; i++) { | |
1050 | struct irq_pin_list *entry = irq_2_pin + i; | |
1051 | if (entry->pin < 0) | |
1052 | continue; | |
04b9267b | 1053 | printk(KERN_DEBUG "IRQ%d ", i); |
1da177e4 LT |
1054 | for (;;) { |
1055 | printk("-> %d:%d", entry->apic, entry->pin); | |
1056 | if (!entry->next) | |
1057 | break; | |
1058 | entry = irq_2_pin + entry->next; | |
1059 | } | |
1060 | printk("\n"); | |
1061 | } | |
1062 | ||
1063 | printk(KERN_INFO ".................................... done.\n"); | |
1064 | ||
1065 | return; | |
1066 | } | |
1067 | ||
1068 | #if 0 | |
1069 | ||
1070 | static __apicdebuginit void print_APIC_bitfield (int base) | |
1071 | { | |
1072 | unsigned int v; | |
1073 | int i, j; | |
1074 | ||
1075 | if (apic_verbosity == APIC_QUIET) | |
1076 | return; | |
1077 | ||
1078 | printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG); | |
1079 | for (i = 0; i < 8; i++) { | |
1080 | v = apic_read(base + i*0x10); | |
1081 | for (j = 0; j < 32; j++) { | |
1082 | if (v & (1<<j)) | |
1083 | printk("1"); | |
1084 | else | |
1085 | printk("0"); | |
1086 | } | |
1087 | printk("\n"); | |
1088 | } | |
1089 | } | |
1090 | ||
1091 | void __apicdebuginit print_local_APIC(void * dummy) | |
1092 | { | |
1093 | unsigned int v, ver, maxlvt; | |
1094 | ||
1095 | if (apic_verbosity == APIC_QUIET) | |
1096 | return; | |
1097 | ||
1098 | printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", | |
1099 | smp_processor_id(), hard_smp_processor_id()); | |
66823114 | 1100 | v = apic_read(APIC_ID); |
05f2d12c | 1101 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(read_apic_id())); |
1da177e4 LT |
1102 | v = apic_read(APIC_LVR); |
1103 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1104 | ver = GET_APIC_VERSION(v); | |
37e650c7 | 1105 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1106 | |
1107 | v = apic_read(APIC_TASKPRI); | |
1108 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1109 | ||
5a40b7c2 AK |
1110 | v = apic_read(APIC_ARBPRI); |
1111 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1112 | v & APIC_ARBPRI_MASK); | |
1113 | v = apic_read(APIC_PROCPRI); | |
1114 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1da177e4 LT |
1115 | |
1116 | v = apic_read(APIC_EOI); | |
1117 | printk(KERN_DEBUG "... APIC EOI: %08x\n", v); | |
1118 | v = apic_read(APIC_RRR); | |
1119 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1120 | v = apic_read(APIC_LDR); | |
1121 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
1122 | v = apic_read(APIC_DFR); | |
1123 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1124 | v = apic_read(APIC_SPIV); | |
1125 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1126 | ||
1127 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
1128 | print_APIC_bitfield(APIC_ISR); | |
1129 | printk(KERN_DEBUG "... APIC TMR field:\n"); | |
1130 | print_APIC_bitfield(APIC_TMR); | |
1131 | printk(KERN_DEBUG "... APIC IRR field:\n"); | |
1132 | print_APIC_bitfield(APIC_IRR); | |
1133 | ||
5a40b7c2 AK |
1134 | v = apic_read(APIC_ESR); |
1135 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1da177e4 LT |
1136 | |
1137 | v = apic_read(APIC_ICR); | |
1138 | printk(KERN_DEBUG "... APIC ICR: %08x\n", v); | |
1139 | v = apic_read(APIC_ICR2); | |
1140 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", v); | |
1141 | ||
1142 | v = apic_read(APIC_LVTT); | |
1143 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1144 | ||
1145 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1146 | v = apic_read(APIC_LVTPC); | |
1147 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1148 | } | |
1149 | v = apic_read(APIC_LVT0); | |
1150 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1151 | v = apic_read(APIC_LVT1); | |
1152 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1153 | ||
1154 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1155 | v = apic_read(APIC_LVTERR); | |
1156 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1157 | } | |
1158 | ||
1159 | v = apic_read(APIC_TMICT); | |
1160 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1161 | v = apic_read(APIC_TMCCT); | |
1162 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1163 | v = apic_read(APIC_TDCR); | |
1164 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
1165 | printk("\n"); | |
1166 | } | |
1167 | ||
1168 | void print_all_local_APICs (void) | |
1169 | { | |
1170 | on_each_cpu(print_local_APIC, NULL, 1, 1); | |
1171 | } | |
1172 | ||
1173 | void __apicdebuginit print_PIC(void) | |
1174 | { | |
1da177e4 LT |
1175 | unsigned int v; |
1176 | unsigned long flags; | |
1177 | ||
1178 | if (apic_verbosity == APIC_QUIET) | |
1179 | return; | |
1180 | ||
1181 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1182 | ||
1183 | spin_lock_irqsave(&i8259A_lock, flags); | |
1184 | ||
1185 | v = inb(0xa1) << 8 | inb(0x21); | |
1186 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1187 | ||
1188 | v = inb(0xa0) << 8 | inb(0x20); | |
1189 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1190 | ||
1191 | outb(0x0b,0xa0); | |
1192 | outb(0x0b,0x20); | |
1193 | v = inb(0xa0) << 8 | inb(0x20); | |
1194 | outb(0x0a,0xa0); | |
1195 | outb(0x0a,0x20); | |
1196 | ||
1197 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
1198 | ||
1199 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1200 | ||
1201 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1202 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1203 | } | |
1204 | ||
1205 | #endif /* 0 */ | |
1206 | ||
1c69524c | 1207 | void __init enable_IO_APIC(void) |
1da177e4 LT |
1208 | { |
1209 | union IO_APIC_reg_01 reg_01; | |
1008fddc EB |
1210 | int i8259_apic, i8259_pin; |
1211 | int i, apic; | |
1da177e4 LT |
1212 | unsigned long flags; |
1213 | ||
1214 | for (i = 0; i < PIN_MAP_SIZE; i++) { | |
1215 | irq_2_pin[i].pin = -1; | |
1216 | irq_2_pin[i].next = 0; | |
1217 | } | |
1da177e4 LT |
1218 | |
1219 | /* | |
1220 | * The number of IO-APIC IRQ registers (== #pins): | |
1221 | */ | |
1008fddc | 1222 | for (apic = 0; apic < nr_ioapics; apic++) { |
1da177e4 | 1223 | spin_lock_irqsave(&ioapic_lock, flags); |
1008fddc | 1224 | reg_01.raw = io_apic_read(apic, 1); |
1da177e4 | 1225 | spin_unlock_irqrestore(&ioapic_lock, flags); |
1008fddc EB |
1226 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; |
1227 | } | |
1228 | for(apic = 0; apic < nr_ioapics; apic++) { | |
1229 | int pin; | |
1230 | /* See if any of the pins is in ExtINT mode */ | |
1231 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1232 | struct IO_APIC_route_entry entry; | |
eea0e11c | 1233 | entry = ioapic_read_entry(apic, pin); |
1008fddc EB |
1234 | |
1235 | /* If the interrupt line is enabled and in ExtInt mode | |
1236 | * I have found the pin where the i8259 is connected. | |
1237 | */ | |
1238 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1239 | ioapic_i8259.apic = apic; | |
1240 | ioapic_i8259.pin = pin; | |
1241 | goto found_i8259; | |
1242 | } | |
1243 | } | |
1244 | } | |
1245 | found_i8259: | |
1246 | /* Look to see what if the MP table has reported the ExtINT */ | |
1247 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1248 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1249 | /* Trust the MP table if nothing is setup in the hardware */ | |
1250 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1251 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1252 | ioapic_i8259.pin = i8259_pin; | |
1253 | ioapic_i8259.apic = i8259_apic; | |
1254 | } | |
1255 | /* Complain if the MP table and the hardware disagree */ | |
1256 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1257 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1258 | { | |
1259 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1260 | } |
1261 | ||
1262 | /* | |
1263 | * Do not trust the IO-APIC being empty at bootup | |
1264 | */ | |
1265 | clear_IO_APIC(); | |
1266 | } | |
1267 | ||
1268 | /* | |
1269 | * Not an __init, needed by the reboot code | |
1270 | */ | |
1271 | void disable_IO_APIC(void) | |
1272 | { | |
1273 | /* | |
1274 | * Clear the IO-APIC before rebooting: | |
1275 | */ | |
1276 | clear_IO_APIC(); | |
1277 | ||
208fb931 | 1278 | /* |
0b968d23 | 1279 | * If the i8259 is routed through an IOAPIC |
208fb931 | 1280 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 1281 | * so legacy interrupts can be delivered. |
208fb931 | 1282 | */ |
1008fddc | 1283 | if (ioapic_i8259.pin != -1) { |
208fb931 | 1284 | struct IO_APIC_route_entry entry; |
208fb931 EB |
1285 | |
1286 | memset(&entry, 0, sizeof(entry)); | |
1287 | entry.mask = 0; /* Enabled */ | |
1288 | entry.trigger = 0; /* Edge */ | |
1289 | entry.irr = 0; | |
1290 | entry.polarity = 0; /* High */ | |
1291 | entry.delivery_status = 0; | |
1292 | entry.dest_mode = 0; /* Physical */ | |
1008fddc | 1293 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
208fb931 | 1294 | entry.vector = 0; |
05f2d12c | 1295 | entry.dest = GET_APIC_ID(read_apic_id()); |
208fb931 | 1296 | |
208fb931 EB |
1297 | /* |
1298 | * Add it to the IO-APIC irq-routing table: | |
1299 | */ | |
eea0e11c | 1300 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
208fb931 EB |
1301 | } |
1302 | ||
1008fddc | 1303 | disconnect_bsp_APIC(ioapic_i8259.pin != -1); |
1da177e4 LT |
1304 | } |
1305 | ||
1da177e4 LT |
1306 | /* |
1307 | * There is a nasty bug in some older SMP boards, their mptable lies | |
1308 | * about the timer IRQ. We do the following to work around the situation: | |
1309 | * | |
1310 | * - timer IRQ defaults to IO-APIC IRQ | |
1311 | * - if this function detects that timer IRQs are defunct, then we fall | |
1312 | * back to ISA timer IRQs | |
1313 | */ | |
1314 | static int __init timer_irq_works(void) | |
1315 | { | |
1316 | unsigned long t1 = jiffies; | |
4aae0702 | 1317 | unsigned long flags; |
1da177e4 | 1318 | |
4aae0702 | 1319 | local_save_flags(flags); |
1da177e4 LT |
1320 | local_irq_enable(); |
1321 | /* Let ten ticks pass... */ | |
1322 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 1323 | local_irq_restore(flags); |
1da177e4 LT |
1324 | |
1325 | /* | |
1326 | * Expect a few ticks at least, to be sure some possible | |
1327 | * glue logic does not lock up after one or two first | |
1328 | * ticks in a non-ExtINT mode. Also the local APIC | |
1329 | * might have cached one ExtINT interrupt. Finally, at | |
1330 | * least one tick may be lost due to delays. | |
1331 | */ | |
1332 | ||
1333 | /* jiffies wrap? */ | |
1d16b53e | 1334 | if (time_after(jiffies, t1 + 4)) |
1da177e4 LT |
1335 | return 1; |
1336 | return 0; | |
1337 | } | |
1338 | ||
1339 | /* | |
1340 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
1341 | * number of pending IRQ events unhandled. These cases are very rare, | |
1342 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
1343 | * better to do it this way as thus we do not have to be aware of | |
1344 | * 'pending' interrupts in the IRQ path, except at this point. | |
1345 | */ | |
1346 | /* | |
1347 | * Edge triggered needs to resend any interrupt | |
1348 | * that was delayed but this is now handled in the device | |
1349 | * independent code. | |
1350 | */ | |
1351 | ||
1352 | /* | |
1353 | * Starting up a edge-triggered IO-APIC interrupt is | |
1354 | * nasty - we need to make sure that we get the edge. | |
1355 | * If it is already asserted for some reason, we need | |
1356 | * return 1 to indicate that is was pending. | |
1357 | * | |
1358 | * This is not complete - we should be able to fake | |
1359 | * an edge even if it isn't on the 8259A... | |
1360 | */ | |
1361 | ||
f29bd1ba | 1362 | static unsigned int startup_ioapic_irq(unsigned int irq) |
1da177e4 LT |
1363 | { |
1364 | int was_pending = 0; | |
1365 | unsigned long flags; | |
1366 | ||
1367 | spin_lock_irqsave(&ioapic_lock, flags); | |
1368 | if (irq < 16) { | |
1369 | disable_8259A_irq(irq); | |
1370 | if (i8259A_irq_pending(irq)) | |
1371 | was_pending = 1; | |
1372 | } | |
1373 | __unmask_IO_APIC_irq(irq); | |
1374 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1375 | ||
1376 | return was_pending; | |
1377 | } | |
1378 | ||
04b9267b | 1379 | static int ioapic_retrigger_irq(unsigned int irq) |
c0ad90a3 | 1380 | { |
13a79503 | 1381 | struct irq_cfg *cfg = &irq_cfg[irq]; |
550f2299 | 1382 | cpumask_t mask; |
6bf2dafa | 1383 | unsigned long flags; |
550f2299 | 1384 | |
6bf2dafa | 1385 | spin_lock_irqsave(&vector_lock, flags); |
7281c96f | 1386 | mask = cpumask_of_cpu(first_cpu(cfg->domain)); |
13a79503 | 1387 | send_IPI_mask(mask, cfg->vector); |
6bf2dafa | 1388 | spin_unlock_irqrestore(&vector_lock, flags); |
c0ad90a3 IM |
1389 | |
1390 | return 1; | |
1391 | } | |
1392 | ||
1da177e4 LT |
1393 | /* |
1394 | * Level and edge triggered IO-APIC interrupts need different handling, | |
1395 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be | |
1396 | * handled with the level-triggered descriptor, but that one has slightly | |
1397 | * more overhead. Level-triggered interrupts cannot be handled with the | |
1398 | * edge-triggered handler, without risking IRQ storms and other ugly | |
1399 | * races. | |
1400 | */ | |
1401 | ||
61014292 EB |
1402 | #ifdef CONFIG_SMP |
1403 | asmlinkage void smp_irq_move_cleanup_interrupt(void) | |
1404 | { | |
1405 | unsigned vector, me; | |
1406 | ack_APIC_irq(); | |
1407 | exit_idle(); | |
1408 | irq_enter(); | |
1409 | ||
1410 | me = smp_processor_id(); | |
1411 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
1412 | unsigned int irq; | |
1413 | struct irq_desc *desc; | |
1414 | struct irq_cfg *cfg; | |
1415 | irq = __get_cpu_var(vector_irq)[vector]; | |
1416 | if (irq >= NR_IRQS) | |
1417 | continue; | |
1418 | ||
1419 | desc = irq_desc + irq; | |
1420 | cfg = irq_cfg + irq; | |
1421 | spin_lock(&desc->lock); | |
1422 | if (!cfg->move_cleanup_count) | |
1423 | goto unlock; | |
1424 | ||
1425 | if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) | |
1426 | goto unlock; | |
1427 | ||
1428 | __get_cpu_var(vector_irq)[vector] = -1; | |
1429 | cfg->move_cleanup_count--; | |
1430 | unlock: | |
1431 | spin_unlock(&desc->lock); | |
1432 | } | |
1433 | ||
1434 | irq_exit(); | |
1435 | } | |
1436 | ||
1437 | static void irq_complete_move(unsigned int irq) | |
1438 | { | |
1439 | struct irq_cfg *cfg = irq_cfg + irq; | |
1440 | unsigned vector, me; | |
1441 | ||
1442 | if (likely(!cfg->move_in_progress)) | |
1443 | return; | |
1444 | ||
65ea5b03 | 1445 | vector = ~get_irq_regs()->orig_ax; |
61014292 | 1446 | me = smp_processor_id(); |
f0e13ae7 | 1447 | if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) { |
61014292 EB |
1448 | cpumask_t cleanup_mask; |
1449 | ||
1450 | cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map); | |
1451 | cfg->move_cleanup_count = cpus_weight(cleanup_mask); | |
1452 | send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); | |
1453 | cfg->move_in_progress = 0; | |
1454 | } | |
1455 | } | |
1456 | #else | |
1457 | static inline void irq_complete_move(unsigned int irq) {} | |
1458 | #endif | |
1459 | ||
0be6652f EB |
1460 | static void ack_apic_edge(unsigned int irq) |
1461 | { | |
61014292 | 1462 | irq_complete_move(irq); |
0be6652f EB |
1463 | move_native_irq(irq); |
1464 | ack_APIC_irq(); | |
1465 | } | |
1466 | ||
1467 | static void ack_apic_level(unsigned int irq) | |
1468 | { | |
1469 | int do_unmask_irq = 0; | |
1470 | ||
61014292 | 1471 | irq_complete_move(irq); |
52e3d90d | 1472 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
0be6652f EB |
1473 | /* If we are moving the irq we need to mask it */ |
1474 | if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) { | |
1475 | do_unmask_irq = 1; | |
1476 | mask_IO_APIC_irq(irq); | |
1477 | } | |
1478 | #endif | |
1479 | ||
1480 | /* | |
1481 | * We must acknowledge the irq before we move it or the acknowledge will | |
beb7dd86 | 1482 | * not propagate properly. |
0be6652f EB |
1483 | */ |
1484 | ack_APIC_irq(); | |
1485 | ||
1486 | /* Now we can move and renable the irq */ | |
ef3e28c5 EB |
1487 | if (unlikely(do_unmask_irq)) { |
1488 | /* Only migrate the irq if the ack has been received. | |
1489 | * | |
1490 | * On rare occasions the broadcast level triggered ack gets | |
1491 | * delayed going to ioapics, and if we reprogram the | |
1492 | * vector while Remote IRR is still set the irq will never | |
1493 | * fire again. | |
1494 | * | |
1495 | * To prevent this scenario we read the Remote IRR bit | |
1496 | * of the ioapic. This has two effects. | |
1497 | * - On any sane system the read of the ioapic will | |
1498 | * flush writes (and acks) going to the ioapic from | |
1499 | * this cpu. | |
1500 | * - We get to see if the ACK has actually been delivered. | |
1501 | * | |
1502 | * Based on failed experiments of reprogramming the | |
1503 | * ioapic entry from outside of irq context starting | |
1504 | * with masking the ioapic entry and then polling until | |
1505 | * Remote IRR was clear before reprogramming the | |
1506 | * ioapic I don't trust the Remote IRR bit to be | |
1507 | * completey accurate. | |
1508 | * | |
1509 | * However there appears to be no other way to plug | |
1510 | * this race, so if the Remote IRR bit is not | |
1511 | * accurate and is causing problems then it is a hardware bug | |
1512 | * and you can go talk to the chipset vendor about it. | |
1513 | */ | |
1514 | if (!io_apic_level_ack_pending(irq)) | |
1515 | move_masked_irq(irq); | |
0be6652f | 1516 | unmask_IO_APIC_irq(irq); |
ef3e28c5 | 1517 | } |
0be6652f EB |
1518 | } |
1519 | ||
f29bd1ba IM |
1520 | static struct irq_chip ioapic_chip __read_mostly = { |
1521 | .name = "IO-APIC", | |
04b9267b EB |
1522 | .startup = startup_ioapic_irq, |
1523 | .mask = mask_IO_APIC_irq, | |
1524 | .unmask = unmask_IO_APIC_irq, | |
0be6652f EB |
1525 | .ack = ack_apic_edge, |
1526 | .eoi = ack_apic_level, | |
54d5d424 | 1527 | #ifdef CONFIG_SMP |
04b9267b | 1528 | .set_affinity = set_ioapic_affinity_irq, |
54d5d424 | 1529 | #endif |
04b9267b | 1530 | .retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
1531 | }; |
1532 | ||
1533 | static inline void init_IO_APIC_traps(void) | |
1534 | { | |
1535 | int irq; | |
1536 | ||
1537 | /* | |
1538 | * NOTE! The local APIC isn't very good at handling | |
1539 | * multiple interrupts at the same interrupt level. | |
1540 | * As the interrupt level is determined by taking the | |
1541 | * vector number and shifting that right by 4, we | |
1542 | * want to spread these out a bit so that they don't | |
1543 | * all fall in the same interrupt level. | |
1544 | * | |
1545 | * Also, we've got to be careful not to trash gate | |
1546 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
1547 | */ | |
1548 | for (irq = 0; irq < NR_IRQS ; irq++) { | |
addfc66b | 1549 | if (IO_APIC_IRQ(irq) && !irq_cfg[irq].vector) { |
1da177e4 LT |
1550 | /* |
1551 | * Hmm.. We don't have an entry for this, | |
1552 | * so default to an old-fashioned 8259 | |
1553 | * interrupt if we can.. | |
1554 | */ | |
1555 | if (irq < 16) | |
1556 | make_8259A_irq(irq); | |
1557 | else | |
1558 | /* Strange. Oh, well.. */ | |
f29bd1ba | 1559 | irq_desc[irq].chip = &no_irq_chip; |
1da177e4 LT |
1560 | } |
1561 | } | |
1562 | } | |
1563 | ||
c88ac1df | 1564 | static void unmask_lapic_irq(unsigned int irq) |
1da177e4 LT |
1565 | { |
1566 | unsigned long v; | |
1567 | ||
1568 | v = apic_read(APIC_LVT0); | |
11a8e778 | 1569 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
1da177e4 LT |
1570 | } |
1571 | ||
c88ac1df | 1572 | static void mask_lapic_irq(unsigned int irq) |
1da177e4 LT |
1573 | { |
1574 | unsigned long v; | |
1575 | ||
1576 | v = apic_read(APIC_LVT0); | |
11a8e778 | 1577 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
1578 | } |
1579 | ||
1580 | static void ack_lapic_irq (unsigned int irq) | |
1581 | { | |
1582 | ack_APIC_irq(); | |
1583 | } | |
1584 | ||
c88ac1df MR |
1585 | static struct irq_chip lapic_chip __read_mostly = { |
1586 | .name = "local-APIC", | |
1587 | .mask = mask_lapic_irq, | |
1588 | .unmask = unmask_lapic_irq, | |
1589 | .ack = ack_lapic_irq, | |
1da177e4 LT |
1590 | }; |
1591 | ||
c88ac1df MR |
1592 | static void lapic_register_intr(int irq) |
1593 | { | |
1594 | irq_desc[irq].status &= ~IRQ_LEVEL; | |
1595 | set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, | |
1596 | "edge"); | |
1597 | } | |
1598 | ||
e9427101 | 1599 | static void __init setup_nmi(void) |
1da177e4 LT |
1600 | { |
1601 | /* | |
1602 | * Dirty trick to enable the NMI watchdog ... | |
1603 | * We put the 8259A master into AEOI mode and | |
1604 | * unmask on all local APICs LVT0 as NMI. | |
1605 | * | |
1606 | * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') | |
1607 | * is from Maciej W. Rozycki - so we do not have to EOI from | |
1608 | * the NMI handler or the timer interrupt. | |
1609 | */ | |
1610 | printk(KERN_INFO "activating NMI Watchdog ..."); | |
1611 | ||
e9427101 | 1612 | enable_NMI_through_LVT0(); |
1da177e4 LT |
1613 | |
1614 | printk(" done.\n"); | |
1615 | } | |
1616 | ||
1617 | /* | |
1618 | * This looks a bit hackish but it's about the only one way of sending | |
1619 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
1620 | * not support the ExtINT mode, unfortunately. We need to send these | |
1621 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
1622 | * 8259A interrupt line asserted until INTA. --macro | |
1623 | */ | |
5afca33a | 1624 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 1625 | { |
1008fddc | 1626 | int apic, pin, i; |
1da177e4 LT |
1627 | struct IO_APIC_route_entry entry0, entry1; |
1628 | unsigned char save_control, save_freq_select; | |
1da177e4 | 1629 | |
1008fddc EB |
1630 | pin = find_isa_irq_pin(8, mp_INT); |
1631 | apic = find_isa_irq_apic(8, mp_INT); | |
1da177e4 LT |
1632 | if (pin == -1) |
1633 | return; | |
1634 | ||
a2249cba AM |
1635 | entry0 = ioapic_read_entry(apic, pin); |
1636 | ||
1008fddc | 1637 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
1638 | |
1639 | memset(&entry1, 0, sizeof(entry1)); | |
1640 | ||
1641 | entry1.dest_mode = 0; /* physical delivery */ | |
1642 | entry1.mask = 0; /* unmask IRQ now */ | |
ee4eff6f | 1643 | entry1.dest = hard_smp_processor_id(); |
1da177e4 LT |
1644 | entry1.delivery_mode = dest_ExtINT; |
1645 | entry1.polarity = entry0.polarity; | |
1646 | entry1.trigger = 0; | |
1647 | entry1.vector = 0; | |
1648 | ||
a2249cba | 1649 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
1650 | |
1651 | save_control = CMOS_READ(RTC_CONTROL); | |
1652 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
1653 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
1654 | RTC_FREQ_SELECT); | |
1655 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
1656 | ||
1657 | i = 100; | |
1658 | while (i-- > 0) { | |
1659 | mdelay(10); | |
1660 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
1661 | i -= 10; | |
1662 | } | |
1663 | ||
1664 | CMOS_WRITE(save_control, RTC_CONTROL); | |
1665 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
1008fddc | 1666 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 1667 | |
a2249cba | 1668 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
1669 | } |
1670 | ||
1671 | /* | |
1672 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
1673 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
1674 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
1675 | * fanatically on his truly buggy board. | |
fea5f1e1 LT |
1676 | * |
1677 | * FIXME: really need to revamp this for modern platforms only. | |
1da177e4 | 1678 | */ |
e9427101 | 1679 | static inline void __init check_timer(void) |
1da177e4 | 1680 | { |
dfbffdd8 | 1681 | struct irq_cfg *cfg = irq_cfg + 0; |
1008fddc | 1682 | int apic1, pin1, apic2, pin2; |
4aae0702 | 1683 | unsigned long flags; |
691874fa | 1684 | int no_pin1 = 0; |
4aae0702 IM |
1685 | |
1686 | local_irq_save(flags); | |
1da177e4 LT |
1687 | |
1688 | /* | |
1689 | * get/set the timer IRQ vector: | |
1690 | */ | |
1691 | disable_8259A_irq(0); | |
dfbffdd8 | 1692 | assign_irq_vector(0, TARGET_CPUS); |
1da177e4 LT |
1693 | |
1694 | /* | |
d11d5794 MR |
1695 | * As IRQ0 is to be enabled in the 8259A, the virtual |
1696 | * wire has to be disabled in the local APIC. | |
1da177e4 | 1697 | */ |
11a8e778 | 1698 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
1da177e4 | 1699 | init_8259A(1); |
1da177e4 | 1700 | |
1008fddc EB |
1701 | pin1 = find_isa_irq_pin(0, mp_INT); |
1702 | apic1 = find_isa_irq_apic(0, mp_INT); | |
1703 | pin2 = ioapic_i8259.pin; | |
1704 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 1705 | |
fea5f1e1 | 1706 | apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n", |
dfbffdd8 | 1707 | cfg->vector, apic1, pin1, apic2, pin2); |
b0268726 | 1708 | |
e2079c43 RW |
1709 | if (mask_ioapic_irq_2) |
1710 | mask_IO_APIC_irq(2); | |
1711 | ||
691874fa MR |
1712 | /* |
1713 | * Some BIOS writers are clueless and report the ExtINTA | |
1714 | * I/O APIC input from the cascaded 8259A as the timer | |
1715 | * interrupt input. So just in case, if only one pin | |
1716 | * was found above, try it both directly and through the | |
1717 | * 8259A. | |
1718 | */ | |
1719 | if (pin1 == -1) { | |
1720 | pin1 = pin2; | |
1721 | apic1 = apic2; | |
1722 | no_pin1 = 1; | |
1723 | } else if (pin2 == -1) { | |
1724 | pin2 = pin1; | |
1725 | apic2 = apic1; | |
1726 | } | |
1727 | ||
fea5f1e1 LT |
1728 | if (pin1 != -1) { |
1729 | /* | |
1730 | * Ok, does IRQ0 through the IOAPIC work? | |
1731 | */ | |
691874fa MR |
1732 | if (no_pin1) { |
1733 | add_pin_to_irq(0, apic1, pin1); | |
b1b57ee1 | 1734 | setup_timer_IRQ0_pin(apic1, pin1, cfg->vector); |
691874fa | 1735 | } |
fea5f1e1 LT |
1736 | unmask_IO_APIC_irq(0); |
1737 | if (!no_timer_check && timer_irq_works()) { | |
fea5f1e1 | 1738 | if (nmi_watchdog == NMI_IO_APIC) { |
fea5f1e1 LT |
1739 | setup_nmi(); |
1740 | enable_8259A_irq(0); | |
1741 | } | |
1742 | if (disable_timer_pin_1 > 0) | |
1743 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 1744 | goto out; |
fea5f1e1 LT |
1745 | } |
1746 | clear_IO_APIC_pin(apic1, pin1); | |
691874fa MR |
1747 | if (!no_pin1) |
1748 | apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: " | |
1749 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 1750 | |
691874fa MR |
1751 | apic_printk(APIC_VERBOSE,KERN_INFO |
1752 | "...trying to set up timer (IRQ0) " | |
1753 | "through the 8259A ... "); | |
fea5f1e1 LT |
1754 | apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...", |
1755 | apic2, pin2); | |
1756 | /* | |
1757 | * legacy devices should be connected to IO APIC #0 | |
1758 | */ | |
0b9f4f49 | 1759 | replace_pin_at_irq(0, apic1, pin1, apic2, pin2); |
f7633ce5 | 1760 | setup_timer_IRQ0_pin(apic2, pin2, cfg->vector); |
24742ece | 1761 | unmask_IO_APIC_irq(0); |
ecd29476 | 1762 | enable_8259A_irq(0); |
fea5f1e1 LT |
1763 | if (timer_irq_works()) { |
1764 | apic_printk(APIC_VERBOSE," works.\n"); | |
35542c5e | 1765 | timer_through_8259 = 1; |
fea5f1e1 | 1766 | if (nmi_watchdog == NMI_IO_APIC) { |
60134ebe | 1767 | disable_8259A_irq(0); |
fea5f1e1 | 1768 | setup_nmi(); |
60134ebe | 1769 | enable_8259A_irq(0); |
fea5f1e1 | 1770 | } |
4aae0702 | 1771 | goto out; |
fea5f1e1 LT |
1772 | } |
1773 | /* | |
1774 | * Cleanup, just in case ... | |
1775 | */ | |
ecd29476 | 1776 | disable_8259A_irq(0); |
fea5f1e1 | 1777 | clear_IO_APIC_pin(apic2, pin2); |
691874fa | 1778 | apic_printk(APIC_VERBOSE," failed.\n"); |
1da177e4 | 1779 | } |
1da177e4 | 1780 | |
1f992153 | 1781 | if (nmi_watchdog == NMI_IO_APIC) { |
1da177e4 | 1782 | printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n"); |
067fa0ff | 1783 | nmi_watchdog = NMI_NONE; |
1da177e4 LT |
1784 | } |
1785 | ||
1786 | apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ..."); | |
1787 | ||
c88ac1df | 1788 | lapic_register_intr(0); |
dfbffdd8 | 1789 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ |
1da177e4 LT |
1790 | enable_8259A_irq(0); |
1791 | ||
1792 | if (timer_irq_works()) { | |
5b922cd4 | 1793 | apic_printk(APIC_VERBOSE," works.\n"); |
4aae0702 | 1794 | goto out; |
1da177e4 | 1795 | } |
e67465f1 | 1796 | disable_8259A_irq(0); |
dfbffdd8 | 1797 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
1da177e4 LT |
1798 | apic_printk(APIC_VERBOSE," failed.\n"); |
1799 | ||
1800 | apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ..."); | |
1801 | ||
1802 | init_8259A(0); | |
1803 | make_8259A_irq(0); | |
11a8e778 | 1804 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
1805 | |
1806 | unlock_ExtINT_logic(); | |
1807 | ||
1808 | if (timer_irq_works()) { | |
1809 | apic_printk(APIC_VERBOSE," works.\n"); | |
4aae0702 | 1810 | goto out; |
1da177e4 LT |
1811 | } |
1812 | apic_printk(APIC_VERBOSE," failed :(.\n"); | |
1813 | panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n"); | |
4aae0702 IM |
1814 | out: |
1815 | local_irq_restore(flags); | |
1da177e4 LT |
1816 | } |
1817 | ||
14d98cad AK |
1818 | static int __init notimercheck(char *s) |
1819 | { | |
1820 | no_timer_check = 1; | |
1821 | return 1; | |
1822 | } | |
1823 | __setup("no_timer_check", notimercheck); | |
1824 | ||
1da177e4 | 1825 | /* |
af174783 MR |
1826 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
1827 | * to devices. However there may be an I/O APIC pin available for | |
1828 | * this interrupt regardless. The pin may be left unconnected, but | |
1829 | * typically it will be reused as an ExtINT cascade interrupt for | |
1830 | * the master 8259A. In the MPS case such a pin will normally be | |
1831 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
1832 | * there is no provision for ExtINT interrupts, and in the absence | |
1833 | * of an override it would be treated as an ordinary ISA I/O APIC | |
1834 | * interrupt, that is edge-triggered and unmasked by default. We | |
1835 | * used to do this, but it caused problems on some systems because | |
1836 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
1837 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
1838 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
1839 | * the I/O APIC in all cases now. No actual device should request | |
1840 | * it anyway. --macro | |
1da177e4 LT |
1841 | */ |
1842 | #define PIC_IRQS (1<<2) | |
1843 | ||
1844 | void __init setup_IO_APIC(void) | |
1845 | { | |
1c69524c YL |
1846 | |
1847 | /* | |
1848 | * calling enable_IO_APIC() is moved to setup_local_APIC for BP | |
1849 | */ | |
1da177e4 | 1850 | |
af174783 | 1851 | io_apic_irqs = ~PIC_IRQS; |
1da177e4 LT |
1852 | |
1853 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); | |
1854 | ||
1da177e4 LT |
1855 | sync_Arb_IDs(); |
1856 | setup_IO_APIC_irqs(); | |
1857 | init_IO_APIC_traps(); | |
1858 | check_timer(); | |
1859 | if (!acpi_ioapic) | |
1860 | print_IO_APIC(); | |
1861 | } | |
1862 | ||
1863 | struct sysfs_ioapic_data { | |
1864 | struct sys_device dev; | |
1865 | struct IO_APIC_route_entry entry[0]; | |
1866 | }; | |
1867 | static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS]; | |
1868 | ||
0b9c33a7 | 1869 | static int ioapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
1870 | { |
1871 | struct IO_APIC_route_entry *entry; | |
1872 | struct sysfs_ioapic_data *data; | |
1da177e4 LT |
1873 | int i; |
1874 | ||
1875 | data = container_of(dev, struct sysfs_ioapic_data, dev); | |
1876 | entry = data->entry; | |
eea0e11c AK |
1877 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) |
1878 | *entry = ioapic_read_entry(dev->id, i); | |
1da177e4 LT |
1879 | |
1880 | return 0; | |
1881 | } | |
1882 | ||
1883 | static int ioapic_resume(struct sys_device *dev) | |
1884 | { | |
1885 | struct IO_APIC_route_entry *entry; | |
1886 | struct sysfs_ioapic_data *data; | |
1887 | unsigned long flags; | |
1888 | union IO_APIC_reg_00 reg_00; | |
1889 | int i; | |
1890 | ||
1891 | data = container_of(dev, struct sysfs_ioapic_data, dev); | |
1892 | entry = data->entry; | |
1893 | ||
1894 | spin_lock_irqsave(&ioapic_lock, flags); | |
1895 | reg_00.raw = io_apic_read(dev->id, 0); | |
ec2cd0a2 AS |
1896 | if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) { |
1897 | reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid; | |
1da177e4 LT |
1898 | io_apic_write(dev->id, 0, reg_00.raw); |
1899 | } | |
1da177e4 | 1900 | spin_unlock_irqrestore(&ioapic_lock, flags); |
eea0e11c AK |
1901 | for (i = 0; i < nr_ioapic_registers[dev->id]; i++) |
1902 | ioapic_write_entry(dev->id, i, entry[i]); | |
1da177e4 LT |
1903 | |
1904 | return 0; | |
1905 | } | |
1906 | ||
1907 | static struct sysdev_class ioapic_sysdev_class = { | |
af5ca3f4 | 1908 | .name = "ioapic", |
1da177e4 LT |
1909 | .suspend = ioapic_suspend, |
1910 | .resume = ioapic_resume, | |
1911 | }; | |
1912 | ||
1913 | static int __init ioapic_init_sysfs(void) | |
1914 | { | |
1915 | struct sys_device * dev; | |
cddf7ff7 | 1916 | int i, size, error; |
1da177e4 LT |
1917 | |
1918 | error = sysdev_class_register(&ioapic_sysdev_class); | |
1919 | if (error) | |
1920 | return error; | |
1921 | ||
1922 | for (i = 0; i < nr_ioapics; i++ ) { | |
1923 | size = sizeof(struct sys_device) + nr_ioapic_registers[i] | |
1924 | * sizeof(struct IO_APIC_route_entry); | |
cddf7ff7 | 1925 | mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL); |
1da177e4 LT |
1926 | if (!mp_ioapic_data[i]) { |
1927 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
1928 | continue; | |
1929 | } | |
1da177e4 LT |
1930 | dev = &mp_ioapic_data[i]->dev; |
1931 | dev->id = i; | |
1932 | dev->cls = &ioapic_sysdev_class; | |
1933 | error = sysdev_register(dev); | |
1934 | if (error) { | |
1935 | kfree(mp_ioapic_data[i]); | |
1936 | mp_ioapic_data[i] = NULL; | |
1937 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
1938 | continue; | |
1939 | } | |
1940 | } | |
1941 | ||
1942 | return 0; | |
1943 | } | |
1944 | ||
1945 | device_initcall(ioapic_init_sysfs); | |
1946 | ||
c4fa0bbf | 1947 | /* |
04b9267b | 1948 | * Dynamic irq allocate and deallocation |
c4fa0bbf EB |
1949 | */ |
1950 | int create_irq(void) | |
1951 | { | |
04b9267b EB |
1952 | /* Allocate an unused irq */ |
1953 | int irq; | |
1954 | int new; | |
c4fa0bbf | 1955 | unsigned long flags; |
c4fa0bbf | 1956 | |
04b9267b EB |
1957 | irq = -ENOSPC; |
1958 | spin_lock_irqsave(&vector_lock, flags); | |
1959 | for (new = (NR_IRQS - 1); new >= 0; new--) { | |
1960 | if (platform_legacy_irq(new)) | |
1961 | continue; | |
13a79503 | 1962 | if (irq_cfg[new].vector != 0) |
04b9267b | 1963 | continue; |
dfbffdd8 | 1964 | if (__assign_irq_vector(new, TARGET_CPUS) == 0) |
04b9267b EB |
1965 | irq = new; |
1966 | break; | |
1967 | } | |
1968 | spin_unlock_irqrestore(&vector_lock, flags); | |
c4fa0bbf | 1969 | |
04b9267b | 1970 | if (irq >= 0) { |
c4fa0bbf EB |
1971 | dynamic_irq_init(irq); |
1972 | } | |
1973 | return irq; | |
1974 | } | |
1975 | ||
1976 | void destroy_irq(unsigned int irq) | |
1977 | { | |
1978 | unsigned long flags; | |
c4fa0bbf EB |
1979 | |
1980 | dynamic_irq_cleanup(irq); | |
1981 | ||
1982 | spin_lock_irqsave(&vector_lock, flags); | |
5df0287e | 1983 | __clear_irq_vector(irq); |
c4fa0bbf EB |
1984 | spin_unlock_irqrestore(&vector_lock, flags); |
1985 | } | |
c4fa0bbf | 1986 | |
589e367f | 1987 | /* |
676b1855 | 1988 | * MSI message composition |
589e367f EB |
1989 | */ |
1990 | #ifdef CONFIG_PCI_MSI | |
3b7d1921 | 1991 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg) |
589e367f | 1992 | { |
dfbffdd8 EB |
1993 | struct irq_cfg *cfg = irq_cfg + irq; |
1994 | int err; | |
589e367f | 1995 | unsigned dest; |
c7111c13 | 1996 | cpumask_t tmp; |
589e367f | 1997 | |
dfbffdd8 EB |
1998 | tmp = TARGET_CPUS; |
1999 | err = assign_irq_vector(irq, tmp); | |
2000 | if (!err) { | |
2001 | cpus_and(tmp, cfg->domain, tmp); | |
589e367f EB |
2002 | dest = cpu_mask_to_apicid(tmp); |
2003 | ||
2004 | msg->address_hi = MSI_ADDR_BASE_HI; | |
2005 | msg->address_lo = | |
2006 | MSI_ADDR_BASE_LO | | |
2007 | ((INT_DEST_MODE == 0) ? | |
2008 | MSI_ADDR_DEST_MODE_PHYSICAL: | |
2009 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
2010 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
2011 | MSI_ADDR_REDIRECTION_CPU: | |
2012 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
2013 | MSI_ADDR_DEST_ID(dest); | |
2014 | ||
2015 | msg->data = | |
2016 | MSI_DATA_TRIGGER_EDGE | | |
2017 | MSI_DATA_LEVEL_ASSERT | | |
2018 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
2019 | MSI_DATA_DELIVERY_FIXED: | |
2020 | MSI_DATA_DELIVERY_LOWPRI) | | |
dfbffdd8 | 2021 | MSI_DATA_VECTOR(cfg->vector); |
589e367f | 2022 | } |
dfbffdd8 | 2023 | return err; |
589e367f EB |
2024 | } |
2025 | ||
3b7d1921 EB |
2026 | #ifdef CONFIG_SMP |
2027 | static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask) | |
589e367f | 2028 | { |
dfbffdd8 | 2029 | struct irq_cfg *cfg = irq_cfg + irq; |
3b7d1921 EB |
2030 | struct msi_msg msg; |
2031 | unsigned int dest; | |
2032 | cpumask_t tmp; | |
3b7d1921 EB |
2033 | |
2034 | cpus_and(tmp, mask, cpu_online_map); | |
2035 | if (cpus_empty(tmp)) | |
5ff5115e | 2036 | return; |
589e367f | 2037 | |
dfbffdd8 | 2038 | if (assign_irq_vector(irq, mask)) |
3b7d1921 | 2039 | return; |
550f2299 | 2040 | |
dfbffdd8 | 2041 | cpus_and(tmp, cfg->domain, mask); |
3b7d1921 | 2042 | dest = cpu_mask_to_apicid(tmp); |
589e367f | 2043 | |
3b7d1921 EB |
2044 | read_msi_msg(irq, &msg); |
2045 | ||
2046 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
dfbffdd8 | 2047 | msg.data |= MSI_DATA_VECTOR(cfg->vector); |
3b7d1921 EB |
2048 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; |
2049 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
2050 | ||
2051 | write_msi_msg(irq, &msg); | |
9f0a5ba5 | 2052 | irq_desc[irq].affinity = mask; |
589e367f | 2053 | } |
3b7d1921 | 2054 | #endif /* CONFIG_SMP */ |
589e367f | 2055 | |
3b7d1921 EB |
2056 | /* |
2057 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
2058 | * which implement the MSI or MSI-X Capability Structure. | |
2059 | */ | |
2060 | static struct irq_chip msi_chip = { | |
2061 | .name = "PCI-MSI", | |
2062 | .unmask = unmask_msi_irq, | |
2063 | .mask = mask_msi_irq, | |
2064 | .ack = ack_apic_edge, | |
2065 | #ifdef CONFIG_SMP | |
2066 | .set_affinity = set_msi_irq_affinity, | |
2067 | #endif | |
2068 | .retrigger = ioapic_retrigger_irq, | |
589e367f EB |
2069 | }; |
2070 | ||
f7feaca7 | 2071 | int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) |
3b7d1921 EB |
2072 | { |
2073 | struct msi_msg msg; | |
f7feaca7 EB |
2074 | int irq, ret; |
2075 | irq = create_irq(); | |
2076 | if (irq < 0) | |
2077 | return irq; | |
2078 | ||
3b7d1921 | 2079 | ret = msi_compose_msg(dev, irq, &msg); |
f7feaca7 EB |
2080 | if (ret < 0) { |
2081 | destroy_irq(irq); | |
3b7d1921 | 2082 | return ret; |
f7feaca7 | 2083 | } |
3b7d1921 | 2084 | |
7fe3730d | 2085 | set_irq_msi(irq, desc); |
3b7d1921 EB |
2086 | write_msi_msg(irq, &msg); |
2087 | ||
a460e745 | 2088 | set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge"); |
3b7d1921 | 2089 | |
7fe3730d | 2090 | return 0; |
3b7d1921 EB |
2091 | } |
2092 | ||
2093 | void arch_teardown_msi_irq(unsigned int irq) | |
2094 | { | |
f7feaca7 | 2095 | destroy_irq(irq); |
3b7d1921 EB |
2096 | } |
2097 | ||
3460a6d9 KA |
2098 | #ifdef CONFIG_DMAR |
2099 | #ifdef CONFIG_SMP | |
2100 | static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask) | |
2101 | { | |
2102 | struct irq_cfg *cfg = irq_cfg + irq; | |
2103 | struct msi_msg msg; | |
2104 | unsigned int dest; | |
2105 | cpumask_t tmp; | |
2106 | ||
2107 | cpus_and(tmp, mask, cpu_online_map); | |
2108 | if (cpus_empty(tmp)) | |
2109 | return; | |
2110 | ||
2111 | if (assign_irq_vector(irq, mask)) | |
2112 | return; | |
2113 | ||
2114 | cpus_and(tmp, cfg->domain, mask); | |
2115 | dest = cpu_mask_to_apicid(tmp); | |
2116 | ||
2117 | dmar_msi_read(irq, &msg); | |
2118 | ||
2119 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
2120 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
2121 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
2122 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
2123 | ||
2124 | dmar_msi_write(irq, &msg); | |
2125 | irq_desc[irq].affinity = mask; | |
2126 | } | |
2127 | #endif /* CONFIG_SMP */ | |
2128 | ||
2129 | struct irq_chip dmar_msi_type = { | |
2130 | .name = "DMAR_MSI", | |
2131 | .unmask = dmar_msi_unmask, | |
2132 | .mask = dmar_msi_mask, | |
2133 | .ack = ack_apic_edge, | |
2134 | #ifdef CONFIG_SMP | |
2135 | .set_affinity = dmar_msi_set_affinity, | |
2136 | #endif | |
2137 | .retrigger = ioapic_retrigger_irq, | |
2138 | }; | |
2139 | ||
2140 | int arch_setup_dmar_msi(unsigned int irq) | |
2141 | { | |
2142 | int ret; | |
2143 | struct msi_msg msg; | |
2144 | ||
2145 | ret = msi_compose_msg(NULL, irq, &msg); | |
2146 | if (ret < 0) | |
2147 | return ret; | |
2148 | dmar_msi_write(irq, &msg); | |
2149 | set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, | |
2150 | "edge"); | |
2151 | return 0; | |
2152 | } | |
2153 | #endif | |
589e367f | 2154 | |
3460a6d9 | 2155 | #endif /* CONFIG_PCI_MSI */ |
8b955b0d EB |
2156 | /* |
2157 | * Hypertransport interrupt support | |
2158 | */ | |
2159 | #ifdef CONFIG_HT_IRQ | |
2160 | ||
2161 | #ifdef CONFIG_SMP | |
2162 | ||
2163 | static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) | |
2164 | { | |
ec68307c EB |
2165 | struct ht_irq_msg msg; |
2166 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 2167 | |
ec68307c EB |
2168 | msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); |
2169 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); | |
8b955b0d | 2170 | |
ec68307c EB |
2171 | msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); |
2172 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); | |
8b955b0d | 2173 | |
ec68307c | 2174 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
2175 | } |
2176 | ||
2177 | static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask) | |
2178 | { | |
dfbffdd8 | 2179 | struct irq_cfg *cfg = irq_cfg + irq; |
8b955b0d EB |
2180 | unsigned int dest; |
2181 | cpumask_t tmp; | |
8b955b0d EB |
2182 | |
2183 | cpus_and(tmp, mask, cpu_online_map); | |
2184 | if (cpus_empty(tmp)) | |
5ff5115e | 2185 | return; |
8b955b0d | 2186 | |
dfbffdd8 | 2187 | if (assign_irq_vector(irq, mask)) |
8b955b0d EB |
2188 | return; |
2189 | ||
dfbffdd8 | 2190 | cpus_and(tmp, cfg->domain, mask); |
8b955b0d EB |
2191 | dest = cpu_mask_to_apicid(tmp); |
2192 | ||
dfbffdd8 | 2193 | target_ht_irq(irq, dest, cfg->vector); |
9f0a5ba5 | 2194 | irq_desc[irq].affinity = mask; |
8b955b0d EB |
2195 | } |
2196 | #endif | |
2197 | ||
c37e108d | 2198 | static struct irq_chip ht_irq_chip = { |
8b955b0d EB |
2199 | .name = "PCI-HT", |
2200 | .mask = mask_ht_irq, | |
2201 | .unmask = unmask_ht_irq, | |
2202 | .ack = ack_apic_edge, | |
2203 | #ifdef CONFIG_SMP | |
2204 | .set_affinity = set_ht_irq_affinity, | |
2205 | #endif | |
2206 | .retrigger = ioapic_retrigger_irq, | |
2207 | }; | |
2208 | ||
2209 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
2210 | { | |
dfbffdd8 EB |
2211 | struct irq_cfg *cfg = irq_cfg + irq; |
2212 | int err; | |
c7111c13 | 2213 | cpumask_t tmp; |
8b955b0d | 2214 | |
dfbffdd8 EB |
2215 | tmp = TARGET_CPUS; |
2216 | err = assign_irq_vector(irq, tmp); | |
2217 | if (!err) { | |
ec68307c | 2218 | struct ht_irq_msg msg; |
8b955b0d | 2219 | unsigned dest; |
8b955b0d | 2220 | |
dfbffdd8 | 2221 | cpus_and(tmp, cfg->domain, tmp); |
8b955b0d EB |
2222 | dest = cpu_mask_to_apicid(tmp); |
2223 | ||
ec68307c | 2224 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 2225 | |
ec68307c EB |
2226 | msg.address_lo = |
2227 | HT_IRQ_LOW_BASE | | |
8b955b0d | 2228 | HT_IRQ_LOW_DEST_ID(dest) | |
dfbffdd8 | 2229 | HT_IRQ_LOW_VECTOR(cfg->vector) | |
8b955b0d EB |
2230 | ((INT_DEST_MODE == 0) ? |
2231 | HT_IRQ_LOW_DM_PHYSICAL : | |
2232 | HT_IRQ_LOW_DM_LOGICAL) | | |
2233 | HT_IRQ_LOW_RQEOI_EDGE | | |
2234 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
2235 | HT_IRQ_LOW_MT_FIXED : | |
ec68307c EB |
2236 | HT_IRQ_LOW_MT_ARBITRATED) | |
2237 | HT_IRQ_LOW_IRQ_MASKED; | |
8b955b0d | 2238 | |
ec68307c | 2239 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 2240 | |
a460e745 IM |
2241 | set_irq_chip_and_handler_name(irq, &ht_irq_chip, |
2242 | handle_edge_irq, "edge"); | |
8b955b0d | 2243 | } |
dfbffdd8 | 2244 | return err; |
8b955b0d EB |
2245 | } |
2246 | #endif /* CONFIG_HT_IRQ */ | |
2247 | ||
1da177e4 LT |
2248 | /* -------------------------------------------------------------------------- |
2249 | ACPI-based IOAPIC Configuration | |
2250 | -------------------------------------------------------------------------- */ | |
2251 | ||
888ba6c6 | 2252 | #ifdef CONFIG_ACPI |
1da177e4 LT |
2253 | |
2254 | #define IO_APIC_MAX_ID 0xFE | |
2255 | ||
1da177e4 LT |
2256 | int __init io_apic_get_redir_entries (int ioapic) |
2257 | { | |
2258 | union IO_APIC_reg_01 reg_01; | |
2259 | unsigned long flags; | |
2260 | ||
2261 | spin_lock_irqsave(&ioapic_lock, flags); | |
2262 | reg_01.raw = io_apic_read(ioapic, 1); | |
2263 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2264 | ||
2265 | return reg_01.bits.entries; | |
2266 | } | |
2267 | ||
2268 | ||
50eca3eb | 2269 | int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity) |
1da177e4 | 2270 | { |
1da177e4 LT |
2271 | if (!IO_APIC_IRQ(irq)) { |
2272 | apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", | |
2273 | ioapic); | |
2274 | return -EINVAL; | |
2275 | } | |
2276 | ||
550f2299 EB |
2277 | /* |
2278 | * IRQs < 16 are already in the irq_2_pin[] map | |
2279 | */ | |
2280 | if (irq >= 16) | |
2281 | add_pin_to_irq(irq, ioapic, pin); | |
2282 | ||
a8c8a367 | 2283 | setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity); |
1da177e4 LT |
2284 | |
2285 | return 0; | |
2286 | } | |
2287 | ||
1da177e4 | 2288 | |
61fd47e0 SL |
2289 | int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity) |
2290 | { | |
2291 | int i; | |
2292 | ||
2293 | if (skip_ioapic_setup) | |
2294 | return -1; | |
2295 | ||
2296 | for (i = 0; i < mp_irq_entries; i++) | |
2fddb6e2 AS |
2297 | if (mp_irqs[i].mp_irqtype == mp_INT && |
2298 | mp_irqs[i].mp_srcbusirq == bus_irq) | |
61fd47e0 SL |
2299 | break; |
2300 | if (i >= mp_irq_entries) | |
2301 | return -1; | |
2302 | ||
2303 | *trigger = irq_trigger(i); | |
2304 | *polarity = irq_polarity(i); | |
2305 | return 0; | |
2306 | } | |
2307 | ||
2308 | #endif /* CONFIG_ACPI */ | |
1da177e4 LT |
2309 | |
2310 | /* | |
2311 | * This function currently is only a helper for the i386 smp boot process where | |
2312 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
2313 | * so mask in all cases should simply be TARGET_CPUS | |
2314 | */ | |
54d5d424 | 2315 | #ifdef CONFIG_SMP |
1da177e4 LT |
2316 | void __init setup_ioapic_dest(void) |
2317 | { | |
2318 | int pin, ioapic, irq, irq_entry; | |
2319 | ||
2320 | if (skip_ioapic_setup == 1) | |
2321 | return; | |
2322 | ||
2323 | for (ioapic = 0; ioapic < nr_ioapics; ioapic++) { | |
2324 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { | |
2325 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); | |
2326 | if (irq_entry == -1) | |
2327 | continue; | |
2328 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
ad892f5e YL |
2329 | |
2330 | /* setup_IO_APIC_irqs could fail to get vector for some device | |
2331 | * when you have too many devices, because at that time only boot | |
2332 | * cpu is online. | |
2333 | */ | |
13a79503 | 2334 | if (!irq_cfg[irq].vector) |
a8c8a367 EB |
2335 | setup_IO_APIC_irq(ioapic, pin, irq, |
2336 | irq_trigger(irq_entry), | |
2337 | irq_polarity(irq_entry)); | |
ad892f5e YL |
2338 | else |
2339 | set_ioapic_affinity_irq(irq, TARGET_CPUS); | |
1da177e4 LT |
2340 | } |
2341 | ||
2342 | } | |
2343 | } | |
54d5d424 | 2344 | #endif |
61fd47e0 | 2345 | |
3e35a0e5 TG |
2346 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
2347 | ||
2348 | static struct resource *ioapic_resources; | |
2349 | ||
2350 | static struct resource * __init ioapic_setup_resources(void) | |
2351 | { | |
2352 | unsigned long n; | |
2353 | struct resource *res; | |
2354 | char *mem; | |
2355 | int i; | |
2356 | ||
2357 | if (nr_ioapics <= 0) | |
2358 | return NULL; | |
2359 | ||
2360 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); | |
2361 | n *= nr_ioapics; | |
2362 | ||
2363 | mem = alloc_bootmem(n); | |
2364 | res = (void *)mem; | |
2365 | ||
2366 | if (mem != NULL) { | |
3e35a0e5 TG |
2367 | mem += sizeof(struct resource) * nr_ioapics; |
2368 | ||
2369 | for (i = 0; i < nr_ioapics; i++) { | |
2370 | res[i].name = mem; | |
2371 | res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
2372 | sprintf(mem, "IOAPIC %u", i); | |
2373 | mem += IOAPIC_RESOURCE_NAME_SIZE; | |
2374 | } | |
2375 | } | |
2376 | ||
2377 | ioapic_resources = res; | |
2378 | ||
2379 | return res; | |
2380 | } | |
2381 | ||
2382 | void __init ioapic_init_mappings(void) | |
2383 | { | |
2384 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
2385 | struct resource *ioapic_res; | |
2386 | int i; | |
2387 | ||
2388 | ioapic_res = ioapic_setup_resources(); | |
2389 | for (i = 0; i < nr_ioapics; i++) { | |
2390 | if (smp_found_config) { | |
ec2cd0a2 | 2391 | ioapic_phys = mp_ioapics[i].mp_apicaddr; |
3e35a0e5 TG |
2392 | } else { |
2393 | ioapic_phys = (unsigned long) | |
2394 | alloc_bootmem_pages(PAGE_SIZE); | |
2395 | ioapic_phys = __pa(ioapic_phys); | |
2396 | } | |
2397 | set_fixmap_nocache(idx, ioapic_phys); | |
2398 | apic_printk(APIC_VERBOSE, | |
2399 | "mapped IOAPIC to %016lx (%016lx)\n", | |
2400 | __fix_to_virt(idx), ioapic_phys); | |
2401 | idx++; | |
2402 | ||
2403 | if (ioapic_res != NULL) { | |
2404 | ioapic_res->start = ioapic_phys; | |
2405 | ioapic_res->end = ioapic_phys + (4 * 1024) - 1; | |
2406 | ioapic_res++; | |
2407 | } | |
2408 | } | |
2409 | } | |
2410 | ||
2411 | static int __init ioapic_insert_resources(void) | |
2412 | { | |
2413 | int i; | |
2414 | struct resource *r = ioapic_resources; | |
2415 | ||
2416 | if (!r) { | |
2417 | printk(KERN_ERR | |
2418 | "IO APIC resources could be not be allocated.\n"); | |
2419 | return -1; | |
2420 | } | |
2421 | ||
2422 | for (i = 0; i < nr_ioapics; i++) { | |
2423 | insert_resource(&iomem_resource, r); | |
2424 | r++; | |
2425 | } | |
2426 | ||
2427 | return 0; | |
2428 | } | |
2429 | ||
2430 | /* Insert the IO APIC resources after PCI initialization has occured to handle | |
2431 | * IO APICS that are mapped in on a BAR in PCI space. */ | |
2432 | late_initcall(ioapic_insert_resources); | |
2433 |