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x86: make __{save,restore}_processor_state static
[deliverable/linux.git] / arch / x86 / kernel / io_apic_64.c
CommitLineData
1da177e4
LT		 1/*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23#include <linux/mm.h>
1da177e4
LT		 24#include <linux/interrupt.h>
25#include <linux/init.h>
26#include <linux/delay.h>
27#include <linux/sched.h>
589e367f 28#include <linux/pci.h>
1da177e4
LT		 29#include <linux/mc146818rtc.h>
30#include <linux/acpi.h>
31#include <linux/sysdev.h>
3b7d1921 32#include <linux/msi.h>
95d77884 33#include <linux/htirq.h>
3460a6d9 34#include <linux/dmar.h>
ab688059
AK		 35#ifdef CONFIG_ACPI
36#include <acpi/acpi_bus.h>
37#endif
3e35a0e5 38#include <linux/bootmem.h>
1da177e4 39
61014292 40#include <asm/idle.h>
1da177e4
LT		 41#include <asm/io.h>
42#include <asm/smp.h>
43#include <asm/desc.h>
44#include <asm/proto.h>
45#include <asm/mach_apic.h>
8d916406 46#include <asm/acpi.h>
ca8642f6 47#include <asm/dma.h>
3e4ff115 48#include <asm/nmi.h>
589e367f 49#include <asm/msidef.h>
8b955b0d 50#include <asm/hypertransport.h>
1da177e4 51
13a79503
EB		 52struct irq_cfg {
53 cpumask_t domain;
61014292
EB		 54 cpumask_t old_domain;
55 unsigned move_cleanup_count;
13a79503 56 u8 vector;
61014292 57 u8 move_in_progress : 1;
13a79503
EB		 58};
59
60/* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
61struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
bc5e81a1
EB		 62 [0] = { .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
63 [1] = { .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
64 [2] = { .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
65 [3] = { .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
66 [4] = { .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
67 [5] = { .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
68 [6] = { .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
69 [7] = { .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
70 [8] = { .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
71 [9] = { .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
72 [10] = { .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
73 [11] = { .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
74 [12] = { .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
75 [13] = { .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
76 [14] = { .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
77 [15] = { .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
13a79503
EB		 78};
79
dfbffdd8 80static int assign_irq_vector(int irq, cpumask_t mask);
04b9267b 81
1da177e4
LT		 82#define __apicdebuginit __init
83
84int sis_apic_bug; /* not actually supported, dummy for compile */
85
14d98cad
AK		 86static int no_timer_check;
87
fea5f1e1
LT		 88static int disable_timer_pin_1 __initdata;
89
90int timer_over_8254 __initdata = 1;
91
1008fddc
EB		 92/* Where if anywhere is the i8259 connect in external int mode */
93static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
94
1da177e4 95static DEFINE_SPINLOCK(ioapic_lock);
70a0a535 96DEFINE_SPINLOCK(vector_lock);
1da177e4
LT		 97
98/*
99 * # of IRQ routing registers
100 */
101int nr_ioapic_registers[MAX_IO_APICS];
102
103/*
104 * Rough estimation of how many shared IRQs there are, can
105 * be changed anytime.
106 */
e273d140 107#define MAX_PLUS_SHARED_IRQS NR_IRQS
1da177e4
LT		 108#define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
109
110/*
111 * This is performance-critical, we want to do it O(1)
112 *
113 * the indexing order of this array favors 1:1 mappings
114 * between pins and IRQs.
115 */
116
117static struct irq_pin_list {
118 short apic, pin, next;
119} irq_2_pin[PIN_MAP_SIZE];
120
6c0ffb9d
LT		 121struct io_apic {
122 unsigned int index;
123 unsigned int unused[3];
124 unsigned int data;
125};
126
127static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
128{
129 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
130 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
131}
132
133static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
134{
135 struct io_apic __iomem *io_apic = io_apic_base(apic);
136 writel(reg, &io_apic->index);
137 return readl(&io_apic->data);
138}
139
140static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
141{
142 struct io_apic __iomem *io_apic = io_apic_base(apic);
143 writel(reg, &io_apic->index);
144 writel(value, &io_apic->data);
145}
146
147/*
148 * Re-write a value: to be used for read-modify-write
149 * cycles where the read already set up the index register.
150 */
151static inline void io_apic_modify(unsigned int apic, unsigned int value)
152{
153 struct io_apic __iomem *io_apic = io_apic_base(apic);
154 writel(value, &io_apic->data);
155}
156
ef3e28c5
EB		 157static int io_apic_level_ack_pending(unsigned int irq)
158{
159 struct irq_pin_list *entry;
160 unsigned long flags;
161 int pending = 0;
162
163 spin_lock_irqsave(&ioapic_lock, flags);
164 entry = irq_2_pin + irq;
165 for (;;) {
166 unsigned int reg;
167 int pin;
168
169 pin = entry->pin;
170 if (pin == -1)
171 break;
172 reg = io_apic_read(entry->apic, 0x10 + pin*2);
173 /* Is the remote IRR bit set? */
174 pending |= (reg >> 14) & 1;
175 if (!entry->next)
176 break;
177 entry = irq_2_pin + entry->next;
178 }
179 spin_unlock_irqrestore(&ioapic_lock, flags);
180 return pending;
181}
182
6c0ffb9d
LT		 183/*
184 * Synchronize the IO-APIC and the CPU by doing
185 * a dummy read from the IO-APIC
186 */
187static inline void io_apic_sync(unsigned int apic)
188{
189 struct io_apic __iomem *io_apic = io_apic_base(apic);
190 readl(&io_apic->data);
191}
192
54d5d424
AR		 193#define __DO_ACTION(R, ACTION, FINAL) \
194 \
195{ \
196 int pin; \
197 struct irq_pin_list *entry = irq_2_pin + irq; \
198 \
6004e1b7 199 BUG_ON(irq >= NR_IRQS); \
54d5d424
AR		 200 for (;;) { \
201 unsigned int reg; \
202 pin = entry->pin; \
203 if (pin == -1) \
204 break; \
205 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
206 reg ACTION; \
207 io_apic_modify(entry->apic, reg); \
f45bcd70 208 FINAL; \
54d5d424
AR		 209 if (!entry->next) \
210 break; \
211 entry = irq_2_pin + entry->next; \
212 } \
54d5d424
AR		 213}
214
eea0e11c
AK		 215union entry_union {
216 struct { u32 w1, w2; };
217 struct IO_APIC_route_entry entry;
218};
219
220static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
221{
222 union entry_union eu;
223 unsigned long flags;
224 spin_lock_irqsave(&ioapic_lock, flags);
225 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
226 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
227 spin_unlock_irqrestore(&ioapic_lock, flags);
228 return eu.entry;
229}
230
48797ebd
LT		 231/*
232 * When we write a new IO APIC routing entry, we need to write the high
233 * word first! If the mask bit in the low word is clear, we will enable
234 * the interrupt, and we need to make sure the entry is fully populated
235 * before that happens.
236 */
516d2836
AK		 237static void
238__ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
eea0e11c 239{
eea0e11c
AK		 240 union entry_union eu;
241 eu.entry = e;
48797ebd
LT		 242 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
243 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
516d2836
AK		 244}
245
246static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
247{
248 unsigned long flags;
249 spin_lock_irqsave(&ioapic_lock, flags);
250 __ioapic_write_entry(apic, pin, e);
48797ebd
LT		 251 spin_unlock_irqrestore(&ioapic_lock, flags);
252}
253
254/*
255 * When we mask an IO APIC routing entry, we need to write the low
256 * word first, in order to set the mask bit before we change the
257 * high bits!
258 */
259static void ioapic_mask_entry(int apic, int pin)
260{
261 unsigned long flags;
262 union entry_union eu = { .entry.mask = 1 };
263
eea0e11c
AK		 264 spin_lock_irqsave(&ioapic_lock, flags);
265 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
266 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
267 spin_unlock_irqrestore(&ioapic_lock, flags);
268}
269
54d5d424 270#ifdef CONFIG_SMP
550f2299
EB		 271static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
272{
273 int apic, pin;
274 struct irq_pin_list *entry = irq_2_pin + irq;
275
276 BUG_ON(irq >= NR_IRQS);
277 for (;;) {
278 unsigned int reg;
279 apic = entry->apic;
280 pin = entry->pin;
281 if (pin == -1)
282 break;
283 io_apic_write(apic, 0x11 + pin*2, dest);
284 reg = io_apic_read(apic, 0x10 + pin*2);
285 reg &= ~0x000000ff;
286 reg |= vector;
287 io_apic_modify(apic, reg);
288 if (!entry->next)
289 break;
290 entry = irq_2_pin + entry->next;
291 }
292}
293
54d5d424
AR		 294static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
295{
dfbffdd8 296 struct irq_cfg *cfg = irq_cfg + irq;
54d5d424
AR		 297 unsigned long flags;
298 unsigned int dest;
299 cpumask_t tmp;
300
301 cpus_and(tmp, mask, cpu_online_map);
302 if (cpus_empty(tmp))
5ff5115e 303 return;
54d5d424 304
dfbffdd8 305 if (assign_irq_vector(irq, mask))
550f2299
EB		 306 return;
307
dfbffdd8 308 cpus_and(tmp, cfg->domain, mask);
550f2299 309 dest = cpu_mask_to_apicid(tmp);
54d5d424
AR		 310
311 /*
312 * Only the high 8 bits are valid.
313 */
314 dest = SET_APIC_LOGICAL_ID(dest);
315
316 spin_lock_irqsave(&ioapic_lock, flags);
dfbffdd8 317 __target_IO_APIC_irq(irq, dest, cfg->vector);
9f0a5ba5 318 irq_desc[irq].affinity = mask;
54d5d424
AR		 319 spin_unlock_irqrestore(&ioapic_lock, flags);
320}
321#endif
322
1da177e4
LT		 323/*
324 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
325 * shared ISA-space IRQs, so we have to support them. We are super
326 * fast in the common case, and fast for shared ISA-space IRQs.
327 */
328static void add_pin_to_irq(unsigned int irq, int apic, int pin)
329{
330 static int first_free_entry = NR_IRQS;
331 struct irq_pin_list *entry = irq_2_pin + irq;
332
6004e1b7 333 BUG_ON(irq >= NR_IRQS);
1da177e4
LT		 334 while (entry->next)
335 entry = irq_2_pin + entry->next;
336
337 if (entry->pin != -1) {
338 entry->next = first_free_entry;
339 entry = irq_2_pin + entry->next;
340 if (++first_free_entry >= PIN_MAP_SIZE)
6004e1b7 341 panic("io_apic.c: ran out of irq_2_pin entries!");
1da177e4
LT		 342 }
343 entry->apic = apic;
344 entry->pin = pin;
345}
346
1da177e4
LT		 347
348#define DO_ACTION(name,R,ACTION, FINAL) \
349 \
350 static void name##_IO_APIC_irq (unsigned int irq) \
351 __DO_ACTION(R, ACTION, FINAL)
352
353DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
354 /* mask = 1 */
355DO_ACTION( __unmask, 0, &= 0xfffeffff, )
356 /* mask = 0 */
357
358static void mask_IO_APIC_irq (unsigned int irq)
359{
360 unsigned long flags;
361
362 spin_lock_irqsave(&ioapic_lock, flags);
363 __mask_IO_APIC_irq(irq);
364 spin_unlock_irqrestore(&ioapic_lock, flags);
365}
366
367static void unmask_IO_APIC_irq (unsigned int irq)
368{
369 unsigned long flags;
370
371 spin_lock_irqsave(&ioapic_lock, flags);
372 __unmask_IO_APIC_irq(irq);
373 spin_unlock_irqrestore(&ioapic_lock, flags);
374}
375
376static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
377{
378 struct IO_APIC_route_entry entry;
1da177e4
LT		 379
380 /* Check delivery_mode to be sure we're not clearing an SMI pin */
eea0e11c 381 entry = ioapic_read_entry(apic, pin);
1da177e4
LT		 382 if (entry.delivery_mode == dest_SMI)
383 return;
384 /*
385 * Disable it in the IO-APIC irq-routing table:
386 */
48797ebd 387 ioapic_mask_entry(apic, pin);
1da177e4
LT		 388}
389
390static void clear_IO_APIC (void)
391{
392 int apic, pin;
393
394 for (apic = 0; apic < nr_ioapics; apic++)
395 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
396 clear_IO_APIC_pin(apic, pin);
397}
398
1da177e4
LT		 399int skip_ioapic_setup;
400int ioapic_force;
401
61ec7567 402static int __init parse_noapic(char *str)
1da177e4 403{
61ec7567 404 disable_ioapic_setup();
2c8c0e6b 405 return 0;
1da177e4 406}
61ec7567 407early_param("noapic", parse_noapic);
1da177e4 408
fea5f1e1
LT		 409/* Actually the next is obsolete, but keep it for paranoid reasons -AK */
410static int __init disable_timer_pin_setup(char *arg)
411{
412 disable_timer_pin_1 = 1;
413 return 1;
414}
415__setup("disable_timer_pin_1", disable_timer_pin_setup);
416
417static int __init setup_disable_8254_timer(char *s)
418{
419 timer_over_8254 = -1;
420 return 1;
421}
422static int __init setup_enable_8254_timer(char *s)
423{
424 timer_over_8254 = 2;
425 return 1;
426}
427
428__setup("disable_8254_timer", setup_disable_8254_timer);
429__setup("enable_8254_timer", setup_enable_8254_timer);
430
431
1da177e4
LT		 432/*
433 * Find the IRQ entry number of a certain pin.
434 */
435static int find_irq_entry(int apic, int pin, int type)
436{
437 int i;
438
439 for (i = 0; i < mp_irq_entries; i++)
440 if (mp_irqs[i].mpc_irqtype == type &&
441 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
442 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
443 mp_irqs[i].mpc_dstirq == pin)
444 return i;
445
446 return -1;
447}
448
449/*
450 * Find the pin to which IRQ[irq] (ISA) is connected
451 */
1008fddc 452static int __init find_isa_irq_pin(int irq, int type)
1da177e4
LT		 453{
454 int i;
455
456 for (i = 0; i < mp_irq_entries; i++) {
457 int lbus = mp_irqs[i].mpc_srcbus;
458
55f05ffa 459 if (test_bit(lbus, mp_bus_not_pci) &&
1da177e4
LT		 460 (mp_irqs[i].mpc_irqtype == type) &&
461 (mp_irqs[i].mpc_srcbusirq == irq))
462
463 return mp_irqs[i].mpc_dstirq;
464 }
465 return -1;
466}
467
1008fddc
EB		 468static int __init find_isa_irq_apic(int irq, int type)
469{
470 int i;
471
472 for (i = 0; i < mp_irq_entries; i++) {
473 int lbus = mp_irqs[i].mpc_srcbus;
474
55f05ffa 475 if (test_bit(lbus, mp_bus_not_pci) &&
1008fddc
EB		 476 (mp_irqs[i].mpc_irqtype == type) &&
477 (mp_irqs[i].mpc_srcbusirq == irq))
478 break;
479 }
480 if (i < mp_irq_entries) {
481 int apic;
482 for(apic = 0; apic < nr_ioapics; apic++) {
483 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
484 return apic;
485 }
486 }
487
488 return -1;
489}
490
1da177e4
LT		 491/*
492 * Find a specific PCI IRQ entry.
493 * Not an __init, possibly needed by modules
494 */
495static int pin_2_irq(int idx, int apic, int pin);
496
497int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
498{
499 int apic, i, best_guess = -1;
500
501 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
502 bus, slot, pin);
503 if (mp_bus_id_to_pci_bus[bus] == -1) {
504 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
505 return -1;
506 }
507 for (i = 0; i < mp_irq_entries; i++) {
508 int lbus = mp_irqs[i].mpc_srcbus;
509
510 for (apic = 0; apic < nr_ioapics; apic++)
511 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
512 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
513 break;
514
55f05ffa 515 if (!test_bit(lbus, mp_bus_not_pci) &&
1da177e4
LT		 516 !mp_irqs[i].mpc_irqtype &&
517 (bus == lbus) &&
518 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
519 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
520
521 if (!(apic || IO_APIC_IRQ(irq)))
522 continue;
523
524 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
525 return irq;
526 /*
527 * Use the first all-but-pin matching entry as a
528 * best-guess fuzzy result for broken mptables.
529 */
530 if (best_guess < 0)
531 best_guess = irq;
532 }
533 }
6004e1b7 534 BUG_ON(best_guess >= NR_IRQS);
1da177e4
LT		 535 return best_guess;
536}
537
1da177e4
LT		 538/* ISA interrupts are always polarity zero edge triggered,
539 * when listed as conforming in the MP table. */
540
541#define default_ISA_trigger(idx) (0)
542#define default_ISA_polarity(idx) (0)
543
544/* PCI interrupts are always polarity one level triggered,
545 * when listed as conforming in the MP table. */
546
547#define default_PCI_trigger(idx) (1)
548#define default_PCI_polarity(idx) (1)
549
61fd47e0 550static int MPBIOS_polarity(int idx)
1da177e4
LT		 551{
552 int bus = mp_irqs[idx].mpc_srcbus;
553 int polarity;
554
555 /*
556 * Determine IRQ line polarity (high active or low active):
557 */
558 switch (mp_irqs[idx].mpc_irqflag & 3)
559 {
560 case 0: /* conforms, ie. bus-type dependent polarity */
55f05ffa
AK		 561 if (test_bit(bus, mp_bus_not_pci))
562 polarity = default_ISA_polarity(idx);
563 else
564 polarity = default_PCI_polarity(idx);
1da177e4 565 break;
1da177e4
LT		 566 case 1: /* high active */
567 {
568 polarity = 0;
569 break;
570 }
571 case 2: /* reserved */
572 {
573 printk(KERN_WARNING "broken BIOS!!\n");
574 polarity = 1;
575 break;
576 }
577 case 3: /* low active */
578 {
579 polarity = 1;
580 break;
581 }
582 default: /* invalid */
583 {
584 printk(KERN_WARNING "broken BIOS!!\n");
585 polarity = 1;
586 break;
587 }
588 }
589 return polarity;
590}
591
592static int MPBIOS_trigger(int idx)
593{
594 int bus = mp_irqs[idx].mpc_srcbus;
595 int trigger;
596
597 /*
598 * Determine IRQ trigger mode (edge or level sensitive):
599 */
600 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
601 {
602 case 0: /* conforms, ie. bus-type dependent */
55f05ffa
AK		 603 if (test_bit(bus, mp_bus_not_pci))
604 trigger = default_ISA_trigger(idx);
605 else
606 trigger = default_PCI_trigger(idx);
1da177e4 607 break;
1da177e4
LT		 608 case 1: /* edge */
609 {
610 trigger = 0;
611 break;
612 }
613 case 2: /* reserved */
614 {
615 printk(KERN_WARNING "broken BIOS!!\n");
616 trigger = 1;
617 break;
618 }
619 case 3: /* level */
620 {
621 trigger = 1;
622 break;
623 }
624 default: /* invalid */
625 {
626 printk(KERN_WARNING "broken BIOS!!\n");
627 trigger = 0;
628 break;
629 }
630 }
631 return trigger;
632}
633
634static inline int irq_polarity(int idx)
635{
636 return MPBIOS_polarity(idx);
637}
638
639static inline int irq_trigger(int idx)
640{
641 return MPBIOS_trigger(idx);
642}
643
644static int pin_2_irq(int idx, int apic, int pin)
645{
646 int irq, i;
647 int bus = mp_irqs[idx].mpc_srcbus;
648
649 /*
650 * Debugging check, we are in big trouble if this message pops up!
651 */
652 if (mp_irqs[idx].mpc_dstirq != pin)
653 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
654
55f05ffa
AK		 655 if (test_bit(bus, mp_bus_not_pci)) {
656 irq = mp_irqs[idx].mpc_srcbusirq;
657 } else {
658 /*
659 * PCI IRQs are mapped in order
660 */
661 i = irq = 0;
662 while (i < apic)
663 irq += nr_ioapic_registers[i++];
664 irq += pin;
1da177e4 665 }
6004e1b7 666 BUG_ON(irq >= NR_IRQS);
1da177e4
LT		 667 return irq;
668}
669
dfbffdd8 670static int __assign_irq_vector(int irq, cpumask_t mask)
1da177e4 671{
550f2299
EB		 672 /*
673 * NOTE! The local APIC isn't very good at handling
674 * multiple interrupts at the same interrupt level.
675 * As the interrupt level is determined by taking the
676 * vector number and shifting that right by 4, we
677 * want to spread these out a bit so that they don't
678 * all fall in the same interrupt level.
679 *
680 * Also, we've got to be careful not to trash gate
681 * 0x80, because int 0x80 is hm, kind of importantish. ;)
682 */
d1752aa8 683 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
dfbffdd8 684 unsigned int old_vector;
550f2299 685 int cpu;
13a79503 686 struct irq_cfg *cfg;
1da177e4 687
e273d140 688 BUG_ON((unsigned)irq >= NR_IRQS);
13a79503 689 cfg = &irq_cfg[irq];
0a1ad60d 690
70a0a535
EB		 691 /* Only try and allocate irqs on cpus that are present */
692 cpus_and(mask, mask, cpu_online_map);
693
61014292
EB		 694 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
695 return -EBUSY;
696
dfbffdd8
EB		 697 old_vector = cfg->vector;
698 if (old_vector) {
699 cpumask_t tmp;
700 cpus_and(tmp, cfg->domain, mask);
701 if (!cpus_empty(tmp))
702 return 0;
0a1ad60d 703 }
550f2299
EB		 704
705 for_each_cpu_mask(cpu, mask) {
70a0a535 706 cpumask_t domain, new_mask;
61014292 707 int new_cpu;
550f2299 708 int vector, offset;
c7111c13
EB		 709
710 domain = vector_allocation_domain(cpu);
70a0a535 711 cpus_and(new_mask, domain, cpu_online_map);
c7111c13 712
d1752aa8
EB		 713 vector = current_vector;
714 offset = current_offset;
1da177e4 715next:
550f2299
EB		 716 vector += 8;
717 if (vector >= FIRST_SYSTEM_VECTOR) {
718 /* If we run out of vectors on large boxen, must share them. */
719 offset = (offset + 1) % 8;
720 vector = FIRST_DEVICE_VECTOR + offset;
721 }
d1752aa8 722 if (unlikely(current_vector == vector))
550f2299
EB		 723 continue;
724 if (vector == IA32_SYSCALL_VECTOR)
725 goto next;
70a0a535 726 for_each_cpu_mask(new_cpu, new_mask)
45edfd1d 727 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
c7111c13 728 goto next;
550f2299 729 /* Found one! */
d1752aa8
EB		 730 current_vector = vector;
731 current_offset = offset;
61014292
EB		 732 if (old_vector) {
733 cfg->move_in_progress = 1;
734 cfg->old_domain = cfg->domain;
735 }
70a0a535 736 for_each_cpu_mask(new_cpu, new_mask)
c7111c13 737 per_cpu(vector_irq, new_cpu)[vector] = irq;
13a79503
EB		 738 cfg->vector = vector;
739 cfg->domain = domain;
dfbffdd8 740 return 0;
1da177e4 741 }
550f2299 742 return -ENOSPC;
04b9267b
EB		 743}
744
dfbffdd8 745static int assign_irq_vector(int irq, cpumask_t mask)
04b9267b 746{
dfbffdd8 747 int err;
04b9267b 748 unsigned long flags;
0a1ad60d 749
04b9267b 750 spin_lock_irqsave(&vector_lock, flags);
dfbffdd8 751 err = __assign_irq_vector(irq, mask);
26a3c49c 752 spin_unlock_irqrestore(&vector_lock, flags);
dfbffdd8 753 return err;
1da177e4
LT		 754}
755
5df0287e
YL		 756static void __clear_irq_vector(int irq)
757{
13a79503 758 struct irq_cfg *cfg;
5df0287e
YL		 759 cpumask_t mask;
760 int cpu, vector;
761
13a79503
EB		 762 BUG_ON((unsigned)irq >= NR_IRQS);
763 cfg = &irq_cfg[irq];
764 BUG_ON(!cfg->vector);
5df0287e 765
13a79503
EB		 766 vector = cfg->vector;
767 cpus_and(mask, cfg->domain, cpu_online_map);
5df0287e
YL		 768 for_each_cpu_mask(cpu, mask)
769 per_cpu(vector_irq, cpu)[vector] = -1;
770
13a79503
EB		 771 cfg->vector = 0;
772 cfg->domain = CPU_MASK_NONE;
5df0287e
YL		 773}
774
70a0a535
EB		 775void __setup_vector_irq(int cpu)
776{
777 /* Initialize vector_irq on a new cpu */
778 /* This function must be called with vector_lock held */
70a0a535
EB		 779 int irq, vector;
780
70a0a535 781 /* Mark the inuse vectors */
e273d140 782 for (irq = 0; irq < NR_IRQS; ++irq) {
13a79503 783 if (!cpu_isset(cpu, irq_cfg[irq].domain))
70a0a535 784 continue;
13a79503 785 vector = irq_cfg[irq].vector;
70a0a535
EB		 786 per_cpu(vector_irq, cpu)[vector] = irq;
787 }
788 /* Mark the free vectors */
789 for (vector = 0; vector < NR_VECTORS; ++vector) {
790 irq = per_cpu(vector_irq, cpu)[vector];
791 if (irq < 0)
792 continue;
13a79503 793 if (!cpu_isset(cpu, irq_cfg[irq].domain))
70a0a535
EB		 794 per_cpu(vector_irq, cpu)[vector] = -1;
795 }
796}
797
798
f29bd1ba 799static struct irq_chip ioapic_chip;
1da177e4 800
a27bc06d 801static void ioapic_register_intr(int irq, unsigned long trigger)
1da177e4 802{
cc75b92d
TG		 803 if (trigger) {
804 irq_desc[irq].status |= IRQ_LEVEL;
a460e745
IM		 805 set_irq_chip_and_handler_name(irq, &ioapic_chip,
806 handle_fasteoi_irq, "fasteoi");
cc75b92d
TG		 807 } else {
808 irq_desc[irq].status &= ~IRQ_LEVEL;
a460e745
IM		 809 set_irq_chip_and_handler_name(irq, &ioapic_chip,
810 handle_edge_irq, "edge");
cc75b92d 811 }
1da177e4 812}
a8c8a367
EB		 813
814static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
815 int trigger, int polarity)
1da177e4 816{
dfbffdd8 817 struct irq_cfg *cfg = irq_cfg + irq;
1da177e4 818 struct IO_APIC_route_entry entry;
a8c8a367 819 cpumask_t mask;
1da177e4 820
a8c8a367
EB		 821 if (!IO_APIC_IRQ(irq))
822 return;
823
dfbffdd8
EB		 824 mask = TARGET_CPUS;
825 if (assign_irq_vector(irq, mask))
a8c8a367
EB		 826 return;
827
dfbffdd8
EB		 828 cpus_and(mask, cfg->domain, mask);
829
a8c8a367
EB		 830 apic_printk(APIC_VERBOSE,KERN_DEBUG
831 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
832 "IRQ %d Mode:%i Active:%i)\n",
dfbffdd8 833 apic, mp_ioapics[apic].mpc_apicid, pin, cfg->vector,
a8c8a367 834 irq, trigger, polarity);
1da177e4 835
ad892f5e
YL		 836 /*
837 * add it to the IO-APIC irq-routing table:
838 */
839 memset(&entry,0,sizeof(entry));
1da177e4 840
ad892f5e
YL		 841 entry.delivery_mode = INT_DELIVERY_MODE;
842 entry.dest_mode = INT_DEST_MODE;
a8c8a367 843 entry.dest = cpu_mask_to_apicid(mask);
ad892f5e 844 entry.mask = 0; /* enable IRQ */
a8c8a367
EB		 845 entry.trigger = trigger;
846 entry.polarity = polarity;
dfbffdd8 847 entry.vector = cfg->vector;
1da177e4 848
a8c8a367
EB		 849 /* Mask level triggered irqs.
850 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
851 */
852 if (trigger)
ad892f5e 853 entry.mask = 1;
ad892f5e 854
a8c8a367
EB		 855 ioapic_register_intr(irq, trigger);
856 if (irq < 16)
857 disable_8259A_irq(irq);
ad892f5e
YL		 858
859 ioapic_write_entry(apic, pin, entry);
ad892f5e
YL		 860}
861
862static void __init setup_IO_APIC_irqs(void)
863{
864 int apic, pin, idx, irq, first_notcon = 1;
865
866 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
867
868 for (apic = 0; apic < nr_ioapics; apic++) {
869 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1da177e4
LT		 870
871 idx = find_irq_entry(apic,pin,mp_INT);
872 if (idx == -1) {
873 if (first_notcon) {
874 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
875 first_notcon = 0;
876 } else
877 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
878 continue;
879 }
20d225b9
YL		 880 if (!first_notcon) {
881 apic_printk(APIC_VERBOSE, " not connected.\n");
882 first_notcon = 1;
883 }
1da177e4 884
1da177e4
LT		 885 irq = pin_2_irq(idx, apic, pin);
886 add_pin_to_irq(irq, apic, pin);
887
a8c8a367
EB		 888 setup_IO_APIC_irq(apic, pin, irq,
889 irq_trigger(idx), irq_polarity(idx));
1da177e4
LT		 890 }
891 }
892
893 if (!first_notcon)
20d225b9 894 apic_printk(APIC_VERBOSE, " not connected.\n");
1da177e4
LT		 895}
896
897/*
898 * Set up the 8259A-master output pin as broadcast to all
899 * CPUs.
900 */
1008fddc 901static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1da177e4
LT		 902{
903 struct IO_APIC_route_entry entry;
904 unsigned long flags;
905
906 memset(&entry,0,sizeof(entry));
907
908 disable_8259A_irq(0);
909
910 /* mask LVT0 */
11a8e778 911 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1da177e4
LT		 912
913 /*
914 * We use logical delivery to get the timer IRQ
915 * to the first CPU.
916 */
917 entry.dest_mode = INT_DEST_MODE;
918 entry.mask = 0; /* unmask IRQ now */
ee4eff6f 919 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
1da177e4
LT		 920 entry.delivery_mode = INT_DELIVERY_MODE;
921 entry.polarity = 0;
922 entry.trigger = 0;
923 entry.vector = vector;
924
925 /*
926 * The timer IRQ doesn't have to know that behind the
927 * scene we have a 8259A-master in AEOI mode ...
928 */
a460e745 929 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1da177e4
LT		 930
931 /*
932 * Add it to the IO-APIC irq-routing table:
933 */
934 spin_lock_irqsave(&ioapic_lock, flags);
1008fddc
EB		 935 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
936 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1da177e4
LT		 937 spin_unlock_irqrestore(&ioapic_lock, flags);
938
939 enable_8259A_irq(0);
940}
941
1da177e4
LT		 942void __apicdebuginit print_IO_APIC(void)
943{
944 int apic, i;
945 union IO_APIC_reg_00 reg_00;
946 union IO_APIC_reg_01 reg_01;
947 union IO_APIC_reg_02 reg_02;
948 unsigned long flags;
949
950 if (apic_verbosity == APIC_QUIET)
951 return;
952
953 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
954 for (i = 0; i < nr_ioapics; i++)
955 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
956 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
957
958 /*
959 * We are a bit conservative about what we expect. We have to
960 * know about every hardware change ASAP.
961 */
962 printk(KERN_INFO "testing the IO APIC.......................\n");
963
964 for (apic = 0; apic < nr_ioapics; apic++) {
965
966 spin_lock_irqsave(&ioapic_lock, flags);
967 reg_00.raw = io_apic_read(apic, 0);
968 reg_01.raw = io_apic_read(apic, 1);
969 if (reg_01.bits.version >= 0x10)
970 reg_02.raw = io_apic_read(apic, 2);
971 spin_unlock_irqrestore(&ioapic_lock, flags);
972
973 printk("\n");
974 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
975 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
976 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1da177e4
LT		 977
978 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
979 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1da177e4
LT		 980
981 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
982 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1da177e4
LT		 983
984 if (reg_01.bits.version >= 0x10) {
985 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
986 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1da177e4
LT		 987 }
988
989 printk(KERN_DEBUG ".... IRQ redirection table:\n");
990
ee4eff6f
BR		 991 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
992 " Stat Dmod Deli Vect: \n");
1da177e4
LT		 993
994 for (i = 0; i <= reg_01.bits.entries; i++) {
995 struct IO_APIC_route_entry entry;
996
eea0e11c 997 entry = ioapic_read_entry(apic, i);
1da177e4 998
ee4eff6f 999 printk(KERN_DEBUG " %02x %03X ",
1da177e4 1000 i,
ee4eff6f 1001 entry.dest
1da177e4
LT		 1002 );
1003
1004 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1005 entry.mask,
1006 entry.trigger,
1007 entry.irr,
1008 entry.polarity,
1009 entry.delivery_status,
1010 entry.dest_mode,
1011 entry.delivery_mode,
1012 entry.vector
1013 );
1014 }
1015 }
1da177e4
LT		 1016 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1017 for (i = 0; i < NR_IRQS; i++) {
1018 struct irq_pin_list *entry = irq_2_pin + i;
1019 if (entry->pin < 0)
1020 continue;
04b9267b 1021 printk(KERN_DEBUG "IRQ%d ", i);
1da177e4
LT		 1022 for (;;) {
1023 printk("-> %d:%d", entry->apic, entry->pin);
1024 if (!entry->next)
1025 break;
1026 entry = irq_2_pin + entry->next;
1027 }
1028 printk("\n");
1029 }
1030
1031 printk(KERN_INFO ".................................... done.\n");
1032
1033 return;
1034}
1035
1036#if 0
1037
1038static __apicdebuginit void print_APIC_bitfield (int base)
1039{
1040 unsigned int v;
1041 int i, j;
1042
1043 if (apic_verbosity == APIC_QUIET)
1044 return;
1045
1046 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1047 for (i = 0; i < 8; i++) {
1048 v = apic_read(base + i*0x10);
1049 for (j = 0; j < 32; j++) {
1050 if (v & (1<<j))
1051 printk("1");
1052 else
1053 printk("0");
1054 }
1055 printk("\n");
1056 }
1057}
1058
1059void __apicdebuginit print_local_APIC(void * dummy)
1060{
1061 unsigned int v, ver, maxlvt;
1062
1063 if (apic_verbosity == APIC_QUIET)
1064 return;
1065
1066 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1067 smp_processor_id(), hard_smp_processor_id());
1068 v = apic_read(APIC_ID);
1069 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
1070 v = apic_read(APIC_LVR);
1071 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1072 ver = GET_APIC_VERSION(v);
37e650c7 1073 maxlvt = lapic_get_maxlvt();
1da177e4
LT		 1074
1075 v = apic_read(APIC_TASKPRI);
1076 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1077
5a40b7c2
AK		 1078 v = apic_read(APIC_ARBPRI);
1079 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1080 v & APIC_ARBPRI_MASK);
1081 v = apic_read(APIC_PROCPRI);
1082 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1da177e4
LT		 1083
1084 v = apic_read(APIC_EOI);
1085 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1086 v = apic_read(APIC_RRR);
1087 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1088 v = apic_read(APIC_LDR);
1089 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1090 v = apic_read(APIC_DFR);
1091 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1092 v = apic_read(APIC_SPIV);
1093 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1094
1095 printk(KERN_DEBUG "... APIC ISR field:\n");
1096 print_APIC_bitfield(APIC_ISR);
1097 printk(KERN_DEBUG "... APIC TMR field:\n");
1098 print_APIC_bitfield(APIC_TMR);
1099 printk(KERN_DEBUG "... APIC IRR field:\n");
1100 print_APIC_bitfield(APIC_IRR);
1101
5a40b7c2
AK		 1102 v = apic_read(APIC_ESR);
1103 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1da177e4
LT		 1104
1105 v = apic_read(APIC_ICR);
1106 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1107 v = apic_read(APIC_ICR2);
1108 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1109
1110 v = apic_read(APIC_LVTT);
1111 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1112
1113 if (maxlvt > 3) { /* PC is LVT#4. */
1114 v = apic_read(APIC_LVTPC);
1115 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1116 }
1117 v = apic_read(APIC_LVT0);
1118 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1119 v = apic_read(APIC_LVT1);
1120 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1121
1122 if (maxlvt > 2) { /* ERR is LVT#3. */
1123 v = apic_read(APIC_LVTERR);
1124 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1125 }
1126
1127 v = apic_read(APIC_TMICT);
1128 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1129 v = apic_read(APIC_TMCCT);
1130 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1131 v = apic_read(APIC_TDCR);
1132 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1133 printk("\n");
1134}
1135
1136void print_all_local_APICs (void)
1137{
1138 on_each_cpu(print_local_APIC, NULL, 1, 1);
1139}
1140
1141void __apicdebuginit print_PIC(void)
1142{
1da177e4
LT		 1143 unsigned int v;
1144 unsigned long flags;
1145
1146 if (apic_verbosity == APIC_QUIET)
1147 return;
1148
1149 printk(KERN_DEBUG "\nprinting PIC contents\n");
1150
1151 spin_lock_irqsave(&i8259A_lock, flags);
1152
1153 v = inb(0xa1) << 8 | inb(0x21);
1154 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1155
1156 v = inb(0xa0) << 8 | inb(0x20);
1157 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1158
1159 outb(0x0b,0xa0);
1160 outb(0x0b,0x20);
1161 v = inb(0xa0) << 8 | inb(0x20);
1162 outb(0x0a,0xa0);
1163 outb(0x0a,0x20);
1164
1165 spin_unlock_irqrestore(&i8259A_lock, flags);
1166
1167 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1168
1169 v = inb(0x4d1) << 8 | inb(0x4d0);
1170 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1171}
1172
1173#endif /* 0 */
1174
1c69524c 1175void __init enable_IO_APIC(void)
1da177e4
LT		 1176{
1177 union IO_APIC_reg_01 reg_01;
1008fddc
EB		 1178 int i8259_apic, i8259_pin;
1179 int i, apic;
1da177e4
LT		 1180 unsigned long flags;
1181
1182 for (i = 0; i < PIN_MAP_SIZE; i++) {
1183 irq_2_pin[i].pin = -1;
1184 irq_2_pin[i].next = 0;
1185 }
1da177e4
LT		 1186
1187 /*
1188 * The number of IO-APIC IRQ registers (== #pins):
1189 */
1008fddc 1190 for (apic = 0; apic < nr_ioapics; apic++) {
1da177e4 1191 spin_lock_irqsave(&ioapic_lock, flags);
1008fddc 1192 reg_01.raw = io_apic_read(apic, 1);
1da177e4 1193 spin_unlock_irqrestore(&ioapic_lock, flags);
1008fddc
EB		 1194 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1195 }
1196 for(apic = 0; apic < nr_ioapics; apic++) {
1197 int pin;
1198 /* See if any of the pins is in ExtINT mode */
1199 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1200 struct IO_APIC_route_entry entry;
eea0e11c 1201 entry = ioapic_read_entry(apic, pin);
1008fddc
EB		 1202
1203 /* If the interrupt line is enabled and in ExtInt mode
1204 * I have found the pin where the i8259 is connected.
1205 */
1206 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1207 ioapic_i8259.apic = apic;
1208 ioapic_i8259.pin = pin;
1209 goto found_i8259;
1210 }
1211 }
1212 }
1213 found_i8259:
1214 /* Look to see what if the MP table has reported the ExtINT */
1215 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1216 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1217 /* Trust the MP table if nothing is setup in the hardware */
1218 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1219 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1220 ioapic_i8259.pin = i8259_pin;
1221 ioapic_i8259.apic = i8259_apic;
1222 }
1223 /* Complain if the MP table and the hardware disagree */
1224 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1225 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1226 {
1227 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1da177e4
LT		 1228 }
1229
1230 /*
1231 * Do not trust the IO-APIC being empty at bootup
1232 */
1233 clear_IO_APIC();
1234}
1235
1236/*
1237 * Not an __init, needed by the reboot code
1238 */
1239void disable_IO_APIC(void)
1240{
1241 /*
1242 * Clear the IO-APIC before rebooting:
1243 */
1244 clear_IO_APIC();
1245
208fb931 1246 /*
0b968d23 1247 * If the i8259 is routed through an IOAPIC
208fb931 1248 * Put that IOAPIC in virtual wire mode
0b968d23 1249 * so legacy interrupts can be delivered.
208fb931 1250 */
1008fddc 1251 if (ioapic_i8259.pin != -1) {
208fb931 1252 struct IO_APIC_route_entry entry;
208fb931
EB		 1253
1254 memset(&entry, 0, sizeof(entry));
1255 entry.mask = 0; /* Enabled */
1256 entry.trigger = 0; /* Edge */
1257 entry.irr = 0;
1258 entry.polarity = 0; /* High */
1259 entry.delivery_status = 0;
1260 entry.dest_mode = 0; /* Physical */
1008fddc 1261 entry.delivery_mode = dest_ExtINT; /* ExtInt */
208fb931 1262 entry.vector = 0;
ee4eff6f 1263 entry.dest = GET_APIC_ID(apic_read(APIC_ID));
208fb931 1264
208fb931
EB		 1265 /*
1266 * Add it to the IO-APIC irq-routing table:
1267 */
eea0e11c 1268 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
208fb931
EB		 1269 }
1270
1008fddc 1271 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1da177e4
LT		 1272}
1273
1da177e4
LT		 1274/*
1275 * There is a nasty bug in some older SMP boards, their mptable lies
1276 * about the timer IRQ. We do the following to work around the situation:
1277 *
1278 * - timer IRQ defaults to IO-APIC IRQ
1279 * - if this function detects that timer IRQs are defunct, then we fall
1280 * back to ISA timer IRQs
1281 */
1282static int __init timer_irq_works(void)
1283{
1284 unsigned long t1 = jiffies;
4aae0702 1285 unsigned long flags;
1da177e4 1286
4aae0702 1287 local_save_flags(flags);
1da177e4
LT		 1288 local_irq_enable();
1289 /* Let ten ticks pass... */
1290 mdelay((10 * 1000) / HZ);
4aae0702 1291 local_irq_restore(flags);
1da177e4
LT		 1292
1293 /*
1294 * Expect a few ticks at least, to be sure some possible
1295 * glue logic does not lock up after one or two first
1296 * ticks in a non-ExtINT mode. Also the local APIC
1297 * might have cached one ExtINT interrupt. Finally, at
1298 * least one tick may be lost due to delays.
1299 */
1300
1301 /* jiffies wrap? */
1302 if (jiffies - t1 > 4)
1303 return 1;
1304 return 0;
1305}
1306
1307/*
1308 * In the SMP+IOAPIC case it might happen that there are an unspecified
1309 * number of pending IRQ events unhandled. These cases are very rare,
1310 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1311 * better to do it this way as thus we do not have to be aware of
1312 * 'pending' interrupts in the IRQ path, except at this point.
1313 */
1314/*
1315 * Edge triggered needs to resend any interrupt
1316 * that was delayed but this is now handled in the device
1317 * independent code.
1318 */
1319
1320/*
1321 * Starting up a edge-triggered IO-APIC interrupt is
1322 * nasty - we need to make sure that we get the edge.
1323 * If it is already asserted for some reason, we need
1324 * return 1 to indicate that is was pending.
1325 *
1326 * This is not complete - we should be able to fake
1327 * an edge even if it isn't on the 8259A...
1328 */
1329
f29bd1ba 1330static unsigned int startup_ioapic_irq(unsigned int irq)
1da177e4
LT		 1331{
1332 int was_pending = 0;
1333 unsigned long flags;
1334
1335 spin_lock_irqsave(&ioapic_lock, flags);
1336 if (irq < 16) {
1337 disable_8259A_irq(irq);
1338 if (i8259A_irq_pending(irq))
1339 was_pending = 1;
1340 }
1341 __unmask_IO_APIC_irq(irq);
1342 spin_unlock_irqrestore(&ioapic_lock, flags);
1343
1344 return was_pending;
1345}
1346
04b9267b 1347static int ioapic_retrigger_irq(unsigned int irq)
c0ad90a3 1348{
13a79503 1349 struct irq_cfg *cfg = &irq_cfg[irq];
550f2299 1350 cpumask_t mask;
6bf2dafa 1351 unsigned long flags;
550f2299 1352
6bf2dafa 1353 spin_lock_irqsave(&vector_lock, flags);
550f2299 1354 cpus_clear(mask);
13a79503 1355 cpu_set(first_cpu(cfg->domain), mask);
550f2299 1356
13a79503 1357 send_IPI_mask(mask, cfg->vector);
6bf2dafa 1358 spin_unlock_irqrestore(&vector_lock, flags);
c0ad90a3
IM		 1359
1360 return 1;
1361}
1362
1da177e4
LT		 1363/*
1364 * Level and edge triggered IO-APIC interrupts need different handling,
1365 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1366 * handled with the level-triggered descriptor, but that one has slightly
1367 * more overhead. Level-triggered interrupts cannot be handled with the
1368 * edge-triggered handler, without risking IRQ storms and other ugly
1369 * races.
1370 */
1371
61014292
EB		 1372#ifdef CONFIG_SMP
1373asmlinkage void smp_irq_move_cleanup_interrupt(void)
1374{
1375 unsigned vector, me;
1376 ack_APIC_irq();
1377 exit_idle();
1378 irq_enter();
1379
1380 me = smp_processor_id();
1381 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
1382 unsigned int irq;
1383 struct irq_desc *desc;
1384 struct irq_cfg *cfg;
1385 irq = __get_cpu_var(vector_irq)[vector];
1386 if (irq >= NR_IRQS)
1387 continue;
1388
1389 desc = irq_desc + irq;
1390 cfg = irq_cfg + irq;
1391 spin_lock(&desc->lock);
1392 if (!cfg->move_cleanup_count)
1393 goto unlock;
1394
1395 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
1396 goto unlock;
1397
1398 __get_cpu_var(vector_irq)[vector] = -1;
1399 cfg->move_cleanup_count--;
1400unlock:
1401 spin_unlock(&desc->lock);
1402 }
1403
1404 irq_exit();
1405}
1406
1407static void irq_complete_move(unsigned int irq)
1408{
1409 struct irq_cfg *cfg = irq_cfg + irq;
1410 unsigned vector, me;
1411
1412 if (likely(!cfg->move_in_progress))
1413 return;
1414
65ea5b03 1415 vector = ~get_irq_regs()->orig_ax;
61014292 1416 me = smp_processor_id();
f0e13ae7 1417 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
61014292
EB		 1418 cpumask_t cleanup_mask;
1419
1420 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
1421 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
1422 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
1423 cfg->move_in_progress = 0;
1424 }
1425}
1426#else
1427static inline void irq_complete_move(unsigned int irq) {}
1428#endif
1429
0be6652f
EB		 1430static void ack_apic_edge(unsigned int irq)
1431{
61014292 1432 irq_complete_move(irq);
0be6652f
EB		 1433 move_native_irq(irq);
1434 ack_APIC_irq();
1435}
1436
1437static void ack_apic_level(unsigned int irq)
1438{
1439 int do_unmask_irq = 0;
1440
61014292 1441 irq_complete_move(irq);
52e3d90d 1442#ifdef CONFIG_GENERIC_PENDING_IRQ
0be6652f
EB		 1443 /* If we are moving the irq we need to mask it */
1444 if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1445 do_unmask_irq = 1;
1446 mask_IO_APIC_irq(irq);
1447 }
1448#endif
1449
1450 /*
1451 * We must acknowledge the irq before we move it or the acknowledge will
beb7dd86 1452 * not propagate properly.
0be6652f
EB		 1453 */
1454 ack_APIC_irq();
1455
1456 /* Now we can move and renable the irq */
ef3e28c5
EB		 1457 if (unlikely(do_unmask_irq)) {
1458 /* Only migrate the irq if the ack has been received.
1459 *
1460 * On rare occasions the broadcast level triggered ack gets
1461 * delayed going to ioapics, and if we reprogram the
1462 * vector while Remote IRR is still set the irq will never
1463 * fire again.
1464 *
1465 * To prevent this scenario we read the Remote IRR bit
1466 * of the ioapic. This has two effects.
1467 * - On any sane system the read of the ioapic will
1468 * flush writes (and acks) going to the ioapic from
1469 * this cpu.
1470 * - We get to see if the ACK has actually been delivered.
1471 *
1472 * Based on failed experiments of reprogramming the
1473 * ioapic entry from outside of irq context starting
1474 * with masking the ioapic entry and then polling until
1475 * Remote IRR was clear before reprogramming the
1476 * ioapic I don't trust the Remote IRR bit to be
1477 * completey accurate.
1478 *
1479 * However there appears to be no other way to plug
1480 * this race, so if the Remote IRR bit is not
1481 * accurate and is causing problems then it is a hardware bug
1482 * and you can go talk to the chipset vendor about it.
1483 */
1484 if (!io_apic_level_ack_pending(irq))
1485 move_masked_irq(irq);
0be6652f 1486 unmask_IO_APIC_irq(irq);
ef3e28c5 1487 }
0be6652f
EB		 1488}
1489
f29bd1ba
IM		 1490static struct irq_chip ioapic_chip __read_mostly = {
1491 .name = "IO-APIC",
04b9267b
EB		 1492 .startup = startup_ioapic_irq,
1493 .mask = mask_IO_APIC_irq,
1494 .unmask = unmask_IO_APIC_irq,
0be6652f
EB		 1495 .ack = ack_apic_edge,
1496 .eoi = ack_apic_level,
54d5d424 1497#ifdef CONFIG_SMP
04b9267b 1498 .set_affinity = set_ioapic_affinity_irq,
54d5d424 1499#endif
04b9267b 1500 .retrigger = ioapic_retrigger_irq,
1da177e4
LT		 1501};
1502
1503static inline void init_IO_APIC_traps(void)
1504{
1505 int irq;
1506
1507 /*
1508 * NOTE! The local APIC isn't very good at handling
1509 * multiple interrupts at the same interrupt level.
1510 * As the interrupt level is determined by taking the
1511 * vector number and shifting that right by 4, we
1512 * want to spread these out a bit so that they don't
1513 * all fall in the same interrupt level.
1514 *
1515 * Also, we've got to be careful not to trash gate
1516 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1517 */
1518 for (irq = 0; irq < NR_IRQS ; irq++) {
1519 int tmp = irq;
13a79503 1520 if (IO_APIC_IRQ(tmp) && !irq_cfg[tmp].vector) {
1da177e4
LT		 1521 /*
1522 * Hmm.. We don't have an entry for this,
1523 * so default to an old-fashioned 8259
1524 * interrupt if we can..
1525 */
1526 if (irq < 16)
1527 make_8259A_irq(irq);
1528 else
1529 /* Strange. Oh, well.. */
f29bd1ba 1530 irq_desc[irq].chip = &no_irq_chip;
1da177e4
LT		 1531 }
1532 }
1533}
1534
1535static void enable_lapic_irq (unsigned int irq)
1536{
1537 unsigned long v;
1538
1539 v = apic_read(APIC_LVT0);
11a8e778 1540 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1da177e4
LT		 1541}
1542
1543static void disable_lapic_irq (unsigned int irq)
1544{
1545 unsigned long v;
1546
1547 v = apic_read(APIC_LVT0);
11a8e778 1548 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1da177e4
LT		 1549}
1550
1551static void ack_lapic_irq (unsigned int irq)
1552{
1553 ack_APIC_irq();
1554}
1555
1556static void end_lapic_irq (unsigned int i) { /* nothing */ }
1557
6c231b7b 1558static struct hw_interrupt_type lapic_irq_type __read_mostly = {
c47e285d 1559 .name = "local-APIC",
1da177e4
LT		 1560 .typename = "local-APIC-edge",
1561 .startup = NULL, /* startup_irq() not used for IRQ0 */
1562 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1563 .enable = enable_lapic_irq,
1564 .disable = disable_lapic_irq,
1565 .ack = ack_lapic_irq,
1566 .end = end_lapic_irq,
1567};
1568
1569static void setup_nmi (void)
1570{
1571 /*
1572 * Dirty trick to enable the NMI watchdog ...
1573 * We put the 8259A master into AEOI mode and
1574 * unmask on all local APICs LVT0 as NMI.
1575 *
1576 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1577 * is from Maciej W. Rozycki - so we do not have to EOI from
1578 * the NMI handler or the timer interrupt.
1579 */
1580 printk(KERN_INFO "activating NMI Watchdog ...");
1581
1582 enable_NMI_through_LVT0(NULL);
1583
1584 printk(" done.\n");
1585}
1586
1587/*
1588 * This looks a bit hackish but it's about the only one way of sending
1589 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1590 * not support the ExtINT mode, unfortunately. We need to send these
1591 * cycles as some i82489DX-based boards have glue logic that keeps the
1592 * 8259A interrupt line asserted until INTA. --macro
1593 */
1594static inline void unlock_ExtINT_logic(void)
1595{
1008fddc 1596 int apic, pin, i;
1da177e4
LT		 1597 struct IO_APIC_route_entry entry0, entry1;
1598 unsigned char save_control, save_freq_select;
1599 unsigned long flags;
1600
1008fddc
EB		 1601 pin = find_isa_irq_pin(8, mp_INT);
1602 apic = find_isa_irq_apic(8, mp_INT);
1da177e4
LT		 1603 if (pin == -1)
1604 return;
1605
1606 spin_lock_irqsave(&ioapic_lock, flags);
1008fddc
EB		 1607 *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1608 *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1da177e4 1609 spin_unlock_irqrestore(&ioapic_lock, flags);
1008fddc 1610 clear_IO_APIC_pin(apic, pin);
1da177e4
LT		 1611
1612 memset(&entry1, 0, sizeof(entry1));
1613
1614 entry1.dest_mode = 0; /* physical delivery */
1615 entry1.mask = 0; /* unmask IRQ now */
ee4eff6f 1616 entry1.dest = hard_smp_processor_id();
1da177e4
LT		 1617 entry1.delivery_mode = dest_ExtINT;
1618 entry1.polarity = entry0.polarity;
1619 entry1.trigger = 0;
1620 entry1.vector = 0;
1621
1622 spin_lock_irqsave(&ioapic_lock, flags);
1008fddc
EB		 1623 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1624 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1da177e4
LT		 1625 spin_unlock_irqrestore(&ioapic_lock, flags);
1626
1627 save_control = CMOS_READ(RTC_CONTROL);
1628 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1629 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1630 RTC_FREQ_SELECT);
1631 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1632
1633 i = 100;
1634 while (i-- > 0) {
1635 mdelay(10);
1636 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1637 i -= 10;
1638 }
1639
1640 CMOS_WRITE(save_control, RTC_CONTROL);
1641 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1008fddc 1642 clear_IO_APIC_pin(apic, pin);
1da177e4
LT		 1643
1644 spin_lock_irqsave(&ioapic_lock, flags);
1008fddc
EB		 1645 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1646 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1da177e4
LT		 1647 spin_unlock_irqrestore(&ioapic_lock, flags);
1648}
1649
1650/*
1651 * This code may look a bit paranoid, but it's supposed to cooperate with
1652 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1653 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1654 * fanatically on his truly buggy board.
fea5f1e1
LT		 1655 *
1656 * FIXME: really need to revamp this for modern platforms only.
1da177e4 1657 */
fea5f1e1 1658static inline void check_timer(void)
1da177e4 1659{
dfbffdd8 1660 struct irq_cfg *cfg = irq_cfg + 0;
1008fddc 1661 int apic1, pin1, apic2, pin2;
4aae0702
IM		 1662 unsigned long flags;
1663
1664 local_irq_save(flags);
1da177e4
LT		 1665
1666 /*
1667 * get/set the timer IRQ vector:
1668 */
1669 disable_8259A_irq(0);
dfbffdd8 1670 assign_irq_vector(0, TARGET_CPUS);
1da177e4
LT		 1671
1672 /*
1673 * Subtle, code in do_timer_interrupt() expects an AEOI
1674 * mode for the 8259A whenever interrupts are routed
1675 * through I/O APICs. Also IRQ0 has to be enabled in
1676 * the 8259A which implies the virtual wire has to be
1677 * disabled in the local APIC.
1678 */
11a8e778 1679 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1da177e4 1680 init_8259A(1);
fea5f1e1
LT		 1681 if (timer_over_8254 > 0)
1682 enable_8259A_irq(0);
1da177e4 1683
1008fddc
EB		 1684 pin1 = find_isa_irq_pin(0, mp_INT);
1685 apic1 = find_isa_irq_apic(0, mp_INT);
1686 pin2 = ioapic_i8259.pin;
1687 apic2 = ioapic_i8259.apic;
1da177e4 1688
fea5f1e1 1689 apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
dfbffdd8 1690 cfg->vector, apic1, pin1, apic2, pin2);
b0268726 1691
fea5f1e1
LT		 1692 if (pin1 != -1) {
1693 /*
1694 * Ok, does IRQ0 through the IOAPIC work?
1695 */
1696 unmask_IO_APIC_irq(0);
1697 if (!no_timer_check && timer_irq_works()) {
1698 nmi_watchdog_default();
1699 if (nmi_watchdog == NMI_IO_APIC) {
1700 disable_8259A_irq(0);
1701 setup_nmi();
1702 enable_8259A_irq(0);
1703 }
1704 if (disable_timer_pin_1 > 0)
1705 clear_IO_APIC_pin(0, pin1);
4aae0702 1706 goto out;
fea5f1e1
LT		 1707 }
1708 clear_IO_APIC_pin(apic1, pin1);
1709 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1710 "connected to IO-APIC\n");
1711 }
1da177e4 1712
fea5f1e1
LT		 1713 apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1714 "through the 8259A ... ");
1da177e4 1715 if (pin2 != -1) {
fea5f1e1
LT		 1716 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1717 apic2, pin2);
1718 /*
1719 * legacy devices should be connected to IO APIC #0
1720 */
dfbffdd8 1721 setup_ExtINT_IRQ0_pin(apic2, pin2, cfg->vector);
fea5f1e1
LT		 1722 if (timer_irq_works()) {
1723 apic_printk(APIC_VERBOSE," works.\n");
1724 nmi_watchdog_default();
1725 if (nmi_watchdog == NMI_IO_APIC) {
1726 setup_nmi();
1727 }
4aae0702 1728 goto out;
fea5f1e1
LT		 1729 }
1730 /*
1731 * Cleanup, just in case ...
1732 */
1733 clear_IO_APIC_pin(apic2, pin2);
1da177e4 1734 }
fea5f1e1 1735 apic_printk(APIC_VERBOSE," failed.\n");
1da177e4 1736
1f992153 1737 if (nmi_watchdog == NMI_IO_APIC) {
1da177e4
LT		 1738 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1739 nmi_watchdog = 0;
1740 }
1741
1742 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1743
1744 disable_8259A_irq(0);
d1bef4ed 1745 irq_desc[0].chip = &lapic_irq_type;
dfbffdd8 1746 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
1da177e4
LT		 1747 enable_8259A_irq(0);
1748
1749 if (timer_irq_works()) {
5b922cd4 1750 apic_printk(APIC_VERBOSE," works.\n");
4aae0702 1751 goto out;
1da177e4 1752 }
dfbffdd8 1753 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
1da177e4
LT		 1754 apic_printk(APIC_VERBOSE," failed.\n");
1755
1756 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1757
1758 init_8259A(0);
1759 make_8259A_irq(0);
11a8e778 1760 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1da177e4
LT		 1761
1762 unlock_ExtINT_logic();
1763
1764 if (timer_irq_works()) {
1765 apic_printk(APIC_VERBOSE," works.\n");
4aae0702 1766 goto out;
1da177e4
LT		 1767 }
1768 apic_printk(APIC_VERBOSE," failed :(.\n");
1769 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
4aae0702
IM		 1770out:
1771 local_irq_restore(flags);
1da177e4
LT		 1772}
1773
14d98cad
AK		 1774static int __init notimercheck(char *s)
1775{
1776 no_timer_check = 1;
1777 return 1;
1778}
1779__setup("no_timer_check", notimercheck);
1780
1da177e4
LT		 1781/*
1782 *
676b1855 1783 * IRQs that are handled by the PIC in the MPS IOAPIC case.
1da177e4
LT		 1784 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1785 * Linux doesn't really care, as it's not actually used
1786 * for any interrupt handling anyway.
1787 */
1788#define PIC_IRQS (1<<2)
1789
1790void __init setup_IO_APIC(void)
1791{
1c69524c
YL		 1792
1793 /*
1794 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
1795 */
1da177e4
LT		 1796
1797 if (acpi_ioapic)
1798 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1799 else
1800 io_apic_irqs = ~PIC_IRQS;
1801
1802 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1803
1da177e4
LT		 1804 sync_Arb_IDs();
1805 setup_IO_APIC_irqs();
1806 init_IO_APIC_traps();
1807 check_timer();
1808 if (!acpi_ioapic)
1809 print_IO_APIC();
1810}
1811
1812struct sysfs_ioapic_data {
1813 struct sys_device dev;
1814 struct IO_APIC_route_entry entry[0];
1815};
1816static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1817
0b9c33a7 1818static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1da177e4
LT		 1819{
1820 struct IO_APIC_route_entry *entry;
1821 struct sysfs_ioapic_data *data;
1da177e4
LT		 1822 int i;
1823
1824 data = container_of(dev, struct sysfs_ioapic_data, dev);
1825 entry = data->entry;
eea0e11c
AK		 1826 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1827 *entry = ioapic_read_entry(dev->id, i);
1da177e4
LT		 1828
1829 return 0;
1830}
1831
1832static int ioapic_resume(struct sys_device *dev)
1833{
1834 struct IO_APIC_route_entry *entry;
1835 struct sysfs_ioapic_data *data;
1836 unsigned long flags;
1837 union IO_APIC_reg_00 reg_00;
1838 int i;
1839
1840 data = container_of(dev, struct sysfs_ioapic_data, dev);
1841 entry = data->entry;
1842
1843 spin_lock_irqsave(&ioapic_lock, flags);
1844 reg_00.raw = io_apic_read(dev->id, 0);
1845 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1846 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1847 io_apic_write(dev->id, 0, reg_00.raw);
1848 }
1da177e4 1849 spin_unlock_irqrestore(&ioapic_lock, flags);
eea0e11c
AK		 1850 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1851 ioapic_write_entry(dev->id, i, entry[i]);
1da177e4
LT		 1852
1853 return 0;
1854}
1855
1856static struct sysdev_class ioapic_sysdev_class = {
af5ca3f4 1857 .name = "ioapic",
1da177e4
LT		 1858 .suspend = ioapic_suspend,
1859 .resume = ioapic_resume,
1860};
1861
1862static int __init ioapic_init_sysfs(void)
1863{
1864 struct sys_device * dev;
cddf7ff7 1865 int i, size, error;
1da177e4
LT		 1866
1867 error = sysdev_class_register(&ioapic_sysdev_class);
1868 if (error)
1869 return error;
1870
1871 for (i = 0; i < nr_ioapics; i++ ) {
1872 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1873 * sizeof(struct IO_APIC_route_entry);
cddf7ff7 1874 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
1da177e4
LT		 1875 if (!mp_ioapic_data[i]) {
1876 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1877 continue;
1878 }
1da177e4
LT		 1879 dev = &mp_ioapic_data[i]->dev;
1880 dev->id = i;
1881 dev->cls = &ioapic_sysdev_class;
1882 error = sysdev_register(dev);
1883 if (error) {
1884 kfree(mp_ioapic_data[i]);
1885 mp_ioapic_data[i] = NULL;
1886 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1887 continue;
1888 }
1889 }
1890
1891 return 0;
1892}
1893
1894device_initcall(ioapic_init_sysfs);
1895
c4fa0bbf 1896/*
04b9267b 1897 * Dynamic irq allocate and deallocation
c4fa0bbf
EB		 1898 */
1899int create_irq(void)
1900{
04b9267b
EB		 1901 /* Allocate an unused irq */
1902 int irq;
1903 int new;
c4fa0bbf 1904 unsigned long flags;
c4fa0bbf 1905
04b9267b
EB		 1906 irq = -ENOSPC;
1907 spin_lock_irqsave(&vector_lock, flags);
1908 for (new = (NR_IRQS - 1); new >= 0; new--) {
1909 if (platform_legacy_irq(new))
1910 continue;
13a79503 1911 if (irq_cfg[new].vector != 0)
04b9267b 1912 continue;
dfbffdd8 1913 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
04b9267b
EB		 1914 irq = new;
1915 break;
1916 }
1917 spin_unlock_irqrestore(&vector_lock, flags);
c4fa0bbf 1918
04b9267b 1919 if (irq >= 0) {
c4fa0bbf
EB		 1920 dynamic_irq_init(irq);
1921 }
1922 return irq;
1923}
1924
1925void destroy_irq(unsigned int irq)
1926{
1927 unsigned long flags;
c4fa0bbf
EB		 1928
1929 dynamic_irq_cleanup(irq);
1930
1931 spin_lock_irqsave(&vector_lock, flags);
5df0287e 1932 __clear_irq_vector(irq);
c4fa0bbf
EB		 1933 spin_unlock_irqrestore(&vector_lock, flags);
1934}
c4fa0bbf 1935
589e367f 1936/*
676b1855 1937 * MSI message composition
589e367f
EB		 1938 */
1939#ifdef CONFIG_PCI_MSI
3b7d1921 1940static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
589e367f 1941{
dfbffdd8
EB		 1942 struct irq_cfg *cfg = irq_cfg + irq;
1943 int err;
589e367f 1944 unsigned dest;
c7111c13 1945 cpumask_t tmp;
589e367f 1946
dfbffdd8
EB		 1947 tmp = TARGET_CPUS;
1948 err = assign_irq_vector(irq, tmp);
1949 if (!err) {
1950 cpus_and(tmp, cfg->domain, tmp);
589e367f
EB		 1951 dest = cpu_mask_to_apicid(tmp);
1952
1953 msg->address_hi = MSI_ADDR_BASE_HI;
1954 msg->address_lo =
1955 MSI_ADDR_BASE_LO |
1956 ((INT_DEST_MODE == 0) ?
1957 MSI_ADDR_DEST_MODE_PHYSICAL:
1958 MSI_ADDR_DEST_MODE_LOGICAL) |
1959 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1960 MSI_ADDR_REDIRECTION_CPU:
1961 MSI_ADDR_REDIRECTION_LOWPRI) |
1962 MSI_ADDR_DEST_ID(dest);
1963
1964 msg->data =
1965 MSI_DATA_TRIGGER_EDGE |
1966 MSI_DATA_LEVEL_ASSERT |
1967 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1968 MSI_DATA_DELIVERY_FIXED:
1969 MSI_DATA_DELIVERY_LOWPRI) |
dfbffdd8 1970 MSI_DATA_VECTOR(cfg->vector);
589e367f 1971 }
dfbffdd8 1972 return err;
589e367f
EB		 1973}
1974
3b7d1921
EB		 1975#ifdef CONFIG_SMP
1976static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
589e367f 1977{
dfbffdd8 1978 struct irq_cfg *cfg = irq_cfg + irq;
3b7d1921
EB		 1979 struct msi_msg msg;
1980 unsigned int dest;
1981 cpumask_t tmp;
3b7d1921
EB		 1982
1983 cpus_and(tmp, mask, cpu_online_map);
1984 if (cpus_empty(tmp))
5ff5115e 1985 return;
589e367f 1986
dfbffdd8 1987 if (assign_irq_vector(irq, mask))
3b7d1921 1988 return;
550f2299 1989
dfbffdd8 1990 cpus_and(tmp, cfg->domain, mask);
3b7d1921 1991 dest = cpu_mask_to_apicid(tmp);
589e367f 1992
3b7d1921
EB		 1993 read_msi_msg(irq, &msg);
1994
1995 msg.data &= ~MSI_DATA_VECTOR_MASK;
dfbffdd8 1996 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3b7d1921
EB		 1997 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
1998 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
1999
2000 write_msi_msg(irq, &msg);
9f0a5ba5 2001 irq_desc[irq].affinity = mask;
589e367f 2002}
3b7d1921 2003#endif /* CONFIG_SMP */
589e367f 2004
3b7d1921
EB		 2005/*
2006 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2007 * which implement the MSI or MSI-X Capability Structure.
2008 */
2009static struct irq_chip msi_chip = {
2010 .name = "PCI-MSI",
2011 .unmask = unmask_msi_irq,
2012 .mask = mask_msi_irq,
2013 .ack = ack_apic_edge,
2014#ifdef CONFIG_SMP
2015 .set_affinity = set_msi_irq_affinity,
2016#endif
2017 .retrigger = ioapic_retrigger_irq,
589e367f
EB		 2018};
2019
f7feaca7 2020int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
3b7d1921
EB		 2021{
2022 struct msi_msg msg;
f7feaca7
EB		 2023 int irq, ret;
2024 irq = create_irq();
2025 if (irq < 0)
2026 return irq;
2027
3b7d1921 2028 ret = msi_compose_msg(dev, irq, &msg);
f7feaca7
EB		 2029 if (ret < 0) {
2030 destroy_irq(irq);
3b7d1921 2031 return ret;
f7feaca7 2032 }
3b7d1921 2033
7fe3730d 2034 set_irq_msi(irq, desc);
3b7d1921
EB		 2035 write_msi_msg(irq, &msg);
2036
a460e745 2037 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3b7d1921 2038
7fe3730d 2039 return 0;
3b7d1921
EB		 2040}
2041
2042void arch_teardown_msi_irq(unsigned int irq)
2043{
f7feaca7 2044 destroy_irq(irq);
3b7d1921
EB		 2045}
2046
3460a6d9
KA		 2047#ifdef CONFIG_DMAR
2048#ifdef CONFIG_SMP
2049static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask)
2050{
2051 struct irq_cfg *cfg = irq_cfg + irq;
2052 struct msi_msg msg;
2053 unsigned int dest;
2054 cpumask_t tmp;
2055
2056 cpus_and(tmp, mask, cpu_online_map);
2057 if (cpus_empty(tmp))
2058 return;
2059
2060 if (assign_irq_vector(irq, mask))
2061 return;
2062
2063 cpus_and(tmp, cfg->domain, mask);
2064 dest = cpu_mask_to_apicid(tmp);
2065
2066 dmar_msi_read(irq, &msg);
2067
2068 msg.data &= ~MSI_DATA_VECTOR_MASK;
2069 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2070 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2071 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2072
2073 dmar_msi_write(irq, &msg);
2074 irq_desc[irq].affinity = mask;
2075}
2076#endif /* CONFIG_SMP */
2077
2078struct irq_chip dmar_msi_type = {
2079 .name = "DMAR_MSI",
2080 .unmask = dmar_msi_unmask,
2081 .mask = dmar_msi_mask,
2082 .ack = ack_apic_edge,
2083#ifdef CONFIG_SMP
2084 .set_affinity = dmar_msi_set_affinity,
2085#endif
2086 .retrigger = ioapic_retrigger_irq,
2087};
2088
2089int arch_setup_dmar_msi(unsigned int irq)
2090{
2091 int ret;
2092 struct msi_msg msg;
2093
2094 ret = msi_compose_msg(NULL, irq, &msg);
2095 if (ret < 0)
2096 return ret;
2097 dmar_msi_write(irq, &msg);
2098 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
2099 "edge");
2100 return 0;
2101}
2102#endif
589e367f 2103
3460a6d9 2104#endif /* CONFIG_PCI_MSI */
8b955b0d
EB		 2105/*
2106 * Hypertransport interrupt support
2107 */
2108#ifdef CONFIG_HT_IRQ
2109
2110#ifdef CONFIG_SMP
2111
2112static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
2113{
ec68307c
EB		 2114 struct ht_irq_msg msg;
2115 fetch_ht_irq_msg(irq, &msg);
8b955b0d 2116
ec68307c
EB		 2117 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
2118 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
8b955b0d 2119
ec68307c
EB		 2120 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
2121 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
8b955b0d 2122
ec68307c 2123 write_ht_irq_msg(irq, &msg);
8b955b0d
EB		 2124}
2125
2126static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2127{
dfbffdd8 2128 struct irq_cfg *cfg = irq_cfg + irq;
8b955b0d
EB		 2129 unsigned int dest;
2130 cpumask_t tmp;
8b955b0d
EB		 2131
2132 cpus_and(tmp, mask, cpu_online_map);
2133 if (cpus_empty(tmp))
5ff5115e 2134 return;
8b955b0d 2135
dfbffdd8 2136 if (assign_irq_vector(irq, mask))
8b955b0d
EB		 2137 return;
2138
dfbffdd8 2139 cpus_and(tmp, cfg->domain, mask);
8b955b0d
EB		 2140 dest = cpu_mask_to_apicid(tmp);
2141
dfbffdd8 2142 target_ht_irq(irq, dest, cfg->vector);
9f0a5ba5 2143 irq_desc[irq].affinity = mask;
8b955b0d
EB		 2144}
2145#endif
2146
c37e108d 2147static struct irq_chip ht_irq_chip = {
8b955b0d
EB		 2148 .name = "PCI-HT",
2149 .mask = mask_ht_irq,
2150 .unmask = unmask_ht_irq,
2151 .ack = ack_apic_edge,
2152#ifdef CONFIG_SMP
2153 .set_affinity = set_ht_irq_affinity,
2154#endif
2155 .retrigger = ioapic_retrigger_irq,
2156};
2157
2158int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2159{
dfbffdd8
EB		 2160 struct irq_cfg *cfg = irq_cfg + irq;
2161 int err;
c7111c13 2162 cpumask_t tmp;
8b955b0d 2163
dfbffdd8
EB		 2164 tmp = TARGET_CPUS;
2165 err = assign_irq_vector(irq, tmp);
2166 if (!err) {
ec68307c 2167 struct ht_irq_msg msg;
8b955b0d 2168 unsigned dest;
8b955b0d 2169
dfbffdd8 2170 cpus_and(tmp, cfg->domain, tmp);
8b955b0d
EB		 2171 dest = cpu_mask_to_apicid(tmp);
2172
ec68307c 2173 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
8b955b0d 2174
ec68307c
EB		 2175 msg.address_lo =
2176 HT_IRQ_LOW_BASE |
8b955b0d 2177 HT_IRQ_LOW_DEST_ID(dest) |
dfbffdd8 2178 HT_IRQ_LOW_VECTOR(cfg->vector) |
8b955b0d
EB		 2179 ((INT_DEST_MODE == 0) ?
2180 HT_IRQ_LOW_DM_PHYSICAL :
2181 HT_IRQ_LOW_DM_LOGICAL) |
2182 HT_IRQ_LOW_RQEOI_EDGE |
2183 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2184 HT_IRQ_LOW_MT_FIXED :
ec68307c
EB		 2185 HT_IRQ_LOW_MT_ARBITRATED) |
2186 HT_IRQ_LOW_IRQ_MASKED;
8b955b0d 2187
ec68307c 2188 write_ht_irq_msg(irq, &msg);
8b955b0d 2189
a460e745
IM		 2190 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2191 handle_edge_irq, "edge");
8b955b0d 2192 }
dfbffdd8 2193 return err;
8b955b0d
EB		 2194}
2195#endif /* CONFIG_HT_IRQ */
2196
1da177e4
LT		 2197/* --------------------------------------------------------------------------
2198 ACPI-based IOAPIC Configuration
2199 -------------------------------------------------------------------------- */
2200
888ba6c6 2201#ifdef CONFIG_ACPI
1da177e4
LT		 2202
2203#define IO_APIC_MAX_ID 0xFE
2204
1da177e4
LT		 2205int __init io_apic_get_redir_entries (int ioapic)
2206{
2207 union IO_APIC_reg_01 reg_01;
2208 unsigned long flags;
2209
2210 spin_lock_irqsave(&ioapic_lock, flags);
2211 reg_01.raw = io_apic_read(ioapic, 1);
2212 spin_unlock_irqrestore(&ioapic_lock, flags);
2213
2214 return reg_01.bits.entries;
2215}
2216
2217
50eca3eb 2218int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
1da177e4 2219{
1da177e4
LT		 2220 if (!IO_APIC_IRQ(irq)) {
2221 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2222 ioapic);
2223 return -EINVAL;
2224 }
2225
550f2299
EB		 2226 /*
2227 * IRQs < 16 are already in the irq_2_pin[] map
2228 */
2229 if (irq >= 16)
2230 add_pin_to_irq(irq, ioapic, pin);
2231
a8c8a367 2232 setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
1da177e4
LT		 2233
2234 return 0;
2235}
2236
1da177e4 2237
61fd47e0
SL		 2238int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
2239{
2240 int i;
2241
2242 if (skip_ioapic_setup)
2243 return -1;
2244
2245 for (i = 0; i < mp_irq_entries; i++)
2246 if (mp_irqs[i].mpc_irqtype == mp_INT &&
2247 mp_irqs[i].mpc_srcbusirq == bus_irq)
2248 break;
2249 if (i >= mp_irq_entries)
2250 return -1;
2251
2252 *trigger = irq_trigger(i);
2253 *polarity = irq_polarity(i);
2254 return 0;
2255}
2256
2257#endif /* CONFIG_ACPI */
1da177e4
LT		 2258
2259/*
2260 * This function currently is only a helper for the i386 smp boot process where
2261 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2262 * so mask in all cases should simply be TARGET_CPUS
2263 */
54d5d424 2264#ifdef CONFIG_SMP
1da177e4
LT		 2265void __init setup_ioapic_dest(void)
2266{
2267 int pin, ioapic, irq, irq_entry;
2268
2269 if (skip_ioapic_setup == 1)
2270 return;
2271
2272 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2273 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2274 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2275 if (irq_entry == -1)
2276 continue;
2277 irq = pin_2_irq(irq_entry, ioapic, pin);
ad892f5e
YL		 2278
2279 /* setup_IO_APIC_irqs could fail to get vector for some device
2280 * when you have too many devices, because at that time only boot
2281 * cpu is online.
2282 */
13a79503 2283 if (!irq_cfg[irq].vector)
a8c8a367
EB		 2284 setup_IO_APIC_irq(ioapic, pin, irq,
2285 irq_trigger(irq_entry),
2286 irq_polarity(irq_entry));
ad892f5e
YL		 2287 else
2288 set_ioapic_affinity_irq(irq, TARGET_CPUS);
1da177e4
LT		 2289 }
2290
2291 }
2292}
54d5d424 2293#endif
61fd47e0 2294
3e35a0e5
TG		 2295#define IOAPIC_RESOURCE_NAME_SIZE 11
2296
2297static struct resource *ioapic_resources;
2298
2299static struct resource * __init ioapic_setup_resources(void)
2300{
2301 unsigned long n;
2302 struct resource *res;
2303 char *mem;
2304 int i;
2305
2306 if (nr_ioapics <= 0)
2307 return NULL;
2308
2309 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
2310 n *= nr_ioapics;
2311
2312 mem = alloc_bootmem(n);
2313 res = (void *)mem;
2314
2315 if (mem != NULL) {
2316 memset(mem, 0, n);
2317 mem += sizeof(struct resource) * nr_ioapics;
2318
2319 for (i = 0; i < nr_ioapics; i++) {
2320 res[i].name = mem;
2321 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
2322 sprintf(mem, "IOAPIC %u", i);
2323 mem += IOAPIC_RESOURCE_NAME_SIZE;
2324 }
2325 }
2326
2327 ioapic_resources = res;
2328
2329 return res;
2330}
2331
2332void __init ioapic_init_mappings(void)
2333{
2334 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2335 struct resource *ioapic_res;
2336 int i;
2337
2338 ioapic_res = ioapic_setup_resources();
2339 for (i = 0; i < nr_ioapics; i++) {
2340 if (smp_found_config) {
2341 ioapic_phys = mp_ioapics[i].mpc_apicaddr;
2342 } else {
2343 ioapic_phys = (unsigned long)
2344 alloc_bootmem_pages(PAGE_SIZE);
2345 ioapic_phys = __pa(ioapic_phys);
2346 }
2347 set_fixmap_nocache(idx, ioapic_phys);
2348 apic_printk(APIC_VERBOSE,
2349 "mapped IOAPIC to %016lx (%016lx)\n",
2350 __fix_to_virt(idx), ioapic_phys);
2351 idx++;
2352
2353 if (ioapic_res != NULL) {
2354 ioapic_res->start = ioapic_phys;
2355 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
2356 ioapic_res++;
2357 }
2358 }
2359}
2360
2361static int __init ioapic_insert_resources(void)
2362{
2363 int i;
2364 struct resource *r = ioapic_resources;
2365
2366 if (!r) {
2367 printk(KERN_ERR
2368 "IO APIC resources could be not be allocated.\n");
2369 return -1;
2370 }
2371
2372 for (i = 0; i < nr_ioapics; i++) {
2373 insert_resource(&iomem_resource, r);
2374 r++;
2375 }
2376
2377 return 0;
2378}
2379
2380/* Insert the IO APIC resources after PCI initialization has occured to handle
2381 * IO APICS that are mapped in on a BAR in PCI space. */
2382late_initcall(ioapic_insert_resources);
2383
Linux kernel - Deliverables
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