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x86: make 64 handle sis_apic_bug like the 32 bit
[deliverable/linux.git] / arch / x86 / kernel / io_apic_64.c
CommitLineData
1da177e4
LT		 1/*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23#include <linux/mm.h>
1da177e4
LT		 24#include <linux/interrupt.h>
25#include <linux/init.h>
26#include <linux/delay.h>
27#include <linux/sched.h>
589e367f 28#include <linux/pci.h>
1da177e4 29#include <linux/mc146818rtc.h>
d4057bdb 30#include <linux/compiler.h>
1da177e4 31#include <linux/acpi.h>
d4057bdb 32#include <linux/module.h>
1da177e4 33#include <linux/sysdev.h>
3b7d1921 34#include <linux/msi.h>
95d77884 35#include <linux/htirq.h>
d4057bdb
YL		 36#include <linux/freezer.h>
37#include <linux/kthread.h>
38#include <linux/jiffies.h> /* time_after() */
ab688059
AK		 39#ifdef CONFIG_ACPI
40#include <acpi/acpi_bus.h>
41#endif
3e35a0e5 42#include <linux/bootmem.h>
89027d35 43#include <linux/dmar.h>
1da177e4 44
61014292 45#include <asm/idle.h>
1da177e4
LT		 46#include <asm/io.h>
47#include <asm/smp.h>
48#include <asm/desc.h>
49#include <asm/proto.h>
8d916406 50#include <asm/acpi.h>
ca8642f6 51#include <asm/dma.h>
d4057bdb 52#include <asm/timer.h>
17c44697 53#include <asm/i8259.h>
3e4ff115 54#include <asm/nmi.h>
589e367f 55#include <asm/msidef.h>
8b955b0d 56#include <asm/hypertransport.h>
d4057bdb 57#include <asm/setup.h>
89027d35 58#include <asm/irq_remapping.h>
1da177e4 59
5af5573e 60#include <mach_ipi.h>
dd46e3ca 61#include <mach_apic.h>
d4057bdb 62#include <mach_apicdef.h>
5af5573e 63
32f71aff
MR		 64#define __apicdebuginit(type) static type __init
65
efa2559f
YL		 66int ioapic_force;
67
f876d213
YL		 68/*
69 * Is the SiS APIC rmw bug present ?
70 * -1 = don't know, 0 = no, 1 = yes
71 */
72int sis_apic_bug = -1;
efa2559f
YL		 73
74static DEFINE_SPINLOCK(ioapic_lock);
75static DEFINE_SPINLOCK(vector_lock);
76
77int first_free_entry;
78/*
79 * Rough estimation of how many shared IRQs there are, can
80 * be changed anytime.
81 */
82int pin_map_size;
83
84/*
85 * # of IRQ routing registers
86 */
87int nr_ioapic_registers[MAX_IO_APICS];
88
89/* I/O APIC entries */
90struct mp_config_ioapic mp_ioapics[MAX_IO_APICS];
91int nr_ioapics;
92
93/* MP IRQ source entries */
94struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
95
96/* # of MP IRQ source entries */
97int mp_irq_entries;
98
99DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
100
101int skip_ioapic_setup;
102
103static int __init parse_noapic(char *str)
104{
105 disable_ioapic_setup();
106 return 0;
107}
108early_param("noapic", parse_noapic);
109
110
3ac2de48 111struct irq_cfg;
e5a53714 112struct irq_pin_list;
13a79503 113struct irq_cfg {
3ac2de48
YL		 114 unsigned int irq;
115 struct irq_cfg *next;
e5a53714 116 struct irq_pin_list *irq_2_pin;
13a79503 117 cpumask_t domain;
61014292
EB		 118 cpumask_t old_domain;
119 unsigned move_cleanup_count;
13a79503 120 u8 vector;
61014292 121 u8 move_in_progress : 1;
13a79503
EB		 122};
123
124/* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
301e6190 125static struct irq_cfg irq_cfg_legacy[] __initdata = {
3ac2de48
YL		 126 [0] = { .irq = 0, .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
127 [1] = { .irq = 1, .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
128 [2] = { .irq = 2, .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
129 [3] = { .irq = 3, .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
130 [4] = { .irq = 4, .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
131 [5] = { .irq = 5, .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
132 [6] = { .irq = 6, .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
133 [7] = { .irq = 7, .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
134 [8] = { .irq = 8, .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
135 [9] = { .irq = 9, .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
136 [10] = { .irq = 10, .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
137 [11] = { .irq = 11, .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
138 [12] = { .irq = 12, .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
139 [13] = { .irq = 13, .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
140 [14] = { .irq = 14, .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
141 [15] = { .irq = 15, .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
13a79503
EB		 142};
143
3ac2de48
YL		 144static struct irq_cfg irq_cfg_init = { .irq = -1U, };
145/* need to be biger than size of irq_cfg_legacy */
146static int nr_irq_cfg = 32;
147
148static int __init parse_nr_irq_cfg(char *arg)
149{
150 if (arg) {
151 nr_irq_cfg = simple_strtoul(arg, NULL, 0);
152 if (nr_irq_cfg < 32)
153 nr_irq_cfg = 32;
154 }
155 return 0;
156}
157
158early_param("nr_irq_cfg", parse_nr_irq_cfg);
159
160static void init_one_irq_cfg(struct irq_cfg *cfg)
161{
162 memcpy(cfg, &irq_cfg_init, sizeof(struct irq_cfg));
163}
301e6190 164
a2f9f438
YL		 165static struct irq_cfg *irq_cfgx;
166static struct irq_cfg *irq_cfgx_free;
301e6190
YL		 167static void __init init_work(void *data)
168{
169 struct dyn_array *da = data;
3ac2de48 170 struct irq_cfg *cfg;
a2f9f438 171 int legacy_count;
3ac2de48 172 int i;
301e6190 173
3ac2de48
YL		 174 cfg = *da->name;
175
176 memcpy(cfg, irq_cfg_legacy, sizeof(irq_cfg_legacy));
177
a2f9f438
YL		 178 legacy_count = sizeof(irq_cfg_legacy)/sizeof(irq_cfg_legacy[0]);
179 for (i = legacy_count; i < *da->nr; i++)
3ac2de48
YL		 180 init_one_irq_cfg(&cfg[i]);
181
182 for (i = 1; i < *da->nr; i++)
183 cfg[i-1].next = &cfg[i];
a2f9f438
YL		 184
185 irq_cfgx_free = &irq_cfgx[legacy_count];
186 irq_cfgx[legacy_count - 1].next = NULL;
301e6190
YL		 187}
188
46b8214d 189#define for_each_irq_cfg(cfg) \
a2f9f438 190 for (cfg = irq_cfgx; cfg; cfg = cfg->next)
46b8214d 191
3ac2de48
YL		 192DEFINE_DYN_ARRAY(irq_cfgx, sizeof(struct irq_cfg), nr_irq_cfg, PAGE_SIZE, init_work);
193
194static struct irq_cfg *irq_cfg(unsigned int irq)
195{
196 struct irq_cfg *cfg;
197
a2f9f438 198 cfg = irq_cfgx;
3ac2de48
YL		 199 while (cfg) {
200 if (cfg->irq == irq)
201 return cfg;
202
3ac2de48
YL		 203 cfg = cfg->next;
204 }
205
206 return NULL;
207}
208
209static struct irq_cfg *irq_cfg_alloc(unsigned int irq)
210{
211 struct irq_cfg *cfg, *cfg_pri;
212 int i;
213 int count = 0;
214
a2f9f438 215 cfg_pri = cfg = irq_cfgx;
3ac2de48
YL		 216 while (cfg) {
217 if (cfg->irq == irq)
218 return cfg;
219
3ac2de48
YL		 220 cfg_pri = cfg;
221 cfg = cfg->next;
222 count++;
223 }
224
a2f9f438
YL		 225 if (!irq_cfgx_free) {
226 unsigned long phys;
227 unsigned long total_bytes;
228 /*
229 * we run out of pre-allocate ones, allocate more
230 */
231 printk(KERN_DEBUG "try to get more irq_cfg %d\n", nr_irq_cfg);
3ac2de48 232
a2f9f438
YL		 233 total_bytes = sizeof(struct irq_cfg) * nr_irq_cfg;
234 if (after_bootmem)
235 cfg = kzalloc(total_bytes, GFP_ATOMIC);
236 else
237 cfg = __alloc_bootmem_nopanic(total_bytes, PAGE_SIZE, 0);
3ac2de48 238
a2f9f438
YL		 239 if (!cfg)
240 panic("please boot with nr_irq_cfg= %d\n", count * 2);
3ac2de48 241
a2f9f438
YL		 242 phys = __pa(cfg);
243 printk(KERN_DEBUG "irq_irq ==> [%#lx - %#lx]\n", phys, phys + total_bytes);
3ac2de48 244
a2f9f438
YL		 245 for (i = 0; i < nr_irq_cfg; i++)
246 init_one_irq_cfg(&cfg[i]);
3ac2de48 247
a2f9f438
YL		 248 for (i = 1; i < nr_irq_cfg; i++)
249 cfg[i-1].next = &cfg[i];
3ac2de48 250
a2f9f438
YL		 251 irq_cfgx_free = cfg;
252 }
253
254 cfg = irq_cfgx_free;
255 irq_cfgx_free = irq_cfgx_free->next;
256 cfg->next = NULL;
257 if (cfg_pri)
258 cfg_pri->next = cfg;
259 else
260 irq_cfgx = cfg;
261 cfg->irq = irq;
262 printk(KERN_DEBUG "found new irq_cfg for irq %d\n", cfg->irq);
263#ifdef CONFIG_HAVE_SPARSE_IRQ_DEBUG
264 {
265 /* dump the results */
266 struct irq_cfg *cfg;
267 unsigned long phys;
268 unsigned long bytes = sizeof(struct irq_cfg);
269
270 printk(KERN_DEBUG "=========================== %d\n", irq);
271 printk(KERN_DEBUG "irq_cfg dump after get that for %d\n", irq);
272 for_each_irq_cfg(cfg) {
273 phys = __pa(cfg);
274 printk(KERN_DEBUG "irq_cfg %d ==> [%#lx - %#lx]\n", cfg->irq, phys, phys + bytes);
275 }
276 printk(KERN_DEBUG "===========================\n");
277 }
278#endif
3ac2de48
YL		 279 return cfg;
280}
301e6190 281
1da177e4
LT		 282/*
283 * This is performance-critical, we want to do it O(1)
284 *
285 * the indexing order of this array favors 1:1 mappings
286 * between pins and IRQs.
287 */
288
e5a53714
YL		 289struct irq_pin_list {
290 int apic, pin;
291 struct irq_pin_list *next;
292};
293
294static struct irq_pin_list *irq_2_pin_head;
295/* fill one page ? */
296static int nr_irq_2_pin = 0x100;
297static struct irq_pin_list *irq_2_pin_ptr;
298static void __init irq_2_pin_init_work(void *data)
299{
300 struct dyn_array *da = data;
301 struct irq_pin_list *pin;
302 int i;
303
304 pin = *da->name;
305
306 for (i = 1; i < *da->nr; i++)
307 pin[i-1].next = &pin[i];
308
309 irq_2_pin_ptr = &pin[0];
310}
311DEFINE_DYN_ARRAY(irq_2_pin_head, sizeof(struct irq_pin_list), nr_irq_2_pin, PAGE_SIZE, irq_2_pin_init_work);
312
313static struct irq_pin_list *get_one_free_irq_2_pin(void)
314{
315 struct irq_pin_list *pin;
316 int i;
317
318 pin = irq_2_pin_ptr;
319
320 if (pin) {
321 irq_2_pin_ptr = pin->next;
322 pin->next = NULL;
323 return pin;
324 }
325
326 /*
327 * we run out of pre-allocate ones, allocate more
328 */
329 printk(KERN_DEBUG "try to get more irq_2_pin %d\n", nr_irq_2_pin);
330
331 if (after_bootmem)
332 pin = kzalloc(sizeof(struct irq_pin_list)*nr_irq_2_pin,
333 GFP_ATOMIC);
334 else
335 pin = __alloc_bootmem_nopanic(sizeof(struct irq_pin_list) *
336 nr_irq_2_pin, PAGE_SIZE, 0);
337
338 if (!pin)
339 panic("can not get more irq_2_pin\n");
301e6190 340
e5a53714
YL		 341 for (i = 1; i < nr_irq_2_pin; i++)
342 pin[i-1].next = &pin[i];
301e6190 343
e5a53714
YL		 344 irq_2_pin_ptr = pin->next;
345 pin->next = NULL;
346
347 return pin;
348}
1da177e4 349
6c0ffb9d
LT		 350struct io_apic {
351 unsigned int index;
352 unsigned int unused[3];
353 unsigned int data;
354};
355
356static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
357{
358 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
ec2cd0a2 359 + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK);
6c0ffb9d
LT		 360}
361
362static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
363{
364 struct io_apic __iomem *io_apic = io_apic_base(apic);
365 writel(reg, &io_apic->index);
366 return readl(&io_apic->data);
367}
368
369static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
370{
371 struct io_apic __iomem *io_apic = io_apic_base(apic);
372 writel(reg, &io_apic->index);
373 writel(value, &io_apic->data);
374}
375
376/*
377 * Re-write a value: to be used for read-modify-write
378 * cycles where the read already set up the index register.
379 */
f876d213 380static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
6c0ffb9d
LT		 381{
382 struct io_apic __iomem *io_apic = io_apic_base(apic);
f876d213
YL		 383 if (sis_apic_bug)
384 writel(reg, &io_apic->index);
6c0ffb9d
LT		 385 writel(value, &io_apic->data);
386}
387
9d25cb08 388static bool io_apic_level_ack_pending(unsigned int irq)
ef3e28c5
EB		 389{
390 struct irq_pin_list *entry;
391 unsigned long flags;
e5a53714 392 struct irq_cfg *cfg = irq_cfg(irq);
ef3e28c5
EB		 393
394 spin_lock_irqsave(&ioapic_lock, flags);
e5a53714 395 entry = cfg->irq_2_pin;
ef3e28c5
EB		 396 for (;;) {
397 unsigned int reg;
398 int pin;
399
e5a53714 400 if (!entry)
ef3e28c5 401 break;
e5a53714 402 pin = entry->pin;
ef3e28c5
EB		 403 reg = io_apic_read(entry->apic, 0x10 + pin*2);
404 /* Is the remote IRR bit set? */
46b3b4ef 405 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
9d25cb08
AM		 406 spin_unlock_irqrestore(&ioapic_lock, flags);
407 return true;
408 }
ef3e28c5
EB		 409 if (!entry->next)
410 break;
e5a53714 411 entry = entry->next;
ef3e28c5
EB		 412 }
413 spin_unlock_irqrestore(&ioapic_lock, flags);
9d25cb08
AM		 414
415 return false;
ef3e28c5
EB		 416}
417
eea0e11c
AK		 418union entry_union {
419 struct { u32 w1, w2; };
420 struct IO_APIC_route_entry entry;
421};
422
423static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
424{
425 union entry_union eu;
426 unsigned long flags;
427 spin_lock_irqsave(&ioapic_lock, flags);
428 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
429 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
430 spin_unlock_irqrestore(&ioapic_lock, flags);
431 return eu.entry;
432}
433
48797ebd
LT		 434/*
435 * When we write a new IO APIC routing entry, we need to write the high
436 * word first! If the mask bit in the low word is clear, we will enable
437 * the interrupt, and we need to make sure the entry is fully populated
438 * before that happens.
439 */
516d2836
AK		 440static void
441__ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
eea0e11c 442{
eea0e11c
AK		 443 union entry_union eu;
444 eu.entry = e;
48797ebd
LT		 445 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
446 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
516d2836
AK		 447}
448
449static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
450{
451 unsigned long flags;
452 spin_lock_irqsave(&ioapic_lock, flags);
453 __ioapic_write_entry(apic, pin, e);
48797ebd
LT		 454 spin_unlock_irqrestore(&ioapic_lock, flags);
455}
456
457/*
458 * When we mask an IO APIC routing entry, we need to write the low
459 * word first, in order to set the mask bit before we change the
460 * high bits!
461 */
462static void ioapic_mask_entry(int apic, int pin)
463{
464 unsigned long flags;
465 union entry_union eu = { .entry.mask = 1 };
466
eea0e11c
AK		 467 spin_lock_irqsave(&ioapic_lock, flags);
468 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
469 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
470 spin_unlock_irqrestore(&ioapic_lock, flags);
471}
472
54d5d424 473#ifdef CONFIG_SMP
550f2299
EB		 474static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
475{
476 int apic, pin;
e5a53714
YL		 477 struct irq_cfg *cfg;
478 struct irq_pin_list *entry;
550f2299 479
e5a53714
YL		 480 cfg = irq_cfg(irq);
481 entry = cfg->irq_2_pin;
550f2299
EB		 482 for (;;) {
483 unsigned int reg;
e5a53714
YL		 484
485 if (!entry)
486 break;
487
550f2299
EB		 488 apic = entry->apic;
489 pin = entry->pin;
efa2559f 490#ifdef CONFIG_INTR_REMAP
89027d35
SS		 491 /*
492 * With interrupt-remapping, destination information comes
493 * from interrupt-remapping table entry.
494 */
495 if (!irq_remapped(irq))
496 io_apic_write(apic, 0x11 + pin*2, dest);
efa2559f
YL		 497#else
498 io_apic_write(apic, 0x11 + pin*2, dest);
499#endif
550f2299 500 reg = io_apic_read(apic, 0x10 + pin*2);
46b3b4ef 501 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
550f2299 502 reg |= vector;
f876d213 503 io_apic_modify(apic, 0x10 + pin*2, reg);
550f2299
EB		 504 if (!entry->next)
505 break;
e5a53714 506 entry = entry->next;
550f2299
EB		 507 }
508}
509
efa2559f
YL		 510static int assign_irq_vector(int irq, cpumask_t mask);
511
54d5d424
AR		 512static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
513{
3ac2de48 514 struct irq_cfg *cfg = irq_cfg(irq);
54d5d424
AR		 515 unsigned long flags;
516 unsigned int dest;
517 cpumask_t tmp;
08678b08 518 struct irq_desc *desc;
54d5d424
AR		 519
520 cpus_and(tmp, mask, cpu_online_map);
521 if (cpus_empty(tmp))
5ff5115e 522 return;
54d5d424 523
dfbffdd8 524 if (assign_irq_vector(irq, mask))
550f2299
EB		 525 return;
526
dfbffdd8 527 cpus_and(tmp, cfg->domain, mask);
550f2299 528 dest = cpu_mask_to_apicid(tmp);
54d5d424
AR		 529
530 /*
531 * Only the high 8 bits are valid.
532 */
533 dest = SET_APIC_LOGICAL_ID(dest);
534
08678b08 535 desc = irq_to_desc(irq);
54d5d424 536 spin_lock_irqsave(&ioapic_lock, flags);
dfbffdd8 537 __target_IO_APIC_irq(irq, dest, cfg->vector);
08678b08 538 desc->affinity = mask;
54d5d424
AR		 539 spin_unlock_irqrestore(&ioapic_lock, flags);
540}
541#endif
542
1da177e4
LT		 543/*
544 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
545 * shared ISA-space IRQs, so we have to support them. We are super
546 * fast in the common case, and fast for shared ISA-space IRQs.
547 */
548static void add_pin_to_irq(unsigned int irq, int apic, int pin)
549{
e5a53714
YL		 550 struct irq_cfg *cfg;
551 struct irq_pin_list *entry;
1da177e4 552
e5a53714
YL		 553 /* first time to refer irq_cfg, so with new */
554 cfg = irq_cfg_alloc(irq);
555 entry = cfg->irq_2_pin;
556 if (!entry) {
557 entry = get_one_free_irq_2_pin();
558 cfg->irq_2_pin = entry;
559 entry->apic = apic;
560 entry->pin = pin;
561 printk(KERN_DEBUG " 0 add_pin_to_irq: irq %d --> apic %d pin %d\n", irq, apic, pin);
562 return;
563 }
3ac2de48 564
e5a53714
YL		 565 while (entry->next) {
566 /* not again, please */
567 if (entry->apic == apic && entry->pin == pin)
568 return;
1da177e4 569
e5a53714 570 entry = entry->next;
1da177e4 571 }
e5a53714
YL		 572
573 entry->next = get_one_free_irq_2_pin();
574 entry = entry->next;
1da177e4
LT		 575 entry->apic = apic;
576 entry->pin = pin;
e5a53714 577 printk(KERN_DEBUG " x add_pin_to_irq: irq %d --> apic %d pin %d\n", irq, apic, pin);
1da177e4
LT		 578}
579
0b9f4f49
MR		 580/*
581 * Reroute an IRQ to a different pin.
582 */
583static void __init replace_pin_at_irq(unsigned int irq,
584 int oldapic, int oldpin,
585 int newapic, int newpin)
586{
e5a53714
YL		 587 struct irq_cfg *cfg = irq_cfg(irq);
588 struct irq_pin_list *entry = cfg->irq_2_pin;
589 int replaced = 0;
0b9f4f49 590
e5a53714 591 while (entry) {
0b9f4f49
MR		 592 if (entry->apic == oldapic && entry->pin == oldpin) {
593 entry->apic = newapic;
594 entry->pin = newpin;
e5a53714
YL		 595 replaced = 1;
596 /* every one is different, right? */
0b9f4f49 597 break;
e5a53714
YL		 598 }
599 entry = entry->next;
0b9f4f49 600 }
e5a53714
YL		 601
602 /* why? call replace before add? */
603 if (!replaced)
604 add_pin_to_irq(irq, newapic, newpin);
0b9f4f49
MR		 605}
606
8ea5371b
YL		 607/*
608 * Synchronize the IO-APIC and the CPU by doing
609 * a dummy read from the IO-APIC
610 */
611static inline void io_apic_sync(unsigned int apic)
612{
613 struct io_apic __iomem *io_apic = io_apic_base(apic);
614 readl(&io_apic->data);
615}
616
617#define __DO_ACTION(R, ACTION, FINAL) \
618 \
619{ \
620 int pin; \
621 struct irq_cfg *cfg; \
622 struct irq_pin_list *entry; \
623 \
624 cfg = irq_cfg(irq); \
625 entry = cfg->irq_2_pin; \
626 for (;;) { \
627 unsigned int reg; \
628 if (!entry) \
629 break; \
630 pin = entry->pin; \
631 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
632 reg ACTION; \
f876d213 633 io_apic_modify(entry->apic, 0x10 + R + pin*2, reg); \
8ea5371b
YL		 634 FINAL; \
635 if (!entry->next) \
636 break; \
637 entry = entry->next; \
638 } \
639}
1da177e4
LT		 640
641#define DO_ACTION(name,R,ACTION, FINAL) \
642 \
643 static void name##_IO_APIC_irq (unsigned int irq) \
644 __DO_ACTION(R, ACTION, FINAL)
645
46b3b4ef
CG		 646/* mask = 1 */
647DO_ACTION(__mask, 0, |= IO_APIC_REDIR_MASKED, io_apic_sync(entry->apic))
648
649/* mask = 0 */
650DO_ACTION(__unmask, 0, &= ~IO_APIC_REDIR_MASKED, )
1da177e4
LT		 651
652static void mask_IO_APIC_irq (unsigned int irq)
653{
654 unsigned long flags;
655
656 spin_lock_irqsave(&ioapic_lock, flags);
657 __mask_IO_APIC_irq(irq);
658 spin_unlock_irqrestore(&ioapic_lock, flags);
659}
660
661static void unmask_IO_APIC_irq (unsigned int irq)
662{
663 unsigned long flags;
664
665 spin_lock_irqsave(&ioapic_lock, flags);
666 __unmask_IO_APIC_irq(irq);
667 spin_unlock_irqrestore(&ioapic_lock, flags);
668}
669
670static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
671{
672 struct IO_APIC_route_entry entry;
1da177e4
LT		 673
674 /* Check delivery_mode to be sure we're not clearing an SMI pin */
eea0e11c 675 entry = ioapic_read_entry(apic, pin);
1da177e4
LT		 676 if (entry.delivery_mode == dest_SMI)
677 return;
678 /*
679 * Disable it in the IO-APIC irq-routing table:
680 */
48797ebd 681 ioapic_mask_entry(apic, pin);
1da177e4
LT		 682}
683
684static void clear_IO_APIC (void)
685{
686 int apic, pin;
687
688 for (apic = 0; apic < nr_ioapics; apic++)
689 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
690 clear_IO_APIC_pin(apic, pin);
691}
692
efa2559f
YL		 693#ifdef CONFIG_INTR_REMAP
694/* I/O APIC RTE contents at the OS boot up */
695static struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS];
696
4dc2f96c
SS		 697/*
698 * Saves and masks all the unmasked IO-APIC RTE's
699 */
700int save_mask_IO_APIC_setup(void)
701{
702 union IO_APIC_reg_01 reg_01;
703 unsigned long flags;
704 int apic, pin;
705
706 /*
707 * The number of IO-APIC IRQ registers (== #pins):
708 */
709 for (apic = 0; apic < nr_ioapics; apic++) {
710 spin_lock_irqsave(&ioapic_lock, flags);
711 reg_01.raw = io_apic_read(apic, 1);
712 spin_unlock_irqrestore(&ioapic_lock, flags);
713 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
714 }
715
716 for (apic = 0; apic < nr_ioapics; apic++) {
717 early_ioapic_entries[apic] =
718 kzalloc(sizeof(struct IO_APIC_route_entry) *
719 nr_ioapic_registers[apic], GFP_KERNEL);
720 if (!early_ioapic_entries[apic])
721 return -ENOMEM;
722 }
723
724 for (apic = 0; apic < nr_ioapics; apic++)
725 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
726 struct IO_APIC_route_entry entry;
727
728 entry = early_ioapic_entries[apic][pin] =
729 ioapic_read_entry(apic, pin);
730 if (!entry.mask) {
731 entry.mask = 1;
732 ioapic_write_entry(apic, pin, entry);
733 }
734 }
735 return 0;
736}
737
738void restore_IO_APIC_setup(void)
739{
740 int apic, pin;
741
742 for (apic = 0; apic < nr_ioapics; apic++)
743 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
744 ioapic_write_entry(apic, pin,
745 early_ioapic_entries[apic][pin]);
746}
747
748void reinit_intr_remapped_IO_APIC(int intr_remapping)
749{
750 /*
751 * for now plain restore of previous settings.
752 * TBD: In the case of OS enabling interrupt-remapping,
753 * IO-APIC RTE's need to be setup to point to interrupt-remapping
754 * table entries. for now, do a plain restore, and wait for
755 * the setup_IO_APIC_irqs() to do proper initialization.
756 */
757 restore_IO_APIC_setup();
758}
efa2559f 759#endif
fea5f1e1 760
1da177e4
LT		 761/*
762 * Find the IRQ entry number of a certain pin.
763 */
764static int find_irq_entry(int apic, int pin, int type)
765{
766 int i;
767
768 for (i = 0; i < mp_irq_entries; i++)
2fddb6e2
AS		 769 if (mp_irqs[i].mp_irqtype == type &&
770 (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid ||
771 mp_irqs[i].mp_dstapic == MP_APIC_ALL) &&
772 mp_irqs[i].mp_dstirq == pin)
1da177e4
LT		 773 return i;
774
775 return -1;
776}
777
778/*
779 * Find the pin to which IRQ[irq] (ISA) is connected
780 */
1008fddc 781static int __init find_isa_irq_pin(int irq, int type)
1da177e4
LT		 782{
783 int i;
784
785 for (i = 0; i < mp_irq_entries; i++) {
2fddb6e2 786 int lbus = mp_irqs[i].mp_srcbus;
1da177e4 787
55f05ffa 788 if (test_bit(lbus, mp_bus_not_pci) &&
2fddb6e2
AS		 789 (mp_irqs[i].mp_irqtype == type) &&
790 (mp_irqs[i].mp_srcbusirq == irq))
1da177e4 791
2fddb6e2 792 return mp_irqs[i].mp_dstirq;
1da177e4
LT		 793 }
794 return -1;
795}
796
1008fddc
EB		 797static int __init find_isa_irq_apic(int irq, int type)
798{
799 int i;
800
801 for (i = 0; i < mp_irq_entries; i++) {
2fddb6e2 802 int lbus = mp_irqs[i].mp_srcbus;
1008fddc 803
55f05ffa 804 if (test_bit(lbus, mp_bus_not_pci) &&
2fddb6e2
AS		 805 (mp_irqs[i].mp_irqtype == type) &&
806 (mp_irqs[i].mp_srcbusirq == irq))
1008fddc
EB		 807 break;
808 }
809 if (i < mp_irq_entries) {
810 int apic;
811 for(apic = 0; apic < nr_ioapics; apic++) {
2fddb6e2 812 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic)
1008fddc
EB		 813 return apic;
814 }
815 }
816
817 return -1;
818}
819
1da177e4
LT		 820/*
821 * Find a specific PCI IRQ entry.
822 * Not an __init, possibly needed by modules
823 */
824static int pin_2_irq(int idx, int apic, int pin);
825
826int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
827{
828 int apic, i, best_guess = -1;
829
830 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
831 bus, slot, pin);
ce6444d3 832 if (test_bit(bus, mp_bus_not_pci)) {
1da177e4
LT		 833 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
834 return -1;
835 }
836 for (i = 0; i < mp_irq_entries; i++) {
2fddb6e2 837 int lbus = mp_irqs[i].mp_srcbus;
1da177e4
LT		 838
839 for (apic = 0; apic < nr_ioapics; apic++)
2fddb6e2
AS		 840 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic ||
841 mp_irqs[i].mp_dstapic == MP_APIC_ALL)
1da177e4
LT		 842 break;
843
55f05ffa 844 if (!test_bit(lbus, mp_bus_not_pci) &&
2fddb6e2 845 !mp_irqs[i].mp_irqtype &&
1da177e4 846 (bus == lbus) &&
2fddb6e2
AS		 847 (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) {
848 int irq = pin_2_irq(i,apic,mp_irqs[i].mp_dstirq);
1da177e4
LT		 849
850 if (!(apic || IO_APIC_IRQ(irq)))
851 continue;
852
2fddb6e2 853 if (pin == (mp_irqs[i].mp_srcbusirq & 3))
1da177e4
LT		 854 return irq;
855 /*
856 * Use the first all-but-pin matching entry as a
857 * best-guess fuzzy result for broken mptables.
858 */
859 if (best_guess < 0)
860 best_guess = irq;
861 }
862 }
863 return best_guess;
864}
865
1da177e4
LT		 866/* ISA interrupts are always polarity zero edge triggered,
867 * when listed as conforming in the MP table. */
868
869#define default_ISA_trigger(idx) (0)
870#define default_ISA_polarity(idx) (0)
871
872/* PCI interrupts are always polarity one level triggered,
873 * when listed as conforming in the MP table. */
874
875#define default_PCI_trigger(idx) (1)
876#define default_PCI_polarity(idx) (1)
877
61fd47e0 878static int MPBIOS_polarity(int idx)
1da177e4 879{
2fddb6e2 880 int bus = mp_irqs[idx].mp_srcbus;
1da177e4
LT		 881 int polarity;
882
883 /*
884 * Determine IRQ line polarity (high active or low active):
885 */
2fddb6e2 886 switch (mp_irqs[idx].mp_irqflag & 3)
1da177e4
LT		 887 {
888 case 0: /* conforms, ie. bus-type dependent polarity */
55f05ffa
AK		 889 if (test_bit(bus, mp_bus_not_pci))
890 polarity = default_ISA_polarity(idx);
891 else
892 polarity = default_PCI_polarity(idx);
1da177e4 893 break;
1da177e4
LT		 894 case 1: /* high active */
895 {
896 polarity = 0;
897 break;
898 }
899 case 2: /* reserved */
900 {
901 printk(KERN_WARNING "broken BIOS!!\n");
902 polarity = 1;
903 break;
904 }
905 case 3: /* low active */
906 {
907 polarity = 1;
908 break;
909 }
910 default: /* invalid */
911 {
912 printk(KERN_WARNING "broken BIOS!!\n");
913 polarity = 1;
914 break;
915 }
916 }
917 return polarity;
918}
919
920static int MPBIOS_trigger(int idx)
921{
2fddb6e2 922 int bus = mp_irqs[idx].mp_srcbus;
1da177e4
LT		 923 int trigger;
924
925 /*
926 * Determine IRQ trigger mode (edge or level sensitive):
927 */
2fddb6e2 928 switch ((mp_irqs[idx].mp_irqflag>>2) & 3)
1da177e4
LT		 929 {
930 case 0: /* conforms, ie. bus-type dependent */
55f05ffa
AK		 931 if (test_bit(bus, mp_bus_not_pci))
932 trigger = default_ISA_trigger(idx);
933 else
934 trigger = default_PCI_trigger(idx);
1da177e4 935 break;
1da177e4
LT		 936 case 1: /* edge */
937 {
938 trigger = 0;
939 break;
940 }
941 case 2: /* reserved */
942 {
943 printk(KERN_WARNING "broken BIOS!!\n");
944 trigger = 1;
945 break;
946 }
947 case 3: /* level */
948 {
949 trigger = 1;
950 break;
951 }
952 default: /* invalid */
953 {
954 printk(KERN_WARNING "broken BIOS!!\n");
955 trigger = 0;
956 break;
957 }
958 }
959 return trigger;
960}
961
962static inline int irq_polarity(int idx)
963{
964 return MPBIOS_polarity(idx);
965}
966
967static inline int irq_trigger(int idx)
968{
969 return MPBIOS_trigger(idx);
970}
971
972static int pin_2_irq(int idx, int apic, int pin)
973{
974 int irq, i;
2fddb6e2 975 int bus = mp_irqs[idx].mp_srcbus;
1da177e4
LT		 976
977 /*
978 * Debugging check, we are in big trouble if this message pops up!
979 */
2fddb6e2 980 if (mp_irqs[idx].mp_dstirq != pin)
1da177e4
LT		 981 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
982
55f05ffa 983 if (test_bit(bus, mp_bus_not_pci)) {
2fddb6e2 984 irq = mp_irqs[idx].mp_srcbusirq;
55f05ffa
AK		 985 } else {
986 /*
987 * PCI IRQs are mapped in order
988 */
989 i = irq = 0;
990 while (i < apic)
991 irq += nr_ioapic_registers[i++];
992 irq += pin;
1da177e4 993 }
1da177e4
LT		 994 return irq;
995}
996
d388e5fd
EB		 997void lock_vector_lock(void)
998{
999 /* Used to the online set of cpus does not change
1000 * during assign_irq_vector.
1001 */
1002 spin_lock(&vector_lock);
1003}
1004
1005void unlock_vector_lock(void)
1006{
1007 spin_unlock(&vector_lock);
1008}
1009
dfbffdd8 1010static int __assign_irq_vector(int irq, cpumask_t mask)
1da177e4 1011{
550f2299
EB		 1012 /*
1013 * NOTE! The local APIC isn't very good at handling
1014 * multiple interrupts at the same interrupt level.
1015 * As the interrupt level is determined by taking the
1016 * vector number and shifting that right by 4, we
1017 * want to spread these out a bit so that they don't
1018 * all fall in the same interrupt level.
1019 *
1020 * Also, we've got to be careful not to trash gate
1021 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1022 */
d1752aa8 1023 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
dfbffdd8 1024 unsigned int old_vector;
550f2299 1025 int cpu;
13a79503 1026 struct irq_cfg *cfg;
1da177e4 1027
3ac2de48 1028 cfg = irq_cfg(irq);
0a1ad60d 1029
70a0a535
EB		 1030 /* Only try and allocate irqs on cpus that are present */
1031 cpus_and(mask, mask, cpu_online_map);
1032
61014292
EB		 1033 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1034 return -EBUSY;
1035
dfbffdd8
EB		 1036 old_vector = cfg->vector;
1037 if (old_vector) {
1038 cpumask_t tmp;
1039 cpus_and(tmp, cfg->domain, mask);
1040 if (!cpus_empty(tmp))
1041 return 0;
0a1ad60d 1042 }
550f2299 1043
334ef7a7 1044 for_each_cpu_mask_nr(cpu, mask) {
70a0a535 1045 cpumask_t domain, new_mask;
61014292 1046 int new_cpu;
550f2299 1047 int vector, offset;
c7111c13
EB		 1048
1049 domain = vector_allocation_domain(cpu);
70a0a535 1050 cpus_and(new_mask, domain, cpu_online_map);
c7111c13 1051
d1752aa8
EB		 1052 vector = current_vector;
1053 offset = current_offset;
1da177e4 1054next:
550f2299 1055 vector += 8;
305b92a2 1056 if (vector >= first_system_vector) {
550f2299
EB		 1057 /* If we run out of vectors on large boxen, must share them. */
1058 offset = (offset + 1) % 8;
1059 vector = FIRST_DEVICE_VECTOR + offset;
1060 }
d1752aa8 1061 if (unlikely(current_vector == vector))
550f2299
EB		 1062 continue;
1063 if (vector == IA32_SYSCALL_VECTOR)
1064 goto next;
334ef7a7 1065 for_each_cpu_mask_nr(new_cpu, new_mask)
45edfd1d 1066 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
c7111c13 1067 goto next;
550f2299 1068 /* Found one! */
d1752aa8
EB		 1069 current_vector = vector;
1070 current_offset = offset;
61014292
EB		 1071 if (old_vector) {
1072 cfg->move_in_progress = 1;
1073 cfg->old_domain = cfg->domain;
1074 }
334ef7a7 1075 for_each_cpu_mask_nr(new_cpu, new_mask)
c7111c13 1076 per_cpu(vector_irq, new_cpu)[vector] = irq;
13a79503
EB		 1077 cfg->vector = vector;
1078 cfg->domain = domain;
dfbffdd8 1079 return 0;
1da177e4 1080 }
550f2299 1081 return -ENOSPC;
04b9267b
EB		 1082}
1083
dfbffdd8 1084static int assign_irq_vector(int irq, cpumask_t mask)
04b9267b 1085{
dfbffdd8 1086 int err;
04b9267b 1087 unsigned long flags;
0a1ad60d 1088
04b9267b 1089 spin_lock_irqsave(&vector_lock, flags);
dfbffdd8 1090 err = __assign_irq_vector(irq, mask);
26a3c49c 1091 spin_unlock_irqrestore(&vector_lock, flags);
dfbffdd8 1092 return err;
1da177e4
LT		 1093}
1094
5df0287e
YL		 1095static void __clear_irq_vector(int irq)
1096{
13a79503 1097 struct irq_cfg *cfg;
5df0287e
YL		 1098 cpumask_t mask;
1099 int cpu, vector;
1100
3ac2de48 1101 cfg = irq_cfg(irq);
13a79503 1102 BUG_ON(!cfg->vector);
5df0287e 1103
13a79503
EB		 1104 vector = cfg->vector;
1105 cpus_and(mask, cfg->domain, cpu_online_map);
334ef7a7 1106 for_each_cpu_mask_nr(cpu, mask)
5df0287e
YL		 1107 per_cpu(vector_irq, cpu)[vector] = -1;
1108
13a79503 1109 cfg->vector = 0;
d366f8cb 1110 cpus_clear(cfg->domain);
5df0287e
YL		 1111}
1112
d388e5fd 1113void __setup_vector_irq(int cpu)
70a0a535
EB		 1114{
1115 /* Initialize vector_irq on a new cpu */
1116 /* This function must be called with vector_lock held */
70a0a535 1117 int irq, vector;
46b8214d 1118 struct irq_cfg *cfg;
70a0a535 1119
70a0a535 1120 /* Mark the inuse vectors */
46b8214d 1121 for_each_irq_cfg(cfg) {
3ac2de48 1122 if (!cpu_isset(cpu, cfg->domain))
70a0a535 1123 continue;
3ac2de48 1124 vector = cfg->vector;
46b8214d 1125 irq = cfg->irq;
70a0a535
EB		 1126 per_cpu(vector_irq, cpu)[vector] = irq;
1127 }
1128 /* Mark the free vectors */
1129 for (vector = 0; vector < NR_VECTORS; ++vector) {
1130 irq = per_cpu(vector_irq, cpu)[vector];
1131 if (irq < 0)
1132 continue;
3ac2de48
YL		 1133
1134 cfg = irq_cfg(irq);
1135 if (!cpu_isset(cpu, cfg->domain))
70a0a535
EB		 1136 per_cpu(vector_irq, cpu)[vector] = -1;
1137 }
1138}
1139
f29bd1ba 1140static struct irq_chip ioapic_chip;
89027d35
SS		 1141#ifdef CONFIG_INTR_REMAP
1142static struct irq_chip ir_ioapic_chip;
1143#endif
1da177e4 1144
a27bc06d 1145static void ioapic_register_intr(int irq, unsigned long trigger)
1da177e4 1146{
08678b08
YL		 1147 struct irq_desc *desc;
1148
cb5bc832
YL		 1149 /* first time to use this irq_desc */
1150 if (irq < 16)
1151 desc = irq_to_desc(irq);
1152 else
1153 desc = irq_to_desc_alloc(irq);
1154
89027d35 1155 if (trigger)
08678b08 1156 desc->status |= IRQ_LEVEL;
89027d35 1157 else
08678b08 1158 desc->status &= ~IRQ_LEVEL;
89027d35
SS		 1159
1160#ifdef CONFIG_INTR_REMAP
1161 if (irq_remapped(irq)) {
08678b08 1162 desc->status |= IRQ_MOVE_PCNTXT;
89027d35
SS		 1163 if (trigger)
1164 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1165 handle_fasteoi_irq,
1166 "fasteoi");
1167 else
1168 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1169 handle_edge_irq, "edge");
1170 return;
1171 }
1172#endif
1173 if (trigger)
1174 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1175 handle_fasteoi_irq,
1176 "fasteoi");
1177 else
a460e745
IM		 1178 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1179 handle_edge_irq, "edge");
89027d35
SS		 1180}
1181
1182static int setup_ioapic_entry(int apic, int irq,
1183 struct IO_APIC_route_entry *entry,
1184 unsigned int destination, int trigger,
1185 int polarity, int vector)
1186{
1187 /*
1188 * add it to the IO-APIC irq-routing table:
1189 */
1190 memset(entry,0,sizeof(*entry));
1191
1192#ifdef CONFIG_INTR_REMAP
1193 if (intr_remapping_enabled) {
1194 struct intel_iommu *iommu = map_ioapic_to_ir(apic);
1195 struct irte irte;
1196 struct IR_IO_APIC_route_entry *ir_entry =
1197 (struct IR_IO_APIC_route_entry *) entry;
1198 int index;
1199
1200 if (!iommu)
1201 panic("No mapping iommu for ioapic %d\n", apic);
1202
1203 index = alloc_irte(iommu, irq, 1);
1204 if (index < 0)
1205 panic("Failed to allocate IRTE for ioapic %d\n", apic);
1206
1207 memset(&irte, 0, sizeof(irte));
1208
1209 irte.present = 1;
1210 irte.dst_mode = INT_DEST_MODE;
1211 irte.trigger_mode = trigger;
1212 irte.dlvry_mode = INT_DELIVERY_MODE;
1213 irte.vector = vector;
1214 irte.dest_id = IRTE_DEST(destination);
1215
1216 modify_irte(irq, &irte);
1217
1218 ir_entry->index2 = (index >> 15) & 0x1;
1219 ir_entry->zero = 0;
1220 ir_entry->format = 1;
1221 ir_entry->index = (index & 0x7fff);
1222 } else
1223#endif
1224 {
1225 entry->delivery_mode = INT_DELIVERY_MODE;
1226 entry->dest_mode = INT_DEST_MODE;
1227 entry->dest = destination;
cc75b92d 1228 }
89027d35
SS		 1229
1230 entry->mask = 0; /* enable IRQ */
1231 entry->trigger = trigger;
1232 entry->polarity = polarity;
1233 entry->vector = vector;
1234
1235 /* Mask level triggered irqs.
1236 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1237 */
1238 if (trigger)
1239 entry->mask = 1;
1240 return 0;
1da177e4 1241}
a8c8a367
EB		 1242
1243static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
1244 int trigger, int polarity)
1da177e4 1245{
3ac2de48 1246 struct irq_cfg *cfg;
1da177e4 1247 struct IO_APIC_route_entry entry;
a8c8a367 1248 cpumask_t mask;
1da177e4 1249
a8c8a367
EB		 1250 if (!IO_APIC_IRQ(irq))
1251 return;
1252
3ac2de48
YL		 1253 cfg = irq_cfg(irq);
1254
dfbffdd8
EB		 1255 mask = TARGET_CPUS;
1256 if (assign_irq_vector(irq, mask))
a8c8a367
EB		 1257 return;
1258
dfbffdd8
EB		 1259 cpus_and(mask, cfg->domain, mask);
1260
a8c8a367
EB		 1261 apic_printk(APIC_VERBOSE,KERN_DEBUG
1262 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1263 "IRQ %d Mode:%i Active:%i)\n",
ec2cd0a2 1264 apic, mp_ioapics[apic].mp_apicid, pin, cfg->vector,
a8c8a367 1265 irq, trigger, polarity);
1da177e4 1266
1da177e4 1267
89027d35
SS		 1268 if (setup_ioapic_entry(mp_ioapics[apic].mp_apicid, irq, &entry,
1269 cpu_mask_to_apicid(mask), trigger, polarity,
1270 cfg->vector)) {
1271 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1272 mp_ioapics[apic].mp_apicid, pin);
1273 __clear_irq_vector(irq);
1274 return;
1275 }
ad892f5e 1276
a8c8a367
EB		 1277 ioapic_register_intr(irq, trigger);
1278 if (irq < 16)
1279 disable_8259A_irq(irq);
ad892f5e
YL		 1280
1281 ioapic_write_entry(apic, pin, entry);
ad892f5e
YL		 1282}
1283
1284static void __init setup_IO_APIC_irqs(void)
1285{
1286 int apic, pin, idx, irq, first_notcon = 1;
1287
1288 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1289
1290 for (apic = 0; apic < nr_ioapics; apic++) {
1291 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1da177e4
LT		 1292
1293 idx = find_irq_entry(apic,pin,mp_INT);
1294 if (idx == -1) {
1295 if (first_notcon) {
ec2cd0a2 1296 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mp_apicid, pin);
1da177e4
LT		 1297 first_notcon = 0;
1298 } else
ec2cd0a2 1299 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mp_apicid, pin);
1da177e4
LT		 1300 continue;
1301 }
20d225b9
YL		 1302 if (!first_notcon) {
1303 apic_printk(APIC_VERBOSE, " not connected.\n");
1304 first_notcon = 1;
1305 }
1da177e4 1306
1da177e4
LT		 1307 irq = pin_2_irq(idx, apic, pin);
1308 add_pin_to_irq(irq, apic, pin);
1309
a8c8a367
EB		 1310 setup_IO_APIC_irq(apic, pin, irq,
1311 irq_trigger(idx), irq_polarity(idx));
1da177e4
LT		 1312 }
1313 }
1314
1315 if (!first_notcon)
20d225b9 1316 apic_printk(APIC_VERBOSE, " not connected.\n");
1da177e4
LT		 1317}
1318
1319/*
f7633ce5 1320 * Set up the timer pin, possibly with the 8259A-master behind.
1da177e4 1321 */
f7633ce5
MR		 1322static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
1323 int vector)
1da177e4
LT		 1324{
1325 struct IO_APIC_route_entry entry;
1da177e4 1326
efa2559f 1327#ifdef CONFIG_INTR_REMAP
89027d35
SS		 1328 if (intr_remapping_enabled)
1329 return;
efa2559f 1330#endif
89027d35 1331
a2249cba 1332 memset(&entry, 0, sizeof(entry));
1da177e4 1333
1da177e4
LT		 1334 /*
1335 * We use logical delivery to get the timer IRQ
1336 * to the first CPU.
1337 */
1338 entry.dest_mode = INT_DEST_MODE;
03be7505 1339 entry.mask = 1; /* mask IRQ now */
ee4eff6f 1340 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
1da177e4
LT		 1341 entry.delivery_mode = INT_DELIVERY_MODE;
1342 entry.polarity = 0;
1343 entry.trigger = 0;
1344 entry.vector = vector;
1345
1346 /*
1347 * The timer IRQ doesn't have to know that behind the
f7633ce5 1348 * scene we may have a 8259A-master in AEOI mode ...
1da177e4 1349 */
a460e745 1350 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1da177e4
LT		 1351
1352 /*
1353 * Add it to the IO-APIC irq-routing table:
1354 */
a2249cba 1355 ioapic_write_entry(apic, pin, entry);
1da177e4
LT		 1356}
1357
32f71aff
MR		 1358
1359__apicdebuginit(void) print_IO_APIC(void)
1da177e4
LT		 1360{
1361 int apic, i;
1362 union IO_APIC_reg_00 reg_00;
1363 union IO_APIC_reg_01 reg_01;
1364 union IO_APIC_reg_02 reg_02;
1365 unsigned long flags;
46b8214d 1366 struct irq_cfg *cfg;
1da177e4
LT		 1367
1368 if (apic_verbosity == APIC_QUIET)
1369 return;
1370
1371 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1372 for (i = 0; i < nr_ioapics; i++)
1373 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
ec2cd0a2 1374 mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]);
1da177e4
LT		 1375
1376 /*
1377 * We are a bit conservative about what we expect. We have to
1378 * know about every hardware change ASAP.
1379 */
1380 printk(KERN_INFO "testing the IO APIC.......................\n");
1381
1382 for (apic = 0; apic < nr_ioapics; apic++) {
1383
1384 spin_lock_irqsave(&ioapic_lock, flags);
1385 reg_00.raw = io_apic_read(apic, 0);
1386 reg_01.raw = io_apic_read(apic, 1);
1387 if (reg_01.bits.version >= 0x10)
1388 reg_02.raw = io_apic_read(apic, 2);
1389 spin_unlock_irqrestore(&ioapic_lock, flags);
1390
1391 printk("\n");
ec2cd0a2 1392 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid);
1da177e4
LT		 1393 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1394 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
7a959cff
YL		 1395 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1396 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1da177e4
LT		 1397
1398 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1399 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1da177e4
LT		 1400
1401 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1402 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1da177e4
LT		 1403
1404 if (reg_01.bits.version >= 0x10) {
1405 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1406 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1da177e4
LT		 1407 }
1408
1409 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1410
ee4eff6f
BR		 1411 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1412 " Stat Dmod Deli Vect: \n");
1da177e4
LT		 1413
1414 for (i = 0; i <= reg_01.bits.entries; i++) {
1415 struct IO_APIC_route_entry entry;
1416
eea0e11c 1417 entry = ioapic_read_entry(apic, i);
1da177e4 1418
ee4eff6f 1419 printk(KERN_DEBUG " %02x %03X ",
1da177e4 1420 i,
ee4eff6f 1421 entry.dest
1da177e4
LT		 1422 );
1423
1424 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1425 entry.mask,
1426 entry.trigger,
1427 entry.irr,
1428 entry.polarity,
1429 entry.delivery_status,
1430 entry.dest_mode,
1431 entry.delivery_mode,
1432 entry.vector
1433 );
1434 }
1435 }
1da177e4 1436 printk(KERN_DEBUG "IRQ to pin mappings:\n");
46b8214d 1437 for_each_irq_cfg(cfg) {
e5a53714
YL		 1438 struct irq_pin_list *entry = cfg->irq_2_pin;
1439 if (!entry)
1da177e4 1440 continue;
46b8214d 1441 printk(KERN_DEBUG "IRQ%d ", cfg->irq);
1da177e4
LT		 1442 for (;;) {
1443 printk("-> %d:%d", entry->apic, entry->pin);
1444 if (!entry->next)
1445 break;
e5a53714 1446 entry = entry->next;
1da177e4
LT		 1447 }
1448 printk("\n");
1449 }
1450
1451 printk(KERN_INFO ".................................... done.\n");
1452
1453 return;
1454}
1455
32f71aff 1456__apicdebuginit(void) print_APIC_bitfield(int base)
1da177e4
LT		 1457{
1458 unsigned int v;
1459 int i, j;
1460
1461 if (apic_verbosity == APIC_QUIET)
1462 return;
1463
1464 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1465 for (i = 0; i < 8; i++) {
1466 v = apic_read(base + i*0x10);
1467 for (j = 0; j < 32; j++) {
1468 if (v & (1<<j))
1469 printk("1");
1470 else
1471 printk("0");
1472 }
1473 printk("\n");
1474 }
1475}
1476
32f71aff 1477__apicdebuginit(void) print_local_APIC(void *dummy)
1da177e4
LT		 1478{
1479 unsigned int v, ver, maxlvt;
1b374e4d 1480 unsigned long icr;
1da177e4
LT		 1481
1482 if (apic_verbosity == APIC_QUIET)
1483 return;
1484
1485 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1486 smp_processor_id(), hard_smp_processor_id());
66823114 1487 v = apic_read(APIC_ID);
4c9961d5 1488 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1da177e4
LT		 1489 v = apic_read(APIC_LVR);
1490 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1491 ver = GET_APIC_VERSION(v);
37e650c7 1492 maxlvt = lapic_get_maxlvt();
1da177e4
LT		 1493
1494 v = apic_read(APIC_TASKPRI);
1495 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1496
5a40b7c2
AK		 1497 v = apic_read(APIC_ARBPRI);
1498 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1499 v & APIC_ARBPRI_MASK);
1500 v = apic_read(APIC_PROCPRI);
1501 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1da177e4
LT		 1502
1503 v = apic_read(APIC_EOI);
1504 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1505 v = apic_read(APIC_RRR);
1506 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1507 v = apic_read(APIC_LDR);
1508 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1509 v = apic_read(APIC_DFR);
1510 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1511 v = apic_read(APIC_SPIV);
1512 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1513
1514 printk(KERN_DEBUG "... APIC ISR field:\n");
1515 print_APIC_bitfield(APIC_ISR);
1516 printk(KERN_DEBUG "... APIC TMR field:\n");
1517 print_APIC_bitfield(APIC_TMR);
1518 printk(KERN_DEBUG "... APIC IRR field:\n");
1519 print_APIC_bitfield(APIC_IRR);
1520
5a40b7c2
AK		 1521 v = apic_read(APIC_ESR);
1522 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1da177e4 1523
1b374e4d 1524 icr = apic_icr_read();
d562353a
IM		 1525 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1526 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1da177e4
LT		 1527
1528 v = apic_read(APIC_LVTT);
1529 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1530
1531 if (maxlvt > 3) { /* PC is LVT#4. */
1532 v = apic_read(APIC_LVTPC);
1533 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1534 }
1535 v = apic_read(APIC_LVT0);
1536 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1537 v = apic_read(APIC_LVT1);
1538 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1539
1540 if (maxlvt > 2) { /* ERR is LVT#3. */
1541 v = apic_read(APIC_LVTERR);
1542 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1543 }
1544
1545 v = apic_read(APIC_TMICT);
1546 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1547 v = apic_read(APIC_TMCCT);
1548 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1549 v = apic_read(APIC_TDCR);
1550 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1551 printk("\n");
1552}
1553
32f71aff 1554__apicdebuginit(void) print_all_local_APICs(void)
1da177e4 1555{
15c8b6c1 1556 on_each_cpu(print_local_APIC, NULL, 1);
1da177e4
LT		 1557}
1558
32f71aff 1559__apicdebuginit(void) print_PIC(void)
1da177e4 1560{
1da177e4
LT		 1561 unsigned int v;
1562 unsigned long flags;
1563
1564 if (apic_verbosity == APIC_QUIET)
1565 return;
1566
1567 printk(KERN_DEBUG "\nprinting PIC contents\n");
1568
1569 spin_lock_irqsave(&i8259A_lock, flags);
1570
1571 v = inb(0xa1) << 8 | inb(0x21);
1572 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1573
1574 v = inb(0xa0) << 8 | inb(0x20);
1575 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1576
1577 outb(0x0b,0xa0);
1578 outb(0x0b,0x20);
1579 v = inb(0xa0) << 8 | inb(0x20);
1580 outb(0x0a,0xa0);
1581 outb(0x0a,0x20);
1582
1583 spin_unlock_irqrestore(&i8259A_lock, flags);
1584
1585 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1586
1587 v = inb(0x4d1) << 8 | inb(0x4d0);
1588 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1589}
1590
32f71aff
MR		 1591__apicdebuginit(int) print_all_ICs(void)
1592{
1593 print_PIC();
1594 print_all_local_APICs();
1595 print_IO_APIC();
1596
1597 return 0;
1598}
1599
1600fs_initcall(print_all_ICs);
1601
1da177e4 1602
efa2559f
YL		 1603/* Where if anywhere is the i8259 connect in external int mode */
1604static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1605
1c69524c 1606void __init enable_IO_APIC(void)
1da177e4
LT		 1607{
1608 union IO_APIC_reg_01 reg_01;
1008fddc 1609 int i8259_apic, i8259_pin;
e5a53714 1610 int apic;
1da177e4
LT		 1611 unsigned long flags;
1612
1da177e4
LT		 1613 /*
1614 * The number of IO-APIC IRQ registers (== #pins):
1615 */
1008fddc 1616 for (apic = 0; apic < nr_ioapics; apic++) {
1da177e4 1617 spin_lock_irqsave(&ioapic_lock, flags);
1008fddc 1618 reg_01.raw = io_apic_read(apic, 1);
1da177e4 1619 spin_unlock_irqrestore(&ioapic_lock, flags);
1008fddc
EB		 1620 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1621 }
1622 for(apic = 0; apic < nr_ioapics; apic++) {
1623 int pin;
1624 /* See if any of the pins is in ExtINT mode */
1625 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1626 struct IO_APIC_route_entry entry;
eea0e11c 1627 entry = ioapic_read_entry(apic, pin);
1008fddc
EB		 1628
1629 /* If the interrupt line is enabled and in ExtInt mode
1630 * I have found the pin where the i8259 is connected.
1631 */
1632 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1633 ioapic_i8259.apic = apic;
1634 ioapic_i8259.pin = pin;
1635 goto found_i8259;
1636 }
1637 }
1638 }
1639 found_i8259:
1640 /* Look to see what if the MP table has reported the ExtINT */
1641 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1642 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1643 /* Trust the MP table if nothing is setup in the hardware */
1644 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1645 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1646 ioapic_i8259.pin = i8259_pin;
1647 ioapic_i8259.apic = i8259_apic;
1648 }
1649 /* Complain if the MP table and the hardware disagree */
1650 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1651 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1652 {
1653 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1da177e4
LT		 1654 }
1655
1656 /*
1657 * Do not trust the IO-APIC being empty at bootup
1658 */
1659 clear_IO_APIC();
1660}
1661
1662/*
1663 * Not an __init, needed by the reboot code
1664 */
1665void disable_IO_APIC(void)
1666{
1667 /*
1668 * Clear the IO-APIC before rebooting:
1669 */
1670 clear_IO_APIC();
1671
208fb931 1672 /*
0b968d23 1673 * If the i8259 is routed through an IOAPIC
208fb931 1674 * Put that IOAPIC in virtual wire mode
0b968d23 1675 * so legacy interrupts can be delivered.
208fb931 1676 */
1008fddc 1677 if (ioapic_i8259.pin != -1) {
208fb931 1678 struct IO_APIC_route_entry entry;
208fb931
EB		 1679
1680 memset(&entry, 0, sizeof(entry));
1681 entry.mask = 0; /* Enabled */
1682 entry.trigger = 0; /* Edge */
1683 entry.irr = 0;
1684 entry.polarity = 0; /* High */
1685 entry.delivery_status = 0;
1686 entry.dest_mode = 0; /* Physical */
1008fddc 1687 entry.delivery_mode = dest_ExtINT; /* ExtInt */
208fb931 1688 entry.vector = 0;
4c9961d5 1689 entry.dest = read_apic_id();
208fb931 1690
208fb931
EB		 1691 /*
1692 * Add it to the IO-APIC irq-routing table:
1693 */
eea0e11c 1694 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
208fb931
EB		 1695 }
1696
1008fddc 1697 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1da177e4
LT		 1698}
1699
d4057bdb 1700int no_timer_check __initdata;
efa2559f
YL		 1701
1702static int __init notimercheck(char *s)
1703{
1704 no_timer_check = 1;
1705 return 1;
1706}
1707__setup("no_timer_check", notimercheck);
1708
1da177e4
LT		 1709/*
1710 * There is a nasty bug in some older SMP boards, their mptable lies
1711 * about the timer IRQ. We do the following to work around the situation:
1712 *
1713 * - timer IRQ defaults to IO-APIC IRQ
1714 * - if this function detects that timer IRQs are defunct, then we fall
1715 * back to ISA timer IRQs
1716 */
1717static int __init timer_irq_works(void)
1718{
1719 unsigned long t1 = jiffies;
4aae0702 1720 unsigned long flags;
1da177e4 1721
efa2559f
YL		 1722 if (no_timer_check)
1723 return 1;
1724
4aae0702 1725 local_save_flags(flags);
1da177e4
LT		 1726 local_irq_enable();
1727 /* Let ten ticks pass... */
1728 mdelay((10 * 1000) / HZ);
4aae0702 1729 local_irq_restore(flags);
1da177e4
LT		 1730
1731 /*
1732 * Expect a few ticks at least, to be sure some possible
1733 * glue logic does not lock up after one or two first
1734 * ticks in a non-ExtINT mode. Also the local APIC
1735 * might have cached one ExtINT interrupt. Finally, at
1736 * least one tick may be lost due to delays.
1737 */
1738
1739 /* jiffies wrap? */
1d16b53e 1740 if (time_after(jiffies, t1 + 4))
1da177e4
LT		 1741 return 1;
1742 return 0;
1743}
1744
1745/*
1746 * In the SMP+IOAPIC case it might happen that there are an unspecified
1747 * number of pending IRQ events unhandled. These cases are very rare,
1748 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1749 * better to do it this way as thus we do not have to be aware of
1750 * 'pending' interrupts in the IRQ path, except at this point.
1751 */
1752/*
1753 * Edge triggered needs to resend any interrupt
1754 * that was delayed but this is now handled in the device
1755 * independent code.
1756 */
1757
1758/*
1759 * Starting up a edge-triggered IO-APIC interrupt is
1760 * nasty - we need to make sure that we get the edge.
1761 * If it is already asserted for some reason, we need
1762 * return 1 to indicate that is was pending.
1763 *
1764 * This is not complete - we should be able to fake
1765 * an edge even if it isn't on the 8259A...
1766 */
1767
f29bd1ba 1768static unsigned int startup_ioapic_irq(unsigned int irq)
1da177e4
LT		 1769{
1770 int was_pending = 0;
1771 unsigned long flags;
1772
1773 spin_lock_irqsave(&ioapic_lock, flags);
1774 if (irq < 16) {
1775 disable_8259A_irq(irq);
1776 if (i8259A_irq_pending(irq))
1777 was_pending = 1;
1778 }
1779 __unmask_IO_APIC_irq(irq);
1780 spin_unlock_irqrestore(&ioapic_lock, flags);
1781
1782 return was_pending;
1783}
1784
04b9267b 1785static int ioapic_retrigger_irq(unsigned int irq)
c0ad90a3 1786{
3ac2de48 1787 struct irq_cfg *cfg = irq_cfg(irq);
6bf2dafa 1788 unsigned long flags;
550f2299 1789
6bf2dafa 1790 spin_lock_irqsave(&vector_lock, flags);
cb6d2be6 1791 send_IPI_mask(cpumask_of_cpu(first_cpu(cfg->domain)), cfg->vector);
6bf2dafa 1792 spin_unlock_irqrestore(&vector_lock, flags);
c0ad90a3
IM		 1793
1794 return 1;
1795}
1796
1da177e4
LT		 1797/*
1798 * Level and edge triggered IO-APIC interrupts need different handling,
1799 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1800 * handled with the level-triggered descriptor, but that one has slightly
1801 * more overhead. Level-triggered interrupts cannot be handled with the
1802 * edge-triggered handler, without risking IRQ storms and other ugly
1803 * races.
1804 */
1805
61014292 1806#ifdef CONFIG_SMP
89027d35
SS		 1807
1808#ifdef CONFIG_INTR_REMAP
1809static void ir_irq_migration(struct work_struct *work);
1810
1811static DECLARE_DELAYED_WORK(ir_migration_work, ir_irq_migration);
1812
1813/*
1814 * Migrate the IO-APIC irq in the presence of intr-remapping.
1815 *
1816 * For edge triggered, irq migration is a simple atomic update(of vector
1817 * and cpu destination) of IRTE and flush the hardware cache.
1818 *
1819 * For level triggered, we need to modify the io-apic RTE aswell with the update
1820 * vector information, along with modifying IRTE with vector and destination.
1821 * So irq migration for level triggered is little bit more complex compared to
1822 * edge triggered migration. But the good news is, we use the same algorithm
1823 * for level triggered migration as we have today, only difference being,
1824 * we now initiate the irq migration from process context instead of the
1825 * interrupt context.
1826 *
1827 * In future, when we do a directed EOI (combined with cpu EOI broadcast
1828 * suppression) to the IO-APIC, level triggered irq migration will also be
1829 * as simple as edge triggered migration and we can do the irq migration
1830 * with a simple atomic update to IO-APIC RTE.
1831 */
1832static void migrate_ioapic_irq(int irq, cpumask_t mask)
1833{
3ac2de48 1834 struct irq_cfg *cfg;
08678b08 1835 struct irq_desc *desc;
89027d35
SS		 1836 cpumask_t tmp, cleanup_mask;
1837 struct irte irte;
08678b08 1838 int modify_ioapic_rte;
89027d35
SS		 1839 unsigned int dest;
1840 unsigned long flags;
1841
1842 cpus_and(tmp, mask, cpu_online_map);
1843 if (cpus_empty(tmp))
1844 return;
1845
1846 if (get_irte(irq, &irte))
1847 return;
1848
1849 if (assign_irq_vector(irq, mask))
1850 return;
1851
3ac2de48 1852 cfg = irq_cfg(irq);
89027d35
SS		 1853 cpus_and(tmp, cfg->domain, mask);
1854 dest = cpu_mask_to_apicid(tmp);
1855
08678b08
YL		 1856 desc = irq_to_desc(irq);
1857 modify_ioapic_rte = desc->status & IRQ_LEVEL;
89027d35
SS		 1858 if (modify_ioapic_rte) {
1859 spin_lock_irqsave(&ioapic_lock, flags);
1860 __target_IO_APIC_irq(irq, dest, cfg->vector);
1861 spin_unlock_irqrestore(&ioapic_lock, flags);
1862 }
1863
1864 irte.vector = cfg->vector;
1865 irte.dest_id = IRTE_DEST(dest);
1866
1867 /*
1868 * Modified the IRTE and flushes the Interrupt entry cache.
1869 */
1870 modify_irte(irq, &irte);
1871
1872 if (cfg->move_in_progress) {
1873 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
1874 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
1875 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
1876 cfg->move_in_progress = 0;
1877 }
1878
08678b08 1879 desc->affinity = mask;
89027d35
SS		 1880}
1881
1882static int migrate_irq_remapped_level(int irq)
1883{
1884 int ret = -1;
08678b08 1885 struct irq_desc *desc = irq_to_desc(irq);
89027d35
SS		 1886
1887 mask_IO_APIC_irq(irq);
1888
1889 if (io_apic_level_ack_pending(irq)) {
1890 /*
1891 * Interrupt in progress. Migrating irq now will change the
1892 * vector information in the IO-APIC RTE and that will confuse
1893 * the EOI broadcast performed by cpu.
1894 * So, delay the irq migration to the next instance.
1895 */
1896 schedule_delayed_work(&ir_migration_work, 1);
1897 goto unmask;
1898 }
1899
1900 /* everthing is clear. we have right of way */
08678b08 1901 migrate_ioapic_irq(irq, desc->pending_mask);
89027d35
SS		 1902
1903 ret = 0;
08678b08
YL		 1904 desc->status &= ~IRQ_MOVE_PENDING;
1905 cpus_clear(desc->pending_mask);
89027d35
SS		 1906
1907unmask:
1908 unmask_IO_APIC_irq(irq);
1909 return ret;
1910}
1911
1912static void ir_irq_migration(struct work_struct *work)
1913{
2c6927a3
YL		 1914 unsigned int irq;
1915 struct irq_desc *desc;
89027d35 1916
2c6927a3 1917 for_each_irq_desc(irq, desc) {
89027d35
SS		 1918 if (desc->status & IRQ_MOVE_PENDING) {
1919 unsigned long flags;
1920
1921 spin_lock_irqsave(&desc->lock, flags);
1922 if (!desc->chip->set_affinity ||
1923 !(desc->status & IRQ_MOVE_PENDING)) {
1924 desc->status &= ~IRQ_MOVE_PENDING;
1925 spin_unlock_irqrestore(&desc->lock, flags);
1926 continue;
1927 }
1928
08678b08 1929 desc->chip->set_affinity(irq, desc->pending_mask);
89027d35
SS		 1930 spin_unlock_irqrestore(&desc->lock, flags);
1931 }
1932 }
1933}
1934
1935/*
1936 * Migrates the IRQ destination in the process context.
1937 */
1938static void set_ir_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
1939{
08678b08
YL		 1940 struct irq_desc *desc = irq_to_desc(irq);
1941
1942 if (desc->status & IRQ_LEVEL) {
1943 desc->status |= IRQ_MOVE_PENDING;
1944 desc->pending_mask = mask;
89027d35
SS		 1945 migrate_irq_remapped_level(irq);
1946 return;
1947 }
1948
1949 migrate_ioapic_irq(irq, mask);
1950}
1951#endif
1952
61014292
EB		 1953asmlinkage void smp_irq_move_cleanup_interrupt(void)
1954{
1955 unsigned vector, me;
1956 ack_APIC_irq();
1957 exit_idle();
1958 irq_enter();
1959
1960 me = smp_processor_id();
1961 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
1962 unsigned int irq;
1963 struct irq_desc *desc;
1964 struct irq_cfg *cfg;
1965 irq = __get_cpu_var(vector_irq)[vector];
61014292 1966
08678b08 1967 desc = irq_to_desc(irq);
cb5bc832
YL		 1968 if (!desc)
1969 continue;
1970
3ac2de48 1971 cfg = irq_cfg(irq);
61014292
EB		 1972 spin_lock(&desc->lock);
1973 if (!cfg->move_cleanup_count)
1974 goto unlock;
1975
1976 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
1977 goto unlock;
1978
1979 __get_cpu_var(vector_irq)[vector] = -1;
1980 cfg->move_cleanup_count--;
1981unlock:
1982 spin_unlock(&desc->lock);
1983 }
1984
1985 irq_exit();
1986}
1987
1988static void irq_complete_move(unsigned int irq)
1989{
3ac2de48 1990 struct irq_cfg *cfg = irq_cfg(irq);
61014292
EB		 1991 unsigned vector, me;
1992
1993 if (likely(!cfg->move_in_progress))
1994 return;
1995
65ea5b03 1996 vector = ~get_irq_regs()->orig_ax;
61014292 1997 me = smp_processor_id();
f0e13ae7 1998 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
61014292
EB		 1999 cpumask_t cleanup_mask;
2000
2001 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
2002 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
2003 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2004 cfg->move_in_progress = 0;
2005 }
2006}
2007#else
2008static inline void irq_complete_move(unsigned int irq) {}
2009#endif
89027d35
SS		 2010#ifdef CONFIG_INTR_REMAP
2011static void ack_x2apic_level(unsigned int irq)
2012{
2013 ack_x2APIC_irq();
2014}
2015
2016static void ack_x2apic_edge(unsigned int irq)
2017{
2018 ack_x2APIC_irq();
2019}
2020#endif
61014292 2021
0be6652f
EB		 2022static void ack_apic_edge(unsigned int irq)
2023{
61014292 2024 irq_complete_move(irq);
0be6652f
EB		 2025 move_native_irq(irq);
2026 ack_APIC_irq();
2027}
2028
2029static void ack_apic_level(unsigned int irq)
2030{
2031 int do_unmask_irq = 0;
2032
61014292 2033 irq_complete_move(irq);
52e3d90d 2034#ifdef CONFIG_GENERIC_PENDING_IRQ
0be6652f 2035 /* If we are moving the irq we need to mask it */
08678b08 2036 if (unlikely(irq_to_desc(irq)->status & IRQ_MOVE_PENDING)) {
0be6652f
EB		 2037 do_unmask_irq = 1;
2038 mask_IO_APIC_irq(irq);
2039 }
2040#endif
2041
2042 /*
2043 * We must acknowledge the irq before we move it or the acknowledge will
beb7dd86 2044 * not propagate properly.
0be6652f
EB		 2045 */
2046 ack_APIC_irq();
2047
2048 /* Now we can move and renable the irq */
ef3e28c5
EB		 2049 if (unlikely(do_unmask_irq)) {
2050 /* Only migrate the irq if the ack has been received.
2051 *
2052 * On rare occasions the broadcast level triggered ack gets
2053 * delayed going to ioapics, and if we reprogram the
2054 * vector while Remote IRR is still set the irq will never
2055 * fire again.
2056 *
2057 * To prevent this scenario we read the Remote IRR bit
2058 * of the ioapic. This has two effects.
2059 * - On any sane system the read of the ioapic will
2060 * flush writes (and acks) going to the ioapic from
2061 * this cpu.
2062 * - We get to see if the ACK has actually been delivered.
2063 *
2064 * Based on failed experiments of reprogramming the
2065 * ioapic entry from outside of irq context starting
2066 * with masking the ioapic entry and then polling until
2067 * Remote IRR was clear before reprogramming the
2068 * ioapic I don't trust the Remote IRR bit to be
2069 * completey accurate.
2070 *
2071 * However there appears to be no other way to plug
2072 * this race, so if the Remote IRR bit is not
2073 * accurate and is causing problems then it is a hardware bug
2074 * and you can go talk to the chipset vendor about it.
2075 */
2076 if (!io_apic_level_ack_pending(irq))
2077 move_masked_irq(irq);
0be6652f 2078 unmask_IO_APIC_irq(irq);
ef3e28c5 2079 }
0be6652f
EB		 2080}
2081
f29bd1ba
IM		 2082static struct irq_chip ioapic_chip __read_mostly = {
2083 .name = "IO-APIC",
04b9267b
EB		 2084 .startup = startup_ioapic_irq,
2085 .mask = mask_IO_APIC_irq,
2086 .unmask = unmask_IO_APIC_irq,
0be6652f
EB		 2087 .ack = ack_apic_edge,
2088 .eoi = ack_apic_level,
54d5d424 2089#ifdef CONFIG_SMP
04b9267b 2090 .set_affinity = set_ioapic_affinity_irq,
54d5d424 2091#endif
04b9267b 2092 .retrigger = ioapic_retrigger_irq,
1da177e4
LT		 2093};
2094
89027d35
SS		 2095#ifdef CONFIG_INTR_REMAP
2096static struct irq_chip ir_ioapic_chip __read_mostly = {
2097 .name = "IR-IO-APIC",
2098 .startup = startup_ioapic_irq,
2099 .mask = mask_IO_APIC_irq,
2100 .unmask = unmask_IO_APIC_irq,
2101 .ack = ack_x2apic_edge,
2102 .eoi = ack_x2apic_level,
2103#ifdef CONFIG_SMP
2104 .set_affinity = set_ir_ioapic_affinity_irq,
2105#endif
2106 .retrigger = ioapic_retrigger_irq,
2107};
2108#endif
2109
1da177e4
LT		 2110static inline void init_IO_APIC_traps(void)
2111{
2112 int irq;
08678b08 2113 struct irq_desc *desc;
46b8214d 2114 struct irq_cfg *cfg;
1da177e4
LT		 2115
2116 /*
2117 * NOTE! The local APIC isn't very good at handling
2118 * multiple interrupts at the same interrupt level.
2119 * As the interrupt level is determined by taking the
2120 * vector number and shifting that right by 4, we
2121 * want to spread these out a bit so that they don't
2122 * all fall in the same interrupt level.
2123 *
2124 * Also, we've got to be careful not to trash gate
2125 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2126 */
46b8214d
YL		 2127 for_each_irq_cfg(cfg) {
2128 irq = cfg->irq;
3ac2de48 2129 if (IO_APIC_IRQ(irq) && !cfg->vector) {
1da177e4
LT		 2130 /*
2131 * Hmm.. We don't have an entry for this,
2132 * so default to an old-fashioned 8259
2133 * interrupt if we can..
2134 */
2135 if (irq < 16)
2136 make_8259A_irq(irq);
08678b08
YL		 2137 else {
2138 desc = irq_to_desc(irq);
1da177e4 2139 /* Strange. Oh, well.. */
08678b08
YL		 2140 desc->chip = &no_irq_chip;
2141 }
1da177e4
LT		 2142 }
2143 }
2144}
2145
c88ac1df 2146static void unmask_lapic_irq(unsigned int irq)
1da177e4
LT		 2147{
2148 unsigned long v;
2149
2150 v = apic_read(APIC_LVT0);
11a8e778 2151 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1da177e4
LT		 2152}
2153
c88ac1df 2154static void mask_lapic_irq(unsigned int irq)
1da177e4
LT		 2155{
2156 unsigned long v;
2157
2158 v = apic_read(APIC_LVT0);
11a8e778 2159 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1da177e4
LT		 2160}
2161
2162static void ack_lapic_irq (unsigned int irq)
2163{
2164 ack_APIC_irq();
2165}
2166
c88ac1df
MR		 2167static struct irq_chip lapic_chip __read_mostly = {
2168 .name = "local-APIC",
2169 .mask = mask_lapic_irq,
2170 .unmask = unmask_lapic_irq,
2171 .ack = ack_lapic_irq,
1da177e4
LT		 2172};
2173
c88ac1df
MR		 2174static void lapic_register_intr(int irq)
2175{
08678b08
YL		 2176 struct irq_desc *desc;
2177
2178 desc = irq_to_desc(irq);
2179 desc->status &= ~IRQ_LEVEL;
c88ac1df
MR		 2180 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2181 "edge");
2182}
2183
e9427101 2184static void __init setup_nmi(void)
1da177e4
LT		 2185{
2186 /*
2187 * Dirty trick to enable the NMI watchdog ...
2188 * We put the 8259A master into AEOI mode and
2189 * unmask on all local APICs LVT0 as NMI.
2190 *
2191 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2192 * is from Maciej W. Rozycki - so we do not have to EOI from
2193 * the NMI handler or the timer interrupt.
2194 */
2195 printk(KERN_INFO "activating NMI Watchdog ...");
2196
e9427101 2197 enable_NMI_through_LVT0();
1da177e4
LT		 2198
2199 printk(" done.\n");
2200}
2201
2202/*
2203 * This looks a bit hackish but it's about the only one way of sending
2204 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2205 * not support the ExtINT mode, unfortunately. We need to send these
2206 * cycles as some i82489DX-based boards have glue logic that keeps the
2207 * 8259A interrupt line asserted until INTA. --macro
2208 */
5afca33a 2209static inline void __init unlock_ExtINT_logic(void)
1da177e4 2210{
1008fddc 2211 int apic, pin, i;
1da177e4
LT		 2212 struct IO_APIC_route_entry entry0, entry1;
2213 unsigned char save_control, save_freq_select;
1da177e4 2214
1008fddc
EB		 2215 pin = find_isa_irq_pin(8, mp_INT);
2216 apic = find_isa_irq_apic(8, mp_INT);
1da177e4
LT		 2217 if (pin == -1)
2218 return;
2219
a2249cba
AM		 2220 entry0 = ioapic_read_entry(apic, pin);
2221
1008fddc 2222 clear_IO_APIC_pin(apic, pin);
1da177e4
LT		 2223
2224 memset(&entry1, 0, sizeof(entry1));
2225
2226 entry1.dest_mode = 0; /* physical delivery */
2227 entry1.mask = 0; /* unmask IRQ now */
ee4eff6f 2228 entry1.dest = hard_smp_processor_id();
1da177e4
LT		 2229 entry1.delivery_mode = dest_ExtINT;
2230 entry1.polarity = entry0.polarity;
2231 entry1.trigger = 0;
2232 entry1.vector = 0;
2233
a2249cba 2234 ioapic_write_entry(apic, pin, entry1);
1da177e4
LT		 2235
2236 save_control = CMOS_READ(RTC_CONTROL);
2237 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2238 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2239 RTC_FREQ_SELECT);
2240 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2241
2242 i = 100;
2243 while (i-- > 0) {
2244 mdelay(10);
2245 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2246 i -= 10;
2247 }
2248
2249 CMOS_WRITE(save_control, RTC_CONTROL);
2250 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1008fddc 2251 clear_IO_APIC_pin(apic, pin);
1da177e4 2252
a2249cba 2253 ioapic_write_entry(apic, pin, entry0);
1da177e4
LT		 2254}
2255
efa2559f
YL		 2256static int disable_timer_pin_1 __initdata;
2257/* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2258static int __init disable_timer_pin_setup(char *arg)
2259{
2260 disable_timer_pin_1 = 1;
2261 return 0;
2262}
2263early_param("disable_timer_pin_1", disable_timer_pin_setup);
2264
2265int timer_through_8259 __initdata;
2266
1da177e4
LT		 2267/*
2268 * This code may look a bit paranoid, but it's supposed to cooperate with
2269 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2270 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2271 * fanatically on his truly buggy board.
fea5f1e1
LT		 2272 *
2273 * FIXME: really need to revamp this for modern platforms only.
1da177e4 2274 */
e9427101 2275static inline void __init check_timer(void)
1da177e4 2276{
3ac2de48 2277 struct irq_cfg *cfg = irq_cfg(0);
1008fddc 2278 int apic1, pin1, apic2, pin2;
4aae0702 2279 unsigned long flags;
691874fa 2280 int no_pin1 = 0;
4aae0702
IM		 2281
2282 local_irq_save(flags);
1da177e4
LT		 2283
2284 /*
2285 * get/set the timer IRQ vector:
2286 */
2287 disable_8259A_irq(0);
dfbffdd8 2288 assign_irq_vector(0, TARGET_CPUS);
1da177e4
LT		 2289
2290 /*
d11d5794
MR		 2291 * As IRQ0 is to be enabled in the 8259A, the virtual
2292 * wire has to be disabled in the local APIC.
1da177e4 2293 */
11a8e778 2294 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1da177e4 2295 init_8259A(1);
1da177e4 2296
1008fddc
EB		 2297 pin1 = find_isa_irq_pin(0, mp_INT);
2298 apic1 = find_isa_irq_apic(0, mp_INT);
2299 pin2 = ioapic_i8259.pin;
2300 apic2 = ioapic_i8259.apic;
1da177e4 2301
49a66a0b
MR		 2302 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2303 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2304 cfg->vector, apic1, pin1, apic2, pin2);
b0268726 2305
691874fa
MR		 2306 /*
2307 * Some BIOS writers are clueless and report the ExtINTA
2308 * I/O APIC input from the cascaded 8259A as the timer
2309 * interrupt input. So just in case, if only one pin
2310 * was found above, try it both directly and through the
2311 * 8259A.
2312 */
2313 if (pin1 == -1) {
efa2559f 2314#ifdef CONFIG_INTR_REMAP
89027d35
SS		 2315 if (intr_remapping_enabled)
2316 panic("BIOS bug: timer not connected to IO-APIC");
efa2559f 2317#endif
691874fa
MR		 2318 pin1 = pin2;
2319 apic1 = apic2;
2320 no_pin1 = 1;
2321 } else if (pin2 == -1) {
2322 pin2 = pin1;
2323 apic2 = apic1;
2324 }
2325
fea5f1e1
LT		 2326 if (pin1 != -1) {
2327 /*
2328 * Ok, does IRQ0 through the IOAPIC work?
2329 */
691874fa
MR		 2330 if (no_pin1) {
2331 add_pin_to_irq(0, apic1, pin1);
b1b57ee1 2332 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
691874fa 2333 }
fea5f1e1 2334 unmask_IO_APIC_irq(0);
efa2559f 2335 if (timer_irq_works()) {
fea5f1e1 2336 if (nmi_watchdog == NMI_IO_APIC) {
fea5f1e1
LT		 2337 setup_nmi();
2338 enable_8259A_irq(0);
2339 }
2340 if (disable_timer_pin_1 > 0)
2341 clear_IO_APIC_pin(0, pin1);
4aae0702 2342 goto out;
fea5f1e1 2343 }
efa2559f 2344#ifdef CONFIG_INTR_REMAP
89027d35
SS		 2345 if (intr_remapping_enabled)
2346 panic("timer doesn't work through Interrupt-remapped IO-APIC");
efa2559f 2347#endif
fea5f1e1 2348 clear_IO_APIC_pin(apic1, pin1);
691874fa 2349 if (!no_pin1)
49a66a0b 2350 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
691874fa 2351 "8254 timer not connected to IO-APIC\n");
1da177e4 2352
49a66a0b
MR		 2353 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2354 "(IRQ0) through the 8259A ...\n");
2355 apic_printk(APIC_QUIET, KERN_INFO
2356 "..... (found apic %d pin %d) ...\n", apic2, pin2);
fea5f1e1
LT		 2357 /*
2358 * legacy devices should be connected to IO APIC #0
2359 */
0b9f4f49 2360 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
f7633ce5 2361 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
24742ece 2362 unmask_IO_APIC_irq(0);
ecd29476 2363 enable_8259A_irq(0);
fea5f1e1 2364 if (timer_irq_works()) {
49a66a0b 2365 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
35542c5e 2366 timer_through_8259 = 1;
fea5f1e1 2367 if (nmi_watchdog == NMI_IO_APIC) {
60134ebe 2368 disable_8259A_irq(0);
fea5f1e1 2369 setup_nmi();
60134ebe 2370 enable_8259A_irq(0);
fea5f1e1 2371 }
4aae0702 2372 goto out;
fea5f1e1
LT		 2373 }
2374 /*
2375 * Cleanup, just in case ...
2376 */
ecd29476 2377 disable_8259A_irq(0);
fea5f1e1 2378 clear_IO_APIC_pin(apic2, pin2);
49a66a0b 2379 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
1da177e4 2380 }
1da177e4 2381
1f992153 2382 if (nmi_watchdog == NMI_IO_APIC) {
49a66a0b
MR		 2383 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2384 "through the IO-APIC - disabling NMI Watchdog!\n");
067fa0ff 2385 nmi_watchdog = NMI_NONE;
1da177e4
LT		 2386 }
2387
49a66a0b
MR		 2388 apic_printk(APIC_QUIET, KERN_INFO
2389 "...trying to set up timer as Virtual Wire IRQ...\n");
1da177e4 2390
c88ac1df 2391 lapic_register_intr(0);
dfbffdd8 2392 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
1da177e4
LT		 2393 enable_8259A_irq(0);
2394
2395 if (timer_irq_works()) {
49a66a0b 2396 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
4aae0702 2397 goto out;
1da177e4 2398 }
e67465f1 2399 disable_8259A_irq(0);
dfbffdd8 2400 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
49a66a0b 2401 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
1da177e4 2402
49a66a0b
MR		 2403 apic_printk(APIC_QUIET, KERN_INFO
2404 "...trying to set up timer as ExtINT IRQ...\n");
1da177e4
LT		 2405
2406 init_8259A(0);
2407 make_8259A_irq(0);
11a8e778 2408 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1da177e4
LT		 2409
2410 unlock_ExtINT_logic();
2411
2412 if (timer_irq_works()) {
49a66a0b 2413 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
4aae0702 2414 goto out;
1da177e4 2415 }
49a66a0b
MR		 2416 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2417 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2418 "report. Then try booting with the 'noapic' option.\n");
4aae0702
IM		 2419out:
2420 local_irq_restore(flags);
1da177e4
LT		 2421}
2422
2423/*
af174783
MR		 2424 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2425 * to devices. However there may be an I/O APIC pin available for
2426 * this interrupt regardless. The pin may be left unconnected, but
2427 * typically it will be reused as an ExtINT cascade interrupt for
2428 * the master 8259A. In the MPS case such a pin will normally be
2429 * reported as an ExtINT interrupt in the MP table. With ACPI
2430 * there is no provision for ExtINT interrupts, and in the absence
2431 * of an override it would be treated as an ordinary ISA I/O APIC
2432 * interrupt, that is edge-triggered and unmasked by default. We
2433 * used to do this, but it caused problems on some systems because
2434 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2435 * the same ExtINT cascade interrupt to drive the local APIC of the
2436 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2437 * the I/O APIC in all cases now. No actual device should request
2438 * it anyway. --macro
1da177e4
LT		 2439 */
2440#define PIC_IRQS (1<<2)
2441
2442void __init setup_IO_APIC(void)
2443{
1c69524c
YL		 2444
2445 /*
2446 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2447 */
1da177e4 2448
af174783 2449 io_apic_irqs = ~PIC_IRQS;
1da177e4
LT		 2450
2451 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2452
1da177e4
LT		 2453 sync_Arb_IDs();
2454 setup_IO_APIC_irqs();
2455 init_IO_APIC_traps();
2456 check_timer();
1da177e4
LT		 2457}
2458
f876d213
YL		 2459/*
2460 * Called after all the initialization is done. If we didnt find any
2461 * APIC bugs then we can allow the modify fast path
2462 */
2463
2464static int __init io_apic_bug_finalize(void)
2465{
2466 if (sis_apic_bug == -1)
2467 sis_apic_bug = 0;
2468 return 0;
2469}
2470
2471late_initcall(io_apic_bug_finalize);
2472
1da177e4
LT		 2473struct sysfs_ioapic_data {
2474 struct sys_device dev;
2475 struct IO_APIC_route_entry entry[0];
2476};
2477static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2478
0b9c33a7 2479static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1da177e4
LT		 2480{
2481 struct IO_APIC_route_entry *entry;
2482 struct sysfs_ioapic_data *data;
1da177e4
LT		 2483 int i;
2484
2485 data = container_of(dev, struct sysfs_ioapic_data, dev);
2486 entry = data->entry;
eea0e11c
AK		 2487 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
2488 *entry = ioapic_read_entry(dev->id, i);
1da177e4
LT		 2489
2490 return 0;
2491}
2492
2493static int ioapic_resume(struct sys_device *dev)
2494{
2495 struct IO_APIC_route_entry *entry;
2496 struct sysfs_ioapic_data *data;
2497 unsigned long flags;
2498 union IO_APIC_reg_00 reg_00;
2499 int i;
2500
2501 data = container_of(dev, struct sysfs_ioapic_data, dev);
2502 entry = data->entry;
2503
2504 spin_lock_irqsave(&ioapic_lock, flags);
2505 reg_00.raw = io_apic_read(dev->id, 0);
ec2cd0a2
AS		 2506 if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) {
2507 reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid;
1da177e4
LT		 2508 io_apic_write(dev->id, 0, reg_00.raw);
2509 }
1da177e4 2510 spin_unlock_irqrestore(&ioapic_lock, flags);
eea0e11c
AK		 2511 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
2512 ioapic_write_entry(dev->id, i, entry[i]);
1da177e4
LT		 2513
2514 return 0;
2515}
2516
2517static struct sysdev_class ioapic_sysdev_class = {
af5ca3f4 2518 .name = "ioapic",
1da177e4
LT		 2519 .suspend = ioapic_suspend,
2520 .resume = ioapic_resume,
2521};
2522
2523static int __init ioapic_init_sysfs(void)
2524{
2525 struct sys_device * dev;
cddf7ff7 2526 int i, size, error;
1da177e4
LT		 2527
2528 error = sysdev_class_register(&ioapic_sysdev_class);
2529 if (error)
2530 return error;
2531
2532 for (i = 0; i < nr_ioapics; i++ ) {
2533 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2534 * sizeof(struct IO_APIC_route_entry);
cddf7ff7 2535 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
1da177e4
LT		 2536 if (!mp_ioapic_data[i]) {
2537 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2538 continue;
2539 }
1da177e4
LT		 2540 dev = &mp_ioapic_data[i]->dev;
2541 dev->id = i;
2542 dev->cls = &ioapic_sysdev_class;
2543 error = sysdev_register(dev);
2544 if (error) {
2545 kfree(mp_ioapic_data[i]);
2546 mp_ioapic_data[i] = NULL;
2547 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2548 continue;
2549 }
2550 }
2551
2552 return 0;
2553}
2554
2555device_initcall(ioapic_init_sysfs);
2556
c4fa0bbf 2557/*
04b9267b 2558 * Dynamic irq allocate and deallocation
c4fa0bbf 2559 */
6d50bc26 2560unsigned int create_irq_nr(unsigned int irq_want)
c4fa0bbf 2561{
04b9267b 2562 /* Allocate an unused irq */
6d50bc26
YL		 2563 unsigned int irq;
2564 unsigned int new;
c4fa0bbf 2565 unsigned long flags;
3ac2de48 2566 struct irq_cfg *cfg_new;
c4fa0bbf 2567
6d50bc26
YL		 2568#ifndef CONFIG_HAVE_SPARSE_IRQ
2569 irq_want = nr_irqs - 1;
2570#endif
2571
2572 irq = 0;
04b9267b 2573 spin_lock_irqsave(&vector_lock, flags);
6d50bc26 2574 for (new = irq_want; new > 0; new--) {
04b9267b
EB		 2575 if (platform_legacy_irq(new))
2576 continue;
3ac2de48
YL		 2577 cfg_new = irq_cfg(new);
2578 if (cfg_new && cfg_new->vector != 0)
04b9267b 2579 continue;
3ac2de48
YL		 2580 /* check if need to create one */
2581 if (!cfg_new)
2582 cfg_new = irq_cfg_alloc(new);
dfbffdd8 2583 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
04b9267b
EB		 2584 irq = new;
2585 break;
2586 }
2587 spin_unlock_irqrestore(&vector_lock, flags);
c4fa0bbf 2588
6d50bc26 2589 if (irq > 0) {
c4fa0bbf
EB		 2590 dynamic_irq_init(irq);
2591 }
2592 return irq;
2593}
2594
6d50bc26
YL		 2595int create_irq(void)
2596{
2597 int irq;
2598
2599 irq = create_irq_nr(nr_irqs - 1);
2600
2601 if (irq == 0)
2602 irq = -1;
2603
2604 return irq;
2605}
2606
c4fa0bbf
EB		 2607void destroy_irq(unsigned int irq)
2608{
2609 unsigned long flags;
c4fa0bbf
EB		 2610
2611 dynamic_irq_cleanup(irq);
2612
75c46fa6
SS		 2613#ifdef CONFIG_INTR_REMAP
2614 free_irte(irq);
2615#endif
c4fa0bbf 2616 spin_lock_irqsave(&vector_lock, flags);
5df0287e 2617 __clear_irq_vector(irq);
c4fa0bbf
EB		 2618 spin_unlock_irqrestore(&vector_lock, flags);
2619}
c4fa0bbf 2620
589e367f 2621/*
676b1855 2622 * MSI message composition
589e367f
EB		 2623 */
2624#ifdef CONFIG_PCI_MSI
3b7d1921 2625static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
589e367f 2626{
3ac2de48 2627 struct irq_cfg *cfg;
dfbffdd8 2628 int err;
589e367f 2629 unsigned dest;
c7111c13 2630 cpumask_t tmp;
589e367f 2631
dfbffdd8
EB		 2632 tmp = TARGET_CPUS;
2633 err = assign_irq_vector(irq, tmp);
75c46fa6
SS		 2634 if (err)
2635 return err;
2636
3ac2de48 2637 cfg = irq_cfg(irq);
75c46fa6
SS		 2638 cpus_and(tmp, cfg->domain, tmp);
2639 dest = cpu_mask_to_apicid(tmp);
2640
2641#ifdef CONFIG_INTR_REMAP
2642 if (irq_remapped(irq)) {
2643 struct irte irte;
2644 int ir_index;
2645 u16 sub_handle;
2646
2647 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
2648 BUG_ON(ir_index == -1);
2649
2650 memset (&irte, 0, sizeof(irte));
2651
2652 irte.present = 1;
2653 irte.dst_mode = INT_DEST_MODE;
2654 irte.trigger_mode = 0; /* edge */
2655 irte.dlvry_mode = INT_DELIVERY_MODE;
2656 irte.vector = cfg->vector;
2657 irte.dest_id = IRTE_DEST(dest);
2658
2659 modify_irte(irq, &irte);
589e367f 2660
75c46fa6
SS		 2661 msg->address_hi = MSI_ADDR_BASE_HI;
2662 msg->data = sub_handle;
2663 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
2664 MSI_ADDR_IR_SHV |
2665 MSI_ADDR_IR_INDEX1(ir_index) |
2666 MSI_ADDR_IR_INDEX2(ir_index);
2667 } else
2668#endif
2669 {
589e367f
EB		 2670 msg->address_hi = MSI_ADDR_BASE_HI;
2671 msg->address_lo =
2672 MSI_ADDR_BASE_LO |
2673 ((INT_DEST_MODE == 0) ?
2674 MSI_ADDR_DEST_MODE_PHYSICAL:
2675 MSI_ADDR_DEST_MODE_LOGICAL) |
2676 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2677 MSI_ADDR_REDIRECTION_CPU:
2678 MSI_ADDR_REDIRECTION_LOWPRI) |
2679 MSI_ADDR_DEST_ID(dest);
2680
2681 msg->data =
2682 MSI_DATA_TRIGGER_EDGE |
2683 MSI_DATA_LEVEL_ASSERT |
2684 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2685 MSI_DATA_DELIVERY_FIXED:
2686 MSI_DATA_DELIVERY_LOWPRI) |
dfbffdd8 2687 MSI_DATA_VECTOR(cfg->vector);
589e367f 2688 }
dfbffdd8 2689 return err;
589e367f
EB		 2690}
2691
3b7d1921
EB		 2692#ifdef CONFIG_SMP
2693static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
589e367f 2694{
3ac2de48 2695 struct irq_cfg *cfg;
3b7d1921
EB		 2696 struct msi_msg msg;
2697 unsigned int dest;
2698 cpumask_t tmp;
08678b08 2699 struct irq_desc *desc;
3b7d1921
EB		 2700
2701 cpus_and(tmp, mask, cpu_online_map);
2702 if (cpus_empty(tmp))
5ff5115e 2703 return;
589e367f 2704
dfbffdd8 2705 if (assign_irq_vector(irq, mask))
3b7d1921 2706 return;
550f2299 2707
3ac2de48 2708 cfg = irq_cfg(irq);
dfbffdd8 2709 cpus_and(tmp, cfg->domain, mask);
3b7d1921 2710 dest = cpu_mask_to_apicid(tmp);
589e367f 2711
3b7d1921
EB		 2712 read_msi_msg(irq, &msg);
2713
2714 msg.data &= ~MSI_DATA_VECTOR_MASK;
dfbffdd8 2715 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3b7d1921
EB		 2716 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2717 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2718
2719 write_msi_msg(irq, &msg);
08678b08
YL		 2720 desc = irq_to_desc(irq);
2721 desc->affinity = mask;
589e367f 2722}
75c46fa6
SS		 2723
2724#ifdef CONFIG_INTR_REMAP
2725/*
2726 * Migrate the MSI irq to another cpumask. This migration is
2727 * done in the process context using interrupt-remapping hardware.
2728 */
2729static void ir_set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2730{
3ac2de48 2731 struct irq_cfg *cfg;
75c46fa6
SS		 2732 unsigned int dest;
2733 cpumask_t tmp, cleanup_mask;
2734 struct irte irte;
08678b08 2735 struct irq_desc *desc;
75c46fa6
SS		 2736
2737 cpus_and(tmp, mask, cpu_online_map);
2738 if (cpus_empty(tmp))
2739 return;
2740
2741 if (get_irte(irq, &irte))
2742 return;
2743
2744 if (assign_irq_vector(irq, mask))
2745 return;
2746
3ac2de48 2747 cfg = irq_cfg(irq);
75c46fa6
SS		 2748 cpus_and(tmp, cfg->domain, mask);
2749 dest = cpu_mask_to_apicid(tmp);
2750
2751 irte.vector = cfg->vector;
2752 irte.dest_id = IRTE_DEST(dest);
2753
2754 /*
2755 * atomically update the IRTE with the new destination and vector.
2756 */
2757 modify_irte(irq, &irte);
2758
2759 /*
2760 * After this point, all the interrupts will start arriving
2761 * at the new destination. So, time to cleanup the previous
2762 * vector allocation.
2763 */
2764 if (cfg->move_in_progress) {
2765 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
2766 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
2767 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2768 cfg->move_in_progress = 0;
2769 }
2770
08678b08
YL		 2771 desc = irq_to_desc(irq);
2772 desc->affinity = mask;
75c46fa6
SS		 2773}
2774#endif
3b7d1921 2775#endif /* CONFIG_SMP */
589e367f 2776
3b7d1921
EB		 2777/*
2778 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2779 * which implement the MSI or MSI-X Capability Structure.
2780 */
2781static struct irq_chip msi_chip = {
2782 .name = "PCI-MSI",
2783 .unmask = unmask_msi_irq,
2784 .mask = mask_msi_irq,
2785 .ack = ack_apic_edge,
2786#ifdef CONFIG_SMP
2787 .set_affinity = set_msi_irq_affinity,
2788#endif
2789 .retrigger = ioapic_retrigger_irq,
589e367f
EB		 2790};
2791
75c46fa6
SS		 2792#ifdef CONFIG_INTR_REMAP
2793static struct irq_chip msi_ir_chip = {
2794 .name = "IR-PCI-MSI",
2795 .unmask = unmask_msi_irq,
2796 .mask = mask_msi_irq,
2797 .ack = ack_x2apic_edge,
2798#ifdef CONFIG_SMP
2799 .set_affinity = ir_set_msi_irq_affinity,
2800#endif
2801 .retrigger = ioapic_retrigger_irq,
2802};
2803
2804/*
2805 * Map the PCI dev to the corresponding remapping hardware unit
2806 * and allocate 'nvec' consecutive interrupt-remapping table entries
2807 * in it.
2808 */
2809static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3b7d1921 2810{
75c46fa6
SS		 2811 struct intel_iommu *iommu;
2812 int index;
2813
2814 iommu = map_dev_to_ir(dev);
2815 if (!iommu) {
2816 printk(KERN_ERR
2817 "Unable to map PCI %s to iommu\n", pci_name(dev));
2818 return -ENOENT;
2819 }
2820
2821 index = alloc_irte(iommu, irq, nvec);
2822 if (index < 0) {
2823 printk(KERN_ERR
2824 "Unable to allocate %d IRTE for PCI %s\n", nvec,
2825 pci_name(dev));
2826 return -ENOSPC;
2827 }
2828 return index;
2829}
2830#endif
2831
2832static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc, int irq)
2833{
2834 int ret;
3b7d1921 2835 struct msi_msg msg;
75c46fa6
SS		 2836
2837 ret = msi_compose_msg(dev, irq, &msg);
2838 if (ret < 0)
2839 return ret;
2840
2841 set_irq_msi(irq, desc);
2842 write_msi_msg(irq, &msg);
2843
2844#ifdef CONFIG_INTR_REMAP
2845 if (irq_remapped(irq)) {
08678b08 2846 struct irq_desc *desc = irq_to_desc(irq);
75c46fa6
SS		 2847 /*
2848 * irq migration in process context
2849 */
2850 desc->status |= IRQ_MOVE_PCNTXT;
2851 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
2852 } else
2853#endif
2854 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
2855
2856 return 0;
2857}
2858
6d50bc26
YL		 2859static unsigned int build_irq_for_pci_dev(struct pci_dev *dev)
2860{
2861 unsigned int irq;
2862
2863 irq = dev->bus->number;
2864 irq <<= 8;
2865 irq |= dev->devfn;
2866 irq <<= 12;
2867
2868 return irq;
2869}
2870
75c46fa6
SS		 2871int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2872{
6d50bc26
YL		 2873 unsigned int irq;
2874 int ret;
2875 unsigned int irq_want;
75c46fa6 2876
6d50bc26
YL		 2877 irq_want = build_irq_for_pci_dev(dev) + 0x100;
2878
2879 irq = create_irq_nr(irq_want);
2880 if (irq == 0)
2881 return -1;
f7feaca7 2882
75c46fa6
SS		 2883#ifdef CONFIG_INTR_REMAP
2884 if (!intr_remapping_enabled)
2885 goto no_ir;
2886
2887 ret = msi_alloc_irte(dev, irq, 1);
2888 if (ret < 0)
2889 goto error;
2890no_ir:
2891#endif
2892 ret = setup_msi_irq(dev, desc, irq);
f7feaca7
EB		 2893 if (ret < 0) {
2894 destroy_irq(irq);
3b7d1921 2895 return ret;
f7feaca7 2896 }
75c46fa6 2897 return 0;
3b7d1921 2898
75c46fa6
SS		 2899#ifdef CONFIG_INTR_REMAP
2900error:
2901 destroy_irq(irq);
2902 return ret;
2903#endif
2904}
3b7d1921 2905
75c46fa6
SS		 2906int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
2907{
6d50bc26
YL		 2908 unsigned int irq;
2909 int ret, sub_handle;
75c46fa6 2910 struct msi_desc *desc;
6d50bc26
YL		 2911 unsigned int irq_want;
2912
75c46fa6
SS		 2913#ifdef CONFIG_INTR_REMAP
2914 struct intel_iommu *iommu = 0;
2915 int index = 0;
2916#endif
2917
6d50bc26 2918 irq_want = build_irq_for_pci_dev(dev) + 0x100;
75c46fa6
SS		 2919 sub_handle = 0;
2920 list_for_each_entry(desc, &dev->msi_list, list) {
6d50bc26
YL		 2921 irq = create_irq_nr(irq_want--);
2922 if (irq == 0)
2923 return -1;
75c46fa6
SS		 2924#ifdef CONFIG_INTR_REMAP
2925 if (!intr_remapping_enabled)
2926 goto no_ir;
3b7d1921 2927
75c46fa6
SS		 2928 if (!sub_handle) {
2929 /*
2930 * allocate the consecutive block of IRTE's
2931 * for 'nvec'
2932 */
2933 index = msi_alloc_irte(dev, irq, nvec);
2934 if (index < 0) {
2935 ret = index;
2936 goto error;
2937 }
2938 } else {
2939 iommu = map_dev_to_ir(dev);
2940 if (!iommu) {
2941 ret = -ENOENT;
2942 goto error;
2943 }
2944 /*
2945 * setup the mapping between the irq and the IRTE
2946 * base index, the sub_handle pointing to the
2947 * appropriate interrupt remap table entry.
2948 */
2949 set_irte_irq(irq, iommu, index, sub_handle);
2950 }
2951no_ir:
2952#endif
2953 ret = setup_msi_irq(dev, desc, irq);
2954 if (ret < 0)
2955 goto error;
2956 sub_handle++;
2957 }
7fe3730d 2958 return 0;
75c46fa6
SS		 2959
2960error:
2961 destroy_irq(irq);
2962 return ret;
3b7d1921
EB		 2963}
2964
2965void arch_teardown_msi_irq(unsigned int irq)
2966{
f7feaca7 2967 destroy_irq(irq);
3b7d1921
EB		 2968}
2969
3460a6d9
KA		 2970#ifdef CONFIG_DMAR
2971#ifdef CONFIG_SMP
2972static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask)
2973{
3ac2de48 2974 struct irq_cfg *cfg;
3460a6d9
KA		 2975 struct msi_msg msg;
2976 unsigned int dest;
2977 cpumask_t tmp;
08678b08 2978 struct irq_desc *desc;
3460a6d9
KA		 2979
2980 cpus_and(tmp, mask, cpu_online_map);
2981 if (cpus_empty(tmp))
2982 return;
2983
2984 if (assign_irq_vector(irq, mask))
2985 return;
2986
3ac2de48 2987 cfg = irq_cfg(irq);
3460a6d9
KA		 2988 cpus_and(tmp, cfg->domain, mask);
2989 dest = cpu_mask_to_apicid(tmp);
2990
2991 dmar_msi_read(irq, &msg);
2992
2993 msg.data &= ~MSI_DATA_VECTOR_MASK;
2994 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2995 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2996 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2997
2998 dmar_msi_write(irq, &msg);
08678b08
YL		 2999 desc = irq_to_desc(irq);
3000 desc->affinity = mask;
3460a6d9
KA		 3001}
3002#endif /* CONFIG_SMP */
3003
3004struct irq_chip dmar_msi_type = {
3005 .name = "DMAR_MSI",
3006 .unmask = dmar_msi_unmask,
3007 .mask = dmar_msi_mask,
3008 .ack = ack_apic_edge,
3009#ifdef CONFIG_SMP
3010 .set_affinity = dmar_msi_set_affinity,
3011#endif
3012 .retrigger = ioapic_retrigger_irq,
3013};
3014
3015int arch_setup_dmar_msi(unsigned int irq)
3016{
3017 int ret;
3018 struct msi_msg msg;
3019
3020 ret = msi_compose_msg(NULL, irq, &msg);
3021 if (ret < 0)
3022 return ret;
3023 dmar_msi_write(irq, &msg);
3024 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3025 "edge");
3026 return 0;
3027}
3028#endif
589e367f 3029
3460a6d9 3030#endif /* CONFIG_PCI_MSI */
8b955b0d
EB		 3031/*
3032 * Hypertransport interrupt support
3033 */
3034#ifdef CONFIG_HT_IRQ
3035
3036#ifdef CONFIG_SMP
3037
3038static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3039{
ec68307c
EB		 3040 struct ht_irq_msg msg;
3041 fetch_ht_irq_msg(irq, &msg);
8b955b0d 3042
ec68307c
EB		 3043 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3044 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
8b955b0d 3045
ec68307c
EB		 3046 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3047 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
8b955b0d 3048
ec68307c 3049 write_ht_irq_msg(irq, &msg);
8b955b0d
EB		 3050}
3051
3052static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
3053{
3ac2de48 3054 struct irq_cfg *cfg;
8b955b0d
EB		 3055 unsigned int dest;
3056 cpumask_t tmp;
08678b08 3057 struct irq_desc *desc;
8b955b0d
EB		 3058
3059 cpus_and(tmp, mask, cpu_online_map);
3060 if (cpus_empty(tmp))
5ff5115e 3061 return;
8b955b0d 3062
dfbffdd8 3063 if (assign_irq_vector(irq, mask))
8b955b0d
EB		 3064 return;
3065
3ac2de48 3066 cfg = irq_cfg(irq);
dfbffdd8 3067 cpus_and(tmp, cfg->domain, mask);
8b955b0d
EB		 3068 dest = cpu_mask_to_apicid(tmp);
3069
dfbffdd8 3070 target_ht_irq(irq, dest, cfg->vector);
08678b08
YL		 3071 desc = irq_to_desc(irq);
3072 desc->affinity = mask;
8b955b0d
EB		 3073}
3074#endif
3075
c37e108d 3076static struct irq_chip ht_irq_chip = {
8b955b0d
EB		 3077 .name = "PCI-HT",
3078 .mask = mask_ht_irq,
3079 .unmask = unmask_ht_irq,
3080 .ack = ack_apic_edge,
3081#ifdef CONFIG_SMP
3082 .set_affinity = set_ht_irq_affinity,
3083#endif
3084 .retrigger = ioapic_retrigger_irq,
3085};
3086
3087int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3088{
3ac2de48 3089 struct irq_cfg *cfg;
dfbffdd8 3090 int err;
c7111c13 3091 cpumask_t tmp;
8b955b0d 3092
dfbffdd8
EB		 3093 tmp = TARGET_CPUS;
3094 err = assign_irq_vector(irq, tmp);
3095 if (!err) {
ec68307c 3096 struct ht_irq_msg msg;
8b955b0d 3097 unsigned dest;
8b955b0d 3098
3ac2de48 3099 cfg = irq_cfg(irq);
dfbffdd8 3100 cpus_and(tmp, cfg->domain, tmp);
8b955b0d
EB		 3101 dest = cpu_mask_to_apicid(tmp);
3102
ec68307c 3103 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
8b955b0d 3104
ec68307c
EB		 3105 msg.address_lo =
3106 HT_IRQ_LOW_BASE |
8b955b0d 3107 HT_IRQ_LOW_DEST_ID(dest) |
dfbffdd8 3108 HT_IRQ_LOW_VECTOR(cfg->vector) |
8b955b0d
EB		 3109 ((INT_DEST_MODE == 0) ?
3110 HT_IRQ_LOW_DM_PHYSICAL :
3111 HT_IRQ_LOW_DM_LOGICAL) |
3112 HT_IRQ_LOW_RQEOI_EDGE |
3113 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3114 HT_IRQ_LOW_MT_FIXED :
ec68307c
EB		 3115 HT_IRQ_LOW_MT_ARBITRATED) |
3116 HT_IRQ_LOW_IRQ_MASKED;
8b955b0d 3117
ec68307c 3118 write_ht_irq_msg(irq, &msg);
8b955b0d 3119
a460e745
IM		 3120 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3121 handle_edge_irq, "edge");
8b955b0d 3122 }
dfbffdd8 3123 return err;
8b955b0d
EB		 3124}
3125#endif /* CONFIG_HT_IRQ */
3126
1da177e4
LT		 3127/* --------------------------------------------------------------------------
3128 ACPI-based IOAPIC Configuration
3129 -------------------------------------------------------------------------- */
3130
888ba6c6 3131#ifdef CONFIG_ACPI
1da177e4
LT		 3132
3133#define IO_APIC_MAX_ID 0xFE
3134
1da177e4
LT		 3135int __init io_apic_get_redir_entries (int ioapic)
3136{
3137 union IO_APIC_reg_01 reg_01;
3138 unsigned long flags;
3139
3140 spin_lock_irqsave(&ioapic_lock, flags);
3141 reg_01.raw = io_apic_read(ioapic, 1);
3142 spin_unlock_irqrestore(&ioapic_lock, flags);
3143
3144 return reg_01.bits.entries;
3145}
3146
3147
50eca3eb 3148int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
1da177e4 3149{
1da177e4
LT		 3150 if (!IO_APIC_IRQ(irq)) {
3151 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3152 ioapic);
3153 return -EINVAL;
3154 }
3155
550f2299
EB		 3156 /*
3157 * IRQs < 16 are already in the irq_2_pin[] map
3158 */
3159 if (irq >= 16)
3160 add_pin_to_irq(irq, ioapic, pin);
3161
a8c8a367 3162 setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
1da177e4
LT		 3163
3164 return 0;
3165}
3166
1da177e4 3167
61fd47e0
SL		 3168int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
3169{
3170 int i;
3171
3172 if (skip_ioapic_setup)
3173 return -1;
3174
3175 for (i = 0; i < mp_irq_entries; i++)
2fddb6e2
AS		 3176 if (mp_irqs[i].mp_irqtype == mp_INT &&
3177 mp_irqs[i].mp_srcbusirq == bus_irq)
61fd47e0
SL		 3178 break;
3179 if (i >= mp_irq_entries)
3180 return -1;
3181
3182 *trigger = irq_trigger(i);
3183 *polarity = irq_polarity(i);
3184 return 0;
3185}
3186
3187#endif /* CONFIG_ACPI */
1da177e4
LT		 3188
3189/*
3190 * This function currently is only a helper for the i386 smp boot process where
3191 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3192 * so mask in all cases should simply be TARGET_CPUS
3193 */
54d5d424 3194#ifdef CONFIG_SMP
1da177e4
LT		 3195void __init setup_ioapic_dest(void)
3196{
3197 int pin, ioapic, irq, irq_entry;
3ac2de48 3198 struct irq_cfg *cfg;
1da177e4
LT		 3199
3200 if (skip_ioapic_setup == 1)
3201 return;
3202
3203 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
3204 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
3205 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
3206 if (irq_entry == -1)
3207 continue;
3208 irq = pin_2_irq(irq_entry, ioapic, pin);
ad892f5e
YL		 3209
3210 /* setup_IO_APIC_irqs could fail to get vector for some device
3211 * when you have too many devices, because at that time only boot
3212 * cpu is online.
3213 */
3ac2de48
YL		 3214 cfg = irq_cfg(irq);
3215 if (!cfg->vector)
a8c8a367
EB		 3216 setup_IO_APIC_irq(ioapic, pin, irq,
3217 irq_trigger(irq_entry),
3218 irq_polarity(irq_entry));
89027d35
SS		 3219#ifdef CONFIG_INTR_REMAP
3220 else if (intr_remapping_enabled)
3221 set_ir_ioapic_affinity_irq(irq, TARGET_CPUS);
3222#endif
ad892f5e
YL		 3223 else
3224 set_ioapic_affinity_irq(irq, TARGET_CPUS);
1da177e4
LT		 3225 }
3226
3227 }
3228}
54d5d424 3229#endif
61fd47e0 3230
3e35a0e5
TG		 3231#define IOAPIC_RESOURCE_NAME_SIZE 11
3232
3233static struct resource *ioapic_resources;
3234
3235static struct resource * __init ioapic_setup_resources(void)
3236{
3237 unsigned long n;
3238 struct resource *res;
3239 char *mem;
3240 int i;
3241
3242 if (nr_ioapics <= 0)
3243 return NULL;
3244
3245 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
3246 n *= nr_ioapics;
3247
3248 mem = alloc_bootmem(n);
3249 res = (void *)mem;
3250
3251 if (mem != NULL) {
3e35a0e5
TG		 3252 mem += sizeof(struct resource) * nr_ioapics;
3253
3254 for (i = 0; i < nr_ioapics; i++) {
3255 res[i].name = mem;
3256 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
3257 sprintf(mem, "IOAPIC %u", i);
3258 mem += IOAPIC_RESOURCE_NAME_SIZE;
3259 }
3260 }
3261
3262 ioapic_resources = res;
3263
3264 return res;
3265}
3266
3267void __init ioapic_init_mappings(void)
3268{
3269 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
3270 struct resource *ioapic_res;
3271 int i;
3272
3273 ioapic_res = ioapic_setup_resources();
3274 for (i = 0; i < nr_ioapics; i++) {
3275 if (smp_found_config) {
ec2cd0a2 3276 ioapic_phys = mp_ioapics[i].mp_apicaddr;
3e35a0e5
TG		 3277 } else {
3278 ioapic_phys = (unsigned long)
3279 alloc_bootmem_pages(PAGE_SIZE);
3280 ioapic_phys = __pa(ioapic_phys);
3281 }
3282 set_fixmap_nocache(idx, ioapic_phys);
3283 apic_printk(APIC_VERBOSE,
3284 "mapped IOAPIC to %016lx (%016lx)\n",
3285 __fix_to_virt(idx), ioapic_phys);
3286 idx++;
3287
3288 if (ioapic_res != NULL) {
3289 ioapic_res->start = ioapic_phys;
3290 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
3291 ioapic_res++;
3292 }
3293 }
3294}
3295
3296static int __init ioapic_insert_resources(void)
3297{
3298 int i;
3299 struct resource *r = ioapic_resources;
3300
3301 if (!r) {
3302 printk(KERN_ERR
3303 "IO APIC resources could be not be allocated.\n");
3304 return -1;
3305 }
3306
3307 for (i = 0; i < nr_ioapics; i++) {
3308 insert_resource(&iomem_resource, r);
3309 r++;
3310 }
3311
3312 return 0;
3313}
3314
3315/* Insert the IO APIC resources after PCI initialization has occured to handle
3316 * IO APICS that are mapped in on a BAR in PCI space. */
3317late_initcall(ioapic_insert_resources);
3318
Linux kernel - Deliverables
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