[deliverable/linux.git] / arch / x86 / kernel / ipi.c

#include <linux/cpumask.h>
#include <linux/interrupt.h>
#include <linux/init.h>

#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/spinlock.h>
#include <linux/kernel_stat.h>
#include <linux/mc146818rtc.h>
#include <linux/cache.h>
#include <linux/cpu.h>
#include <linux/module.h>

#include <asm/smp.h>
#include <asm/mtrr.h>
#include <asm/tlbflush.h>
#include <asm/mmu_context.h>
#include <asm/apic.h>
#include <asm/proto.h>

#ifdef CONFIG_X86_32
#include <mach_apic.h>
#include <mach_ipi.h>

/*
 * the following functions deal with sending IPIs between CPUs.
 *
 * We use 'broadcast', CPU->CPU IPIs and self-IPIs too.
 */

static inline int __prepare_ICR(unsigned int shortcut, int vector)
{
	unsigned int icr = shortcut | APIC_DEST_LOGICAL;

	switch (vector) {
	default:
		icr |= APIC_DM_FIXED | vector;
		break;
	case NMI_VECTOR:
		icr |= APIC_DM_NMI;
		break;
	}
	return icr;
}

static inline int __prepare_ICR2(unsigned int mask)
{
	return SET_APIC_DEST_FIELD(mask);
}

void __send_IPI_shortcut(unsigned int shortcut, int vector)
{
	/*
	 * Subtle. In the case of the 'never do double writes' workaround
	 * we have to lock out interrupts to be safe.  As we don't care
	 * of the value read we use an atomic rmw access to avoid costly
	 * cli/sti.  Otherwise we use an even cheaper single atomic write
	 * to the APIC.
	 */
	unsigned int cfg;

	/*
	 * Wait for idle.
	 */
	apic_wait_icr_idle();

	/*
	 * No need to touch the target chip field
	 */
	cfg = __prepare_ICR(shortcut, vector);

	/*
	 * Send the IPI. The write to APIC_ICR fires this off.
	 */
	apic_write(APIC_ICR, cfg);
}

void send_IPI_self(int vector)
{
	__send_IPI_shortcut(APIC_DEST_SELF, vector);
}

/*
 * This is used to send an IPI with no shorthand notation (the destination is
 * specified in bits 56 to 63 of the ICR).
 */
static inline void __send_IPI_dest_field(unsigned long mask, int vector)
{
	unsigned long cfg;

	/*
	 * Wait for idle.
	 */
	if (unlikely(vector == NMI_VECTOR))
		safe_apic_wait_icr_idle();
	else
		apic_wait_icr_idle();

	/*
	 * prepare target chip field
	 */
	cfg = __prepare_ICR2(mask);
	apic_write(APIC_ICR2, cfg);

	/*
	 * program the ICR
	 */
	cfg = __prepare_ICR(0, vector);

	/*
	 * Send the IPI. The write to APIC_ICR fires this off.
	 */
	apic_write(APIC_ICR, cfg);
}

/*
 * This is only used on smaller machines.
 */
void send_IPI_mask_bitmask(cpumask_t cpumask, int vector)
{
	unsigned long mask = cpus_addr(cpumask)[0];
	unsigned long flags;

	local_irq_save(flags);
	WARN_ON(mask & ~cpus_addr(cpu_online_map)[0]);
	__send_IPI_dest_field(mask, vector);
	local_irq_restore(flags);
}

void send_IPI_mask_sequence(cpumask_t mask, int vector)
{
	unsigned long flags;
	unsigned int query_cpu;

	/*
	 * Hack. The clustered APIC addressing mode doesn't allow us to send
	 * to an arbitrary mask, so I do a unicasts to each CPU instead. This
	 * should be modified to do 1 message per cluster ID - mbligh
	 */

	local_irq_save(flags);
	for_each_possible_cpu(query_cpu) {
		if (cpu_isset(query_cpu, mask)) {
			__send_IPI_dest_field(cpu_to_logical_apicid(query_cpu),
					      vector);
		}
	}
	local_irq_restore(flags);
}

/* must come after the send_IPI functions above for inlining */
static int convert_apicid_to_cpu(int apic_id)
{
	int i;

	for_each_possible_cpu(i) {
		if (per_cpu(x86_cpu_to_apicid, i) == apic_id)
			return i;
	}
	return -1;
}

int safe_smp_processor_id(void)
{
	int apicid, cpuid;

	if (!boot_cpu_has(X86_FEATURE_APIC))
		return 0;

	apicid = hard_smp_processor_id();
	if (apicid == BAD_APICID)
		return 0;

	cpuid = convert_apicid_to_cpu(apicid);

	return cpuid >= 0 ? cpuid : 0;
}
#endif
Commit	Line	Data
82023503 GC	1	#include <linux/cpumask.h>
	2	#include <linux/interrupt.h>
	3	#include <linux/init.h>
	4
	5	#include <linux/mm.h>
	6	#include <linux/delay.h>
	7	#include <linux/spinlock.h>
	8	#include <linux/kernel_stat.h>
	9	#include <linux/mc146818rtc.h>
	10	#include <linux/cache.h>
82023503 GC	11	#include <linux/cpu.h>
	12	#include <linux/module.h>
	13
	14	#include <asm/smp.h>
	15	#include <asm/mtrr.h>
	16	#include <asm/tlbflush.h>
	17	#include <asm/mmu_context.h>
	18	#include <asm/apic.h>
	19	#include <asm/proto.h>
	20
	21	#ifdef CONFIG_X86_32
	22	#include <mach_apic.h>
2907829c JS	23	#include <mach_ipi.h>
2907829c JS	24
82023503 GC	25	/*
	26	* the following functions deal with sending IPIs between CPUs.
	27	*
	28	* We use 'broadcast', CPU->CPU IPIs and self-IPIs too.
	29	*/
	30
	31	static inline int __prepare_ICR(unsigned int shortcut, int vector)
	32	{
	33	unsigned int icr = shortcut \| APIC_DEST_LOGICAL;
	34
	35	switch (vector) {
	36	default:
	37	icr \|= APIC_DM_FIXED \| vector;
	38	break;
	39	case NMI_VECTOR:
	40	icr \|= APIC_DM_NMI;
	41	break;
	42	}
	43	return icr;
	44	}
	45
	46	static inline int __prepare_ICR2(unsigned int mask)
	47	{
	48	return SET_APIC_DEST_FIELD(mask);
	49	}
	50
	51	void __send_IPI_shortcut(unsigned int shortcut, int vector)
	52	{
	53	/*
	54	* Subtle. In the case of the 'never do double writes' workaround
	55	* we have to lock out interrupts to be safe. As we don't care
	56	* of the value read we use an atomic rmw access to avoid costly
	57	* cli/sti. Otherwise we use an even cheaper single atomic write
	58	* to the APIC.
	59	*/
	60	unsigned int cfg;
	61
	62	/*
	63	* Wait for idle.
	64	*/
	65	apic_wait_icr_idle();
	66
	67	/*
	68	* No need to touch the target chip field
	69	*/
	70	cfg = __prepare_ICR(shortcut, vector);
	71
	72	/*
	73	* Send the IPI. The write to APIC_ICR fires this off.
	74	*/
593f4a78	75	apic_write(APIC_ICR, cfg);
82023503 GC	76	}
	77
	78	void send_IPI_self(int vector)
	79	{
	80	__send_IPI_shortcut(APIC_DEST_SELF, vector);
	81	}
	82
	83	/*
	84	* This is used to send an IPI with no shorthand notation (the destination is
	85	* specified in bits 56 to 63 of the ICR).
	86	*/
	87	static inline void __send_IPI_dest_field(unsigned long mask, int vector)
	88	{
	89	unsigned long cfg;
	90
	91	/*
	92	* Wait for idle.
	93	*/
	94	if (unlikely(vector == NMI_VECTOR))
	95	safe_apic_wait_icr_idle();
	96	else
	97	apic_wait_icr_idle();
	98
	99	/*
	100	* prepare target chip field
	101	*/
	102	cfg = __prepare_ICR2(mask);
593f4a78	103	apic_write(APIC_ICR2, cfg);
82023503 GC	104
	105	/*
	106	* program the ICR
	107	*/
	108	cfg = __prepare_ICR(0, vector);
	109
	110	/*
	111	* Send the IPI. The write to APIC_ICR fires this off.
	112	*/
593f4a78	113	apic_write(APIC_ICR, cfg);
82023503 GC	114	}
	115
	116	/*
	117	* This is only used on smaller machines.
	118	*/
	119	void send_IPI_mask_bitmask(cpumask_t cpumask, int vector)
	120	{
	121	unsigned long mask = cpus_addr(cpumask)[0];
	122	unsigned long flags;
	123
	124	local_irq_save(flags);
	125	WARN_ON(mask & ~cpus_addr(cpu_online_map)[0]);
	126	__send_IPI_dest_field(mask, vector);
	127	local_irq_restore(flags);
	128	}
	129
	130	void send_IPI_mask_sequence(cpumask_t mask, int vector)
	131	{
	132	unsigned long flags;
	133	unsigned int query_cpu;
	134
	135	/*
	136	* Hack. The clustered APIC addressing mode doesn't allow us to send
	137	* to an arbitrary mask, so I do a unicasts to each CPU instead. This
	138	* should be modified to do 1 message per cluster ID - mbligh
	139	*/
	140
	141	local_irq_save(flags);
	142	for_each_possible_cpu(query_cpu) {
	143	if (cpu_isset(query_cpu, mask)) {
	144	__send_IPI_dest_field(cpu_to_logical_apicid(query_cpu),
	145	vector);
	146	}
	147	}
	148	local_irq_restore(flags);
	149	}
	150
	151	/* must come after the send_IPI functions above for inlining */
82023503 GC	152	static int convert_apicid_to_cpu(int apic_id)
	153	{
	154	int i;
	155
	156	for_each_possible_cpu(i) {
	157	if (per_cpu(x86_cpu_to_apicid, i) == apic_id)
	158	return i;
	159	}
	160	return -1;
	161	}
	162
	163	int safe_smp_processor_id(void)
	164	{
	165	int apicid, cpuid;
	166
	167	if (!boot_cpu_has(X86_FEATURE_APIC))
	168	return 0;
	169
	170	apicid = hard_smp_processor_id();
	171	if (apicid == BAD_APICID)
	172	return 0;
	173
	174	cpuid = convert_apicid_to_cpu(apicid);
	175
	176	return cpuid >= 0 ? cpuid : 0;
	177	}
	178	#endif