[deliverable/linux.git] / arch / x86 / kernel / irq_32.c

/*
 *	Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar
 *
 * This file contains the lowest level x86-specific interrupt
 * entry, irq-stacks and irq statistics code. All the remaining
 * irq logic is done by the generic kernel/irq/ code and
 * by the x86-specific irq controller code. (e.g. i8259.c and
 * io_apic.c.)
 */

#include <linux/module.h>
#include <linux/seq_file.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <linux/notifier.h>
#include <linux/cpu.h>
#include <linux/delay.h>

#include <asm/apic.h>
#include <asm/uaccess.h>

DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
EXPORT_PER_CPU_SYMBOL(irq_stat);

DEFINE_PER_CPU(struct pt_regs *, irq_regs);
EXPORT_PER_CPU_SYMBOL(irq_regs);

/*
 * 'what should we do if we get a hw irq event on an illegal vector'.
 * each architecture has to answer this themselves.
 */
void ack_bad_irq(unsigned int irq)
{
	printk(KERN_ERR "unexpected IRQ trap at vector %02x\n", irq);

#ifdef CONFIG_X86_LOCAL_APIC
	/*
	 * Currently unexpected vectors happen only on SMP and APIC.
	 * We _must_ ack these because every local APIC has only N
	 * irq slots per priority level, and a 'hanging, unacked' IRQ
	 * holds up an irq slot - in excessive cases (when multiple
	 * unexpected vectors occur) that might lock up the APIC
	 * completely.
	 * But only ack when the APIC is enabled -AK
	 */
	if (cpu_has_apic)
		ack_APIC_irq();
#endif
}

#ifdef CONFIG_DEBUG_STACKOVERFLOW
/* Debugging check for stack overflow: is there less than 1KB free? */
static int check_stack_overflow(void)
{
	long sp;

	__asm__ __volatile__("andl %%esp,%0" :
			     "=r" (sp) : "0" (THREAD_SIZE - 1));

	return sp < (sizeof(struct thread_info) + STACK_WARN);
}

static void print_stack_overflow(void)
{
	printk(KERN_WARNING "low stack detected by irq handler\n");
	dump_stack();
}

#else
static inline int check_stack_overflow(void) { return 0; }
static inline void print_stack_overflow(void) { }
#endif

#ifdef CONFIG_4KSTACKS
/*
 * per-CPU IRQ handling contexts (thread information and stack)
 */
union irq_ctx {
	struct thread_info      tinfo;
	u32                     stack[THREAD_SIZE/sizeof(u32)];
};

static union irq_ctx *hardirq_ctx[NR_CPUS] __read_mostly;
static union irq_ctx *softirq_ctx[NR_CPUS] __read_mostly;

static char softirq_stack[NR_CPUS * THREAD_SIZE] __page_aligned_bss;
static char hardirq_stack[NR_CPUS * THREAD_SIZE] __page_aligned_bss;

static void call_on_stack(void *func, void *stack)
{
	asm volatile("xchgl	%%ebx,%%esp	\n"
		     "call	*%%edi		\n"
		     "movl	%%ebx,%%esp	\n"
		     : "=b" (stack)
		     : "0" (stack),
		       "D"(func)
		     : "memory", "cc", "edx", "ecx", "eax");
}

static inline int
execute_on_irq_stack(int overflow, struct irq_desc *desc, int irq)
{
	union irq_ctx *curctx, *irqctx;
	u32 *isp, arg1, arg2;

	curctx = (union irq_ctx *) current_thread_info();
	irqctx = hardirq_ctx[smp_processor_id()];

	/*
	 * this is where we switch to the IRQ stack. However, if we are
	 * already using the IRQ stack (because we interrupted a hardirq
	 * handler) we can't do that and just have to keep using the
	 * current stack (which is the irq stack already after all)
	 */
	if (unlikely(curctx == irqctx))
		return 0;

	/* build the stack frame on the IRQ stack */
	isp = (u32 *) ((char*)irqctx + sizeof(*irqctx));
	irqctx->tinfo.task = curctx->tinfo.task;
	irqctx->tinfo.previous_esp = current_stack_pointer;

	/*
	 * Copy the softirq bits in preempt_count so that the
	 * softirq checks work in the hardirq context.
	 */
	irqctx->tinfo.preempt_count =
		(irqctx->tinfo.preempt_count & ~SOFTIRQ_MASK) |
		(curctx->tinfo.preempt_count & SOFTIRQ_MASK);

	if (unlikely(overflow))
		call_on_stack(print_stack_overflow, isp);

	asm volatile("xchgl	%%ebx,%%esp	\n"
		     "call	*%%edi		\n"
		     "movl	%%ebx,%%esp	\n"
		     : "=a" (arg1), "=d" (arg2), "=b" (isp)
		     :  "0" (irq),   "1" (desc),  "2" (isp),
			"D" (desc->handle_irq)
		     : "memory", "cc", "ecx");
	return 1;
}

/*
 * allocate per-cpu stacks for hardirq and for softirq processing
 */
void __cpuinit irq_ctx_init(int cpu)
{
	union irq_ctx *irqctx;

	if (hardirq_ctx[cpu])
		return;

	irqctx = (union irq_ctx*) &hardirq_stack[cpu*THREAD_SIZE];
	irqctx->tinfo.task		= NULL;
	irqctx->tinfo.exec_domain	= NULL;
	irqctx->tinfo.cpu		= cpu;
	irqctx->tinfo.preempt_count	= HARDIRQ_OFFSET;
	irqctx->tinfo.addr_limit	= MAKE_MM_SEG(0);

	hardirq_ctx[cpu] = irqctx;

	irqctx = (union irq_ctx*) &softirq_stack[cpu*THREAD_SIZE];
	irqctx->tinfo.task		= NULL;
	irqctx->tinfo.exec_domain	= NULL;
	irqctx->tinfo.cpu		= cpu;
	irqctx->tinfo.preempt_count	= 0;
	irqctx->tinfo.addr_limit	= MAKE_MM_SEG(0);

	softirq_ctx[cpu] = irqctx;

	printk(KERN_DEBUG "CPU %u irqstacks, hard=%p soft=%p\n",
	       cpu,hardirq_ctx[cpu],softirq_ctx[cpu]);
}

void irq_ctx_exit(int cpu)
{
	hardirq_ctx[cpu] = NULL;
}

asmlinkage void do_softirq(void)
{
	unsigned long flags;
	struct thread_info *curctx;
	union irq_ctx *irqctx;
	u32 *isp;

	if (in_interrupt())
		return;

	local_irq_save(flags);

	if (local_softirq_pending()) {
		curctx = current_thread_info();
		irqctx = softirq_ctx[smp_processor_id()];
		irqctx->tinfo.task = curctx->task;
		irqctx->tinfo.previous_esp = current_stack_pointer;

		/* build the stack frame on the softirq stack */
		isp = (u32*) ((char*)irqctx + sizeof(*irqctx));

		call_on_stack(__do_softirq, isp);
		/*
		 * Shouldnt happen, we returned above if in_interrupt():
		 */
		WARN_ON_ONCE(softirq_count());
	}

	local_irq_restore(flags);
}

#else
static inline int
execute_on_irq_stack(int overflow, struct irq_desc *desc, int irq) { return 0; }
#endif

/*
 * do_IRQ handles all normal device IRQ's (the special
 * SMP cross-CPU interrupts have their own specific
 * handlers).
 */
unsigned int do_IRQ(struct pt_regs *regs)
{
	struct pt_regs *old_regs;
	/* high bit used in ret_from_ code */
	int overflow, irq = ~regs->orig_ax;
	struct irq_desc *desc = irq_to_desc(irq);

	if (unlikely((unsigned)irq >= nr_irqs)) {
		printk(KERN_EMERG "%s: cannot handle IRQ %d\n",
					__func__, irq);
		BUG();
	}

	old_regs = set_irq_regs(regs);
	irq_enter();

	overflow = check_stack_overflow();

	if (!execute_on_irq_stack(overflow, desc, irq)) {
		if (unlikely(overflow))
			print_stack_overflow();
		desc->handle_irq(irq, desc);
	}

	irq_exit();
	set_irq_regs(old_regs);
	return 1;
}

/*
 * Interrupt statistics:
 */

atomic_t irq_err_count;

/*
 * /proc/interrupts printing:
 */

int show_interrupts(struct seq_file *p, void *v)
{
	int i = *(loff_t *) v, j;
	struct irqaction * action;
	unsigned long flags;

	if (i == 0) {
		seq_printf(p, "           ");
		for_each_online_cpu(j)
			seq_printf(p, "CPU%-8d",j);
		seq_putc(p, '\n');
	}

	if (i < nr_irqs) {
		unsigned any_count = 0;
		struct irq_desc *desc = irq_to_desc(i);

		spin_lock_irqsave(&desc->lock, flags);
#ifndef CONFIG_SMP
		any_count = kstat_irqs(i);
#else
		for_each_online_cpu(j)
			any_count |= kstat_irqs_cpu(i, j);
#endif
		action = desc->action;
		if (!action && !any_count)
			goto skip;
		seq_printf(p, "%3d: ",i);
#ifndef CONFIG_SMP
		seq_printf(p, "%10u ", kstat_irqs(i));
#else
		for_each_online_cpu(j)
			seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
#endif
		seq_printf(p, " %8s", desc->chip->name);
		seq_printf(p, "-%-8s", desc->name);

		if (action) {
			seq_printf(p, "  %s", action->name);
			while ((action = action->next) != NULL)
				seq_printf(p, ", %s", action->name);
		}

		seq_putc(p, '\n');
skip:
		spin_unlock_irqrestore(&desc->lock, flags);
	} else if (i == nr_irqs) {
		seq_printf(p, "NMI: ");
		for_each_online_cpu(j)
			seq_printf(p, "%10u ", nmi_count(j));
		seq_printf(p, "  Non-maskable interrupts\n");
#ifdef CONFIG_X86_LOCAL_APIC
		seq_printf(p, "LOC: ");
		for_each_online_cpu(j)
			seq_printf(p, "%10u ",
				per_cpu(irq_stat,j).apic_timer_irqs);
		seq_printf(p, "  Local timer interrupts\n");
#endif
#ifdef CONFIG_SMP
		seq_printf(p, "RES: ");
		for_each_online_cpu(j)
			seq_printf(p, "%10u ",
				per_cpu(irq_stat,j).irq_resched_count);
		seq_printf(p, "  Rescheduling interrupts\n");
		seq_printf(p, "CAL: ");
		for_each_online_cpu(j)
			seq_printf(p, "%10u ",
				per_cpu(irq_stat,j).irq_call_count);
		seq_printf(p, "  Function call interrupts\n");
		seq_printf(p, "TLB: ");
		for_each_online_cpu(j)
			seq_printf(p, "%10u ",
				per_cpu(irq_stat,j).irq_tlb_count);
		seq_printf(p, "  TLB shootdowns\n");
#endif
#ifdef CONFIG_X86_MCE
		seq_printf(p, "TRM: ");
		for_each_online_cpu(j)
			seq_printf(p, "%10u ",
				per_cpu(irq_stat,j).irq_thermal_count);
		seq_printf(p, "  Thermal event interrupts\n");
#endif
#ifdef CONFIG_X86_LOCAL_APIC
		seq_printf(p, "SPU: ");
		for_each_online_cpu(j)
			seq_printf(p, "%10u ",
				per_cpu(irq_stat,j).irq_spurious_count);
		seq_printf(p, "  Spurious interrupts\n");
#endif
		seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
#if defined(CONFIG_X86_IO_APIC)
		seq_printf(p, "MIS: %10u\n", atomic_read(&irq_mis_count));
#endif
	}
	return 0;
}

/*
 * /proc/stat helpers
 */
u64 arch_irq_stat_cpu(unsigned int cpu)
{
	u64 sum = nmi_count(cpu);

#ifdef CONFIG_X86_LOCAL_APIC
	sum += per_cpu(irq_stat, cpu).apic_timer_irqs;
#endif
#ifdef CONFIG_SMP
	sum += per_cpu(irq_stat, cpu).irq_resched_count;
	sum += per_cpu(irq_stat, cpu).irq_call_count;
	sum += per_cpu(irq_stat, cpu).irq_tlb_count;
#endif
#ifdef CONFIG_X86_MCE
	sum += per_cpu(irq_stat, cpu).irq_thermal_count;
#endif
#ifdef CONFIG_X86_LOCAL_APIC
	sum += per_cpu(irq_stat, cpu).irq_spurious_count;
#endif
	return sum;
}

u64 arch_irq_stat(void)
{
	u64 sum = atomic_read(&irq_err_count);

#ifdef CONFIG_X86_IO_APIC
	sum += atomic_read(&irq_mis_count);
#endif
	return sum;
}

#ifdef CONFIG_HOTPLUG_CPU
#include <mach_apic.h>

void fixup_irqs(cpumask_t map)
{
	unsigned int irq;
	static int warned;

	for (irq = 0; irq < nr_irqs; irq++) {
		cpumask_t mask;
		struct irq_desc *desc;

		if (irq == 2)
			continue;

		desc = irq_to_desc(irq);
		cpus_and(mask, desc->affinity, map);
		if (any_online_cpu(mask) == NR_CPUS) {
			printk("Breaking affinity for irq %i\n", irq);
			mask = map;
		}
		if (desc->chip->set_affinity)
			desc->chip->set_affinity(irq, mask);
		else if (desc->action && !(warned++))
			printk("Cannot set affinity for irq %i\n", irq);
	}

#if 0
	barrier();
	/* Ingo Molnar says: "after the IO-APIC masks have been redirected
	   [note the nop - the interrupt-enable boundary on x86 is two
	   instructions from sti] - to flush out pending hardirqs and
	   IPIs. After this point nothing is supposed to reach this CPU." */
	__asm__ __volatile__("sti; nop; cli");
	barrier();
#else
	/* That doesn't seem sufficient.  Give it 1ms. */
	local_irq_enable();
	mdelay(1);
	local_irq_disable();
#endif
}
#endif
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar
	3	*
	4	* This file contains the lowest level x86-specific interrupt
	5	* entry, irq-stacks and irq statistics code. All the remaining
	6	* irq logic is done by the generic kernel/irq/ code and
	7	* by the x86-specific irq controller code. (e.g. i8259.c and
	8	* io_apic.c.)
	9	*/
	10
1da177e4 LT	11	#include <linux/module.h>
	12	#include <linux/seq_file.h>
	13	#include <linux/interrupt.h>
	14	#include <linux/kernel_stat.h>
f3705136 ZM	15	#include <linux/notifier.h>
	16	#include <linux/cpu.h>
	17	#include <linux/delay.h>
1da177e4	18
e05d723f TG	19	#include <asm/apic.h>
	20	#include <asm/uaccess.h>
	21
f34e3b61	22	DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
1da177e4 LT	23	EXPORT_PER_CPU_SYMBOL(irq_stat);
1da177e4 LT	24
7c3576d2 JF	25	DEFINE_PER_CPU(struct pt_regs *, irq_regs);
	26	EXPORT_PER_CPU_SYMBOL(irq_regs);
	27
1da177e4 LT	28	/*
	29	* 'what should we do if we get a hw irq event on an illegal vector'.
	30	* each architecture has to answer this themselves.
	31	*/
	32	void ack_bad_irq(unsigned int irq)
	33	{
e05d723f TG	34	printk(KERN_ERR "unexpected IRQ trap at vector %02x\n", irq);
	35
	36	#ifdef CONFIG_X86_LOCAL_APIC
	37	/*
	38	* Currently unexpected vectors happen only on SMP and APIC.
	39	* We _must_ ack these because every local APIC has only N
	40	* irq slots per priority level, and a 'hanging, unacked' IRQ
	41	* holds up an irq slot - in excessive cases (when multiple
	42	* unexpected vectors occur) that might lock up the APIC
	43	* completely.
	44	* But only ack when the APIC is enabled -AK
	45	*/
	46	if (cpu_has_apic)
	47	ack_APIC_irq();
1da177e4	48	#endif
e05d723f	49	}
1da177e4	50
de9b10af TG	51	#ifdef CONFIG_DEBUG_STACKOVERFLOW
	52	/* Debugging check for stack overflow: is there less than 1KB free? */
	53	static int check_stack_overflow(void)
	54	{
	55	long sp;
	56
	57	__asm__ __volatile__("andl %%esp,%0" :
	58	"=r" (sp) : "0" (THREAD_SIZE - 1));
	59
	60	return sp < (sizeof(struct thread_info) + STACK_WARN);
	61	}
	62
	63	static void print_stack_overflow(void)
	64	{
	65	printk(KERN_WARNING "low stack detected by irq handler\n");
	66	dump_stack();
	67	}
	68
	69	#else
	70	static inline int check_stack_overflow(void) { return 0; }
	71	static inline void print_stack_overflow(void) { }
	72	#endif
	73
1da177e4 LT	74	#ifdef CONFIG_4KSTACKS
	75	/*
	76	* per-CPU IRQ handling contexts (thread information and stack)
	77	*/
	78	union irq_ctx {
	79	struct thread_info tinfo;
	80	u32 stack[THREAD_SIZE/sizeof(u32)];
	81	};
	82
22722051 AM	83	static union irq_ctx *hardirq_ctx[NR_CPUS] __read_mostly;
22722051 AM	84	static union irq_ctx *softirq_ctx[NR_CPUS] __read_mostly;
1da177e4	85
cbcd79c2 JF	86	static char softirq_stack[NR_CPUS * THREAD_SIZE] __page_aligned_bss;
cbcd79c2 JF	87	static char hardirq_stack[NR_CPUS * THREAD_SIZE] __page_aligned_bss;
a052b68b	88
403d8efc	89	static void call_on_stack(void func, void stack)
04b361ab	90	{
403d8efc TG	91	asm volatile("xchgl %%ebx,%%esp \n"
	92	"call *%%edi \n"
	93	"movl %%ebx,%%esp \n"
	94	: "=b" (stack)
	95	: "0" (stack),
	96	"D"(func)
	97	: "memory", "cc", "edx", "ecx", "eax");
04b361ab	98	}
1da177e4	99
de9b10af TG	100	static inline int
	101	execute_on_irq_stack(int overflow, struct irq_desc *desc, int irq)
	102	{
	103	union irq_ctx curctx, irqctx;
403d8efc	104	u32 *isp, arg1, arg2;
1da177e4 LT	105
	106	curctx = (union irq_ctx *) current_thread_info();
	107	irqctx = hardirq_ctx[smp_processor_id()];
	108
	109	/*
	110	* this is where we switch to the IRQ stack. However, if we are
	111	* already using the IRQ stack (because we interrupted a hardirq
	112	* handler) we can't do that and just have to keep using the
	113	* current stack (which is the irq stack already after all)
	114	*/
de9b10af TG	115	if (unlikely(curctx == irqctx))
de9b10af TG	116	return 0;
1da177e4	117
de9b10af TG	118	/* build the stack frame on the IRQ stack */
	119	isp = (u32 ) ((char)irqctx + sizeof(*irqctx));
	120	irqctx->tinfo.task = curctx->tinfo.task;
	121	irqctx->tinfo.previous_esp = current_stack_pointer;
1da177e4	122
de9b10af TG	123	/*
	124	* Copy the softirq bits in preempt_count so that the
	125	* softirq checks work in the hardirq context.
	126	*/
	127	irqctx->tinfo.preempt_count =
	128	(irqctx->tinfo.preempt_count & ~SOFTIRQ_MASK) \|
	129	(curctx->tinfo.preempt_count & SOFTIRQ_MASK);
	130
	131	if (unlikely(overflow))
403d8efc TG	132	call_on_stack(print_stack_overflow, isp);
	133
	134	asm volatile("xchgl %%ebx,%%esp \n"
	135	"call *%%edi \n"
	136	"movl %%ebx,%%esp \n"
	137	: "=a" (arg1), "=d" (arg2), "=b" (isp)
	138	: "0" (irq), "1" (desc), "2" (isp),
	139	"D" (desc->handle_irq)
	140	: "memory", "cc", "ecx");
1da177e4 LT	141	return 1;
	142	}
	143
1da177e4 LT	144	/*
	145	* allocate per-cpu stacks for hardirq and for softirq processing
	146	*/
403d8efc	147	void __cpuinit irq_ctx_init(int cpu)
1da177e4 LT	148	{
	149	union irq_ctx *irqctx;
	150
	151	if (hardirq_ctx[cpu])
	152	return;
	153
	154	irqctx = (union irq_ctx) &hardirq_stack[cpuTHREAD_SIZE];
403d8efc TG	155	irqctx->tinfo.task = NULL;
	156	irqctx->tinfo.exec_domain = NULL;
	157	irqctx->tinfo.cpu = cpu;
	158	irqctx->tinfo.preempt_count = HARDIRQ_OFFSET;
	159	irqctx->tinfo.addr_limit = MAKE_MM_SEG(0);
1da177e4 LT	160
	161	hardirq_ctx[cpu] = irqctx;
	162
	163	irqctx = (union irq_ctx) &softirq_stack[cpuTHREAD_SIZE];
403d8efc TG	164	irqctx->tinfo.task = NULL;
	165	irqctx->tinfo.exec_domain = NULL;
	166	irqctx->tinfo.cpu = cpu;
	167	irqctx->tinfo.preempt_count = 0;
	168	irqctx->tinfo.addr_limit = MAKE_MM_SEG(0);
1da177e4 LT	169
	170	softirq_ctx[cpu] = irqctx;
	171
403d8efc TG	172	printk(KERN_DEBUG "CPU %u irqstacks, hard=%p soft=%p\n",
403d8efc TG	173	cpu,hardirq_ctx[cpu],softirq_ctx[cpu]);
1da177e4 LT	174	}
1da177e4 LT	175
e1367daf LS	176	void irq_ctx_exit(int cpu)
	177	{
	178	hardirq_ctx[cpu] = NULL;
	179	}
	180
1da177e4 LT	181	asmlinkage void do_softirq(void)
	182	{
	183	unsigned long flags;
	184	struct thread_info *curctx;
	185	union irq_ctx *irqctx;
	186	u32 *isp;
	187
	188	if (in_interrupt())
	189	return;
	190
	191	local_irq_save(flags);
	192
	193	if (local_softirq_pending()) {
	194	curctx = current_thread_info();
	195	irqctx = softirq_ctx[smp_processor_id()];
	196	irqctx->tinfo.task = curctx->task;
	197	irqctx->tinfo.previous_esp = current_stack_pointer;
	198
	199	/* build the stack frame on the softirq stack */
	200	isp = (u32) ((char)irqctx + sizeof(*irqctx));
	201
403d8efc	202	call_on_stack(__do_softirq, isp);
55f327fa IM	203	/*
55f327fa IM	204	* Shouldnt happen, we returned above if in_interrupt():
403d8efc	205	*/
55f327fa	206	WARN_ON_ONCE(softirq_count());
1da177e4 LT	207	}
	208
	209	local_irq_restore(flags);
	210	}
403d8efc TG	211
	212	#else
	213	static inline int
	214	execute_on_irq_stack(int overflow, struct irq_desc *desc, int irq) { return 0; }
1da177e4 LT	215	#endif
1da177e4 LT	216
403d8efc TG	217	/*
	218	* do_IRQ handles all normal device IRQ's (the special
	219	* SMP cross-CPU interrupts have their own specific
	220	* handlers).
	221	*/
	222	unsigned int do_IRQ(struct pt_regs *regs)
	223	{
	224	struct pt_regs *old_regs;
	225	/* high bit used in ret_from_ code */
	226	int overflow, irq = ~regs->orig_ax;
08678b08	227	struct irq_desc *desc = irq_to_desc(irq);
403d8efc	228
0799e432	229	if (unlikely((unsigned)irq >= nr_irqs)) {
403d8efc TG	230	printk(KERN_EMERG "%s: cannot handle IRQ %d\n",
	231	__func__, irq);
	232	BUG();
	233	}
	234
	235	old_regs = set_irq_regs(regs);
	236	irq_enter();
	237
	238	overflow = check_stack_overflow();
	239
	240	if (!execute_on_irq_stack(overflow, desc, irq)) {
	241	if (unlikely(overflow))
	242	print_stack_overflow();
	243	desc->handle_irq(irq, desc);
	244	}
	245
	246	irq_exit();
	247	set_irq_regs(old_regs);
	248	return 1;
	249	}
	250
1da177e4 LT	251	/*
	252	* Interrupt statistics:
	253	*/
	254
	255	atomic_t irq_err_count;
	256
	257	/*
	258	* /proc/interrupts printing:
	259	*/
	260
	261	int show_interrupts(struct seq_file p, void v)
	262	{
	263	int i = (loff_t ) v, j;
	264	struct irqaction * action;
	265	unsigned long flags;
	266
	267	if (i == 0) {
	268	seq_printf(p, " ");
9f40a72a	269	for_each_online_cpu(j)
bdbdaa79	270	seq_printf(p, "CPU%-8d",j);
1da177e4 LT	271	seq_putc(p, '\n');
	272	}
	273
0799e432	274	if (i < nr_irqs) {
072f5d82	275	unsigned any_count = 0;
08678b08	276	struct irq_desc *desc = irq_to_desc(i);
072f5d82	277
08678b08	278	spin_lock_irqsave(&desc->lock, flags);
072f5d82 JB	279	#ifndef CONFIG_SMP
	280	any_count = kstat_irqs(i);
	281	#else
	282	for_each_online_cpu(j)
7f95ec9e	283	any_count \|= kstat_irqs_cpu(i, j);
072f5d82	284	#endif
08678b08	285	action = desc->action;
072f5d82	286	if (!action && !any_count)
1da177e4 LT	287	goto skip;
	288	seq_printf(p, "%3d: ",i);
	289	#ifndef CONFIG_SMP
	290	seq_printf(p, "%10u ", kstat_irqs(i));
	291	#else
9f40a72a	292	for_each_online_cpu(j)
7f95ec9e	293	seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
1da177e4	294	#endif
08678b08 YL	295	seq_printf(p, " %8s", desc->chip->name);
08678b08 YL	296	seq_printf(p, "-%-8s", desc->name);
1da177e4	297
072f5d82 JB	298	if (action) {
	299	seq_printf(p, " %s", action->name);
	300	while ((action = action->next) != NULL)
	301	seq_printf(p, ", %s", action->name);
	302	}
1da177e4 LT	303
	304	seq_putc(p, '\n');
	305	skip:
08678b08	306	spin_unlock_irqrestore(&desc->lock, flags);
0799e432	307	} else if (i == nr_irqs) {
1da177e4	308	seq_printf(p, "NMI: ");
9f40a72a	309	for_each_online_cpu(j)
f3705136	310	seq_printf(p, "%10u ", nmi_count(j));
38e760a1	311	seq_printf(p, " Non-maskable interrupts\n");
1da177e4 LT	312	#ifdef CONFIG_X86_LOCAL_APIC
1da177e4 LT	313	seq_printf(p, "LOC: ");
9f40a72a	314	for_each_online_cpu(j)
f3705136 ZM	315	seq_printf(p, "%10u ",
f3705136 ZM	316	per_cpu(irq_stat,j).apic_timer_irqs);
38e760a1	317	seq_printf(p, " Local timer interrupts\n");
1da177e4	318	#endif
38e760a1 JK	319	#ifdef CONFIG_SMP
	320	seq_printf(p, "RES: ");
	321	for_each_online_cpu(j)
	322	seq_printf(p, "%10u ",
	323	per_cpu(irq_stat,j).irq_resched_count);
	324	seq_printf(p, " Rescheduling interrupts\n");
	325	seq_printf(p, "CAL: ");
	326	for_each_online_cpu(j)
	327	seq_printf(p, "%10u ",
	328	per_cpu(irq_stat,j).irq_call_count);
dc44e659	329	seq_printf(p, " Function call interrupts\n");
38e760a1 JK	330	seq_printf(p, "TLB: ");
	331	for_each_online_cpu(j)
	332	seq_printf(p, "%10u ",
	333	per_cpu(irq_stat,j).irq_tlb_count);
	334	seq_printf(p, " TLB shootdowns\n");
	335	#endif
a2eddfa9	336	#ifdef CONFIG_X86_MCE
38e760a1 JK	337	seq_printf(p, "TRM: ");
	338	for_each_online_cpu(j)
	339	seq_printf(p, "%10u ",
	340	per_cpu(irq_stat,j).irq_thermal_count);
	341	seq_printf(p, " Thermal event interrupts\n");
a2eddfa9 JB	342	#endif
a2eddfa9 JB	343	#ifdef CONFIG_X86_LOCAL_APIC
38e760a1 JK	344	seq_printf(p, "SPU: ");
	345	for_each_online_cpu(j)
	346	seq_printf(p, "%10u ",
	347	per_cpu(irq_stat,j).irq_spurious_count);
	348	seq_printf(p, " Spurious interrupts\n");
a2eddfa9	349	#endif
1da177e4 LT	350	seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
	351	#if defined(CONFIG_X86_IO_APIC)
	352	seq_printf(p, "MIS: %10u\n", atomic_read(&irq_mis_count));
	353	#endif
	354	}
	355	return 0;
	356	}
f3705136	357
a2eddfa9 JB	358	/*
	359	* /proc/stat helpers
	360	*/
	361	u64 arch_irq_stat_cpu(unsigned int cpu)
	362	{
	363	u64 sum = nmi_count(cpu);
	364
	365	#ifdef CONFIG_X86_LOCAL_APIC
	366	sum += per_cpu(irq_stat, cpu).apic_timer_irqs;
	367	#endif
	368	#ifdef CONFIG_SMP
	369	sum += per_cpu(irq_stat, cpu).irq_resched_count;
	370	sum += per_cpu(irq_stat, cpu).irq_call_count;
	371	sum += per_cpu(irq_stat, cpu).irq_tlb_count;
	372	#endif
	373	#ifdef CONFIG_X86_MCE
	374	sum += per_cpu(irq_stat, cpu).irq_thermal_count;
	375	#endif
	376	#ifdef CONFIG_X86_LOCAL_APIC
	377	sum += per_cpu(irq_stat, cpu).irq_spurious_count;
	378	#endif
	379	return sum;
	380	}
	381
	382	u64 arch_irq_stat(void)
	383	{
	384	u64 sum = atomic_read(&irq_err_count);
	385
	386	#ifdef CONFIG_X86_IO_APIC
	387	sum += atomic_read(&irq_mis_count);
	388	#endif
	389	return sum;
	390	}
	391
f3705136 ZM	392	#ifdef CONFIG_HOTPLUG_CPU
	393	#include <mach_apic.h>
	394
	395	void fixup_irqs(cpumask_t map)
	396	{
	397	unsigned int irq;
	398	static int warned;
	399
0799e432	400	for (irq = 0; irq < nr_irqs; irq++) {
f3705136	401	cpumask_t mask;
08678b08 YL	402	struct irq_desc *desc;
08678b08 YL	403
f3705136 ZM	404	if (irq == 2)
	405	continue;
	406
08678b08 YL	407	desc = irq_to_desc(irq);
08678b08 YL	408	cpus_and(mask, desc->affinity, map);
f3705136 ZM	409	if (any_online_cpu(mask) == NR_CPUS) {
	410	printk("Breaking affinity for irq %i\n", irq);
	411	mask = map;
	412	}
08678b08 YL	413	if (desc->chip->set_affinity)
	414	desc->chip->set_affinity(irq, mask);
	415	else if (desc->action && !(warned++))
f3705136 ZM	416	printk("Cannot set affinity for irq %i\n", irq);
	417	}
	418
	419	#if 0
	420	barrier();
	421	/* Ingo Molnar says: "after the IO-APIC masks have been redirected
	422	[note the nop - the interrupt-enable boundary on x86 is two
	423	instructions from sti] - to flush out pending hardirqs and
	424	IPIs. After this point nothing is supposed to reach this CPU." */
	425	__asm__ __volatile__("sti; nop; cli");
	426	barrier();
	427	#else
	428	/* That doesn't seem sufficient. Give it 1ms. */
	429	local_irq_enable();
	430	mdelay(1);
	431	local_irq_disable();
	432	#endif
	433	}
	434	#endif
	435