[deliverable/linux.git] / arch / x86 / kernel / irq_64.c

/*
 *	Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar
 *
 * This file contains the lowest level x86_64-specific interrupt
 * entry and irq statistics code. All the remaining irq logic is
 * done by the generic kernel/irq/ code and in the
 * x86_64-specific irq controller code. (e.g. i8259.c and
 * io_apic.c.)
 */

#include <linux/kernel_stat.h>
#include <linux/interrupt.h>
#include <linux/seq_file.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <asm/uaccess.h>
#include <asm/io_apic.h>
#include <asm/idle.h>
#include <asm/smp.h>

atomic_t irq_err_count;

/*
 * 'what should we do if we get a hw irq event on an illegal vector'.
 * each architecture has to answer this themselves.
 */
void ack_bad_irq(unsigned int irq)
{
	printk(KERN_WARNING "unexpected IRQ trap at vector %02x\n", irq);
	/*
	 * Currently unexpected vectors happen only on SMP and APIC.
	 * We _must_ ack these because every local APIC has only N
	 * irq slots per priority level, and a 'hanging, unacked' IRQ
	 * holds up an irq slot - in excessive cases (when multiple
	 * unexpected vectors occur) that might lock up the APIC
	 * completely.
	 * But don't ack when the APIC is disabled. -AK
	 */
	if (!disable_apic)
		ack_APIC_irq();
}

#ifdef CONFIG_DEBUG_STACKOVERFLOW
/*
 * Probabilistic stack overflow check:
 *
 * Only check the stack in process context, because everything else
 * runs on the big interrupt stacks. Checking reliably is too expensive,
 * so we just check from interrupts.
 */
static inline void stack_overflow_check(struct pt_regs *regs)
{
	u64 curbase = (u64)task_stack_page(current);
	static unsigned long warned = -60*HZ;

	if (regs->sp >= curbase && regs->sp <= curbase + THREAD_SIZE &&
	    regs->sp <  curbase + sizeof(struct thread_info) + 128 &&
	    time_after(jiffies, warned + 60*HZ)) {
		printk("do_IRQ: %s near stack overflow (cur:%Lx,sp:%lx)\n",
		       current->comm, curbase, regs->sp);
		show_stack(NULL,NULL);
		warned = jiffies;
	}
}
#endif

/*
 * Generic, controller-independent functions:
 */

int show_interrupts(struct seq_file *p, void *v)
{
	int i, j;
	struct irqaction * action;
	unsigned long flags;
	unsigned int entries;
	struct irq_desc *desc;
	int tail = 0;

#ifdef CONFIG_HAVE_SPARSE_IRQ
	desc = (struct irq_desc *)v;
	entries = -1U;
	i = desc->irq;
	if (!desc->next)
		tail = 1;
#else
	entries = nr_irqs - 1;
	i = *(loff_t *) v;
	if (i == nr_irqs)
		tail = 1;
	else
		desc = irq_to_desc(i);
#endif

	if (i == 0) {
		seq_printf(p, "           ");
		for_each_online_cpu(j)
			seq_printf(p, "CPU%-8d",j);
		seq_putc(p, '\n');
	}

	if (i <= entries) {
		unsigned any_count = 0;

		spin_lock_irqsave(&desc->lock, flags);
#ifndef CONFIG_SMP
		any_count = kstat_irqs(i);
#else
		for_each_online_cpu(j)
			any_count |= kstat_irqs_cpu(i, j);
#endif
		action = desc->action;
		if (!action && !any_count)
			goto skip;
		seq_printf(p, "%3d: ",i);
#ifndef CONFIG_SMP
		seq_printf(p, "%10u ", kstat_irqs(i));
#else
		for_each_online_cpu(j)
			seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
#endif
		seq_printf(p, " %8s", desc->chip->name);
		seq_printf(p, "-%-8s", desc->name);

		if (action) {
			seq_printf(p, "  %s", action->name);
			while ((action = action->next) != NULL)
				seq_printf(p, ", %s", action->name);
		}
		seq_putc(p, '\n');
skip:
		spin_unlock_irqrestore(&desc->lock, flags);
	}

	if (tail) {
		seq_printf(p, "NMI: ");
		for_each_online_cpu(j)
			seq_printf(p, "%10u ", cpu_pda(j)->__nmi_count);
		seq_printf(p, "  Non-maskable interrupts\n");
		seq_printf(p, "LOC: ");
		for_each_online_cpu(j)
			seq_printf(p, "%10u ", cpu_pda(j)->apic_timer_irqs);
		seq_printf(p, "  Local timer interrupts\n");
#ifdef CONFIG_SMP
		seq_printf(p, "RES: ");
		for_each_online_cpu(j)
			seq_printf(p, "%10u ", cpu_pda(j)->irq_resched_count);
		seq_printf(p, "  Rescheduling interrupts\n");
		seq_printf(p, "CAL: ");
		for_each_online_cpu(j)
			seq_printf(p, "%10u ", cpu_pda(j)->irq_call_count);
		seq_printf(p, "  Function call interrupts\n");
		seq_printf(p, "TLB: ");
		for_each_online_cpu(j)
			seq_printf(p, "%10u ", cpu_pda(j)->irq_tlb_count);
		seq_printf(p, "  TLB shootdowns\n");
#endif
#ifdef CONFIG_X86_MCE
		seq_printf(p, "TRM: ");
		for_each_online_cpu(j)
			seq_printf(p, "%10u ", cpu_pda(j)->irq_thermal_count);
		seq_printf(p, "  Thermal event interrupts\n");
		seq_printf(p, "THR: ");
		for_each_online_cpu(j)
			seq_printf(p, "%10u ", cpu_pda(j)->irq_threshold_count);
		seq_printf(p, "  Threshold APIC interrupts\n");
#endif
		seq_printf(p, "SPU: ");
		for_each_online_cpu(j)
			seq_printf(p, "%10u ", cpu_pda(j)->irq_spurious_count);
		seq_printf(p, "  Spurious interrupts\n");
		seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
	}

	return 0;
}

/*
 * /proc/stat helpers
 */
u64 arch_irq_stat_cpu(unsigned int cpu)
{
	u64 sum = cpu_pda(cpu)->__nmi_count;

	sum += cpu_pda(cpu)->apic_timer_irqs;
#ifdef CONFIG_SMP
	sum += cpu_pda(cpu)->irq_resched_count;
	sum += cpu_pda(cpu)->irq_call_count;
	sum += cpu_pda(cpu)->irq_tlb_count;
#endif
#ifdef CONFIG_X86_MCE
	sum += cpu_pda(cpu)->irq_thermal_count;
	sum += cpu_pda(cpu)->irq_threshold_count;
#endif
	sum += cpu_pda(cpu)->irq_spurious_count;
	return sum;
}

u64 arch_irq_stat(void)
{
	return atomic_read(&irq_err_count);
}

/*
 * do_IRQ handles all normal device IRQ's (the special
 * SMP cross-CPU interrupts have their own specific
 * handlers).
 */
asmlinkage unsigned int do_IRQ(struct pt_regs *regs)
{
	struct pt_regs *old_regs = set_irq_regs(regs);
	struct irq_desc *desc;

	/* high bit used in ret_from_ code  */
	unsigned vector = ~regs->orig_ax;
	unsigned irq;

	exit_idle();
	irq_enter();
	irq = __get_cpu_var(vector_irq)[vector];

#ifdef CONFIG_DEBUG_STACKOVERFLOW
	stack_overflow_check(regs);
#endif

	desc = irq_to_desc(irq);
	if (likely(desc))
		generic_handle_irq_desc(irq, desc);
	else {
		if (!disable_apic)
			ack_APIC_irq();

		if (printk_ratelimit())
			printk(KERN_EMERG "%s: %d.%d No irq handler for vector\n",
				__func__, smp_processor_id(), vector);
	}

	irq_exit();

	set_irq_regs(old_regs);
	return 1;
}

#ifdef CONFIG_HOTPLUG_CPU
void fixup_irqs(cpumask_t map)
{
	unsigned int irq;
	static int warned;
	struct irq_desc *desc;

	for_each_irq_desc(irq, desc) {
		cpumask_t mask;
		int break_affinity = 0;
		int set_affinity = 1;

		if (irq == 2)
			continue;

		/* interrupt's are disabled at this point */
		spin_lock(&desc->lock);

		if (!irq_has_action(irq) ||
		    cpus_equal(desc->affinity, map)) {
			spin_unlock(&desc->lock);
			continue;
		}

		cpus_and(mask, desc->affinity, map);
		if (cpus_empty(mask)) {
			break_affinity = 1;
			mask = map;
		}

		if (desc->chip->mask)
			desc->chip->mask(irq);

		if (desc->chip->set_affinity)
			desc->chip->set_affinity(irq, mask);
		else if (!(warned++))
			set_affinity = 0;

		if (desc->chip->unmask)
			desc->chip->unmask(irq);

		spin_unlock(&desc->lock);

		if (break_affinity && set_affinity)
			printk("Broke affinity for irq %i\n", irq);
		else if (!set_affinity)
			printk("Cannot set affinity for irq %i\n", irq);
	}

	/* That doesn't seem sufficient.  Give it 1ms. */
	local_irq_enable();
	mdelay(1);
	local_irq_disable();
}
#endif

extern void call_softirq(void);

asmlinkage void do_softirq(void)
{
 	__u32 pending;
 	unsigned long flags;

 	if (in_interrupt())
 		return;

 	local_irq_save(flags);
 	pending = local_softirq_pending();
 	/* Switch to interrupt stack */
 	if (pending) {
		call_softirq();
		WARN_ON_ONCE(softirq_count());
	}
 	local_irq_restore(flags);
}
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar
	3	*
	4	* This file contains the lowest level x86_64-specific interrupt
	5	* entry and irq statistics code. All the remaining irq logic is
	6	* done by the generic kernel/irq/ code and in the
	7	* x86_64-specific irq controller code. (e.g. i8259.c and
	8	* io_apic.c.)
	9	*/
	10
	11	#include <linux/kernel_stat.h>
	12	#include <linux/interrupt.h>
	13	#include <linux/seq_file.h>
	14	#include <linux/module.h>
76e4f660	15	#include <linux/delay.h>
1da177e4 LT	16	#include <asm/uaccess.h>
1da177e4 LT	17	#include <asm/io_apic.h>
95833c83	18	#include <asm/idle.h>
2fb12a9b	19	#include <asm/smp.h>
1da177e4 LT	20
1da177e4 LT	21	atomic_t irq_err_count;
1da177e4	22
87ebecf1 TG	23	/*
	24	* 'what should we do if we get a hw irq event on an illegal vector'.
	25	* each architecture has to answer this themselves.
	26	*/
	27	void ack_bad_irq(unsigned int irq)
	28	{
	29	printk(KERN_WARNING "unexpected IRQ trap at vector %02x\n", irq);
	30	/*
	31	* Currently unexpected vectors happen only on SMP and APIC.
	32	* We _must_ ack these because every local APIC has only N
	33	* irq slots per priority level, and a 'hanging, unacked' IRQ
	34	* holds up an irq slot - in excessive cases (when multiple
	35	* unexpected vectors occur) that might lock up the APIC
	36	* completely.
	37	* But don't ack when the APIC is disabled. -AK
	38	*/
	39	if (!disable_apic)
	40	ack_APIC_irq();
	41	}
	42
4961f10e ES	43	#ifdef CONFIG_DEBUG_STACKOVERFLOW
	44	/*
	45	* Probabilistic stack overflow check:
	46	*
	47	* Only check the stack in process context, because everything else
	48	* runs on the big interrupt stacks. Checking reliably is too expensive,
	49	* so we just check from interrupts.
	50	*/
	51	static inline void stack_overflow_check(struct pt_regs *regs)
	52	{
c9f4f06d	53	u64 curbase = (u64)task_stack_page(current);
4961f10e ES	54	static unsigned long warned = -60*HZ;
4961f10e ES	55
65ea5b03 PA	56	if (regs->sp >= curbase && regs->sp <= curbase + THREAD_SIZE &&
65ea5b03 PA	57	regs->sp < curbase + sizeof(struct thread_info) + 128 &&
4961f10e	58	time_after(jiffies, warned + 60*HZ)) {
65ea5b03 PA	59	printk("do_IRQ: %s near stack overflow (cur:%Lx,sp:%lx)\n",
65ea5b03 PA	60	current->comm, curbase, regs->sp);
4961f10e ES	61	show_stack(NULL,NULL);
	62	warned = jiffies;
	63	}
	64	}
	65	#endif
	66
1da177e4 LT	67	/*
	68	* Generic, controller-independent functions:
	69	*/
	70
	71	int show_interrupts(struct seq_file p, void v)
	72	{
52b17329	73	int i, j;
1da177e4 LT	74	struct irqaction * action;
1da177e4 LT	75	unsigned long flags;
52b17329 YL	76	unsigned int entries;
	77	struct irq_desc *desc;
	78	int tail = 0;
	79
	80	#ifdef CONFIG_HAVE_SPARSE_IRQ
	81	desc = (struct irq_desc *)v;
	82	entries = -1U;
	83	i = desc->irq;
	84	if (!desc->next)
	85	tail = 1;
	86	#else
	87	entries = nr_irqs - 1;
	88	i = (loff_t ) v;
	89	if (i == nr_irqs)
	90	tail = 1;
	91	else
	92	desc = irq_to_desc(i);
	93	#endif
1da177e4 LT	94
	95	if (i == 0) {
	96	seq_printf(p, " ");
394e3902	97	for_each_online_cpu(j)
bdbdaa79	98	seq_printf(p, "CPU%-8d",j);
1da177e4 LT	99	seq_putc(p, '\n');
	100	}
	101
52b17329	102	if (i <= entries) {
072f5d82 JB	103	unsigned any_count = 0;
072f5d82 JB	104
08678b08	105	spin_lock_irqsave(&desc->lock, flags);
072f5d82 JB	106	#ifndef CONFIG_SMP
	107	any_count = kstat_irqs(i);
	108	#else
	109	for_each_online_cpu(j)
7f95ec9e	110	any_count \|= kstat_irqs_cpu(i, j);
072f5d82	111	#endif
08678b08	112	action = desc->action;
072f5d82	113	if (!action && !any_count)
1da177e4 LT	114	goto skip;
	115	seq_printf(p, "%3d: ",i);
	116	#ifndef CONFIG_SMP
	117	seq_printf(p, "%10u ", kstat_irqs(i));
	118	#else
394e3902	119	for_each_online_cpu(j)
7f95ec9e	120	seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
1da177e4	121	#endif
08678b08 YL	122	seq_printf(p, " %8s", desc->chip->name);
08678b08 YL	123	seq_printf(p, "-%-8s", desc->name);
1da177e4	124
072f5d82 JB	125	if (action) {
	126	seq_printf(p, " %s", action->name);
	127	while ((action = action->next) != NULL)
	128	seq_printf(p, ", %s", action->name);
	129	}
1da177e4 LT	130	seq_putc(p, '\n');
1da177e4 LT	131	skip:
08678b08	132	spin_unlock_irqrestore(&desc->lock, flags);
52b17329 YL	133	}
	134
	135	if (tail) {
1da177e4	136	seq_printf(p, "NMI: ");
394e3902 AM	137	for_each_online_cpu(j)
394e3902 AM	138	seq_printf(p, "%10u ", cpu_pda(j)->__nmi_count);
38e760a1	139	seq_printf(p, " Non-maskable interrupts\n");
1da177e4	140	seq_printf(p, "LOC: ");
394e3902 AM	141	for_each_online_cpu(j)
394e3902 AM	142	seq_printf(p, "%10u ", cpu_pda(j)->apic_timer_irqs);
38e760a1 JK	143	seq_printf(p, " Local timer interrupts\n");
	144	#ifdef CONFIG_SMP
	145	seq_printf(p, "RES: ");
	146	for_each_online_cpu(j)
	147	seq_printf(p, "%10u ", cpu_pda(j)->irq_resched_count);
	148	seq_printf(p, " Rescheduling interrupts\n");
	149	seq_printf(p, "CAL: ");
	150	for_each_online_cpu(j)
	151	seq_printf(p, "%10u ", cpu_pda(j)->irq_call_count);
dc44e659	152	seq_printf(p, " Function call interrupts\n");
38e760a1 JK	153	seq_printf(p, "TLB: ");
	154	for_each_online_cpu(j)
	155	seq_printf(p, "%10u ", cpu_pda(j)->irq_tlb_count);
	156	seq_printf(p, " TLB shootdowns\n");
	157	#endif
a2eddfa9	158	#ifdef CONFIG_X86_MCE
38e760a1 JK	159	seq_printf(p, "TRM: ");
	160	for_each_online_cpu(j)
	161	seq_printf(p, "%10u ", cpu_pda(j)->irq_thermal_count);
	162	seq_printf(p, " Thermal event interrupts\n");
	163	seq_printf(p, "THR: ");
	164	for_each_online_cpu(j)
	165	seq_printf(p, "%10u ", cpu_pda(j)->irq_threshold_count);
	166	seq_printf(p, " Threshold APIC interrupts\n");
a2eddfa9	167	#endif
38e760a1 JK	168	seq_printf(p, "SPU: ");
	169	for_each_online_cpu(j)
	170	seq_printf(p, "%10u ", cpu_pda(j)->irq_spurious_count);
	171	seq_printf(p, " Spurious interrupts\n");
1da177e4	172	seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
1da177e4	173	}
52b17329	174
1da177e4 LT	175	return 0;
	176	}
	177
a2eddfa9 JB	178	/*
	179	* /proc/stat helpers
	180	*/
	181	u64 arch_irq_stat_cpu(unsigned int cpu)
	182	{
	183	u64 sum = cpu_pda(cpu)->__nmi_count;
	184
	185	sum += cpu_pda(cpu)->apic_timer_irqs;
	186	#ifdef CONFIG_SMP
	187	sum += cpu_pda(cpu)->irq_resched_count;
	188	sum += cpu_pda(cpu)->irq_call_count;
	189	sum += cpu_pda(cpu)->irq_tlb_count;
	190	#endif
	191	#ifdef CONFIG_X86_MCE
	192	sum += cpu_pda(cpu)->irq_thermal_count;
	193	sum += cpu_pda(cpu)->irq_threshold_count;
	194	#endif
	195	sum += cpu_pda(cpu)->irq_spurious_count;
	196	return sum;
	197	}
	198
	199	u64 arch_irq_stat(void)
	200	{
	201	return atomic_read(&irq_err_count);
	202	}
	203
1da177e4 LT	204	/*
	205	* do_IRQ handles all normal device IRQ's (the special
	206	* SMP cross-CPU interrupts have their own specific
	207	* handlers).
	208	*/
	209	asmlinkage unsigned int do_IRQ(struct pt_regs *regs)
7d12e780 DH	210	{
7d12e780 DH	211	struct pt_regs *old_regs = set_irq_regs(regs);
46926b67	212	struct irq_desc *desc;
7d12e780	213
19eadf98	214	/* high bit used in ret_from_ code */
65ea5b03	215	unsigned vector = ~regs->orig_ax;
e500f574 EB	216	unsigned irq;
	217
	218	exit_idle();
	219	irq_enter();
550f2299	220	irq = __get_cpu_var(vector_irq)[vector];
1da177e4	221
4961f10e ES	222	#ifdef CONFIG_DEBUG_STACKOVERFLOW
	223	stack_overflow_check(regs);
	224	#endif
d3696cf7	225
cb5bc832	226	desc = irq_to_desc(irq);
46926b67 YL	227	if (likely(desc))
46926b67 YL	228	generic_handle_irq_desc(irq, desc);
2fb12a9b EB	229	else {
	230	if (!disable_apic)
	231	ack_APIC_irq();
	232
	233	if (printk_ratelimit())
	234	printk(KERN_EMERG "%s: %d.%d No irq handler for vector\n",
	235	__func__, smp_processor_id(), vector);
	236	}
d3696cf7	237
1da177e4 LT	238	irq_exit();
1da177e4 LT	239
7d12e780	240	set_irq_regs(old_regs);
1da177e4 LT	241	return 1;
	242	}
	243
76e4f660 AR	244	#ifdef CONFIG_HOTPLUG_CPU
	245	void fixup_irqs(cpumask_t map)
	246	{
	247	unsigned int irq;
	248	static int warned;
2c6927a3	249	struct irq_desc *desc;
76e4f660	250
2c6927a3	251	for_each_irq_desc(irq, desc) {
76e4f660	252	cpumask_t mask;
48d8d7ee SS	253	int break_affinity = 0;
	254	int set_affinity = 1;
	255
76e4f660 AR	256	if (irq == 2)
	257	continue;
	258
48d8d7ee	259	/* interrupt's are disabled at this point */
08678b08	260	spin_lock(&desc->lock);
48d8d7ee SS	261
48d8d7ee SS	262	if (!irq_has_action(irq) \|\|
08678b08 YL	263	cpus_equal(desc->affinity, map)) {
08678b08 YL	264	spin_unlock(&desc->lock);
48d8d7ee SS	265	continue;
	266	}
	267
08678b08	268	cpus_and(mask, desc->affinity, map);
48d8d7ee SS	269	if (cpus_empty(mask)) {
48d8d7ee SS	270	break_affinity = 1;
76e4f660 AR	271	mask = map;
76e4f660 AR	272	}
48d8d7ee	273
08678b08 YL	274	if (desc->chip->mask)
08678b08 YL	275	desc->chip->mask(irq);
48d8d7ee	276
08678b08 YL	277	if (desc->chip->set_affinity)
08678b08 YL	278	desc->chip->set_affinity(irq, mask);
48d8d7ee SS	279	else if (!(warned++))
	280	set_affinity = 0;
	281
08678b08 YL	282	if (desc->chip->unmask)
08678b08 YL	283	desc->chip->unmask(irq);
48d8d7ee	284
08678b08	285	spin_unlock(&desc->lock);
48d8d7ee SS	286
	287	if (break_affinity && set_affinity)
	288	printk("Broke affinity for irq %i\n", irq);
	289	else if (!set_affinity)
76e4f660 AR	290	printk("Cannot set affinity for irq %i\n", irq);
	291	}
	292
	293	/* That doesn't seem sufficient. Give it 1ms. */
	294	local_irq_enable();
	295	mdelay(1);
	296	local_irq_disable();
	297	}
	298	#endif
ed6b676c AK	299
	300	extern void call_softirq(void);
	301
	302	asmlinkage void do_softirq(void)
	303	{
	304	__u32 pending;
	305	unsigned long flags;
	306
	307	if (in_interrupt())
	308	return;
	309
	310	local_irq_save(flags);
	311	pending = local_softirq_pending();
	312	/* Switch to interrupt stack */
2601e64d	313	if (pending) {
ed6b676c	314	call_softirq();
2601e64d IM	315	WARN_ON_ONCE(softirq_count());
2601e64d IM	316	}
ed6b676c AK	317	local_irq_restore(flags);
ed6b676c AK	318	}