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1da177e4 LT |
1 | #include <linux/errno.h> |
2 | #include <linux/signal.h> | |
3 | #include <linux/sched.h> | |
4 | #include <linux/ioport.h> | |
5 | #include <linux/interrupt.h> | |
6 | #include <linux/slab.h> | |
7 | #include <linux/random.h> | |
1da177e4 LT |
8 | #include <linux/init.h> |
9 | #include <linux/kernel_stat.h> | |
10 | #include <linux/sysdev.h> | |
11 | #include <linux/bitops.h> | |
12 | ||
1da177e4 LT |
13 | #include <asm/atomic.h> |
14 | #include <asm/system.h> | |
15 | #include <asm/io.h> | |
1da177e4 LT |
16 | #include <asm/timer.h> |
17 | #include <asm/pgtable.h> | |
18 | #include <asm/delay.h> | |
19 | #include <asm/desc.h> | |
20 | #include <asm/apic.h> | |
21 | #include <asm/arch_hooks.h> | |
22 | #include <asm/i8259.h> | |
23 | ||
1da177e4 | 24 | |
1da177e4 LT |
25 | |
26 | /* | |
27 | * Note that on a 486, we don't want to do a SIGFPE on an irq13 | |
28 | * as the irq is unreliable, and exception 16 works correctly | |
29 | * (ie as explained in the intel literature). On a 386, you | |
30 | * can't use exception 16 due to bad IBM design, so we have to | |
31 | * rely on the less exact irq13. | |
32 | * | |
33 | * Careful.. Not only is IRQ13 unreliable, but it is also | |
34 | * leads to races. IBM designers who came up with it should | |
35 | * be shot. | |
36 | */ | |
37 | ||
38 | ||
7d12e780 | 39 | static irqreturn_t math_error_irq(int cpl, void *dev_id) |
1da177e4 LT |
40 | { |
41 | extern void math_error(void __user *); | |
42 | outb(0,0xF0); | |
43 | if (ignore_fpu_irq || !boot_cpu_data.hard_math) | |
44 | return IRQ_NONE; | |
65ea5b03 | 45 | math_error((void __user *)get_irq_regs()->ip); |
1da177e4 LT |
46 | return IRQ_HANDLED; |
47 | } | |
48 | ||
49 | /* | |
50 | * New motherboards sometimes make IRQ 13 be a PCI interrupt, | |
51 | * so allow interrupt sharing. | |
52 | */ | |
6a61f6a5 TG |
53 | static struct irqaction fpu_irq = { |
54 | .handler = math_error_irq, | |
55 | .mask = CPU_MASK_NONE, | |
56 | .name = "fpu", | |
57 | }; | |
1da177e4 LT |
58 | |
59 | void __init init_ISA_irqs (void) | |
60 | { | |
61 | int i; | |
62 | ||
63 | #ifdef CONFIG_X86_LOCAL_APIC | |
64 | init_bsp_APIC(); | |
65 | #endif | |
66 | init_8259A(0); | |
67 | ||
7c6357da AD |
68 | /* |
69 | * 16 old-style INTA-cycle interrupts: | |
70 | */ | |
71 | for (i = 0; i < 16; i++) { | |
72 | set_irq_chip_and_handler_name(i, &i8259A_chip, | |
73 | handle_level_irq, "XT"); | |
1da177e4 LT |
74 | } |
75 | } | |
76 | ||
d3561b7f RR |
77 | /* Overridden in paravirt.c */ |
78 | void init_IRQ(void) __attribute__((weak, alias("native_init_IRQ"))); | |
79 | ||
80 | void __init native_init_IRQ(void) | |
1da177e4 LT |
81 | { |
82 | int i; | |
83 | ||
84 | /* all the set up before the call gates are initialised */ | |
85 | pre_intr_init_hook(); | |
86 | ||
87 | /* | |
88 | * Cover the whole vector space, no vector can escape | |
89 | * us. (some of these will be overridden and become | |
90 | * 'special' SMP interrupts) | |
91 | */ | |
92 | for (i = 0; i < (NR_VECTORS - FIRST_EXTERNAL_VECTOR); i++) { | |
93 | int vector = FIRST_EXTERNAL_VECTOR + i; | |
94 | if (i >= NR_IRQS) | |
95 | break; | |
dbeb2be2 RR |
96 | /* SYSCALL_VECTOR was reserved in trap_init. */ |
97 | if (!test_bit(vector, used_vectors)) | |
1da177e4 LT |
98 | set_intr_gate(vector, interrupt[i]); |
99 | } | |
100 | ||
101 | /* setup after call gates are initialised (usually add in | |
102 | * the architecture specific gates) | |
103 | */ | |
104 | intr_init_hook(); | |
105 | ||
1da177e4 LT |
106 | /* |
107 | * External FPU? Set up irq13 if so, for | |
108 | * original braindamaged IBM FERR coupling. | |
109 | */ | |
110 | if (boot_cpu_data.hard_math && !cpu_has_fpu) | |
111 | setup_irq(FPU_IRQ, &fpu_irq); | |
112 | ||
113 | irq_ctx_init(smp_processor_id()); | |
114 | } |