Commit | Line | Data |
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83d7384f AS |
1 | /* |
2 | * Driver/API for AMD Geode Multi-Function General Purpose Timers (MFGPT) | |
3 | * | |
4 | * Copyright (C) 2006, Advanced Micro Devices, Inc. | |
5 | * Copyright (C) 2007, Andres Salomon <dilinger@debian.org> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of version 2 of the GNU General Public License | |
9 | * as published by the Free Software Foundation. | |
10 | * | |
11 | * The MFGPTs are documented in AMD Geode CS5536 Companion Device Data Book. | |
12 | */ | |
13 | ||
14 | /* | |
36445cf3 | 15 | * We are using the 32.768kHz input clock - it's the only one that has the |
83d7384f | 16 | * ranges we find desirable. The following table lists the suitable |
36445cf3 | 17 | * divisors and the associated Hz, minimum interval and the maximum interval: |
83d7384f | 18 | * |
36445cf3 WT |
19 | * Divisor Hz Min Delta (s) Max Delta (s) |
20 | * 1 32768 .00048828125 2.000 | |
21 | * 2 16384 .0009765625 4.000 | |
22 | * 4 8192 .001953125 8.000 | |
23 | * 8 4096 .00390625 16.000 | |
24 | * 16 2048 .0078125 32.000 | |
25 | * 32 1024 .015625 64.000 | |
26 | * 64 512 .03125 128.000 | |
27 | * 128 256 .0625 256.000 | |
28 | * 256 128 .125 512.000 | |
83d7384f AS |
29 | */ |
30 | ||
31 | #include <linux/kernel.h> | |
32 | #include <linux/interrupt.h> | |
923a0cf8 | 33 | #include <linux/module.h> |
83d7384f AS |
34 | #include <asm/geode.h> |
35 | ||
83d7384f | 36 | static struct mfgpt_timer_t { |
9501b2ef | 37 | unsigned int avail:1; |
83d7384f AS |
38 | } mfgpt_timers[MFGPT_MAX_TIMERS]; |
39 | ||
40 | /* Selected from the table above */ | |
41 | ||
42 | #define MFGPT_DIVISOR 16 | |
43 | #define MFGPT_SCALE 4 /* divisor = 2^(scale) */ | |
36445cf3 | 44 | #define MFGPT_HZ (32768 / MFGPT_DIVISOR) |
83d7384f AS |
45 | #define MFGPT_PERIODIC (MFGPT_HZ / HZ) |
46 | ||
47 | /* Allow for disabling of MFGPTs */ | |
48 | static int disable; | |
49 | static int __init mfgpt_disable(char *s) | |
50 | { | |
51 | disable = 1; | |
52 | return 1; | |
53 | } | |
54 | __setup("nomfgpt", mfgpt_disable); | |
55 | ||
e6c4dc6c WT |
56 | /* Reset the MFGPT timers. This is required by some broken BIOSes which already |
57 | * do the same and leave the system in an unstable state. TinyBIOS 0.98 is | |
58 | * affected at least (0.99 is OK with MFGPT workaround left to off). | |
59 | */ | |
60 | static int __init mfgpt_fix(char *s) | |
61 | { | |
62 | u32 val, dummy; | |
63 | ||
64 | /* The following udocumented bit resets the MFGPT timers */ | |
65 | val = 0xFF; dummy = 0; | |
32bf87e3 | 66 | wrmsr(MSR_MFGPT_SETUP, val, dummy); |
e6c4dc6c WT |
67 | return 1; |
68 | } | |
69 | __setup("mfgptfix", mfgpt_fix); | |
70 | ||
83d7384f AS |
71 | /* |
72 | * Check whether any MFGPTs are available for the kernel to use. In most | |
73 | * cases, firmware that uses AMD's VSA code will claim all timers during | |
74 | * bootup; we certainly don't want to take them if they're already in use. | |
75 | * In other cases (such as with VSAless OpenFirmware), the system firmware | |
76 | * leaves timers available for us to use. | |
77 | */ | |
f087515c JC |
78 | |
79 | ||
80 | static int timers = -1; | |
81 | ||
82 | static void geode_mfgpt_detect(void) | |
83d7384f | 83 | { |
f087515c | 84 | int i; |
83d7384f AS |
85 | u16 val; |
86 | ||
f087515c JC |
87 | timers = 0; |
88 | ||
83d7384f | 89 | if (disable) { |
f087515c JC |
90 | printk(KERN_INFO "geode-mfgpt: MFGPT support is disabled\n"); |
91 | goto done; | |
92 | } | |
93 | ||
94 | if (!geode_get_dev_base(GEODE_DEV_MFGPT)) { | |
95 | printk(KERN_INFO "geode-mfgpt: MFGPT LBAR is not set up\n"); | |
96 | goto done; | |
83d7384f AS |
97 | } |
98 | ||
99 | for (i = 0; i < MFGPT_MAX_TIMERS; i++) { | |
100 | val = geode_mfgpt_read(i, MFGPT_REG_SETUP); | |
101 | if (!(val & MFGPT_SETUP_SETUP)) { | |
9501b2ef | 102 | mfgpt_timers[i].avail = 1; |
f087515c | 103 | timers++; |
83d7384f AS |
104 | } |
105 | } | |
106 | ||
f087515c JC |
107 | done: |
108 | printk(KERN_INFO "geode-mfgpt: %d MFGPT timers available.\n", timers); | |
83d7384f AS |
109 | } |
110 | ||
111 | int geode_mfgpt_toggle_event(int timer, int cmp, int event, int enable) | |
112 | { | |
113 | u32 msr, mask, value, dummy; | |
114 | int shift = (cmp == MFGPT_CMP1) ? 0 : 8; | |
115 | ||
116 | if (timer < 0 || timer >= MFGPT_MAX_TIMERS) | |
117 | return -EIO; | |
118 | ||
119 | /* | |
120 | * The register maps for these are described in sections 6.17.1.x of | |
121 | * the AMD Geode CS5536 Companion Device Data Book. | |
122 | */ | |
123 | switch (event) { | |
124 | case MFGPT_EVENT_RESET: | |
125 | /* | |
126 | * XXX: According to the docs, we cannot reset timers above | |
127 | * 6; that is, resets for 7 and 8 will be ignored. Is this | |
128 | * a problem? -dilinger | |
129 | */ | |
32bf87e3 | 130 | msr = MSR_MFGPT_NR; |
83d7384f AS |
131 | mask = 1 << (timer + 24); |
132 | break; | |
133 | ||
134 | case MFGPT_EVENT_NMI: | |
32bf87e3 | 135 | msr = MSR_MFGPT_NR; |
83d7384f AS |
136 | mask = 1 << (timer + shift); |
137 | break; | |
138 | ||
139 | case MFGPT_EVENT_IRQ: | |
32bf87e3 | 140 | msr = MSR_MFGPT_IRQ; |
83d7384f AS |
141 | mask = 1 << (timer + shift); |
142 | break; | |
143 | ||
144 | default: | |
145 | return -EIO; | |
146 | } | |
147 | ||
148 | rdmsr(msr, value, dummy); | |
149 | ||
150 | if (enable) | |
151 | value |= mask; | |
152 | else | |
153 | value &= ~mask; | |
154 | ||
155 | wrmsr(msr, value, dummy); | |
156 | return 0; | |
157 | } | |
3703f399 | 158 | EXPORT_SYMBOL_GPL(geode_mfgpt_toggle_event); |
83d7384f AS |
159 | |
160 | int geode_mfgpt_set_irq(int timer, int cmp, int irq, int enable) | |
161 | { | |
162 | u32 val, dummy; | |
163 | int offset; | |
164 | ||
165 | if (timer < 0 || timer >= MFGPT_MAX_TIMERS) | |
166 | return -EIO; | |
167 | ||
168 | if (geode_mfgpt_toggle_event(timer, cmp, MFGPT_EVENT_IRQ, enable)) | |
169 | return -EIO; | |
170 | ||
171 | rdmsr(MSR_PIC_ZSEL_LOW, val, dummy); | |
172 | ||
173 | offset = (timer % 4) * 4; | |
174 | ||
175 | val &= ~((0xF << offset) | (0xF << (offset + 16))); | |
176 | ||
177 | if (enable) { | |
178 | val |= (irq & 0x0F) << (offset); | |
179 | val |= (irq & 0x0F) << (offset + 16); | |
180 | } | |
181 | ||
182 | wrmsr(MSR_PIC_ZSEL_LOW, val, dummy); | |
183 | return 0; | |
184 | } | |
185 | ||
fa28e067 | 186 | static int mfgpt_get(int timer) |
83d7384f | 187 | { |
9501b2ef | 188 | mfgpt_timers[timer].avail = 0; |
83d7384f AS |
189 | printk(KERN_INFO "geode-mfgpt: Registered timer %d\n", timer); |
190 | return timer; | |
191 | } | |
192 | ||
fa28e067 | 193 | int geode_mfgpt_alloc_timer(int timer, int domain) |
83d7384f AS |
194 | { |
195 | int i; | |
196 | ||
f087515c JC |
197 | if (timers == -1) { |
198 | /* timers haven't been detected yet */ | |
199 | geode_mfgpt_detect(); | |
200 | } | |
201 | ||
202 | if (!timers) | |
203 | return -1; | |
204 | ||
83d7384f | 205 | if (timer >= MFGPT_MAX_TIMERS) |
f087515c | 206 | return -1; |
83d7384f AS |
207 | |
208 | if (timer < 0) { | |
209 | /* Try to find an available timer */ | |
210 | for (i = 0; i < MFGPT_MAX_TIMERS; i++) { | |
9501b2ef | 211 | if (mfgpt_timers[i].avail) |
fa28e067 | 212 | return mfgpt_get(i); |
83d7384f AS |
213 | |
214 | if (i == 5 && domain == MFGPT_DOMAIN_WORKING) | |
215 | break; | |
216 | } | |
217 | } else { | |
218 | /* If they requested a specific timer, try to honor that */ | |
9501b2ef | 219 | if (mfgpt_timers[timer].avail) |
fa28e067 | 220 | return mfgpt_get(timer); |
83d7384f AS |
221 | } |
222 | ||
223 | /* No timers available - too bad */ | |
224 | return -1; | |
225 | } | |
3703f399 | 226 | EXPORT_SYMBOL_GPL(geode_mfgpt_alloc_timer); |
83d7384f | 227 | |
8f36881b AS |
228 | |
229 | #ifdef CONFIG_GEODE_MFGPT_TIMER | |
230 | ||
231 | /* | |
232 | * The MFPGT timers on the CS5536 provide us with suitable timers to use | |
233 | * as clock event sources - not as good as a HPET or APIC, but certainly | |
234 | * better then the PIT. This isn't a general purpose MFGPT driver, but | |
235 | * a simplified one designed specifically to act as a clock event source. | |
236 | * For full details about the MFGPT, please consult the CS5536 data sheet. | |
237 | */ | |
238 | ||
239 | #include <linux/clocksource.h> | |
240 | #include <linux/clockchips.h> | |
241 | ||
242 | static unsigned int mfgpt_tick_mode = CLOCK_EVT_MODE_SHUTDOWN; | |
243 | static u16 mfgpt_event_clock; | |
244 | ||
245 | static int irq = 7; | |
246 | static int __init mfgpt_setup(char *str) | |
247 | { | |
248 | get_option(&str, &irq); | |
249 | return 1; | |
250 | } | |
251 | __setup("mfgpt_irq=", mfgpt_setup); | |
252 | ||
e78a77c3 | 253 | static void mfgpt_disable_timer(u16 clock) |
8f36881b | 254 | { |
f54ae69b AS |
255 | /* avoid races by clearing CMP1 and CMP2 unconditionally */ |
256 | geode_mfgpt_write(clock, MFGPT_REG_SETUP, (u16) ~MFGPT_SETUP_CNTEN | | |
257 | MFGPT_SETUP_CMP1 | MFGPT_SETUP_CMP2); | |
8f36881b AS |
258 | } |
259 | ||
260 | static int mfgpt_next_event(unsigned long, struct clock_event_device *); | |
261 | static void mfgpt_set_mode(enum clock_event_mode, struct clock_event_device *); | |
262 | ||
263 | static struct clock_event_device mfgpt_clockevent = { | |
264 | .name = "mfgpt-timer", | |
265 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | |
266 | .set_mode = mfgpt_set_mode, | |
267 | .set_next_event = mfgpt_next_event, | |
268 | .rating = 250, | |
269 | .cpumask = CPU_MASK_ALL, | |
270 | .shift = 32 | |
271 | }; | |
272 | ||
e78a77c3 | 273 | static void mfgpt_start_timer(u16 delta) |
8f36881b AS |
274 | { |
275 | geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_CMP2, (u16) delta); | |
276 | geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_COUNTER, 0); | |
277 | ||
278 | geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_SETUP, | |
279 | MFGPT_SETUP_CNTEN | MFGPT_SETUP_CMP2); | |
280 | } | |
281 | ||
282 | static void mfgpt_set_mode(enum clock_event_mode mode, | |
283 | struct clock_event_device *evt) | |
284 | { | |
285 | mfgpt_disable_timer(mfgpt_event_clock); | |
286 | ||
287 | if (mode == CLOCK_EVT_MODE_PERIODIC) | |
e78a77c3 | 288 | mfgpt_start_timer(MFGPT_PERIODIC); |
8f36881b AS |
289 | |
290 | mfgpt_tick_mode = mode; | |
291 | } | |
292 | ||
293 | static int mfgpt_next_event(unsigned long delta, struct clock_event_device *evt) | |
294 | { | |
e78a77c3 | 295 | mfgpt_start_timer(delta); |
8f36881b AS |
296 | return 0; |
297 | } | |
298 | ||
8f36881b AS |
299 | static irqreturn_t mfgpt_tick(int irq, void *dev_id) |
300 | { | |
dcee77be JC |
301 | u16 val = geode_mfgpt_read(mfgpt_event_clock, MFGPT_REG_SETUP); |
302 | ||
303 | /* See if the interrupt was for us */ | |
304 | if (!(val & (MFGPT_SETUP_SETUP | MFGPT_SETUP_CMP2 | MFGPT_SETUP_CMP1))) | |
305 | return IRQ_NONE; | |
306 | ||
667984d9 JC |
307 | /* Turn off the clock (and clear the event) */ |
308 | mfgpt_disable_timer(mfgpt_event_clock); | |
309 | ||
8f36881b AS |
310 | if (mfgpt_tick_mode == CLOCK_EVT_MODE_SHUTDOWN) |
311 | return IRQ_HANDLED; | |
312 | ||
8f36881b AS |
313 | /* Clear the counter */ |
314 | geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_COUNTER, 0); | |
315 | ||
316 | /* Restart the clock in periodic mode */ | |
317 | ||
318 | if (mfgpt_tick_mode == CLOCK_EVT_MODE_PERIODIC) { | |
319 | geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_SETUP, | |
320 | MFGPT_SETUP_CNTEN | MFGPT_SETUP_CMP2); | |
321 | } | |
322 | ||
323 | mfgpt_clockevent.event_handler(&mfgpt_clockevent); | |
324 | return IRQ_HANDLED; | |
325 | } | |
326 | ||
327 | static struct irqaction mfgptirq = { | |
328 | .handler = mfgpt_tick, | |
329 | .flags = IRQF_DISABLED | IRQF_NOBALANCING, | |
330 | .mask = CPU_MASK_NONE, | |
331 | .name = "mfgpt-timer" | |
332 | }; | |
333 | ||
b0e6bf25 | 334 | int __init mfgpt_timer_setup(void) |
8f36881b AS |
335 | { |
336 | int timer, ret; | |
337 | u16 val; | |
338 | ||
fa28e067 | 339 | timer = geode_mfgpt_alloc_timer(MFGPT_TIMER_ANY, MFGPT_DOMAIN_WORKING); |
8f36881b AS |
340 | if (timer < 0) { |
341 | printk(KERN_ERR | |
342 | "mfgpt-timer: Could not allocate a MFPGT timer\n"); | |
343 | return -ENODEV; | |
344 | } | |
345 | ||
346 | mfgpt_event_clock = timer; | |
8f36881b AS |
347 | |
348 | /* Set up the IRQ on the MFGPT side */ | |
349 | if (geode_mfgpt_setup_irq(mfgpt_event_clock, MFGPT_CMP2, irq)) { | |
350 | printk(KERN_ERR "mfgpt-timer: Could not set up IRQ %d\n", irq); | |
351 | return -EIO; | |
352 | } | |
353 | ||
354 | /* And register it with the kernel */ | |
355 | ret = setup_irq(irq, &mfgptirq); | |
356 | ||
357 | if (ret) { | |
358 | printk(KERN_ERR | |
359 | "mfgpt-timer: Unable to set up the interrupt.\n"); | |
360 | goto err; | |
361 | } | |
362 | ||
667984d9 JC |
363 | /* Set the clock scale and enable the event mode for CMP2 */ |
364 | val = MFGPT_SCALE | (3 << 8); | |
365 | ||
366 | geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_SETUP, val); | |
367 | ||
8f36881b | 368 | /* Set up the clock event */ |
877084fb AM |
369 | mfgpt_clockevent.mult = div_sc(MFGPT_HZ, NSEC_PER_SEC, |
370 | mfgpt_clockevent.shift); | |
8f36881b AS |
371 | mfgpt_clockevent.min_delta_ns = clockevent_delta2ns(0xF, |
372 | &mfgpt_clockevent); | |
373 | mfgpt_clockevent.max_delta_ns = clockevent_delta2ns(0xFFFE, | |
374 | &mfgpt_clockevent); | |
375 | ||
376 | printk(KERN_INFO | |
3406c158 | 377 | "mfgpt-timer: registering the MFGPT timer as a clock event.\n"); |
8f36881b AS |
378 | clockevents_register_device(&mfgpt_clockevent); |
379 | ||
380 | return 0; | |
381 | ||
382 | err: | |
383 | geode_mfgpt_release_irq(mfgpt_event_clock, MFGPT_CMP2, irq); | |
384 | printk(KERN_ERR | |
385 | "mfgpt-timer: Unable to set up the MFGPT clock source\n"); | |
386 | return -EIO; | |
387 | } | |
388 | ||
389 | #endif |