[deliverable/linux.git] / arch / x86 / kernel / microcode_amd.c

/*
 *  AMD CPU Microcode Update Driver for Linux
 *  Copyright (C) 2008-2011 Advanced Micro Devices Inc.
 *
 *  Author: Peter Oruba <peter.oruba@amd.com>
 *
 *  Based on work by:
 *  Tigran Aivazian <tigran@aivazian.fsnet.co.uk>
 *
 *  Maintainers:
 *  Andreas Herrmann <herrmann.der.user@googlemail.com>
 *  Borislav Petkov <bp@alien8.de>
 *
 *  This driver allows to upgrade microcode on F10h AMD
 *  CPUs and later.
 *
 *  Licensed under the terms of the GNU General Public
 *  License version 2. See file COPYING for details.
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/firmware.h>
#include <linux/pci_ids.h>
#include <linux/uaccess.h>
#include <linux/vmalloc.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>

#include <asm/microcode.h>
#include <asm/processor.h>
#include <asm/msr.h>

MODULE_DESCRIPTION("AMD Microcode Update Driver");
MODULE_AUTHOR("Peter Oruba");
MODULE_LICENSE("GPL v2");

#define UCODE_MAGIC                0x00414d44
#define UCODE_EQUIV_CPU_TABLE_TYPE 0x00000000
#define UCODE_UCODE_TYPE           0x00000001

struct equiv_cpu_entry {
	u32	installed_cpu;
	u32	fixed_errata_mask;
	u32	fixed_errata_compare;
	u16	equiv_cpu;
	u16	res;
} __attribute__((packed));

struct microcode_header_amd {
	u32	data_code;
	u32	patch_id;
	u16	mc_patch_data_id;
	u8	mc_patch_data_len;
	u8	init_flag;
	u32	mc_patch_data_checksum;
	u32	nb_dev_id;
	u32	sb_dev_id;
	u16	processor_rev_id;
	u8	nb_rev_id;
	u8	sb_rev_id;
	u8	bios_api_rev;
	u8	reserved1[3];
	u32	match_reg[8];
} __attribute__((packed));

struct microcode_amd {
	struct microcode_header_amd	hdr;
	unsigned int			mpb[0];
};

#define SECTION_HDR_SIZE	8
#define CONTAINER_HDR_SZ	12

static struct equiv_cpu_entry *equiv_cpu_table;

struct ucode_patch {
	struct list_head plist;
	void *data;
	u32 patch_id;
	u16 equiv_cpu;
};

static LIST_HEAD(pcache);

static u16 find_equiv_id(unsigned int cpu)
{
	struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
	int i = 0;

	if (!equiv_cpu_table)
		return 0;

	while (equiv_cpu_table[i].installed_cpu != 0) {
		if (uci->cpu_sig.sig == equiv_cpu_table[i].installed_cpu)
			return equiv_cpu_table[i].equiv_cpu;

		i++;
	}
	return 0;
}

static u32 find_cpu_family_by_equiv_cpu(u16 equiv_cpu)
{
	int i = 0;

	BUG_ON(!equiv_cpu_table);

	while (equiv_cpu_table[i].equiv_cpu != 0) {
		if (equiv_cpu == equiv_cpu_table[i].equiv_cpu)
			return equiv_cpu_table[i].installed_cpu;
		i++;
	}
	return 0;
}

/*
 * a small, trivial cache of per-family ucode patches
 */
static struct ucode_patch *cache_find_patch(u16 equiv_cpu)
{
	struct ucode_patch *p;

	list_for_each_entry(p, &pcache, plist)
		if (p->equiv_cpu == equiv_cpu)
			return p;
	return NULL;
}

static void update_cache(struct ucode_patch *new_patch)
{
	struct ucode_patch *p;

	list_for_each_entry(p, &pcache, plist) {
		if (p->equiv_cpu == new_patch->equiv_cpu) {
			if (p->patch_id >= new_patch->patch_id)
				/* we already have the latest patch */
				return;

			list_replace(&p->plist, &new_patch->plist);
			kfree(p->data);
			kfree(p);
			return;
		}
	}
	/* no patch found, add it */
	list_add_tail(&new_patch->plist, &pcache);
}

static void free_cache(void)
{
	struct ucode_patch *p, *tmp;

	list_for_each_entry_safe(p, tmp, &pcache, plist) {
		__list_del(p->plist.prev, p->plist.next);
		kfree(p->data);
		kfree(p);
	}
}

static struct ucode_patch *find_patch(unsigned int cpu)
{
	u16 equiv_id;

	equiv_id = find_equiv_id(cpu);
	if (!equiv_id)
		return NULL;

	return cache_find_patch(equiv_id);
}

static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig)
{
	struct cpuinfo_x86 *c = &cpu_data(cpu);

	csig->sig = cpuid_eax(0x00000001);
	csig->rev = c->microcode;
	pr_info("CPU%d: patch_level=0x%08x\n", cpu, csig->rev);

	return 0;
}

static unsigned int verify_patch_size(int cpu, u32 patch_size,
				      unsigned int size)
{
	struct cpuinfo_x86 *c = &cpu_data(cpu);
	u32 max_size;

#define F1XH_MPB_MAX_SIZE 2048
#define F14H_MPB_MAX_SIZE 1824
#define F15H_MPB_MAX_SIZE 4096
#define F16H_MPB_MAX_SIZE 3458

	switch (c->x86) {
	case 0x14:
		max_size = F14H_MPB_MAX_SIZE;
		break;
	case 0x15:
		max_size = F15H_MPB_MAX_SIZE;
		break;
	case 0x16:
		max_size = F16H_MPB_MAX_SIZE;
		break;
	default:
		max_size = F1XH_MPB_MAX_SIZE;
		break;
	}

	if (patch_size > min_t(u32, size, max_size)) {
		pr_err("patch size mismatch\n");
		return 0;
	}

	return patch_size;
}

static int apply_microcode_amd(int cpu)
{
	struct cpuinfo_x86 *c = &cpu_data(cpu);
	struct microcode_amd *mc_amd;
	struct ucode_cpu_info *uci;
	struct ucode_patch *p;
	u32 rev, dummy;

	BUG_ON(raw_smp_processor_id() != cpu);

	uci = ucode_cpu_info + cpu;

	p = find_patch(cpu);
	if (!p)
		return 0;

	mc_amd  = p->data;
	uci->mc = p->data;

	rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);

	/* need to apply patch? */
	if (rev >= mc_amd->hdr.patch_id) {
		c->microcode = rev;
		return 0;
	}

	wrmsrl(MSR_AMD64_PATCH_LOADER, (u64)(long)&mc_amd->hdr.data_code);

	/* verify patch application was successful */
	rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
	if (rev != mc_amd->hdr.patch_id) {
		pr_err("CPU%d: update failed for patch_level=0x%08x\n",
		       cpu, mc_amd->hdr.patch_id);
		return -1;
	}

	pr_info("CPU%d: new patch_level=0x%08x\n", cpu, rev);
	uci->cpu_sig.rev = rev;
	c->microcode = rev;

	return 0;
}

static int install_equiv_cpu_table(const u8 *buf)
{
	unsigned int *ibuf = (unsigned int *)buf;
	unsigned int type = ibuf[1];
	unsigned int size = ibuf[2];

	if (type != UCODE_EQUIV_CPU_TABLE_TYPE || !size) {
		pr_err("empty section/"
		       "invalid type field in container file section header\n");
		return -EINVAL;
	}

	equiv_cpu_table = vmalloc(size);
	if (!equiv_cpu_table) {
		pr_err("failed to allocate equivalent CPU table\n");
		return -ENOMEM;
	}

	memcpy(equiv_cpu_table, buf + CONTAINER_HDR_SZ, size);

	/* add header length */
	return size + CONTAINER_HDR_SZ;
}

static void free_equiv_cpu_table(void)
{
	vfree(equiv_cpu_table);
	equiv_cpu_table = NULL;
}

static void cleanup(void)
{
	free_equiv_cpu_table();
	free_cache();
}

/*
 * We return the current size even if some of the checks failed so that
 * we can skip over the next patch. If we return a negative value, we
 * signal a grave error like a memory allocation has failed and the
 * driver cannot continue functioning normally. In such cases, we tear
 * down everything we've used up so far and exit.
 */
static int verify_and_add_patch(unsigned int cpu, u8 *fw, unsigned int leftover)
{
	struct cpuinfo_x86 *c = &cpu_data(cpu);
	struct microcode_header_amd *mc_hdr;
	struct ucode_patch *patch;
	unsigned int patch_size, crnt_size, ret;
	u32 proc_fam;
	u16 proc_id;

	patch_size  = *(u32 *)(fw + 4);
	crnt_size   = patch_size + SECTION_HDR_SIZE;
	mc_hdr	    = (struct microcode_header_amd *)(fw + SECTION_HDR_SIZE);
	proc_id	    = mc_hdr->processor_rev_id;

	proc_fam = find_cpu_family_by_equiv_cpu(proc_id);
	if (!proc_fam) {
		pr_err("No patch family for equiv ID: 0x%04x\n", proc_id);
		return crnt_size;
	}

	/* check if patch is for the current family */
	proc_fam = ((proc_fam >> 8) & 0xf) + ((proc_fam >> 20) & 0xff);
	if (proc_fam != c->x86)
		return crnt_size;

	if (mc_hdr->nb_dev_id || mc_hdr->sb_dev_id) {
		pr_err("Patch-ID 0x%08x: chipset-specific code unsupported.\n",
			mc_hdr->patch_id);
		return crnt_size;
	}

	ret = verify_patch_size(cpu, patch_size, leftover);
	if (!ret) {
		pr_err("Patch-ID 0x%08x: size mismatch.\n", mc_hdr->patch_id);
		return crnt_size;
	}

	patch = kzalloc(sizeof(*patch), GFP_KERNEL);
	if (!patch) {
		pr_err("Patch allocation failure.\n");
		return -EINVAL;
	}

	patch->data = kzalloc(patch_size, GFP_KERNEL);
	if (!patch->data) {
		pr_err("Patch data allocation failure.\n");
		kfree(patch);
		return -EINVAL;
	}

	/* All looks ok, copy patch... */
	memcpy(patch->data, fw + SECTION_HDR_SIZE, patch_size);
	INIT_LIST_HEAD(&patch->plist);
	patch->patch_id  = mc_hdr->patch_id;
	patch->equiv_cpu = proc_id;

	/* ... and add to cache. */
	update_cache(patch);

	return crnt_size;
}

static enum ucode_state load_microcode_amd(int cpu, const u8 *data, size_t size)
{
	enum ucode_state ret = UCODE_ERROR;
	unsigned int leftover;
	u8 *fw = (u8 *)data;
	int crnt_size = 0;
	int offset;

	offset = install_equiv_cpu_table(data);
	if (offset < 0) {
		pr_err("failed to create equivalent cpu table\n");
		return ret;
	}
	fw += offset;
	leftover = size - offset;

	if (*(u32 *)fw != UCODE_UCODE_TYPE) {
		pr_err("invalid type field in container file section header\n");
		free_equiv_cpu_table();
		return ret;
	}

	while (leftover) {
		crnt_size = verify_and_add_patch(cpu, fw, leftover);
		if (crnt_size < 0)
			return ret;

		fw	 += crnt_size;
		leftover -= crnt_size;
	}

	return UCODE_OK;
}

/*
 * AMD microcode firmware naming convention, up to family 15h they are in
 * the legacy file:
 *
 *    amd-ucode/microcode_amd.bin
 *
 * This legacy file is always smaller than 2K in size.
 *
 * Beginning with family 15h, they are in family-specific firmware files:
 *
 *    amd-ucode/microcode_amd_fam15h.bin
 *    amd-ucode/microcode_amd_fam16h.bin
 *    ...
 *
 * These might be larger than 2K.
 */
static enum ucode_state request_microcode_amd(int cpu, struct device *device,
					      bool refresh_fw)
{
	char fw_name[36] = "amd-ucode/microcode_amd.bin";
	struct cpuinfo_x86 *c = &cpu_data(cpu);
	enum ucode_state ret = UCODE_NFOUND;
	const struct firmware *fw;

	/* reload ucode container only on the boot cpu */
	if (!refresh_fw || c->cpu_index != boot_cpu_data.cpu_index)
		return UCODE_OK;

	if (c->x86 >= 0x15)
		snprintf(fw_name, sizeof(fw_name), "amd-ucode/microcode_amd_fam%.2xh.bin", c->x86);

	if (request_firmware(&fw, (const char *)fw_name, device)) {
		pr_err("failed to load file %s\n", fw_name);
		goto out;
	}

	ret = UCODE_ERROR;
	if (*(u32 *)fw->data != UCODE_MAGIC) {
		pr_err("invalid magic value (0x%08x)\n", *(u32 *)fw->data);
		goto fw_release;
	}

	/* free old equiv table */
	free_equiv_cpu_table();

	ret = load_microcode_amd(cpu, fw->data, fw->size);
	if (ret != UCODE_OK)
		cleanup();

 fw_release:
	release_firmware(fw);

 out:
	return ret;
}

static enum ucode_state
request_microcode_user(int cpu, const void __user *buf, size_t size)
{
	return UCODE_ERROR;
}

static void microcode_fini_cpu_amd(int cpu)
{
	struct ucode_cpu_info *uci = ucode_cpu_info + cpu;

	uci->mc = NULL;
}

static struct microcode_ops microcode_amd_ops = {
	.request_microcode_user           = request_microcode_user,
	.request_microcode_fw             = request_microcode_amd,
	.collect_cpu_info                 = collect_cpu_info_amd,
	.apply_microcode                  = apply_microcode_amd,
	.microcode_fini_cpu               = microcode_fini_cpu_amd,
};

struct microcode_ops * __init init_amd_microcode(void)
{
	struct cpuinfo_x86 *c = &cpu_data(0);

	if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) {
		pr_warning("AMD CPU family 0x%x not supported\n", c->x86);
		return NULL;
	}

	return &microcode_amd_ops;
}

void __exit exit_amd_microcode(void)
{
	cleanup();
}
Commit	Line	Data
80cc9f10 PO	1	/*
80cc9f10 PO	2	* AMD CPU Microcode Update Driver for Linux
597e11a3	3	* Copyright (C) 2008-2011 Advanced Micro Devices Inc.
80cc9f10 PO	4	*
	5	* Author: Peter Oruba <peter.oruba@amd.com>
	6	*
	7	* Based on work by:
	8	* Tigran Aivazian <tigran@aivazian.fsnet.co.uk>
	9	*
597e11a3	10	* Maintainers:
943482d0 AH	11	* Andreas Herrmann <herrmann.der.user@googlemail.com>
943482d0 AH	12	* Borislav Petkov <bp@alien8.de>
597e11a3 BP	13	*
	14	* This driver allows to upgrade microcode on F10h AMD
	15	* CPUs and later.
80cc9f10	16	*
2a3282a7	17	* Licensed under the terms of the GNU General Public
80cc9f10	18	* License version 2. See file COPYING for details.
4bae1967	19	*/
f58e1f53 JP	20
	21	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
	22
4bae1967	23	#include <linux/firmware.h>
4bae1967 IM	24	#include <linux/pci_ids.h>
	25	#include <linux/uaccess.h>
	26	#include <linux/vmalloc.h>
	27	#include <linux/kernel.h>
	28	#include <linux/module.h>
80cc9f10	29	#include <linux/pci.h>
80cc9f10	30
80cc9f10	31	#include <asm/microcode.h>
4bae1967 IM	32	#include <asm/processor.h>
4bae1967 IM	33	#include <asm/msr.h>
80cc9f10 PO	34
80cc9f10 PO	35	MODULE_DESCRIPTION("AMD Microcode Update Driver");
3c52204b	36	MODULE_AUTHOR("Peter Oruba");
5d7b6052	37	MODULE_LICENSE("GPL v2");
80cc9f10 PO	38
	39	#define UCODE_MAGIC 0x00414d44
	40	#define UCODE_EQUIV_CPU_TABLE_TYPE 0x00000000
	41	#define UCODE_UCODE_TYPE 0x00000001
	42
18dbc916	43	struct equiv_cpu_entry {
5549b94b AH	44	u32 installed_cpu;
	45	u32 fixed_errata_mask;
	46	u32 fixed_errata_compare;
	47	u16 equiv_cpu;
	48	u16 res;
	49	} __attribute__((packed));
18dbc916 DA	50
18dbc916 DA	51	struct microcode_header_amd {
5549b94b AH	52	u32 data_code;
	53	u32 patch_id;
	54	u16 mc_patch_data_id;
	55	u8 mc_patch_data_len;
	56	u8 init_flag;
	57	u32 mc_patch_data_checksum;
	58	u32 nb_dev_id;
	59	u32 sb_dev_id;
	60	u16 processor_rev_id;
	61	u8 nb_rev_id;
	62	u8 sb_rev_id;
	63	u8 bios_api_rev;
	64	u8 reserved1[3];
	65	u32 match_reg[8];
	66	} __attribute__((packed));
18dbc916 DA	67
18dbc916 DA	68	struct microcode_amd {
4bae1967 IM	69	struct microcode_header_amd hdr;
4bae1967 IM	70	unsigned int mpb[0];
18dbc916 DA	71	};
18dbc916 DA	72
40b7f3df BP	73	#define SECTION_HDR_SIZE 8
40b7f3df BP	74	#define CONTAINER_HDR_SZ 12
80cc9f10	75
a0a29b62	76	static struct equiv_cpu_entry *equiv_cpu_table;
80cc9f10	77
a3eb3b4d BP	78	struct ucode_patch {
	79	struct list_head plist;
	80	void *data;
	81	u32 patch_id;
	82	u16 equiv_cpu;
	83	};
	84
	85	static LIST_HEAD(pcache);
	86
c96d2c09 BP	87	static u16 find_equiv_id(unsigned int cpu)
	88	{
	89	struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
	90	int i = 0;
	91
a3eb3b4d BP	92	if (!equiv_cpu_table)
a3eb3b4d BP	93	return 0;
c96d2c09 BP	94
	95	while (equiv_cpu_table[i].installed_cpu != 0) {
	96	if (uci->cpu_sig.sig == equiv_cpu_table[i].installed_cpu)
	97	return equiv_cpu_table[i].equiv_cpu;
	98
	99	i++;
	100	}
	101	return 0;
	102	}
	103
	104	static u32 find_cpu_family_by_equiv_cpu(u16 equiv_cpu)
	105	{
	106	int i = 0;
	107
	108	BUG_ON(!equiv_cpu_table);
	109
	110	while (equiv_cpu_table[i].equiv_cpu != 0) {
	111	if (equiv_cpu == equiv_cpu_table[i].equiv_cpu)
	112	return equiv_cpu_table[i].installed_cpu;
	113	i++;
	114	}
	115	return 0;
	116	}
	117
a3eb3b4d BP	118	/*
	119	* a small, trivial cache of per-family ucode patches
	120	*/
	121	static struct ucode_patch *cache_find_patch(u16 equiv_cpu)
	122	{
	123	struct ucode_patch *p;
	124
	125	list_for_each_entry(p, &pcache, plist)
	126	if (p->equiv_cpu == equiv_cpu)
	127	return p;
	128	return NULL;
	129	}
	130
	131	static void update_cache(struct ucode_patch *new_patch)
	132	{
	133	struct ucode_patch *p;
	134
	135	list_for_each_entry(p, &pcache, plist) {
	136	if (p->equiv_cpu == new_patch->equiv_cpu) {
	137	if (p->patch_id >= new_patch->patch_id)
	138	/* we already have the latest patch */
	139	return;
	140
	141	list_replace(&p->plist, &new_patch->plist);
	142	kfree(p->data);
	143	kfree(p);
	144	return;
	145	}
	146	}
	147	/* no patch found, add it */
	148	list_add_tail(&new_patch->plist, &pcache);
	149	}
	150
	151	static void free_cache(void)
	152	{
2d297480	153	struct ucode_patch p, tmp;
a3eb3b4d	154
2d297480	155	list_for_each_entry_safe(p, tmp, &pcache, plist) {
a3eb3b4d BP	156	__list_del(p->plist.prev, p->plist.next);
	157	kfree(p->data);
	158	kfree(p);
	159	}
	160	}
	161
	162	static struct ucode_patch *find_patch(unsigned int cpu)
	163	{
	164	u16 equiv_id;
	165
	166	equiv_id = find_equiv_id(cpu);
	167	if (!equiv_id)
	168	return NULL;
	169
	170	return cache_find_patch(equiv_id);
	171	}
	172
d45de409	173	static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig)
80cc9f10	174	{
3b2e3d85	175	struct cpuinfo_x86 *c = &cpu_data(cpu);
80cc9f10	176
5f5b7472	177	csig->sig = cpuid_eax(0x00000001);
bcb80e53	178	csig->rev = c->microcode;
258721ef BP	179	pr_info("CPU%d: patch_level=0x%08x\n", cpu, csig->rev);
258721ef BP	180
d45de409	181	return 0;
80cc9f10 PO	182	}
80cc9f10 PO	183
2efb05e8	184	static unsigned int verify_patch_size(int cpu, u32 patch_size,
be62adb4	185	unsigned int size)
80cc9f10	186	{
be62adb4 BP	187	struct cpuinfo_x86 *c = &cpu_data(cpu);
	188	u32 max_size;
	189
	190	#define F1XH_MPB_MAX_SIZE 2048
	191	#define F14H_MPB_MAX_SIZE 1824
	192	#define F15H_MPB_MAX_SIZE 4096
36c46ca4	193	#define F16H_MPB_MAX_SIZE 3458
be62adb4 BP	194
	195	switch (c->x86) {
	196	case 0x14:
	197	max_size = F14H_MPB_MAX_SIZE;
	198	break;
	199	case 0x15:
	200	max_size = F15H_MPB_MAX_SIZE;
	201	break;
36c46ca4 BO	202	case 0x16:
	203	max_size = F16H_MPB_MAX_SIZE;
	204	break;
be62adb4 BP	205	default:
	206	max_size = F1XH_MPB_MAX_SIZE;
	207	break;
	208	}
	209
	210	if (patch_size > min_t(u32, size, max_size)) {
	211	pr_err("patch size mismatch\n");
	212	return 0;
	213	}
	214
	215	return patch_size;
	216	}
	217
871b72dd	218	static int apply_microcode_amd(int cpu)
80cc9f10	219	{
bcb80e53	220	struct cpuinfo_x86 *c = &cpu_data(cpu);
2efb05e8 BP	221	struct microcode_amd *mc_amd;
	222	struct ucode_cpu_info *uci;
	223	struct ucode_patch *p;
	224	u32 rev, dummy;
	225
	226	BUG_ON(raw_smp_processor_id() != cpu);
80cc9f10	227
2efb05e8	228	uci = ucode_cpu_info + cpu;
80cc9f10	229
2efb05e8 BP	230	p = find_patch(cpu);
2efb05e8 BP	231	if (!p)
871b72dd	232	return 0;
80cc9f10	233
2efb05e8 BP	234	mc_amd = p->data;
	235	uci->mc = p->data;
	236
29d0887f	237	rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
80cc9f10	238
685ca6d7 BP	239	/* need to apply patch? */
	240	if (rev >= mc_amd->hdr.patch_id) {
	241	c->microcode = rev;
	242	return 0;
	243	}
	244
	245	wrmsrl(MSR_AMD64_PATCH_LOADER, (u64)(long)&mc_amd->hdr.data_code);
	246
	247	/* verify patch application was successful */
	248	rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
18dbc916	249	if (rev != mc_amd->hdr.patch_id) {
258721ef	250	pr_err("CPU%d: update failed for patch_level=0x%08x\n",
f58e1f53	251	cpu, mc_amd->hdr.patch_id);
871b72dd	252	return -1;
80cc9f10 PO	253	}
80cc9f10 PO	254
258721ef	255	pr_info("CPU%d: new patch_level=0x%08x\n", cpu, rev);
d45de409	256	uci->cpu_sig.rev = rev;
bcb80e53	257	c->microcode = rev;
871b72dd DA	258
871b72dd DA	259	return 0;
80cc9f10 PO	260	}
80cc9f10 PO	261
0657d9eb	262	static int install_equiv_cpu_table(const u8 *buf)
80cc9f10	263	{
10de52d6 BP	264	unsigned int ibuf = (unsigned int )buf;
	265	unsigned int type = ibuf[1];
	266	unsigned int size = ibuf[2];
80cc9f10	267
10de52d6	268	if (type != UCODE_EQUIV_CPU_TABLE_TYPE \|\| !size) {
258721ef BP	269	pr_err("empty section/"
258721ef BP	270	"invalid type field in container file section header\n");
10de52d6	271	return -EINVAL;
80cc9f10 PO	272	}
80cc9f10 PO	273
8e5e9521	274	equiv_cpu_table = vmalloc(size);
80cc9f10	275	if (!equiv_cpu_table) {
f58e1f53	276	pr_err("failed to allocate equivalent CPU table\n");
10de52d6	277	return -ENOMEM;
80cc9f10 PO	278	}
80cc9f10 PO	279
e7e632f5	280	memcpy(equiv_cpu_table, buf + CONTAINER_HDR_SZ, size);
80cc9f10	281
40b7f3df BP	282	/* add header length */
40b7f3df BP	283	return size + CONTAINER_HDR_SZ;
80cc9f10 PO	284	}
80cc9f10 PO	285
a0a29b62	286	static void free_equiv_cpu_table(void)
80cc9f10	287	{
aeef50bc F	288	vfree(equiv_cpu_table);
aeef50bc F	289	equiv_cpu_table = NULL;
a0a29b62	290	}
80cc9f10	291
2efb05e8	292	static void cleanup(void)
a0a29b62	293	{
2efb05e8 BP	294	free_equiv_cpu_table();
	295	free_cache();
	296	}
	297
	298	/*
	299	* We return the current size even if some of the checks failed so that
	300	* we can skip over the next patch. If we return a negative value, we
	301	* signal a grave error like a memory allocation has failed and the
	302	* driver cannot continue functioning normally. In such cases, we tear
	303	* down everything we've used up so far and exit.
	304	*/
	305	static int verify_and_add_patch(unsigned int cpu, u8 *fw, unsigned int leftover)
	306	{
	307	struct cpuinfo_x86 *c = &cpu_data(cpu);
	308	struct microcode_header_amd *mc_hdr;
	309	struct ucode_patch *patch;
	310	unsigned int patch_size, crnt_size, ret;
	311	u32 proc_fam;
	312	u16 proc_id;
	313
	314	patch_size = (u32 )(fw + 4);
	315	crnt_size = patch_size + SECTION_HDR_SIZE;
	316	mc_hdr = (struct microcode_header_amd *)(fw + SECTION_HDR_SIZE);
	317	proc_id = mc_hdr->processor_rev_id;
	318
	319	proc_fam = find_cpu_family_by_equiv_cpu(proc_id);
	320	if (!proc_fam) {
	321	pr_err("No patch family for equiv ID: 0x%04x\n", proc_id);
	322	return crnt_size;
	323	}
	324
	325	/* check if patch is for the current family */
	326	proc_fam = ((proc_fam >> 8) & 0xf) + ((proc_fam >> 20) & 0xff);
	327	if (proc_fam != c->x86)
	328	return crnt_size;
	329
	330	if (mc_hdr->nb_dev_id \|\| mc_hdr->sb_dev_id) {
	331	pr_err("Patch-ID 0x%08x: chipset-specific code unsupported.\n",
	332	mc_hdr->patch_id);
	333	return crnt_size;
	334	}
	335
	336	ret = verify_patch_size(cpu, patch_size, leftover);
	337	if (!ret) {
	338	pr_err("Patch-ID 0x%08x: size mismatch.\n", mc_hdr->patch_id);
	339	return crnt_size;
	340	}
	341
	342	patch = kzalloc(sizeof(*patch), GFP_KERNEL);
	343	if (!patch) {
	344	pr_err("Patch allocation failure.\n");
	345	return -EINVAL;
	346	}
	347
	348	patch->data = kzalloc(patch_size, GFP_KERNEL);
	349	if (!patch->data) {
	350	pr_err("Patch data allocation failure.\n");
	351	kfree(patch);
	352	return -EINVAL;
	353	}
	354
	355	/* All looks ok, copy patch... */
	356	memcpy(patch->data, fw + SECTION_HDR_SIZE, patch_size);
	357	INIT_LIST_HEAD(&patch->plist);
358	patch->patch_id = mc_hdr->patch_id;
359	patch->equiv_cpu = proc_id;
360
361	/* ... and add to cache. */
362	update_cache(patch);
363
364	return crnt_size;
365	}
366
367	static enum ucode_state load_microcode_amd(int cpu, const u8 *data, size_t size)
368	{
369	enum ucode_state ret = UCODE_ERROR;
370	unsigned int leftover;
371	u8 fw = (u8 )data;
372	int crnt_size = 0;
1396fa9c	373	int offset;
80cc9f10	374
2efb05e8	375	offset = install_equiv_cpu_table(data);
10de52d6	376	if (offset < 0) {
f58e1f53	377	pr_err("failed to create equivalent cpu table\n");
2efb05e8	378	return ret;
80cc9f10	379	}
2efb05e8	380	fw += offset;
a0a29b62 DA	381	leftover = size - offset;
a0a29b62 DA	382
2efb05e8	383	if ((u32 )fw != UCODE_UCODE_TYPE) {
be62adb4	384	pr_err("invalid type field in container file section header\n");
2efb05e8 BP	385	free_equiv_cpu_table();
2efb05e8 BP	386	return ret;
be62adb4	387	}
a0a29b62	388
be62adb4	389	while (leftover) {
2efb05e8 BP	390	crnt_size = verify_and_add_patch(cpu, fw, leftover);
	391	if (crnt_size < 0)
	392	return ret;
d733689a	393
2efb05e8 BP	394	fw += crnt_size;
2efb05e8 BP	395	leftover -= crnt_size;
80cc9f10	396	}
a0a29b62	397
2efb05e8	398	return UCODE_OK;
a0a29b62 DA	399	}
a0a29b62 DA	400
5b68edc9 AH	401	/*
	402	* AMD microcode firmware naming convention, up to family 15h they are in
	403	* the legacy file:
	404	*
	405	* amd-ucode/microcode_amd.bin
	406	*
	407	* This legacy file is always smaller than 2K in size.
	408	*
2efb05e8	409	* Beginning with family 15h, they are in family-specific firmware files:
5b68edc9 AH	410	*
	411	* amd-ucode/microcode_amd_fam15h.bin
	412	* amd-ucode/microcode_amd_fam16h.bin
	413	* ...
	414	*
	415	* These might be larger than 2K.
	416	*/
48e30685 BP	417	static enum ucode_state request_microcode_amd(int cpu, struct device *device,
48e30685 BP	418	bool refresh_fw)
a0a29b62	419	{
5b68edc9	420	char fw_name[36] = "amd-ucode/microcode_amd.bin";
5b68edc9	421	struct cpuinfo_x86 *c = &cpu_data(cpu);
2efb05e8 BP	422	enum ucode_state ret = UCODE_NFOUND;
	423	const struct firmware *fw;
	424
	425	/* reload ucode container only on the boot cpu */
	426	if (!refresh_fw \|\| c->cpu_index != boot_cpu_data.cpu_index)
	427	return UCODE_OK;
5b68edc9 AH	428
	429	if (c->x86 >= 0x15)
	430	snprintf(fw_name, sizeof(fw_name), "amd-ucode/microcode_amd_fam%.2xh.bin", c->x86);
a0a29b62	431
5b68edc9	432	if (request_firmware(&fw, (const char *)fw_name, device)) {
258721ef	433	pr_err("failed to load file %s\n", fw_name);
ffc7e8ac	434	goto out;
3b2e3d85	435	}
a0a29b62	436
ffc7e8ac BP	437	ret = UCODE_ERROR;
ffc7e8ac BP	438	if ((u32 )fw->data != UCODE_MAGIC) {
258721ef	439	pr_err("invalid magic value (0x%08x)\n", (u32 )fw->data);
ffc7e8ac	440	goto fw_release;
506f90ee BP	441	}
506f90ee BP	442
2efb05e8 BP	443	/* free old equiv table */
	444	free_equiv_cpu_table();
	445
	446	ret = load_microcode_amd(cpu, fw->data, fw->size);
	447	if (ret != UCODE_OK)
	448	cleanup();
a0a29b62	449
2efb05e8	450	fw_release:
ffc7e8ac	451	release_firmware(fw);
3b2e3d85	452
2efb05e8	453	out:
a0a29b62 DA	454	return ret;
	455	}
	456
871b72dd DA	457	static enum ucode_state
871b72dd DA	458	request_microcode_user(int cpu, const void __user *buf, size_t size)
a0a29b62	459	{
871b72dd	460	return UCODE_ERROR;
80cc9f10 PO	461	}
80cc9f10 PO	462
80cc9f10 PO	463	static void microcode_fini_cpu_amd(int cpu)
	464	{
	465	struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
	466
18dbc916	467	uci->mc = NULL;
80cc9f10 PO	468	}
	469
	470	static struct microcode_ops microcode_amd_ops = {
a0a29b62	471	.request_microcode_user = request_microcode_user,
ffc7e8ac	472	.request_microcode_fw = request_microcode_amd,
80cc9f10 PO	473	.collect_cpu_info = collect_cpu_info_amd,
	474	.apply_microcode = apply_microcode_amd,
	475	.microcode_fini_cpu = microcode_fini_cpu_amd,
	476	};
	477
18dbc916	478	struct microcode_ops * __init init_amd_microcode(void)
80cc9f10	479	{
283c1f25 AH	480	struct cpuinfo_x86 *c = &cpu_data(0);
	481
	482	if (c->x86_vendor != X86_VENDOR_AMD \|\| c->x86 < 0x10) {
	483	pr_warning("AMD CPU family 0x%x not supported\n", c->x86);
	484	return NULL;
	485	}
	486
18dbc916	487	return &microcode_amd_ops;
80cc9f10	488	}
f72c1a57 BP	489
	490	void __exit exit_amd_microcode(void)
	491	{
2efb05e8	492	cleanup();
f72c1a57	493	}