Commit | Line | Data |
---|---|---|
80cc9f10 PO |
1 | /* |
2 | * AMD CPU Microcode Update Driver for Linux | |
597e11a3 | 3 | * Copyright (C) 2008-2011 Advanced Micro Devices Inc. |
80cc9f10 PO |
4 | * |
5 | * Author: Peter Oruba <peter.oruba@amd.com> | |
6 | * | |
7 | * Based on work by: | |
8 | * Tigran Aivazian <tigran@aivazian.fsnet.co.uk> | |
9 | * | |
597e11a3 BP |
10 | * Maintainers: |
11 | * Andreas Herrmann <andreas.herrmann3@amd.com> | |
12 | * Borislav Petkov <borislav.petkov@amd.com> | |
13 | * | |
14 | * This driver allows to upgrade microcode on F10h AMD | |
15 | * CPUs and later. | |
80cc9f10 | 16 | * |
2a3282a7 | 17 | * Licensed under the terms of the GNU General Public |
80cc9f10 | 18 | * License version 2. See file COPYING for details. |
4bae1967 | 19 | */ |
f58e1f53 JP |
20 | |
21 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
22 | ||
4bae1967 | 23 | #include <linux/firmware.h> |
4bae1967 IM |
24 | #include <linux/pci_ids.h> |
25 | #include <linux/uaccess.h> | |
26 | #include <linux/vmalloc.h> | |
27 | #include <linux/kernel.h> | |
28 | #include <linux/module.h> | |
80cc9f10 | 29 | #include <linux/pci.h> |
80cc9f10 | 30 | |
80cc9f10 | 31 | #include <asm/microcode.h> |
4bae1967 IM |
32 | #include <asm/processor.h> |
33 | #include <asm/msr.h> | |
80cc9f10 PO |
34 | |
35 | MODULE_DESCRIPTION("AMD Microcode Update Driver"); | |
3c52204b | 36 | MODULE_AUTHOR("Peter Oruba"); |
5d7b6052 | 37 | MODULE_LICENSE("GPL v2"); |
80cc9f10 PO |
38 | |
39 | #define UCODE_MAGIC 0x00414d44 | |
40 | #define UCODE_EQUIV_CPU_TABLE_TYPE 0x00000000 | |
41 | #define UCODE_UCODE_TYPE 0x00000001 | |
42 | ||
18dbc916 | 43 | struct equiv_cpu_entry { |
5549b94b AH |
44 | u32 installed_cpu; |
45 | u32 fixed_errata_mask; | |
46 | u32 fixed_errata_compare; | |
47 | u16 equiv_cpu; | |
48 | u16 res; | |
49 | } __attribute__((packed)); | |
18dbc916 DA |
50 | |
51 | struct microcode_header_amd { | |
5549b94b AH |
52 | u32 data_code; |
53 | u32 patch_id; | |
54 | u16 mc_patch_data_id; | |
55 | u8 mc_patch_data_len; | |
56 | u8 init_flag; | |
57 | u32 mc_patch_data_checksum; | |
58 | u32 nb_dev_id; | |
59 | u32 sb_dev_id; | |
60 | u16 processor_rev_id; | |
61 | u8 nb_rev_id; | |
62 | u8 sb_rev_id; | |
63 | u8 bios_api_rev; | |
64 | u8 reserved1[3]; | |
65 | u32 match_reg[8]; | |
66 | } __attribute__((packed)); | |
18dbc916 DA |
67 | |
68 | struct microcode_amd { | |
4bae1967 IM |
69 | struct microcode_header_amd hdr; |
70 | unsigned int mpb[0]; | |
18dbc916 DA |
71 | }; |
72 | ||
40b7f3df BP |
73 | #define SECTION_HDR_SIZE 8 |
74 | #define CONTAINER_HDR_SZ 12 | |
80cc9f10 | 75 | |
a0a29b62 | 76 | static struct equiv_cpu_entry *equiv_cpu_table; |
80cc9f10 | 77 | |
96b0ee45 BP |
78 | /* page-sized ucode patch buffer */ |
79 | void *patch; | |
80 | ||
d45de409 | 81 | static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig) |
80cc9f10 | 82 | { |
3b2e3d85 | 83 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
80cc9f10 | 84 | |
bcb80e53 | 85 | csig->rev = c->microcode; |
258721ef BP |
86 | pr_info("CPU%d: patch_level=0x%08x\n", cpu, csig->rev); |
87 | ||
d45de409 | 88 | return 0; |
80cc9f10 PO |
89 | } |
90 | ||
be62adb4 BP |
91 | static unsigned int verify_ucode_size(int cpu, u32 patch_size, |
92 | unsigned int size) | |
80cc9f10 | 93 | { |
be62adb4 BP |
94 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
95 | u32 max_size; | |
96 | ||
97 | #define F1XH_MPB_MAX_SIZE 2048 | |
98 | #define F14H_MPB_MAX_SIZE 1824 | |
99 | #define F15H_MPB_MAX_SIZE 4096 | |
100 | ||
101 | switch (c->x86) { | |
102 | case 0x14: | |
103 | max_size = F14H_MPB_MAX_SIZE; | |
104 | break; | |
105 | case 0x15: | |
106 | max_size = F15H_MPB_MAX_SIZE; | |
107 | break; | |
108 | default: | |
109 | max_size = F1XH_MPB_MAX_SIZE; | |
110 | break; | |
111 | } | |
112 | ||
113 | if (patch_size > min_t(u32, size, max_size)) { | |
114 | pr_err("patch size mismatch\n"); | |
115 | return 0; | |
116 | } | |
117 | ||
118 | return patch_size; | |
119 | } | |
120 | ||
121 | static u16 find_equiv_id(void) | |
122 | { | |
123 | unsigned int current_cpu_id, i = 0; | |
80cc9f10 | 124 | |
a0a29b62 | 125 | BUG_ON(equiv_cpu_table == NULL); |
be62adb4 | 126 | |
80cc9f10 PO |
127 | current_cpu_id = cpuid_eax(0x00000001); |
128 | ||
129 | while (equiv_cpu_table[i].installed_cpu != 0) { | |
be62adb4 BP |
130 | if (current_cpu_id == equiv_cpu_table[i].installed_cpu) |
131 | return equiv_cpu_table[i].equiv_cpu; | |
132 | ||
80cc9f10 PO |
133 | i++; |
134 | } | |
be62adb4 BP |
135 | return 0; |
136 | } | |
80cc9f10 | 137 | |
be62adb4 BP |
138 | /* |
139 | * we signal a good patch is found by returning its size > 0 | |
140 | */ | |
141 | static int get_matching_microcode(int cpu, const u8 *ucode_ptr, | |
142 | unsigned int leftover_size, int rev, | |
143 | unsigned int *current_size) | |
144 | { | |
145 | struct microcode_header_amd *mc_hdr; | |
36bf50d7 | 146 | unsigned int actual_size, patch_size; |
be62adb4 BP |
147 | u16 equiv_cpu_id; |
148 | ||
149 | /* size of the current patch we're staring at */ | |
36bf50d7 AH |
150 | patch_size = *(u32 *)(ucode_ptr + 4); |
151 | *current_size = patch_size + SECTION_HDR_SIZE; | |
be62adb4 BP |
152 | |
153 | equiv_cpu_id = find_equiv_id(); | |
14c56942 | 154 | if (!equiv_cpu_id) |
80cc9f10 | 155 | return 0; |
80cc9f10 | 156 | |
be62adb4 BP |
157 | /* |
158 | * let's look at the patch header itself now | |
159 | */ | |
160 | mc_hdr = (struct microcode_header_amd *)(ucode_ptr + SECTION_HDR_SIZE); | |
161 | ||
7cc27349 | 162 | if (mc_hdr->processor_rev_id != equiv_cpu_id) |
80cc9f10 | 163 | return 0; |
80cc9f10 | 164 | |
98415301 | 165 | /* ucode might be chipset specific -- currently we don't support this */ |
7cc27349 | 166 | if (mc_hdr->nb_dev_id || mc_hdr->sb_dev_id) { |
258721ef | 167 | pr_err("CPU%d: chipset specific code not yet supported\n", |
f58e1f53 | 168 | cpu); |
98415301 | 169 | return 0; |
80cc9f10 PO |
170 | } |
171 | ||
7cc27349 | 172 | if (mc_hdr->patch_id <= rev) |
80cc9f10 PO |
173 | return 0; |
174 | ||
be62adb4 BP |
175 | /* |
176 | * now that the header looks sane, verify its size | |
177 | */ | |
36bf50d7 | 178 | actual_size = verify_ucode_size(cpu, patch_size, leftover_size); |
be62adb4 BP |
179 | if (!actual_size) |
180 | return 0; | |
181 | ||
182 | /* clear the patch buffer */ | |
183 | memset(patch, 0, PAGE_SIZE); | |
184 | ||
185 | /* all looks ok, get the binary patch */ | |
186 | get_ucode_data(patch, ucode_ptr + SECTION_HDR_SIZE, actual_size); | |
187 | ||
188 | return actual_size; | |
80cc9f10 PO |
189 | } |
190 | ||
871b72dd | 191 | static int apply_microcode_amd(int cpu) |
80cc9f10 | 192 | { |
29d0887f | 193 | u32 rev, dummy; |
80cc9f10 PO |
194 | int cpu_num = raw_smp_processor_id(); |
195 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu_num; | |
18dbc916 | 196 | struct microcode_amd *mc_amd = uci->mc; |
bcb80e53 | 197 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
80cc9f10 PO |
198 | |
199 | /* We should bind the task to the CPU */ | |
200 | BUG_ON(cpu_num != cpu); | |
201 | ||
18dbc916 | 202 | if (mc_amd == NULL) |
871b72dd | 203 | return 0; |
80cc9f10 | 204 | |
f34a10bd | 205 | wrmsrl(MSR_AMD64_PATCH_LOADER, (u64)(long)&mc_amd->hdr.data_code); |
80cc9f10 | 206 | /* get patch id after patching */ |
29d0887f | 207 | rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy); |
80cc9f10 PO |
208 | |
209 | /* check current patch id and patch's id for match */ | |
18dbc916 | 210 | if (rev != mc_amd->hdr.patch_id) { |
258721ef | 211 | pr_err("CPU%d: update failed for patch_level=0x%08x\n", |
f58e1f53 | 212 | cpu, mc_amd->hdr.patch_id); |
871b72dd | 213 | return -1; |
80cc9f10 PO |
214 | } |
215 | ||
258721ef | 216 | pr_info("CPU%d: new patch_level=0x%08x\n", cpu, rev); |
d45de409 | 217 | uci->cpu_sig.rev = rev; |
bcb80e53 | 218 | c->microcode = rev; |
871b72dd DA |
219 | |
220 | return 0; | |
80cc9f10 PO |
221 | } |
222 | ||
0657d9eb | 223 | static int install_equiv_cpu_table(const u8 *buf) |
80cc9f10 | 224 | { |
10de52d6 BP |
225 | unsigned int *ibuf = (unsigned int *)buf; |
226 | unsigned int type = ibuf[1]; | |
227 | unsigned int size = ibuf[2]; | |
80cc9f10 | 228 | |
10de52d6 | 229 | if (type != UCODE_EQUIV_CPU_TABLE_TYPE || !size) { |
258721ef BP |
230 | pr_err("empty section/" |
231 | "invalid type field in container file section header\n"); | |
10de52d6 | 232 | return -EINVAL; |
80cc9f10 PO |
233 | } |
234 | ||
8e5e9521 | 235 | equiv_cpu_table = vmalloc(size); |
80cc9f10 | 236 | if (!equiv_cpu_table) { |
f58e1f53 | 237 | pr_err("failed to allocate equivalent CPU table\n"); |
10de52d6 | 238 | return -ENOMEM; |
80cc9f10 PO |
239 | } |
240 | ||
40b7f3df | 241 | get_ucode_data(equiv_cpu_table, buf + CONTAINER_HDR_SZ, size); |
80cc9f10 | 242 | |
40b7f3df BP |
243 | /* add header length */ |
244 | return size + CONTAINER_HDR_SZ; | |
80cc9f10 PO |
245 | } |
246 | ||
a0a29b62 | 247 | static void free_equiv_cpu_table(void) |
80cc9f10 | 248 | { |
aeef50bc F |
249 | vfree(equiv_cpu_table); |
250 | equiv_cpu_table = NULL; | |
a0a29b62 | 251 | } |
80cc9f10 | 252 | |
871b72dd DA |
253 | static enum ucode_state |
254 | generic_load_microcode(int cpu, const u8 *data, size_t size) | |
a0a29b62 DA |
255 | { |
256 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; | |
7cc27349 | 257 | struct microcode_header_amd *mc_hdr = NULL; |
be62adb4 | 258 | unsigned int mc_size, leftover, current_size = 0; |
1396fa9c | 259 | int offset; |
8c135206 AH |
260 | const u8 *ucode_ptr = data; |
261 | void *new_mc = NULL; | |
258721ef | 262 | unsigned int new_rev = uci->cpu_sig.rev; |
be62adb4 | 263 | enum ucode_state state = UCODE_ERROR; |
80cc9f10 | 264 | |
0657d9eb | 265 | offset = install_equiv_cpu_table(ucode_ptr); |
10de52d6 | 266 | if (offset < 0) { |
f58e1f53 | 267 | pr_err("failed to create equivalent cpu table\n"); |
be62adb4 | 268 | goto out; |
80cc9f10 | 269 | } |
a0a29b62 DA |
270 | ucode_ptr += offset; |
271 | leftover = size - offset; | |
272 | ||
be62adb4 BP |
273 | if (*(u32 *)ucode_ptr != UCODE_UCODE_TYPE) { |
274 | pr_err("invalid type field in container file section header\n"); | |
275 | goto free_table; | |
276 | } | |
a0a29b62 | 277 | |
be62adb4 BP |
278 | while (leftover) { |
279 | mc_size = get_matching_microcode(cpu, ucode_ptr, leftover, | |
280 | new_rev, ¤t_size); | |
281 | if (mc_size) { | |
282 | mc_hdr = patch; | |
283 | new_mc = patch; | |
7cc27349 | 284 | new_rev = mc_hdr->patch_id; |
d733689a | 285 | goto out_ok; |
be62adb4 | 286 | } |
d733689a BP |
287 | |
288 | ucode_ptr += current_size; | |
289 | leftover -= current_size; | |
80cc9f10 | 290 | } |
a0a29b62 | 291 | |
7cc27349 | 292 | if (!new_mc) { |
871b72dd | 293 | state = UCODE_NFOUND; |
7cc27349 BP |
294 | goto free_table; |
295 | } | |
296 | ||
d733689a BP |
297 | out_ok: |
298 | uci->mc = new_mc; | |
299 | state = UCODE_OK; | |
300 | pr_debug("CPU%d update ucode (0x%08x -> 0x%08x)\n", | |
301 | cpu, uci->cpu_sig.rev, new_rev); | |
a0a29b62 | 302 | |
7cc27349 | 303 | free_table: |
a0a29b62 DA |
304 | free_equiv_cpu_table(); |
305 | ||
be62adb4 | 306 | out: |
871b72dd | 307 | return state; |
a0a29b62 DA |
308 | } |
309 | ||
5b68edc9 AH |
310 | /* |
311 | * AMD microcode firmware naming convention, up to family 15h they are in | |
312 | * the legacy file: | |
313 | * | |
314 | * amd-ucode/microcode_amd.bin | |
315 | * | |
316 | * This legacy file is always smaller than 2K in size. | |
317 | * | |
318 | * Starting at family 15h they are in family specific firmware files: | |
319 | * | |
320 | * amd-ucode/microcode_amd_fam15h.bin | |
321 | * amd-ucode/microcode_amd_fam16h.bin | |
322 | * ... | |
323 | * | |
324 | * These might be larger than 2K. | |
325 | */ | |
ffc7e8ac | 326 | static enum ucode_state request_microcode_amd(int cpu, struct device *device) |
a0a29b62 | 327 | { |
5b68edc9 | 328 | char fw_name[36] = "amd-ucode/microcode_amd.bin"; |
ffc7e8ac BP |
329 | const struct firmware *fw; |
330 | enum ucode_state ret = UCODE_NFOUND; | |
5b68edc9 AH |
331 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
332 | ||
333 | if (c->x86 >= 0x15) | |
334 | snprintf(fw_name, sizeof(fw_name), "amd-ucode/microcode_amd_fam%.2xh.bin", c->x86); | |
a0a29b62 | 335 | |
5b68edc9 | 336 | if (request_firmware(&fw, (const char *)fw_name, device)) { |
258721ef | 337 | pr_err("failed to load file %s\n", fw_name); |
ffc7e8ac | 338 | goto out; |
3b2e3d85 | 339 | } |
a0a29b62 | 340 | |
ffc7e8ac BP |
341 | ret = UCODE_ERROR; |
342 | if (*(u32 *)fw->data != UCODE_MAGIC) { | |
258721ef | 343 | pr_err("invalid magic value (0x%08x)\n", *(u32 *)fw->data); |
ffc7e8ac | 344 | goto fw_release; |
506f90ee BP |
345 | } |
346 | ||
ffc7e8ac | 347 | ret = generic_load_microcode(cpu, fw->data, fw->size); |
a0a29b62 | 348 | |
ffc7e8ac BP |
349 | fw_release: |
350 | release_firmware(fw); | |
3b2e3d85 | 351 | |
ffc7e8ac | 352 | out: |
a0a29b62 DA |
353 | return ret; |
354 | } | |
355 | ||
871b72dd DA |
356 | static enum ucode_state |
357 | request_microcode_user(int cpu, const void __user *buf, size_t size) | |
a0a29b62 | 358 | { |
871b72dd | 359 | return UCODE_ERROR; |
80cc9f10 PO |
360 | } |
361 | ||
80cc9f10 PO |
362 | static void microcode_fini_cpu_amd(int cpu) |
363 | { | |
364 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; | |
365 | ||
18dbc916 | 366 | uci->mc = NULL; |
80cc9f10 PO |
367 | } |
368 | ||
369 | static struct microcode_ops microcode_amd_ops = { | |
a0a29b62 | 370 | .request_microcode_user = request_microcode_user, |
ffc7e8ac | 371 | .request_microcode_fw = request_microcode_amd, |
80cc9f10 PO |
372 | .collect_cpu_info = collect_cpu_info_amd, |
373 | .apply_microcode = apply_microcode_amd, | |
374 | .microcode_fini_cpu = microcode_fini_cpu_amd, | |
375 | }; | |
376 | ||
18dbc916 | 377 | struct microcode_ops * __init init_amd_microcode(void) |
80cc9f10 | 378 | { |
283c1f25 AH |
379 | struct cpuinfo_x86 *c = &cpu_data(0); |
380 | ||
381 | if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) { | |
382 | pr_warning("AMD CPU family 0x%x not supported\n", c->x86); | |
383 | return NULL; | |
384 | } | |
385 | ||
96b0ee45 BP |
386 | patch = (void *)get_zeroed_page(GFP_KERNEL); |
387 | if (!patch) | |
388 | return NULL; | |
389 | ||
18dbc916 | 390 | return µcode_amd_ops; |
80cc9f10 | 391 | } |
f72c1a57 BP |
392 | |
393 | void __exit exit_amd_microcode(void) | |
394 | { | |
96b0ee45 | 395 | free_page((unsigned long)patch); |
f72c1a57 | 396 | } |