[deliverable/linux.git] / arch / x86 / kernel / microcode_amd.c

/*
 *  AMD CPU Microcode Update Driver for Linux
 *  Copyright (C) 2008-2011 Advanced Micro Devices Inc.
 *
 *  Author: Peter Oruba <peter.oruba@amd.com>
 *
 *  Based on work by:
 *  Tigran Aivazian <tigran@aivazian.fsnet.co.uk>
 *
 *  Maintainers:
 *  Andreas Herrmann <herrmann.der.user@googlemail.com>
 *  Borislav Petkov <bp@alien8.de>
 *
 *  This driver allows to upgrade microcode on F10h AMD
 *  CPUs and later.
 *
 *  Licensed under the terms of the GNU General Public
 *  License version 2. See file COPYING for details.
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/firmware.h>
#include <linux/pci_ids.h>
#include <linux/uaccess.h>
#include <linux/vmalloc.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>

#include <asm/microcode.h>
#include <asm/processor.h>
#include <asm/msr.h>
#include <asm/microcode_amd.h>

MODULE_DESCRIPTION("AMD Microcode Update Driver");
MODULE_AUTHOR("Peter Oruba");
MODULE_LICENSE("GPL v2");

static struct equiv_cpu_entry *equiv_cpu_table;

struct ucode_patch {
	struct list_head plist;
	void *data;
	u32 patch_id;
	u16 equiv_cpu;
};

static LIST_HEAD(pcache);

static u16 __find_equiv_id(unsigned int cpu)
{
	struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
	return find_equiv_id(equiv_cpu_table, uci->cpu_sig.sig);
}

static u32 find_cpu_family_by_equiv_cpu(u16 equiv_cpu)
{
	int i = 0;

	BUG_ON(!equiv_cpu_table);

	while (equiv_cpu_table[i].equiv_cpu != 0) {
		if (equiv_cpu == equiv_cpu_table[i].equiv_cpu)
			return equiv_cpu_table[i].installed_cpu;
		i++;
	}
	return 0;
}

/*
 * a small, trivial cache of per-family ucode patches
 */
static struct ucode_patch *cache_find_patch(u16 equiv_cpu)
{
	struct ucode_patch *p;

	list_for_each_entry(p, &pcache, plist)
		if (p->equiv_cpu == equiv_cpu)
			return p;
	return NULL;
}

static void update_cache(struct ucode_patch *new_patch)
{
	struct ucode_patch *p;

	list_for_each_entry(p, &pcache, plist) {
		if (p->equiv_cpu == new_patch->equiv_cpu) {
			if (p->patch_id >= new_patch->patch_id)
				/* we already have the latest patch */
				return;

			list_replace(&p->plist, &new_patch->plist);
			kfree(p->data);
			kfree(p);
			return;
		}
	}
	/* no patch found, add it */
	list_add_tail(&new_patch->plist, &pcache);
}

static void free_cache(void)
{
	struct ucode_patch *p, *tmp;

	list_for_each_entry_safe(p, tmp, &pcache, plist) {
		__list_del(p->plist.prev, p->plist.next);
		kfree(p->data);
		kfree(p);
	}
}

static struct ucode_patch *find_patch(unsigned int cpu)
{
	u16 equiv_id;

	equiv_id = __find_equiv_id(cpu);
	if (!equiv_id)
		return NULL;

	return cache_find_patch(equiv_id);
}

static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig)
{
	struct cpuinfo_x86 *c = &cpu_data(cpu);
	struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
	struct ucode_patch *p;

	csig->sig = cpuid_eax(0x00000001);
	csig->rev = c->microcode;

	/*
	 * a patch could have been loaded early, set uci->mc so that
	 * mc_bp_resume() can call apply_microcode()
	 */
	p = find_patch(cpu);
	if (p && (p->patch_id == csig->rev))
		uci->mc = p->data;

	pr_info("CPU%d: patch_level=0x%08x\n", cpu, csig->rev);

	return 0;
}

static unsigned int verify_patch_size(u8 family, u32 patch_size,
				      unsigned int size)
{
	u32 max_size;

#define F1XH_MPB_MAX_SIZE 2048
#define F14H_MPB_MAX_SIZE 1824
#define F15H_MPB_MAX_SIZE 4096
#define F16H_MPB_MAX_SIZE 3458

	switch (family) {
	case 0x14:
		max_size = F14H_MPB_MAX_SIZE;
		break;
	case 0x15:
		max_size = F15H_MPB_MAX_SIZE;
		break;
	case 0x16:
		max_size = F16H_MPB_MAX_SIZE;
		break;
	default:
		max_size = F1XH_MPB_MAX_SIZE;
		break;
	}

	if (patch_size > min_t(u32, size, max_size)) {
		pr_err("patch size mismatch\n");
		return 0;
	}

	return patch_size;
}

int __apply_microcode_amd(struct microcode_amd *mc_amd)
{
	u32 rev, dummy;

	wrmsrl(MSR_AMD64_PATCH_LOADER, (u64)(long)&mc_amd->hdr.data_code);

	/* verify patch application was successful */
	rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
	if (rev != mc_amd->hdr.patch_id)
		return -1;

	return 0;
}

int apply_microcode_amd(int cpu)
{
	struct cpuinfo_x86 *c = &cpu_data(cpu);
	struct microcode_amd *mc_amd;
	struct ucode_cpu_info *uci;
	struct ucode_patch *p;
	u32 rev, dummy;

	BUG_ON(raw_smp_processor_id() != cpu);

	uci = ucode_cpu_info + cpu;

	p = find_patch(cpu);
	if (!p)
		return 0;

	mc_amd  = p->data;
	uci->mc = p->data;

	rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);

	/* need to apply patch? */
	if (rev >= mc_amd->hdr.patch_id) {
		c->microcode = rev;
		uci->cpu_sig.rev = rev;
		return 0;
	}

	if (__apply_microcode_amd(mc_amd)) {
		pr_err("CPU%d: update failed for patch_level=0x%08x\n",
			cpu, mc_amd->hdr.patch_id);
		return -1;
	}
	pr_info("CPU%d: new patch_level=0x%08x\n", cpu,
		mc_amd->hdr.patch_id);

	uci->cpu_sig.rev = mc_amd->hdr.patch_id;
	c->microcode = mc_amd->hdr.patch_id;

	return 0;
}

static int install_equiv_cpu_table(const u8 *buf)
{
	unsigned int *ibuf = (unsigned int *)buf;
	unsigned int type = ibuf[1];
	unsigned int size = ibuf[2];

	if (type != UCODE_EQUIV_CPU_TABLE_TYPE || !size) {
		pr_err("empty section/"
		       "invalid type field in container file section header\n");
		return -EINVAL;
	}

	equiv_cpu_table = vmalloc(size);
	if (!equiv_cpu_table) {
		pr_err("failed to allocate equivalent CPU table\n");
		return -ENOMEM;
	}

	memcpy(equiv_cpu_table, buf + CONTAINER_HDR_SZ, size);

	/* add header length */
	return size + CONTAINER_HDR_SZ;
}

static void free_equiv_cpu_table(void)
{
	vfree(equiv_cpu_table);
	equiv_cpu_table = NULL;
}

static void cleanup(void)
{
	free_equiv_cpu_table();
	free_cache();
}

/*
 * We return the current size even if some of the checks failed so that
 * we can skip over the next patch. If we return a negative value, we
 * signal a grave error like a memory allocation has failed and the
 * driver cannot continue functioning normally. In such cases, we tear
 * down everything we've used up so far and exit.
 */
static int verify_and_add_patch(u8 family, u8 *fw, unsigned int leftover)
{
	struct microcode_header_amd *mc_hdr;
	struct ucode_patch *patch;
	unsigned int patch_size, crnt_size, ret;
	u32 proc_fam;
	u16 proc_id;

	patch_size  = *(u32 *)(fw + 4);
	crnt_size   = patch_size + SECTION_HDR_SIZE;
	mc_hdr	    = (struct microcode_header_amd *)(fw + SECTION_HDR_SIZE);
	proc_id	    = mc_hdr->processor_rev_id;

	proc_fam = find_cpu_family_by_equiv_cpu(proc_id);
	if (!proc_fam) {
		pr_err("No patch family for equiv ID: 0x%04x\n", proc_id);
		return crnt_size;
	}

	/* check if patch is for the current family */
	proc_fam = ((proc_fam >> 8) & 0xf) + ((proc_fam >> 20) & 0xff);
	if (proc_fam != family)
		return crnt_size;

	if (mc_hdr->nb_dev_id || mc_hdr->sb_dev_id) {
		pr_err("Patch-ID 0x%08x: chipset-specific code unsupported.\n",
			mc_hdr->patch_id);
		return crnt_size;
	}

	ret = verify_patch_size(family, patch_size, leftover);
	if (!ret) {
		pr_err("Patch-ID 0x%08x: size mismatch.\n", mc_hdr->patch_id);
		return crnt_size;
	}

	patch = kzalloc(sizeof(*patch), GFP_KERNEL);
	if (!patch) {
		pr_err("Patch allocation failure.\n");
		return -EINVAL;
	}

	patch->data = kzalloc(patch_size, GFP_KERNEL);
	if (!patch->data) {
		pr_err("Patch data allocation failure.\n");
		kfree(patch);
		return -EINVAL;
	}

	/* All looks ok, copy patch... */
	memcpy(patch->data, fw + SECTION_HDR_SIZE, patch_size);
	INIT_LIST_HEAD(&patch->plist);
	patch->patch_id  = mc_hdr->patch_id;
	patch->equiv_cpu = proc_id;

	/* ... and add to cache. */
	update_cache(patch);

	return crnt_size;
}

static enum ucode_state __load_microcode_amd(u8 family, const u8 *data,
					     size_t size)
{
	enum ucode_state ret = UCODE_ERROR;
	unsigned int leftover;
	u8 *fw = (u8 *)data;
	int crnt_size = 0;
	int offset;

	offset = install_equiv_cpu_table(data);
	if (offset < 0) {
		pr_err("failed to create equivalent cpu table\n");
		return ret;
	}
	fw += offset;
	leftover = size - offset;

	if (*(u32 *)fw != UCODE_UCODE_TYPE) {
		pr_err("invalid type field in container file section header\n");
		free_equiv_cpu_table();
		return ret;
	}

	while (leftover) {
		crnt_size = verify_and_add_patch(family, fw, leftover);
		if (crnt_size < 0)
			return ret;

		fw	 += crnt_size;
		leftover -= crnt_size;
	}

	return UCODE_OK;
}

enum ucode_state load_microcode_amd(u8 family, const u8 *data, size_t size)
{
	enum ucode_state ret;

	/* free old equiv table */
	free_equiv_cpu_table();

	ret = __load_microcode_amd(family, data, size);

	if (ret != UCODE_OK)
		cleanup();

#if defined(CONFIG_MICROCODE_AMD_EARLY) && defined(CONFIG_X86_32)
	/* save BSP's matching patch for early load */
	if (cpu_data(smp_processor_id()).cpu_index == boot_cpu_data.cpu_index) {
		struct ucode_patch *p = find_patch(smp_processor_id());
		if (p) {
			memset(amd_bsp_mpb, 0, MPB_MAX_SIZE);
			memcpy(amd_bsp_mpb, p->data, min_t(u32, ksize(p->data),
							   MPB_MAX_SIZE));
		}
	}
#endif
	return ret;
}

/*
 * AMD microcode firmware naming convention, up to family 15h they are in
 * the legacy file:
 *
 *    amd-ucode/microcode_amd.bin
 *
 * This legacy file is always smaller than 2K in size.
 *
 * Beginning with family 15h, they are in family-specific firmware files:
 *
 *    amd-ucode/microcode_amd_fam15h.bin
 *    amd-ucode/microcode_amd_fam16h.bin
 *    ...
 *
 * These might be larger than 2K.
 */
static enum ucode_state request_microcode_amd(int cpu, struct device *device,
					      bool refresh_fw)
{
	char fw_name[36] = "amd-ucode/microcode_amd.bin";
	struct cpuinfo_x86 *c = &cpu_data(cpu);
	enum ucode_state ret = UCODE_NFOUND;
	const struct firmware *fw;

	/* reload ucode container only on the boot cpu */
	if (!refresh_fw || c->cpu_index != boot_cpu_data.cpu_index)
		return UCODE_OK;

	if (c->x86 >= 0x15)
		snprintf(fw_name, sizeof(fw_name), "amd-ucode/microcode_amd_fam%.2xh.bin", c->x86);

	if (request_firmware(&fw, (const char *)fw_name, device)) {
		pr_err("failed to load file %s\n", fw_name);
		goto out;
	}

	ret = UCODE_ERROR;
	if (*(u32 *)fw->data != UCODE_MAGIC) {
		pr_err("invalid magic value (0x%08x)\n", *(u32 *)fw->data);
		goto fw_release;
	}

	ret = load_microcode_amd(c->x86, fw->data, fw->size);

 fw_release:
	release_firmware(fw);

 out:
	return ret;
}

static enum ucode_state
request_microcode_user(int cpu, const void __user *buf, size_t size)
{
	return UCODE_ERROR;
}

static void microcode_fini_cpu_amd(int cpu)
{
	struct ucode_cpu_info *uci = ucode_cpu_info + cpu;

	uci->mc = NULL;
}

static struct microcode_ops microcode_amd_ops = {
	.request_microcode_user           = request_microcode_user,
	.request_microcode_fw             = request_microcode_amd,
	.collect_cpu_info                 = collect_cpu_info_amd,
	.apply_microcode                  = apply_microcode_amd,
	.microcode_fini_cpu               = microcode_fini_cpu_amd,
};

struct microcode_ops * __init init_amd_microcode(void)
{
	struct cpuinfo_x86 *c = &cpu_data(0);

	if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) {
		pr_warning("AMD CPU family 0x%x not supported\n", c->x86);
		return NULL;
	}

	return &microcode_amd_ops;
}

void __exit exit_amd_microcode(void)
{
	cleanup();
}
Commit	Line	Data
80cc9f10 PO	1	/*
80cc9f10 PO	2	* AMD CPU Microcode Update Driver for Linux
597e11a3	3	* Copyright (C) 2008-2011 Advanced Micro Devices Inc.
80cc9f10 PO	4	*
	5	* Author: Peter Oruba <peter.oruba@amd.com>
	6	*
	7	* Based on work by:
	8	* Tigran Aivazian <tigran@aivazian.fsnet.co.uk>
	9	*
597e11a3	10	* Maintainers:
943482d0 AH	11	* Andreas Herrmann <herrmann.der.user@googlemail.com>
943482d0 AH	12	* Borislav Petkov <bp@alien8.de>
597e11a3 BP	13	*
	14	* This driver allows to upgrade microcode on F10h AMD
	15	* CPUs and later.
80cc9f10	16	*
2a3282a7	17	* Licensed under the terms of the GNU General Public
80cc9f10	18	* License version 2. See file COPYING for details.
4bae1967	19	*/
f58e1f53 JP	20
	21	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
	22
4bae1967	23	#include <linux/firmware.h>
4bae1967 IM	24	#include <linux/pci_ids.h>
	25	#include <linux/uaccess.h>
	26	#include <linux/vmalloc.h>
	27	#include <linux/kernel.h>
	28	#include <linux/module.h>
80cc9f10	29	#include <linux/pci.h>
80cc9f10	30
80cc9f10	31	#include <asm/microcode.h>
4bae1967 IM	32	#include <asm/processor.h>
4bae1967 IM	33	#include <asm/msr.h>
a76096a6	34	#include <asm/microcode_amd.h>
80cc9f10 PO	35
80cc9f10 PO	36	MODULE_DESCRIPTION("AMD Microcode Update Driver");
3c52204b	37	MODULE_AUTHOR("Peter Oruba");
5d7b6052	38	MODULE_LICENSE("GPL v2");
80cc9f10	39
a0a29b62	40	static struct equiv_cpu_entry *equiv_cpu_table;
80cc9f10	41
a3eb3b4d BP	42	struct ucode_patch {
	43	struct list_head plist;
	44	void *data;
	45	u32 patch_id;
	46	u16 equiv_cpu;
	47	};
	48
	49	static LIST_HEAD(pcache);
	50
a76096a6	51	static u16 __find_equiv_id(unsigned int cpu)
c96d2c09 BP	52	{
c96d2c09 BP	53	struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
a76096a6	54	return find_equiv_id(equiv_cpu_table, uci->cpu_sig.sig);
c96d2c09 BP	55	}
	56
	57	static u32 find_cpu_family_by_equiv_cpu(u16 equiv_cpu)
	58	{
	59	int i = 0;
	60
	61	BUG_ON(!equiv_cpu_table);
	62
	63	while (equiv_cpu_table[i].equiv_cpu != 0) {
	64	if (equiv_cpu == equiv_cpu_table[i].equiv_cpu)
	65	return equiv_cpu_table[i].installed_cpu;
	66	i++;
	67	}
	68	return 0;
	69	}
	70
a3eb3b4d BP	71	/*
	72	* a small, trivial cache of per-family ucode patches
	73	*/
	74	static struct ucode_patch *cache_find_patch(u16 equiv_cpu)
	75	{
	76	struct ucode_patch *p;
	77
	78	list_for_each_entry(p, &pcache, plist)
	79	if (p->equiv_cpu == equiv_cpu)
	80	return p;
	81	return NULL;
	82	}
	83
	84	static void update_cache(struct ucode_patch *new_patch)
	85	{
	86	struct ucode_patch *p;
	87
	88	list_for_each_entry(p, &pcache, plist) {
	89	if (p->equiv_cpu == new_patch->equiv_cpu) {
	90	if (p->patch_id >= new_patch->patch_id)
	91	/* we already have the latest patch */
	92	return;
	93
	94	list_replace(&p->plist, &new_patch->plist);
	95	kfree(p->data);
	96	kfree(p);
	97	return;
	98	}
	99	}
	100	/* no patch found, add it */
	101	list_add_tail(&new_patch->plist, &pcache);
	102	}
	103
	104	static void free_cache(void)
	105	{
2d297480	106	struct ucode_patch p, tmp;
a3eb3b4d	107
2d297480	108	list_for_each_entry_safe(p, tmp, &pcache, plist) {
a3eb3b4d BP	109	__list_del(p->plist.prev, p->plist.next);
	110	kfree(p->data);
	111	kfree(p);
	112	}
	113	}
	114
	115	static struct ucode_patch *find_patch(unsigned int cpu)
	116	{
	117	u16 equiv_id;
	118
a76096a6	119	equiv_id = __find_equiv_id(cpu);
a3eb3b4d BP	120	if (!equiv_id)
	121	return NULL;
	122
	123	return cache_find_patch(equiv_id);
	124	}
	125
d45de409	126	static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig)
80cc9f10	127	{
3b2e3d85	128	struct cpuinfo_x86 *c = &cpu_data(cpu);
757885e9 JS	129	struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
757885e9 JS	130	struct ucode_patch *p;
80cc9f10	131
5f5b7472	132	csig->sig = cpuid_eax(0x00000001);
bcb80e53	133	csig->rev = c->microcode;
757885e9 JS	134
	135	/*
	136	* a patch could have been loaded early, set uci->mc so that
	137	* mc_bp_resume() can call apply_microcode()
	138	*/
	139	p = find_patch(cpu);
	140	if (p && (p->patch_id == csig->rev))
	141	uci->mc = p->data;
	142
258721ef BP	143	pr_info("CPU%d: patch_level=0x%08x\n", cpu, csig->rev);
258721ef BP	144
d45de409	145	return 0;
80cc9f10 PO	146	}
80cc9f10 PO	147
84516098	148	static unsigned int verify_patch_size(u8 family, u32 patch_size,
be62adb4	149	unsigned int size)
80cc9f10	150	{
be62adb4 BP	151	u32 max_size;
	152
	153	#define F1XH_MPB_MAX_SIZE 2048
	154	#define F14H_MPB_MAX_SIZE 1824
	155	#define F15H_MPB_MAX_SIZE 4096
36c46ca4	156	#define F16H_MPB_MAX_SIZE 3458
be62adb4	157
84516098	158	switch (family) {
be62adb4 BP	159	case 0x14:
	160	max_size = F14H_MPB_MAX_SIZE;
	161	break;
	162	case 0x15:
	163	max_size = F15H_MPB_MAX_SIZE;
	164	break;
36c46ca4 BO	165	case 0x16:
	166	max_size = F16H_MPB_MAX_SIZE;
	167	break;
be62adb4 BP	168	default:
	169	max_size = F1XH_MPB_MAX_SIZE;
	170	break;
	171	}
	172
	173	if (patch_size > min_t(u32, size, max_size)) {
	174	pr_err("patch size mismatch\n");
	175	return 0;
	176	}
	177
	178	return patch_size;
	179	}
	180
a76096a6 JS	181	int __apply_microcode_amd(struct microcode_amd *mc_amd)
	182	{
	183	u32 rev, dummy;
	184
	185	wrmsrl(MSR_AMD64_PATCH_LOADER, (u64)(long)&mc_amd->hdr.data_code);
	186
	187	/* verify patch application was successful */
	188	rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
	189	if (rev != mc_amd->hdr.patch_id)
	190	return -1;
	191
	192	return 0;
	193	}
	194
	195	int apply_microcode_amd(int cpu)
80cc9f10	196	{
bcb80e53	197	struct cpuinfo_x86 *c = &cpu_data(cpu);
2efb05e8 BP	198	struct microcode_amd *mc_amd;
	199	struct ucode_cpu_info *uci;
	200	struct ucode_patch *p;
	201	u32 rev, dummy;
	202
	203	BUG_ON(raw_smp_processor_id() != cpu);
80cc9f10	204
2efb05e8	205	uci = ucode_cpu_info + cpu;
80cc9f10	206
2efb05e8 BP	207	p = find_patch(cpu);
2efb05e8 BP	208	if (!p)
871b72dd	209	return 0;
80cc9f10	210
2efb05e8 BP	211	mc_amd = p->data;
	212	uci->mc = p->data;
	213
29d0887f	214	rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
80cc9f10	215
685ca6d7 BP	216	/* need to apply patch? */
	217	if (rev >= mc_amd->hdr.patch_id) {
	218	c->microcode = rev;
accd1e82	219	uci->cpu_sig.rev = rev;
685ca6d7 BP	220	return 0;
	221	}
	222
d982057f	223	if (__apply_microcode_amd(mc_amd)) {
258721ef	224	pr_err("CPU%d: update failed for patch_level=0x%08x\n",
a76096a6	225	cpu, mc_amd->hdr.patch_id);
d982057f TK	226	return -1;
	227	}
	228	pr_info("CPU%d: new patch_level=0x%08x\n", cpu,
	229	mc_amd->hdr.patch_id);
80cc9f10	230
a76096a6 JS	231	uci->cpu_sig.rev = mc_amd->hdr.patch_id;
a76096a6 JS	232	c->microcode = mc_amd->hdr.patch_id;
871b72dd DA	233
871b72dd DA	234	return 0;
80cc9f10 PO	235	}
80cc9f10 PO	236
0657d9eb	237	static int install_equiv_cpu_table(const u8 *buf)
80cc9f10	238	{
10de52d6 BP	239	unsigned int ibuf = (unsigned int )buf;
	240	unsigned int type = ibuf[1];
	241	unsigned int size = ibuf[2];
80cc9f10	242
10de52d6	243	if (type != UCODE_EQUIV_CPU_TABLE_TYPE \|\| !size) {
258721ef BP	244	pr_err("empty section/"
258721ef BP	245	"invalid type field in container file section header\n");
10de52d6	246	return -EINVAL;
80cc9f10 PO	247	}
80cc9f10 PO	248
8e5e9521	249	equiv_cpu_table = vmalloc(size);
80cc9f10	250	if (!equiv_cpu_table) {
f58e1f53	251	pr_err("failed to allocate equivalent CPU table\n");
10de52d6	252	return -ENOMEM;
80cc9f10 PO	253	}
80cc9f10 PO	254
e7e632f5	255	memcpy(equiv_cpu_table, buf + CONTAINER_HDR_SZ, size);
80cc9f10	256
40b7f3df BP	257	/* add header length */
40b7f3df BP	258	return size + CONTAINER_HDR_SZ;
80cc9f10 PO	259	}
80cc9f10 PO	260
a0a29b62	261	static void free_equiv_cpu_table(void)
80cc9f10	262	{
aeef50bc F	263	vfree(equiv_cpu_table);
aeef50bc F	264	equiv_cpu_table = NULL;
a0a29b62	265	}
80cc9f10	266
2efb05e8	267	static void cleanup(void)
a0a29b62	268	{
2efb05e8 BP	269	free_equiv_cpu_table();
	270	free_cache();
	271	}
	272
	273	/*
	274	* We return the current size even if some of the checks failed so that
	275	* we can skip over the next patch. If we return a negative value, we
	276	* signal a grave error like a memory allocation has failed and the
	277	* driver cannot continue functioning normally. In such cases, we tear
	278	* down everything we've used up so far and exit.
	279	*/
84516098	280	static int verify_and_add_patch(u8 family, u8 *fw, unsigned int leftover)
2efb05e8	281	{
2efb05e8 BP	282	struct microcode_header_amd *mc_hdr;
	283	struct ucode_patch *patch;
	284	unsigned int patch_size, crnt_size, ret;
	285	u32 proc_fam;
	286	u16 proc_id;
	287
	288	patch_size = (u32 )(fw + 4);
	289	crnt_size = patch_size + SECTION_HDR_SIZE;
	290	mc_hdr = (struct microcode_header_amd *)(fw + SECTION_HDR_SIZE);
	291	proc_id = mc_hdr->processor_rev_id;
	292
	293	proc_fam = find_cpu_family_by_equiv_cpu(proc_id);
	294	if (!proc_fam) {
	295	pr_err("No patch family for equiv ID: 0x%04x\n", proc_id);
	296	return crnt_size;
	297	}
	298
	299	/* check if patch is for the current family */
	300	proc_fam = ((proc_fam >> 8) & 0xf) + ((proc_fam >> 20) & 0xff);
84516098	301	if (proc_fam != family)
2efb05e8 BP	302	return crnt_size;
	303
	304	if (mc_hdr->nb_dev_id \|\| mc_hdr->sb_dev_id) {
	305	pr_err("Patch-ID 0x%08x: chipset-specific code unsupported.\n",
	306	mc_hdr->patch_id);
	307	return crnt_size;
	308	}
	309
84516098	310	ret = verify_patch_size(family, patch_size, leftover);
2efb05e8 BP	311	if (!ret) {
	312	pr_err("Patch-ID 0x%08x: size mismatch.\n", mc_hdr->patch_id);
	313	return crnt_size;
	314	}
	315
	316	patch = kzalloc(sizeof(*patch), GFP_KERNEL);
	317	if (!patch) {
	318	pr_err("Patch allocation failure.\n");
	319	return -EINVAL;
	320	}
	321
	322	patch->data = kzalloc(patch_size, GFP_KERNEL);
	323	if (!patch->data) {
	324	pr_err("Patch data allocation failure.\n");
	325	kfree(patch);
	326	return -EINVAL;
	327	}
	328
	329	/* All looks ok, copy patch... */
	330	memcpy(patch->data, fw + SECTION_HDR_SIZE, patch_size);
	331	INIT_LIST_HEAD(&patch->plist);
	332	patch->patch_id = mc_hdr->patch_id;
	333	patch->equiv_cpu = proc_id;
	334
	335	/* ... and add to cache. */
	336	update_cache(patch);
	337
	338	return crnt_size;
	339	}
	340
84516098 TK	341	static enum ucode_state __load_microcode_amd(u8 family, const u8 *data,
84516098 TK	342	size_t size)
2efb05e8 BP	343	{
	344	enum ucode_state ret = UCODE_ERROR;
	345	unsigned int leftover;
	346	u8 fw = (u8 )data;
	347	int crnt_size = 0;
1396fa9c	348	int offset;
80cc9f10	349
2efb05e8	350	offset = install_equiv_cpu_table(data);
10de52d6	351	if (offset < 0) {
f58e1f53	352	pr_err("failed to create equivalent cpu table\n");
2efb05e8	353	return ret;
80cc9f10	354	}
2efb05e8	355	fw += offset;
a0a29b62 DA	356	leftover = size - offset;
a0a29b62 DA	357
2efb05e8	358	if ((u32 )fw != UCODE_UCODE_TYPE) {
be62adb4	359	pr_err("invalid type field in container file section header\n");
2efb05e8 BP	360	free_equiv_cpu_table();
2efb05e8 BP	361	return ret;
be62adb4	362	}
a0a29b62	363
be62adb4	364	while (leftover) {
84516098	365	crnt_size = verify_and_add_patch(family, fw, leftover);
2efb05e8 BP	366	if (crnt_size < 0)
2efb05e8 BP	367	return ret;
d733689a	368
2efb05e8 BP	369	fw += crnt_size;
2efb05e8 BP	370	leftover -= crnt_size;
80cc9f10	371	}
a0a29b62	372
2efb05e8	373	return UCODE_OK;
a0a29b62 DA	374	}
a0a29b62 DA	375
84516098	376	enum ucode_state load_microcode_amd(u8 family, const u8 *data, size_t size)
a76096a6 JS	377	{
	378	enum ucode_state ret;
	379
	380	/* free old equiv table */
	381	free_equiv_cpu_table();
	382
84516098	383	ret = __load_microcode_amd(family, data, size);
a76096a6 JS	384
	385	if (ret != UCODE_OK)
	386	cleanup();
	387
757885e9 JS	388	#if defined(CONFIG_MICROCODE_AMD_EARLY) && defined(CONFIG_X86_32)
757885e9 JS	389	/* save BSP's matching patch for early load */
84516098 TK	390	if (cpu_data(smp_processor_id()).cpu_index == boot_cpu_data.cpu_index) {
84516098 TK	391	struct ucode_patch *p = find_patch(smp_processor_id());
757885e9 JS	392	if (p) {
	393	memset(amd_bsp_mpb, 0, MPB_MAX_SIZE);
	394	memcpy(amd_bsp_mpb, p->data, min_t(u32, ksize(p->data),
	395	MPB_MAX_SIZE));
	396	}
	397	}
	398	#endif
a76096a6 JS	399	return ret;
	400	}
	401
5b68edc9 AH	402	/*
	403	* AMD microcode firmware naming convention, up to family 15h they are in
	404	* the legacy file:
	405	*
	406	* amd-ucode/microcode_amd.bin
	407	*
	408	* This legacy file is always smaller than 2K in size.
	409	*
2efb05e8	410	* Beginning with family 15h, they are in family-specific firmware files:
5b68edc9 AH	411	*
	412	* amd-ucode/microcode_amd_fam15h.bin
	413	* amd-ucode/microcode_amd_fam16h.bin
	414	* ...
	415	*
	416	* These might be larger than 2K.
	417	*/
48e30685 BP	418	static enum ucode_state request_microcode_amd(int cpu, struct device *device,
48e30685 BP	419	bool refresh_fw)
a0a29b62	420	{
5b68edc9	421	char fw_name[36] = "amd-ucode/microcode_amd.bin";
5b68edc9	422	struct cpuinfo_x86 *c = &cpu_data(cpu);
2efb05e8 BP	423	enum ucode_state ret = UCODE_NFOUND;
	424	const struct firmware *fw;
	425
	426	/* reload ucode container only on the boot cpu */
	427	if (!refresh_fw \|\| c->cpu_index != boot_cpu_data.cpu_index)
	428	return UCODE_OK;
5b68edc9 AH	429
	430	if (c->x86 >= 0x15)
	431	snprintf(fw_name, sizeof(fw_name), "amd-ucode/microcode_amd_fam%.2xh.bin", c->x86);
a0a29b62	432
5b68edc9	433	if (request_firmware(&fw, (const char *)fw_name, device)) {
258721ef	434	pr_err("failed to load file %s\n", fw_name);
ffc7e8ac	435	goto out;
3b2e3d85	436	}
a0a29b62	437
ffc7e8ac BP	438	ret = UCODE_ERROR;
ffc7e8ac BP	439	if ((u32 )fw->data != UCODE_MAGIC) {
258721ef	440	pr_err("invalid magic value (0x%08x)\n", (u32 )fw->data);
ffc7e8ac	441	goto fw_release;
506f90ee BP	442	}
506f90ee BP	443
84516098	444	ret = load_microcode_amd(c->x86, fw->data, fw->size);
a0a29b62	445
2efb05e8	446	fw_release:
ffc7e8ac	447	release_firmware(fw);
3b2e3d85	448
2efb05e8	449	out:
a0a29b62 DA	450	return ret;
	451	}
	452
871b72dd DA	453	static enum ucode_state
871b72dd DA	454	request_microcode_user(int cpu, const void __user *buf, size_t size)
a0a29b62	455	{
871b72dd	456	return UCODE_ERROR;
80cc9f10 PO	457	}
80cc9f10 PO	458
80cc9f10 PO	459	static void microcode_fini_cpu_amd(int cpu)
	460	{
	461	struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
	462
18dbc916	463	uci->mc = NULL;
80cc9f10 PO	464	}
	465
	466	static struct microcode_ops microcode_amd_ops = {
a0a29b62	467	.request_microcode_user = request_microcode_user,
ffc7e8ac	468	.request_microcode_fw = request_microcode_amd,
80cc9f10 PO	469	.collect_cpu_info = collect_cpu_info_amd,
	470	.apply_microcode = apply_microcode_amd,
	471	.microcode_fini_cpu = microcode_fini_cpu_amd,
	472	};
	473
18dbc916	474	struct microcode_ops * __init init_amd_microcode(void)
80cc9f10	475	{
283c1f25 AH	476	struct cpuinfo_x86 *c = &cpu_data(0);
	477
	478	if (c->x86_vendor != X86_VENDOR_AMD \|\| c->x86 < 0x10) {
	479	pr_warning("AMD CPU family 0x%x not supported\n", c->x86);
	480	return NULL;
	481	}
	482
18dbc916	483	return &microcode_amd_ops;
80cc9f10	484	}
f72c1a57 BP	485
	486	void __exit exit_amd_microcode(void)
	487	{
2efb05e8	488	cleanup();
f72c1a57	489	}