[deliverable/linux.git] / arch / x86 / kernel / microcode_amd.c

/*
 *  AMD CPU Microcode Update Driver for Linux
 *  Copyright (C) 2008-2011 Advanced Micro Devices Inc.
 *
 *  Author: Peter Oruba <peter.oruba@amd.com>
 *
 *  Based on work by:
 *  Tigran Aivazian <tigran@aivazian.fsnet.co.uk>
 *
 *  Maintainers:
 *  Andreas Herrmann <andreas.herrmann3@amd.com>
 *  Borislav Petkov <borislav.petkov@amd.com>
 *
 *  This driver allows to upgrade microcode on F10h AMD
 *  CPUs and later.
 *
 *  Licensed under the terms of the GNU General Public
 *  License version 2. See file COPYING for details.
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/firmware.h>
#include <linux/pci_ids.h>
#include <linux/uaccess.h>
#include <linux/vmalloc.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>

#include <asm/microcode.h>
#include <asm/processor.h>
#include <asm/msr.h>

MODULE_DESCRIPTION("AMD Microcode Update Driver");
MODULE_AUTHOR("Peter Oruba");
MODULE_LICENSE("GPL v2");

#define UCODE_MAGIC                0x00414d44
#define UCODE_EQUIV_CPU_TABLE_TYPE 0x00000000
#define UCODE_UCODE_TYPE           0x00000001

struct equiv_cpu_entry {
	u32	installed_cpu;
	u32	fixed_errata_mask;
	u32	fixed_errata_compare;
	u16	equiv_cpu;
	u16	res;
} __attribute__((packed));

struct microcode_header_amd {
	u32	data_code;
	u32	patch_id;
	u16	mc_patch_data_id;
	u8	mc_patch_data_len;
	u8	init_flag;
	u32	mc_patch_data_checksum;
	u32	nb_dev_id;
	u32	sb_dev_id;
	u16	processor_rev_id;
	u8	nb_rev_id;
	u8	sb_rev_id;
	u8	bios_api_rev;
	u8	reserved1[3];
	u32	match_reg[8];
} __attribute__((packed));

struct microcode_amd {
	struct microcode_header_amd	hdr;
	unsigned int			mpb[0];
};

#define SECTION_HDR_SIZE	8
#define CONTAINER_HDR_SZ	12

static struct equiv_cpu_entry *equiv_cpu_table;

/* page-sized ucode patch buffer */
void *patch;

static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig)
{
	struct cpuinfo_x86 *c = &cpu_data(cpu);

	csig->rev = c->microcode;
	pr_info("CPU%d: patch_level=0x%08x\n", cpu, csig->rev);

	return 0;
}

static unsigned int verify_ucode_size(int cpu, u32 patch_size,
				      unsigned int size)
{
	struct cpuinfo_x86 *c = &cpu_data(cpu);
	u32 max_size;

#define F1XH_MPB_MAX_SIZE 2048
#define F14H_MPB_MAX_SIZE 1824
#define F15H_MPB_MAX_SIZE 4096

	switch (c->x86) {
	case 0x14:
		max_size = F14H_MPB_MAX_SIZE;
		break;
	case 0x15:
		max_size = F15H_MPB_MAX_SIZE;
		break;
	default:
		max_size = F1XH_MPB_MAX_SIZE;
		break;
	}

	if (patch_size > min_t(u32, size, max_size)) {
		pr_err("patch size mismatch\n");
		return 0;
	}

	return patch_size;
}

static u16 find_equiv_id(void)
{
	unsigned int current_cpu_id, i = 0;

	BUG_ON(equiv_cpu_table == NULL);

	current_cpu_id = cpuid_eax(0x00000001);

	while (equiv_cpu_table[i].installed_cpu != 0) {
		if (current_cpu_id == equiv_cpu_table[i].installed_cpu)
			return equiv_cpu_table[i].equiv_cpu;

		i++;
	}
	return 0;
}

/*
 * we signal a good patch is found by returning its size > 0
 */
static int get_matching_microcode(int cpu, const u8 *ucode_ptr,
				  unsigned int leftover_size, int rev,
				  unsigned int *current_size)
{
	struct microcode_header_amd *mc_hdr;
	unsigned int actual_size, patch_size;
	u16 equiv_cpu_id;

	/* size of the current patch we're staring at */
	patch_size = *(u32 *)(ucode_ptr + 4);
	*current_size = patch_size + SECTION_HDR_SIZE;

	equiv_cpu_id = find_equiv_id();
	if (!equiv_cpu_id)
		return 0;

	/*
	 * let's look at the patch header itself now
	 */
	mc_hdr = (struct microcode_header_amd *)(ucode_ptr + SECTION_HDR_SIZE);

	if (mc_hdr->processor_rev_id != equiv_cpu_id)
		return 0;

	/* ucode might be chipset specific -- currently we don't support this */
	if (mc_hdr->nb_dev_id || mc_hdr->sb_dev_id) {
		pr_err("CPU%d: chipset specific code not yet supported\n",
		       cpu);
		return 0;
	}

	if (mc_hdr->patch_id <= rev)
		return 0;

	/*
	 * now that the header looks sane, verify its size
	 */
	actual_size = verify_ucode_size(cpu, patch_size, leftover_size);
	if (!actual_size)
		return 0;

	/* clear the patch buffer */
	memset(patch, 0, PAGE_SIZE);

	/* all looks ok, get the binary patch */
	memcpy(patch, ucode_ptr + SECTION_HDR_SIZE, actual_size);

	return actual_size;
}

static int apply_microcode_amd(int cpu)
{
	u32 rev, dummy;
	int cpu_num = raw_smp_processor_id();
	struct ucode_cpu_info *uci = ucode_cpu_info + cpu_num;
	struct microcode_amd *mc_amd = uci->mc;
	struct cpuinfo_x86 *c = &cpu_data(cpu);

	/* We should bind the task to the CPU */
	BUG_ON(cpu_num != cpu);

	if (mc_amd == NULL)
		return 0;

	rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);

	/* need to apply patch? */
	if (rev >= mc_amd->hdr.patch_id) {
		c->microcode = rev;
		return 0;
	}

	wrmsrl(MSR_AMD64_PATCH_LOADER, (u64)(long)&mc_amd->hdr.data_code);

	/* verify patch application was successful */
	rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
	if (rev != mc_amd->hdr.patch_id) {
		pr_err("CPU%d: update failed for patch_level=0x%08x\n",
		       cpu, mc_amd->hdr.patch_id);
		return -1;
	}

	pr_info("CPU%d: new patch_level=0x%08x\n", cpu, rev);
	uci->cpu_sig.rev = rev;
	c->microcode = rev;

	return 0;
}

static int install_equiv_cpu_table(const u8 *buf)
{
	unsigned int *ibuf = (unsigned int *)buf;
	unsigned int type = ibuf[1];
	unsigned int size = ibuf[2];

	if (type != UCODE_EQUIV_CPU_TABLE_TYPE || !size) {
		pr_err("empty section/"
		       "invalid type field in container file section header\n");
		return -EINVAL;
	}

	equiv_cpu_table = vmalloc(size);
	if (!equiv_cpu_table) {
		pr_err("failed to allocate equivalent CPU table\n");
		return -ENOMEM;
	}

	memcpy(equiv_cpu_table, buf + CONTAINER_HDR_SZ, size);

	/* add header length */
	return size + CONTAINER_HDR_SZ;
}

static void free_equiv_cpu_table(void)
{
	vfree(equiv_cpu_table);
	equiv_cpu_table = NULL;
}

static enum ucode_state
generic_load_microcode(int cpu, const u8 *data, size_t size)
{
	struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
	struct microcode_header_amd *mc_hdr = NULL;
	unsigned int mc_size, leftover, current_size = 0;
	int offset;
	const u8 *ucode_ptr = data;
	void *new_mc = NULL;
	unsigned int new_rev = uci->cpu_sig.rev;
	enum ucode_state state = UCODE_ERROR;

	offset = install_equiv_cpu_table(ucode_ptr);
	if (offset < 0) {
		pr_err("failed to create equivalent cpu table\n");
		goto out;
	}
	ucode_ptr += offset;
	leftover = size - offset;

	if (*(u32 *)ucode_ptr != UCODE_UCODE_TYPE) {
		pr_err("invalid type field in container file section header\n");
		goto free_table;
	}

	while (leftover) {
		mc_size = get_matching_microcode(cpu, ucode_ptr, leftover,
						 new_rev, &current_size);
		if (mc_size) {
			mc_hdr  = patch;
			new_mc  = patch;
			new_rev = mc_hdr->patch_id;
			goto out_ok;
		}

		ucode_ptr += current_size;
		leftover  -= current_size;
	}

	if (!new_mc) {
		state = UCODE_NFOUND;
		goto free_table;
	}

out_ok:
	uci->mc = new_mc;
	state = UCODE_OK;
	pr_debug("CPU%d update ucode (0x%08x -> 0x%08x)\n",
		 cpu, uci->cpu_sig.rev, new_rev);

free_table:
	free_equiv_cpu_table();

out:
	return state;
}

/*
 * AMD microcode firmware naming convention, up to family 15h they are in
 * the legacy file:
 *
 *    amd-ucode/microcode_amd.bin
 *
 * This legacy file is always smaller than 2K in size.
 *
 * Starting at family 15h they are in family specific firmware files:
 *
 *    amd-ucode/microcode_amd_fam15h.bin
 *    amd-ucode/microcode_amd_fam16h.bin
 *    ...
 *
 * These might be larger than 2K.
 */
static enum ucode_state request_microcode_amd(int cpu, struct device *device)
{
	char fw_name[36] = "amd-ucode/microcode_amd.bin";
	const struct firmware *fw;
	enum ucode_state ret = UCODE_NFOUND;
	struct cpuinfo_x86 *c = &cpu_data(cpu);

	if (c->x86 >= 0x15)
		snprintf(fw_name, sizeof(fw_name), "amd-ucode/microcode_amd_fam%.2xh.bin", c->x86);

	if (request_firmware(&fw, (const char *)fw_name, device)) {
		pr_err("failed to load file %s\n", fw_name);
		goto out;
	}

	ret = UCODE_ERROR;
	if (*(u32 *)fw->data != UCODE_MAGIC) {
		pr_err("invalid magic value (0x%08x)\n", *(u32 *)fw->data);
		goto fw_release;
	}

	ret = generic_load_microcode(cpu, fw->data, fw->size);

fw_release:
	release_firmware(fw);

out:
	return ret;
}

static enum ucode_state
request_microcode_user(int cpu, const void __user *buf, size_t size)
{
	return UCODE_ERROR;
}

static void microcode_fini_cpu_amd(int cpu)
{
	struct ucode_cpu_info *uci = ucode_cpu_info + cpu;

	uci->mc = NULL;
}

static struct microcode_ops microcode_amd_ops = {
	.request_microcode_user           = request_microcode_user,
	.request_microcode_fw             = request_microcode_amd,
	.collect_cpu_info                 = collect_cpu_info_amd,
	.apply_microcode                  = apply_microcode_amd,
	.microcode_fini_cpu               = microcode_fini_cpu_amd,
};

struct microcode_ops * __init init_amd_microcode(void)
{
	struct cpuinfo_x86 *c = &cpu_data(0);

	if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) {
		pr_warning("AMD CPU family 0x%x not supported\n", c->x86);
		return NULL;
	}

	patch = (void *)get_zeroed_page(GFP_KERNEL);
	if (!patch)
		return NULL;

	return &microcode_amd_ops;
}

void __exit exit_amd_microcode(void)
{
	free_page((unsigned long)patch);
}
Commit	Line	Data
80cc9f10 PO	1	/*
80cc9f10 PO	2	* AMD CPU Microcode Update Driver for Linux
597e11a3	3	* Copyright (C) 2008-2011 Advanced Micro Devices Inc.
80cc9f10 PO	4	*
	5	* Author: Peter Oruba <peter.oruba@amd.com>
	6	*
	7	* Based on work by:
	8	* Tigran Aivazian <tigran@aivazian.fsnet.co.uk>
	9	*
597e11a3 BP	10	* Maintainers:
	11	* Andreas Herrmann <andreas.herrmann3@amd.com>
	12	* Borislav Petkov <borislav.petkov@amd.com>
	13	*
	14	* This driver allows to upgrade microcode on F10h AMD
	15	* CPUs and later.
80cc9f10	16	*
2a3282a7	17	* Licensed under the terms of the GNU General Public
80cc9f10	18	* License version 2. See file COPYING for details.
4bae1967	19	*/
f58e1f53 JP	20
	21	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
	22
4bae1967	23	#include <linux/firmware.h>
4bae1967 IM	24	#include <linux/pci_ids.h>
	25	#include <linux/uaccess.h>
	26	#include <linux/vmalloc.h>
	27	#include <linux/kernel.h>
	28	#include <linux/module.h>
80cc9f10	29	#include <linux/pci.h>
80cc9f10	30
80cc9f10	31	#include <asm/microcode.h>
4bae1967 IM	32	#include <asm/processor.h>
4bae1967 IM	33	#include <asm/msr.h>
80cc9f10 PO	34
80cc9f10 PO	35	MODULE_DESCRIPTION("AMD Microcode Update Driver");
3c52204b	36	MODULE_AUTHOR("Peter Oruba");
5d7b6052	37	MODULE_LICENSE("GPL v2");
80cc9f10 PO	38
	39	#define UCODE_MAGIC 0x00414d44
	40	#define UCODE_EQUIV_CPU_TABLE_TYPE 0x00000000
	41	#define UCODE_UCODE_TYPE 0x00000001
	42
18dbc916	43	struct equiv_cpu_entry {
5549b94b AH	44	u32 installed_cpu;
	45	u32 fixed_errata_mask;
	46	u32 fixed_errata_compare;
	47	u16 equiv_cpu;
	48	u16 res;
	49	} __attribute__((packed));
18dbc916 DA	50
18dbc916 DA	51	struct microcode_header_amd {
5549b94b AH	52	u32 data_code;
	53	u32 patch_id;
	54	u16 mc_patch_data_id;
	55	u8 mc_patch_data_len;
	56	u8 init_flag;
	57	u32 mc_patch_data_checksum;
	58	u32 nb_dev_id;
	59	u32 sb_dev_id;
	60	u16 processor_rev_id;
	61	u8 nb_rev_id;
	62	u8 sb_rev_id;
	63	u8 bios_api_rev;
	64	u8 reserved1[3];
	65	u32 match_reg[8];
	66	} __attribute__((packed));
18dbc916 DA	67
18dbc916 DA	68	struct microcode_amd {
4bae1967 IM	69	struct microcode_header_amd hdr;
4bae1967 IM	70	unsigned int mpb[0];
18dbc916 DA	71	};
18dbc916 DA	72
40b7f3df BP	73	#define SECTION_HDR_SIZE 8
40b7f3df BP	74	#define CONTAINER_HDR_SZ 12
80cc9f10	75
a0a29b62	76	static struct equiv_cpu_entry *equiv_cpu_table;
80cc9f10	77
96b0ee45 BP	78	/* page-sized ucode patch buffer */
	79	void *patch;
	80
d45de409	81	static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig)
80cc9f10	82	{
3b2e3d85	83	struct cpuinfo_x86 *c = &cpu_data(cpu);
80cc9f10	84
bcb80e53	85	csig->rev = c->microcode;
258721ef BP	86	pr_info("CPU%d: patch_level=0x%08x\n", cpu, csig->rev);
258721ef BP	87
d45de409	88	return 0;
80cc9f10 PO	89	}
80cc9f10 PO	90
be62adb4 BP	91	static unsigned int verify_ucode_size(int cpu, u32 patch_size,
be62adb4 BP	92	unsigned int size)
80cc9f10	93	{
be62adb4 BP	94	struct cpuinfo_x86 *c = &cpu_data(cpu);
	95	u32 max_size;
	96
	97	#define F1XH_MPB_MAX_SIZE 2048
	98	#define F14H_MPB_MAX_SIZE 1824
	99	#define F15H_MPB_MAX_SIZE 4096
	100
	101	switch (c->x86) {
	102	case 0x14:
	103	max_size = F14H_MPB_MAX_SIZE;
	104	break;
	105	case 0x15:
	106	max_size = F15H_MPB_MAX_SIZE;
	107	break;
	108	default:
	109	max_size = F1XH_MPB_MAX_SIZE;
	110	break;
	111	}
	112
	113	if (patch_size > min_t(u32, size, max_size)) {
	114	pr_err("patch size mismatch\n");
	115	return 0;
	116	}
	117
	118	return patch_size;
	119	}
	120
	121	static u16 find_equiv_id(void)
	122	{
	123	unsigned int current_cpu_id, i = 0;
80cc9f10	124
a0a29b62	125	BUG_ON(equiv_cpu_table == NULL);
be62adb4	126
80cc9f10 PO	127	current_cpu_id = cpuid_eax(0x00000001);
	128
	129	while (equiv_cpu_table[i].installed_cpu != 0) {
be62adb4 BP	130	if (current_cpu_id == equiv_cpu_table[i].installed_cpu)
	131	return equiv_cpu_table[i].equiv_cpu;
	132
80cc9f10 PO	133	i++;
80cc9f10 PO	134	}
be62adb4 BP	135	return 0;
be62adb4 BP	136	}
80cc9f10	137
be62adb4 BP	138	/*
	139	* we signal a good patch is found by returning its size > 0
	140	*/
	141	static int get_matching_microcode(int cpu, const u8 *ucode_ptr,
	142	unsigned int leftover_size, int rev,
	143	unsigned int *current_size)
	144	{
	145	struct microcode_header_amd *mc_hdr;
36bf50d7	146	unsigned int actual_size, patch_size;
be62adb4 BP	147	u16 equiv_cpu_id;
	148
	149	/* size of the current patch we're staring at */
36bf50d7 AH	150	patch_size = (u32 )(ucode_ptr + 4);
36bf50d7 AH	151	*current_size = patch_size + SECTION_HDR_SIZE;
be62adb4 BP	152
be62adb4 BP	153	equiv_cpu_id = find_equiv_id();
14c56942	154	if (!equiv_cpu_id)
80cc9f10	155	return 0;
80cc9f10	156
be62adb4 BP	157	/*
	158	* let's look at the patch header itself now
	159	*/
	160	mc_hdr = (struct microcode_header_amd *)(ucode_ptr + SECTION_HDR_SIZE);
	161
7cc27349	162	if (mc_hdr->processor_rev_id != equiv_cpu_id)
80cc9f10	163	return 0;
80cc9f10	164
98415301	165	/* ucode might be chipset specific -- currently we don't support this */
7cc27349	166	if (mc_hdr->nb_dev_id \|\| mc_hdr->sb_dev_id) {
258721ef	167	pr_err("CPU%d: chipset specific code not yet supported\n",
f58e1f53	168	cpu);
98415301	169	return 0;
80cc9f10 PO	170	}
80cc9f10 PO	171
7cc27349	172	if (mc_hdr->patch_id <= rev)
80cc9f10 PO	173	return 0;
80cc9f10 PO	174
be62adb4 BP	175	/*
	176	* now that the header looks sane, verify its size
	177	*/
36bf50d7	178	actual_size = verify_ucode_size(cpu, patch_size, leftover_size);
be62adb4 BP	179	if (!actual_size)
	180	return 0;
	181
	182	/* clear the patch buffer */
	183	memset(patch, 0, PAGE_SIZE);
	184
	185	/* all looks ok, get the binary patch */
e7e632f5	186	memcpy(patch, ucode_ptr + SECTION_HDR_SIZE, actual_size);
be62adb4 BP	187
be62adb4 BP	188	return actual_size;
80cc9f10 PO	189	}
80cc9f10 PO	190
871b72dd	191	static int apply_microcode_amd(int cpu)
80cc9f10	192	{
29d0887f	193	u32 rev, dummy;
80cc9f10 PO	194	int cpu_num = raw_smp_processor_id();
80cc9f10 PO	195	struct ucode_cpu_info *uci = ucode_cpu_info + cpu_num;
18dbc916	196	struct microcode_amd *mc_amd = uci->mc;
bcb80e53	197	struct cpuinfo_x86 *c = &cpu_data(cpu);
80cc9f10 PO	198
	199	/* We should bind the task to the CPU */
	200	BUG_ON(cpu_num != cpu);
	201
18dbc916	202	if (mc_amd == NULL)
871b72dd	203	return 0;
80cc9f10	204
29d0887f	205	rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
80cc9f10	206
685ca6d7 BP	207	/* need to apply patch? */
	208	if (rev >= mc_amd->hdr.patch_id) {
	209	c->microcode = rev;
	210	return 0;
	211	}
	212
	213	wrmsrl(MSR_AMD64_PATCH_LOADER, (u64)(long)&mc_amd->hdr.data_code);
	214
	215	/* verify patch application was successful */
	216	rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
18dbc916	217	if (rev != mc_amd->hdr.patch_id) {
258721ef	218	pr_err("CPU%d: update failed for patch_level=0x%08x\n",
f58e1f53	219	cpu, mc_amd->hdr.patch_id);
871b72dd	220	return -1;
80cc9f10 PO	221	}
80cc9f10 PO	222
258721ef	223	pr_info("CPU%d: new patch_level=0x%08x\n", cpu, rev);
d45de409	224	uci->cpu_sig.rev = rev;
bcb80e53	225	c->microcode = rev;
871b72dd DA	226
871b72dd DA	227	return 0;
80cc9f10 PO	228	}
80cc9f10 PO	229
0657d9eb	230	static int install_equiv_cpu_table(const u8 *buf)
80cc9f10	231	{
10de52d6 BP	232	unsigned int ibuf = (unsigned int )buf;
	233	unsigned int type = ibuf[1];
	234	unsigned int size = ibuf[2];
80cc9f10	235
10de52d6	236	if (type != UCODE_EQUIV_CPU_TABLE_TYPE \|\| !size) {
258721ef BP	237	pr_err("empty section/"
258721ef BP	238	"invalid type field in container file section header\n");
10de52d6	239	return -EINVAL;
80cc9f10 PO	240	}
80cc9f10 PO	241
8e5e9521	242	equiv_cpu_table = vmalloc(size);
80cc9f10	243	if (!equiv_cpu_table) {
f58e1f53	244	pr_err("failed to allocate equivalent CPU table\n");
10de52d6	245	return -ENOMEM;
80cc9f10 PO	246	}
80cc9f10 PO	247
e7e632f5	248	memcpy(equiv_cpu_table, buf + CONTAINER_HDR_SZ, size);
80cc9f10	249
40b7f3df BP	250	/* add header length */
40b7f3df BP	251	return size + CONTAINER_HDR_SZ;
80cc9f10 PO	252	}
80cc9f10 PO	253
a0a29b62	254	static void free_equiv_cpu_table(void)
80cc9f10	255	{
aeef50bc F	256	vfree(equiv_cpu_table);
aeef50bc F	257	equiv_cpu_table = NULL;
a0a29b62	258	}
80cc9f10	259
871b72dd DA	260	static enum ucode_state
871b72dd DA	261	generic_load_microcode(int cpu, const u8 *data, size_t size)
a0a29b62 DA	262	{
a0a29b62 DA	263	struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
7cc27349	264	struct microcode_header_amd *mc_hdr = NULL;
be62adb4	265	unsigned int mc_size, leftover, current_size = 0;
1396fa9c	266	int offset;
8c135206 AH	267	const u8 *ucode_ptr = data;
8c135206 AH	268	void *new_mc = NULL;
258721ef	269	unsigned int new_rev = uci->cpu_sig.rev;
be62adb4	270	enum ucode_state state = UCODE_ERROR;
80cc9f10	271
0657d9eb	272	offset = install_equiv_cpu_table(ucode_ptr);
10de52d6	273	if (offset < 0) {
f58e1f53	274	pr_err("failed to create equivalent cpu table\n");
be62adb4	275	goto out;
80cc9f10	276	}
a0a29b62 DA	277	ucode_ptr += offset;
	278	leftover = size - offset;
	279
be62adb4 BP	280	if ((u32 )ucode_ptr != UCODE_UCODE_TYPE) {
	281	pr_err("invalid type field in container file section header\n");
	282	goto free_table;
	283	}
a0a29b62	284
be62adb4 BP	285	while (leftover) {
	286	mc_size = get_matching_microcode(cpu, ucode_ptr, leftover,
	287	new_rev, &current_size);
	288	if (mc_size) {
	289	mc_hdr = patch;
	290	new_mc = patch;
7cc27349	291	new_rev = mc_hdr->patch_id;
d733689a	292	goto out_ok;
be62adb4	293	}
d733689a BP	294
	295	ucode_ptr += current_size;
	296	leftover -= current_size;
80cc9f10	297	}
a0a29b62	298
7cc27349	299	if (!new_mc) {
871b72dd	300	state = UCODE_NFOUND;
7cc27349 BP	301	goto free_table;
	302	}
	303
d733689a BP	304	out_ok:
	305	uci->mc = new_mc;
	306	state = UCODE_OK;
	307	pr_debug("CPU%d update ucode (0x%08x -> 0x%08x)\n",
	308	cpu, uci->cpu_sig.rev, new_rev);
a0a29b62	309
7cc27349	310	free_table:
a0a29b62 DA	311	free_equiv_cpu_table();
a0a29b62 DA	312
be62adb4	313	out:
871b72dd	314	return state;
a0a29b62 DA	315	}
a0a29b62 DA	316
5b68edc9 AH	317	/*
	318	* AMD microcode firmware naming convention, up to family 15h they are in
	319	* the legacy file:
	320	*
	321	* amd-ucode/microcode_amd.bin
	322	*
	323	* This legacy file is always smaller than 2K in size.
	324	*
	325	* Starting at family 15h they are in family specific firmware files:
	326	*
	327	* amd-ucode/microcode_amd_fam15h.bin
	328	* amd-ucode/microcode_amd_fam16h.bin
	329	* ...
	330	*
	331	* These might be larger than 2K.
	332	*/
ffc7e8ac	333	static enum ucode_state request_microcode_amd(int cpu, struct device *device)
a0a29b62	334	{
5b68edc9	335	char fw_name[36] = "amd-ucode/microcode_amd.bin";
ffc7e8ac BP	336	const struct firmware *fw;
ffc7e8ac BP	337	enum ucode_state ret = UCODE_NFOUND;
5b68edc9 AH	338	struct cpuinfo_x86 *c = &cpu_data(cpu);
	339
	340	if (c->x86 >= 0x15)
	341	snprintf(fw_name, sizeof(fw_name), "amd-ucode/microcode_amd_fam%.2xh.bin", c->x86);
a0a29b62	342
5b68edc9	343	if (request_firmware(&fw, (const char *)fw_name, device)) {
258721ef	344	pr_err("failed to load file %s\n", fw_name);
ffc7e8ac	345	goto out;
3b2e3d85	346	}
a0a29b62	347
ffc7e8ac BP	348	ret = UCODE_ERROR;
ffc7e8ac BP	349	if ((u32 )fw->data != UCODE_MAGIC) {
258721ef	350	pr_err("invalid magic value (0x%08x)\n", (u32 )fw->data);
ffc7e8ac	351	goto fw_release;
506f90ee BP	352	}
506f90ee BP	353
ffc7e8ac	354	ret = generic_load_microcode(cpu, fw->data, fw->size);
a0a29b62	355
ffc7e8ac BP	356	fw_release:
ffc7e8ac BP	357	release_firmware(fw);
3b2e3d85	358
ffc7e8ac	359	out:
a0a29b62 DA	360	return ret;
	361	}
	362
871b72dd DA	363	static enum ucode_state
871b72dd DA	364	request_microcode_user(int cpu, const void __user *buf, size_t size)
a0a29b62	365	{
871b72dd	366	return UCODE_ERROR;
80cc9f10 PO	367	}
80cc9f10 PO	368
80cc9f10 PO	369	static void microcode_fini_cpu_amd(int cpu)
	370	{
	371	struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
	372
18dbc916	373	uci->mc = NULL;
80cc9f10 PO	374	}
	375
	376	static struct microcode_ops microcode_amd_ops = {
a0a29b62	377	.request_microcode_user = request_microcode_user,
ffc7e8ac	378	.request_microcode_fw = request_microcode_amd,
80cc9f10 PO	379	.collect_cpu_info = collect_cpu_info_amd,
	380	.apply_microcode = apply_microcode_amd,
	381	.microcode_fini_cpu = microcode_fini_cpu_amd,
	382	};
	383
18dbc916	384	struct microcode_ops * __init init_amd_microcode(void)
80cc9f10	385	{
283c1f25 AH	386	struct cpuinfo_x86 *c = &cpu_data(0);
	387
	388	if (c->x86_vendor != X86_VENDOR_AMD \|\| c->x86 < 0x10) {
	389	pr_warning("AMD CPU family 0x%x not supported\n", c->x86);
	390	return NULL;
	391	}
	392
96b0ee45 BP	393	patch = (void *)get_zeroed_page(GFP_KERNEL);
	394	if (!patch)
	395	return NULL;
	396
18dbc916	397	return &microcode_amd_ops;
80cc9f10	398	}
f72c1a57 BP	399
	400	void __exit exit_amd_microcode(void)
	401	{
96b0ee45	402	free_page((unsigned long)patch);
f72c1a57	403	}