Commit | Line | Data |
---|---|---|
80cc9f10 PO |
1 | /* |
2 | * AMD CPU Microcode Update Driver for Linux | |
3 | * Copyright (C) 2008 Advanced Micro Devices Inc. | |
4 | * | |
5 | * Author: Peter Oruba <peter.oruba@amd.com> | |
6 | * | |
7 | * Based on work by: | |
8 | * Tigran Aivazian <tigran@aivazian.fsnet.co.uk> | |
9 | * | |
10 | * This driver allows to upgrade microcode on AMD | |
11 | * family 0x10 and 0x11 processors. | |
12 | * | |
2a3282a7 | 13 | * Licensed under the terms of the GNU General Public |
80cc9f10 | 14 | * License version 2. See file COPYING for details. |
4bae1967 | 15 | */ |
f58e1f53 JP |
16 | |
17 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
18 | ||
4bae1967 | 19 | #include <linux/firmware.h> |
4bae1967 IM |
20 | #include <linux/pci_ids.h> |
21 | #include <linux/uaccess.h> | |
22 | #include <linux/vmalloc.h> | |
23 | #include <linux/kernel.h> | |
24 | #include <linux/module.h> | |
80cc9f10 | 25 | #include <linux/pci.h> |
80cc9f10 | 26 | |
80cc9f10 | 27 | #include <asm/microcode.h> |
4bae1967 IM |
28 | #include <asm/processor.h> |
29 | #include <asm/msr.h> | |
80cc9f10 PO |
30 | |
31 | MODULE_DESCRIPTION("AMD Microcode Update Driver"); | |
3c52204b | 32 | MODULE_AUTHOR("Peter Oruba"); |
5d7b6052 | 33 | MODULE_LICENSE("GPL v2"); |
80cc9f10 PO |
34 | |
35 | #define UCODE_MAGIC 0x00414d44 | |
36 | #define UCODE_EQUIV_CPU_TABLE_TYPE 0x00000000 | |
37 | #define UCODE_UCODE_TYPE 0x00000001 | |
38 | ||
18dbc916 | 39 | struct equiv_cpu_entry { |
5549b94b AH |
40 | u32 installed_cpu; |
41 | u32 fixed_errata_mask; | |
42 | u32 fixed_errata_compare; | |
43 | u16 equiv_cpu; | |
44 | u16 res; | |
45 | } __attribute__((packed)); | |
18dbc916 DA |
46 | |
47 | struct microcode_header_amd { | |
5549b94b AH |
48 | u32 data_code; |
49 | u32 patch_id; | |
50 | u16 mc_patch_data_id; | |
51 | u8 mc_patch_data_len; | |
52 | u8 init_flag; | |
53 | u32 mc_patch_data_checksum; | |
54 | u32 nb_dev_id; | |
55 | u32 sb_dev_id; | |
56 | u16 processor_rev_id; | |
57 | u8 nb_rev_id; | |
58 | u8 sb_rev_id; | |
59 | u8 bios_api_rev; | |
60 | u8 reserved1[3]; | |
61 | u32 match_reg[8]; | |
62 | } __attribute__((packed)); | |
18dbc916 DA |
63 | |
64 | struct microcode_amd { | |
4bae1967 IM |
65 | struct microcode_header_amd hdr; |
66 | unsigned int mpb[0]; | |
18dbc916 DA |
67 | }; |
68 | ||
6cc9b6d9 AH |
69 | #define UCODE_MAX_SIZE 2048 |
70 | #define UCODE_CONTAINER_SECTION_HDR 8 | |
71 | #define UCODE_CONTAINER_HEADER_SIZE 12 | |
80cc9f10 | 72 | |
a0a29b62 | 73 | static struct equiv_cpu_entry *equiv_cpu_table; |
80cc9f10 | 74 | |
d45de409 | 75 | static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig) |
80cc9f10 | 76 | { |
3b2e3d85 | 77 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
29d0887f | 78 | u32 dummy; |
80cc9f10 | 79 | |
8cc2361b | 80 | memset(csig, 0, sizeof(*csig)); |
3b2e3d85 AH |
81 | if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) { |
82 | pr_warning("microcode: CPU%d: AMD CPU family 0x%x not " | |
83 | "supported\n", cpu, c->x86); | |
84 | return -1; | |
85 | } | |
29d0887f | 86 | rdmsr(MSR_AMD64_PATCH_LEVEL, csig->rev, dummy); |
f58e1f53 | 87 | pr_info("CPU%d: patch_level=0x%x\n", cpu, csig->rev); |
d45de409 | 88 | return 0; |
80cc9f10 PO |
89 | } |
90 | ||
a0a29b62 | 91 | static int get_matching_microcode(int cpu, void *mc, int rev) |
80cc9f10 | 92 | { |
80cc9f10 | 93 | struct microcode_header_amd *mc_header = mc; |
80cc9f10 | 94 | unsigned int current_cpu_id; |
5549b94b | 95 | u16 equiv_cpu_id = 0; |
80cc9f10 PO |
96 | unsigned int i = 0; |
97 | ||
a0a29b62 | 98 | BUG_ON(equiv_cpu_table == NULL); |
80cc9f10 PO |
99 | current_cpu_id = cpuid_eax(0x00000001); |
100 | ||
101 | while (equiv_cpu_table[i].installed_cpu != 0) { | |
102 | if (current_cpu_id == equiv_cpu_table[i].installed_cpu) { | |
5549b94b | 103 | equiv_cpu_id = equiv_cpu_table[i].equiv_cpu; |
80cc9f10 PO |
104 | break; |
105 | } | |
106 | i++; | |
107 | } | |
108 | ||
14c56942 | 109 | if (!equiv_cpu_id) |
80cc9f10 | 110 | return 0; |
80cc9f10 | 111 | |
6e18da75 | 112 | if (mc_header->processor_rev_id != equiv_cpu_id) |
80cc9f10 | 113 | return 0; |
80cc9f10 | 114 | |
98415301 AH |
115 | /* ucode might be chipset specific -- currently we don't support this */ |
116 | if (mc_header->nb_dev_id || mc_header->sb_dev_id) { | |
f58e1f53 JP |
117 | pr_err("CPU%d: loading of chipset specific code not yet supported\n", |
118 | cpu); | |
98415301 | 119 | return 0; |
80cc9f10 PO |
120 | } |
121 | ||
a0a29b62 | 122 | if (mc_header->patch_id <= rev) |
80cc9f10 PO |
123 | return 0; |
124 | ||
80cc9f10 PO |
125 | return 1; |
126 | } | |
127 | ||
871b72dd | 128 | static int apply_microcode_amd(int cpu) |
80cc9f10 | 129 | { |
29d0887f | 130 | u32 rev, dummy; |
80cc9f10 PO |
131 | int cpu_num = raw_smp_processor_id(); |
132 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu_num; | |
18dbc916 | 133 | struct microcode_amd *mc_amd = uci->mc; |
80cc9f10 PO |
134 | |
135 | /* We should bind the task to the CPU */ | |
136 | BUG_ON(cpu_num != cpu); | |
137 | ||
18dbc916 | 138 | if (mc_amd == NULL) |
871b72dd | 139 | return 0; |
80cc9f10 | 140 | |
f34a10bd | 141 | wrmsrl(MSR_AMD64_PATCH_LOADER, (u64)(long)&mc_amd->hdr.data_code); |
80cc9f10 | 142 | /* get patch id after patching */ |
29d0887f | 143 | rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy); |
80cc9f10 PO |
144 | |
145 | /* check current patch id and patch's id for match */ | |
18dbc916 | 146 | if (rev != mc_amd->hdr.patch_id) { |
f58e1f53 JP |
147 | pr_err("CPU%d: update failed (for patch_level=0x%x)\n", |
148 | cpu, mc_amd->hdr.patch_id); | |
871b72dd | 149 | return -1; |
80cc9f10 PO |
150 | } |
151 | ||
f58e1f53 | 152 | pr_info("CPU%d: updated (new patch_level=0x%x)\n", cpu, rev); |
d45de409 | 153 | uci->cpu_sig.rev = rev; |
871b72dd DA |
154 | |
155 | return 0; | |
80cc9f10 PO |
156 | } |
157 | ||
4bae1967 IM |
158 | static void * |
159 | get_next_ucode(const u8 *buf, unsigned int size, unsigned int *mc_size) | |
80cc9f10 | 160 | { |
a0a29b62 | 161 | unsigned int total_size; |
d4738792 | 162 | u8 section_hdr[UCODE_CONTAINER_SECTION_HDR]; |
a0a29b62 | 163 | void *mc; |
80cc9f10 | 164 | |
c7657ac0 | 165 | get_ucode_data(section_hdr, buf, UCODE_CONTAINER_SECTION_HDR); |
80cc9f10 | 166 | |
d4738792 | 167 | if (section_hdr[0] != UCODE_UCODE_TYPE) { |
f58e1f53 | 168 | pr_err("error: invalid type field in container file section header\n"); |
a0a29b62 | 169 | return NULL; |
80cc9f10 PO |
170 | } |
171 | ||
d4738792 | 172 | total_size = (unsigned long) (section_hdr[4] + (section_hdr[5] << 8)); |
80cc9f10 | 173 | |
a0a29b62 | 174 | if (total_size > size || total_size > UCODE_MAX_SIZE) { |
f58e1f53 | 175 | pr_err("error: size mismatch\n"); |
a0a29b62 | 176 | return NULL; |
80cc9f10 PO |
177 | } |
178 | ||
1ea6be21 JJ |
179 | mc = vzalloc(UCODE_MAX_SIZE); |
180 | if (!mc) | |
181 | return NULL; | |
182 | ||
c7657ac0 BP |
183 | get_ucode_data(mc, buf + UCODE_CONTAINER_SECTION_HDR, total_size); |
184 | *mc_size = total_size + UCODE_CONTAINER_SECTION_HDR; | |
1ea6be21 | 185 | |
a0a29b62 | 186 | return mc; |
80cc9f10 PO |
187 | } |
188 | ||
0657d9eb | 189 | static int install_equiv_cpu_table(const u8 *buf) |
80cc9f10 | 190 | { |
b6cffde1 PO |
191 | u8 *container_hdr[UCODE_CONTAINER_HEADER_SIZE]; |
192 | unsigned int *buf_pos = (unsigned int *)container_hdr; | |
a0a29b62 | 193 | unsigned long size; |
80cc9f10 | 194 | |
c7657ac0 | 195 | get_ucode_data(&container_hdr, buf, UCODE_CONTAINER_HEADER_SIZE); |
80cc9f10 | 196 | |
a0a29b62 | 197 | size = buf_pos[2]; |
80cc9f10 | 198 | |
a0a29b62 | 199 | if (buf_pos[1] != UCODE_EQUIV_CPU_TABLE_TYPE || !size) { |
f58e1f53 | 200 | pr_err("error: invalid type field in container file section header\n"); |
80cc9f10 PO |
201 | return 0; |
202 | } | |
203 | ||
8e5e9521 | 204 | equiv_cpu_table = vmalloc(size); |
80cc9f10 | 205 | if (!equiv_cpu_table) { |
f58e1f53 | 206 | pr_err("failed to allocate equivalent CPU table\n"); |
80cc9f10 PO |
207 | return 0; |
208 | } | |
209 | ||
b6cffde1 | 210 | buf += UCODE_CONTAINER_HEADER_SIZE; |
c7657ac0 | 211 | get_ucode_data(equiv_cpu_table, buf, size); |
80cc9f10 | 212 | |
b6cffde1 | 213 | return size + UCODE_CONTAINER_HEADER_SIZE; /* add header length */ |
80cc9f10 PO |
214 | } |
215 | ||
a0a29b62 | 216 | static void free_equiv_cpu_table(void) |
80cc9f10 | 217 | { |
aeef50bc F |
218 | vfree(equiv_cpu_table); |
219 | equiv_cpu_table = NULL; | |
a0a29b62 | 220 | } |
80cc9f10 | 221 | |
871b72dd DA |
222 | static enum ucode_state |
223 | generic_load_microcode(int cpu, const u8 *data, size_t size) | |
a0a29b62 DA |
224 | { |
225 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; | |
8c135206 AH |
226 | const u8 *ucode_ptr = data; |
227 | void *new_mc = NULL; | |
228 | void *mc; | |
a0a29b62 DA |
229 | int new_rev = uci->cpu_sig.rev; |
230 | unsigned int leftover; | |
231 | unsigned long offset; | |
871b72dd | 232 | enum ucode_state state = UCODE_OK; |
80cc9f10 | 233 | |
0657d9eb | 234 | offset = install_equiv_cpu_table(ucode_ptr); |
80cc9f10 | 235 | if (!offset) { |
f58e1f53 | 236 | pr_err("failed to create equivalent cpu table\n"); |
871b72dd | 237 | return UCODE_ERROR; |
80cc9f10 PO |
238 | } |
239 | ||
a0a29b62 DA |
240 | ucode_ptr += offset; |
241 | leftover = size - offset; | |
242 | ||
243 | while (leftover) { | |
2f9284e4 | 244 | unsigned int uninitialized_var(mc_size); |
a0a29b62 DA |
245 | struct microcode_header_amd *mc_header; |
246 | ||
0657d9eb | 247 | mc = get_next_ucode(ucode_ptr, leftover, &mc_size); |
a0a29b62 | 248 | if (!mc) |
80cc9f10 | 249 | break; |
a0a29b62 DA |
250 | |
251 | mc_header = (struct microcode_header_amd *)mc; | |
252 | if (get_matching_microcode(cpu, mc, new_rev)) { | |
aeef50bc | 253 | vfree(new_mc); |
a0a29b62 DA |
254 | new_rev = mc_header->patch_id; |
255 | new_mc = mc; | |
be957763 | 256 | } else |
a0a29b62 DA |
257 | vfree(mc); |
258 | ||
259 | ucode_ptr += mc_size; | |
260 | leftover -= mc_size; | |
80cc9f10 | 261 | } |
a0a29b62 DA |
262 | |
263 | if (new_mc) { | |
264 | if (!leftover) { | |
aeef50bc | 265 | vfree(uci->mc); |
18dbc916 | 266 | uci->mc = new_mc; |
f58e1f53 | 267 | pr_debug("CPU%d found a matching microcode update with version 0x%x (current=0x%x)\n", |
be957763 | 268 | cpu, new_rev, uci->cpu_sig.rev); |
871b72dd | 269 | } else { |
a0a29b62 | 270 | vfree(new_mc); |
871b72dd DA |
271 | state = UCODE_ERROR; |
272 | } | |
273 | } else | |
274 | state = UCODE_NFOUND; | |
a0a29b62 DA |
275 | |
276 | free_equiv_cpu_table(); | |
277 | ||
871b72dd | 278 | return state; |
a0a29b62 DA |
279 | } |
280 | ||
871b72dd | 281 | static enum ucode_state request_microcode_fw(int cpu, struct device *device) |
a0a29b62 | 282 | { |
3b2e3d85 AH |
283 | const char *fw_name = "amd-ucode/microcode_amd.bin"; |
284 | const struct firmware *firmware; | |
871b72dd | 285 | enum ucode_state ret; |
a0a29b62 | 286 | |
3b2e3d85 AH |
287 | if (request_firmware(&firmware, fw_name, device)) { |
288 | printk(KERN_ERR "microcode: failed to load file %s\n", fw_name); | |
871b72dd | 289 | return UCODE_NFOUND; |
3b2e3d85 | 290 | } |
a0a29b62 | 291 | |
506f90ee | 292 | if (*(u32 *)firmware->data != UCODE_MAGIC) { |
f58e1f53 | 293 | pr_err("invalid UCODE_MAGIC (0x%08x)\n", |
506f90ee BP |
294 | *(u32 *)firmware->data); |
295 | return UCODE_ERROR; | |
296 | } | |
297 | ||
0657d9eb | 298 | ret = generic_load_microcode(cpu, firmware->data, firmware->size); |
a0a29b62 | 299 | |
3b2e3d85 AH |
300 | release_firmware(firmware); |
301 | ||
a0a29b62 DA |
302 | return ret; |
303 | } | |
304 | ||
871b72dd DA |
305 | static enum ucode_state |
306 | request_microcode_user(int cpu, const void __user *buf, size_t size) | |
a0a29b62 | 307 | { |
f58e1f53 | 308 | pr_info("AMD microcode update via /dev/cpu/microcode not supported\n"); |
871b72dd | 309 | return UCODE_ERROR; |
80cc9f10 PO |
310 | } |
311 | ||
80cc9f10 PO |
312 | static void microcode_fini_cpu_amd(int cpu) |
313 | { | |
314 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; | |
315 | ||
18dbc916 DA |
316 | vfree(uci->mc); |
317 | uci->mc = NULL; | |
80cc9f10 PO |
318 | } |
319 | ||
320 | static struct microcode_ops microcode_amd_ops = { | |
a0a29b62 DA |
321 | .request_microcode_user = request_microcode_user, |
322 | .request_microcode_fw = request_microcode_fw, | |
80cc9f10 PO |
323 | .collect_cpu_info = collect_cpu_info_amd, |
324 | .apply_microcode = apply_microcode_amd, | |
325 | .microcode_fini_cpu = microcode_fini_cpu_amd, | |
326 | }; | |
327 | ||
18dbc916 | 328 | struct microcode_ops * __init init_amd_microcode(void) |
80cc9f10 | 329 | { |
18dbc916 | 330 | return µcode_amd_ops; |
80cc9f10 | 331 | } |