Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Intel CPU Microcode Update Driver for Linux | |
3 | * | |
69688262 | 4 | * Copyright (C) 2000-2006 Tigran Aivazian <tigran@aivazian.fsnet.co.uk> |
9a3110bf | 5 | * 2006 Shaohua Li <shaohua.li@intel.com> |
1da177e4 LT |
6 | * |
7 | * This driver allows to upgrade microcode on Intel processors | |
bc4e0f9a | 8 | * belonging to IA-32 family - PentiumPro, Pentium II, |
1da177e4 LT |
9 | * Pentium III, Xeon, Pentium 4, etc. |
10 | * | |
bc4e0f9a BC |
11 | * Reference: Section 8.11 of Volume 3a, IA-32 Intel? Architecture |
12 | * Software Developer's Manual | |
13 | * Order Number 253668 or free download from: | |
14 | * | |
50a23e6e | 15 | * http://developer.intel.com/Assets/PDF/manual/253668.pdf |
1da177e4 LT |
16 | * |
17 | * For more information, go to http://www.urbanmyth.org/microcode | |
18 | * | |
19 | * This program is free software; you can redistribute it and/or | |
20 | * modify it under the terms of the GNU General Public License | |
21 | * as published by the Free Software Foundation; either version | |
22 | * 2 of the License, or (at your option) any later version. | |
23 | * | |
24 | * 1.0 16 Feb 2000, Tigran Aivazian <tigran@sco.com> | |
25 | * Initial release. | |
26 | * 1.01 18 Feb 2000, Tigran Aivazian <tigran@sco.com> | |
27 | * Added read() support + cleanups. | |
28 | * 1.02 21 Feb 2000, Tigran Aivazian <tigran@sco.com> | |
29 | * Added 'device trimming' support. open(O_WRONLY) zeroes | |
30 | * and frees the saved copy of applied microcode. | |
31 | * 1.03 29 Feb 2000, Tigran Aivazian <tigran@sco.com> | |
32 | * Made to use devfs (/dev/cpu/microcode) + cleanups. | |
33 | * 1.04 06 Jun 2000, Simon Trimmer <simon@veritas.com> | |
34 | * Added misc device support (now uses both devfs and misc). | |
35 | * Added MICROCODE_IOCFREE ioctl to clear memory. | |
36 | * 1.05 09 Jun 2000, Simon Trimmer <simon@veritas.com> | |
37 | * Messages for error cases (non Intel & no suitable microcode). | |
38 | * 1.06 03 Aug 2000, Tigran Aivazian <tigran@veritas.com> | |
39 | * Removed ->release(). Removed exclusive open and status bitmap. | |
40 | * Added microcode_rwsem to serialize read()/write()/ioctl(). | |
41 | * Removed global kernel lock usage. | |
42 | * 1.07 07 Sep 2000, Tigran Aivazian <tigran@veritas.com> | |
43 | * Write 0 to 0x8B msr and then cpuid before reading revision, | |
44 | * so that it works even if there were no update done by the | |
45 | * BIOS. Otherwise, reading from 0x8B gives junk (which happened | |
46 | * to be 0 on my machine which is why it worked even when I | |
47 | * disabled update by the BIOS) | |
48 | * Thanks to Eric W. Biederman <ebiederman@lnxi.com> for the fix. | |
49 | * 1.08 11 Dec 2000, Richard Schaal <richard.schaal@intel.com> and | |
50 | * Tigran Aivazian <tigran@veritas.com> | |
51 | * Intel Pentium 4 processor support and bugfixes. | |
52 | * 1.09 30 Oct 2001, Tigran Aivazian <tigran@veritas.com> | |
53 | * Bugfix for HT (Hyper-Threading) enabled processors | |
54 | * whereby processor resources are shared by all logical processors | |
55 | * in a single CPU package. | |
56 | * 1.10 28 Feb 2002 Asit K Mallick <asit.k.mallick@intel.com> and | |
57 | * Tigran Aivazian <tigran@veritas.com>, | |
f516526f PO |
58 | * Serialize updates as required on HT processors due to |
59 | * speculative nature of implementation. | |
1da177e4 LT |
60 | * 1.11 22 Mar 2002 Tigran Aivazian <tigran@veritas.com> |
61 | * Fix the panic when writing zero-length microcode chunk. | |
bc4e0f9a | 62 | * 1.12 29 Sep 2003 Nitin Kamble <nitin.a.kamble@intel.com>, |
1da177e4 LT |
63 | * Jun Nakajima <jun.nakajima@intel.com> |
64 | * Support for the microcode updates in the new format. | |
65 | * 1.13 10 Oct 2003 Tigran Aivazian <tigran@veritas.com> | |
66 | * Removed ->read() method and obsoleted MICROCODE_IOCFREE ioctl | |
bc4e0f9a | 67 | * because we no longer hold a copy of applied microcode |
1da177e4 LT |
68 | * in kernel memory. |
69 | * 1.14 25 Jun 2004 Tigran Aivazian <tigran@veritas.com> | |
70 | * Fix sigmatch() macro to handle old CPUs with pf == 0. | |
71 | * Thanks to Stuart Swales for pointing out this bug. | |
72 | */ | |
f58e1f53 JP |
73 | |
74 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
75 | ||
4bae1967 | 76 | #include <linux/firmware.h> |
4bae1967 | 77 | #include <linux/uaccess.h> |
4bae1967 IM |
78 | #include <linux/kernel.h> |
79 | #include <linux/module.h> | |
871b72dd | 80 | #include <linux/vmalloc.h> |
1da177e4 | 81 | |
9a56a0f8 | 82 | #include <asm/microcode.h> |
4bae1967 IM |
83 | #include <asm/processor.h> |
84 | #include <asm/msr.h> | |
1da177e4 | 85 | |
3e135d88 | 86 | MODULE_DESCRIPTION("Microcode Update Driver"); |
69688262 | 87 | MODULE_AUTHOR("Tigran Aivazian <tigran@aivazian.fsnet.co.uk>"); |
1da177e4 LT |
88 | MODULE_LICENSE("GPL"); |
89 | ||
18dbc916 DA |
90 | struct microcode_header_intel { |
91 | unsigned int hdrver; | |
92 | unsigned int rev; | |
93 | unsigned int date; | |
94 | unsigned int sig; | |
95 | unsigned int cksum; | |
96 | unsigned int ldrver; | |
97 | unsigned int pf; | |
98 | unsigned int datasize; | |
99 | unsigned int totalsize; | |
100 | unsigned int reserved[3]; | |
101 | }; | |
102 | ||
103 | struct microcode_intel { | |
104 | struct microcode_header_intel hdr; | |
105 | unsigned int bits[0]; | |
106 | }; | |
107 | ||
108 | /* microcode format is extended from prescott processors */ | |
109 | struct extended_signature { | |
110 | unsigned int sig; | |
111 | unsigned int pf; | |
112 | unsigned int cksum; | |
113 | }; | |
114 | ||
115 | struct extended_sigtable { | |
116 | unsigned int count; | |
117 | unsigned int cksum; | |
118 | unsigned int reserved[3]; | |
119 | struct extended_signature sigs[0]; | |
120 | }; | |
121 | ||
4bae1967 | 122 | #define DEFAULT_UCODE_DATASIZE (2000) |
f516526f PO |
123 | #define MC_HEADER_SIZE (sizeof(struct microcode_header_intel)) |
124 | #define DEFAULT_UCODE_TOTALSIZE (DEFAULT_UCODE_DATASIZE + MC_HEADER_SIZE) | |
125 | #define EXT_HEADER_SIZE (sizeof(struct extended_sigtable)) | |
126 | #define EXT_SIGNATURE_SIZE (sizeof(struct extended_signature)) | |
3e135d88 | 127 | #define DWSIZE (sizeof(u32)) |
4bae1967 | 128 | |
1da177e4 | 129 | #define get_totalsize(mc) \ |
d4ee3668 PO |
130 | (((struct microcode_intel *)mc)->hdr.totalsize ? \ |
131 | ((struct microcode_intel *)mc)->hdr.totalsize : \ | |
132 | DEFAULT_UCODE_TOTALSIZE) | |
133 | ||
1da177e4 | 134 | #define get_datasize(mc) \ |
d4ee3668 PO |
135 | (((struct microcode_intel *)mc)->hdr.datasize ? \ |
136 | ((struct microcode_intel *)mc)->hdr.datasize : DEFAULT_UCODE_DATASIZE) | |
1da177e4 LT |
137 | |
138 | #define sigmatch(s1, s2, p1, p2) \ | |
139 | (((s1) == (s2)) && (((p1) & (p2)) || (((p1) == 0) && ((p2) == 0)))) | |
140 | ||
141 | #define exttable_size(et) ((et)->count * EXT_SIGNATURE_SIZE + EXT_HEADER_SIZE) | |
142 | ||
d45de409 | 143 | static int collect_cpu_info(int cpu_num, struct cpu_signature *csig) |
1da177e4 | 144 | { |
92cb7612 | 145 | struct cpuinfo_x86 *c = &cpu_data(cpu_num); |
1da177e4 LT |
146 | unsigned int val[2]; |
147 | ||
d45de409 | 148 | memset(csig, 0, sizeof(*csig)); |
1da177e4 LT |
149 | |
150 | if (c->x86_vendor != X86_VENDOR_INTEL || c->x86 < 6 || | |
3e135d88 | 151 | cpu_has(c, X86_FEATURE_IA64)) { |
f58e1f53 | 152 | pr_err("CPU%d not a capable Intel processor\n", cpu_num); |
d45de409 | 153 | return -1; |
9a3110bf | 154 | } |
1da177e4 | 155 | |
d45de409 | 156 | csig->sig = cpuid_eax(0x00000001); |
9a3110bf SL |
157 | |
158 | if ((c->x86_model >= 5) || (c->x86 > 6)) { | |
159 | /* get processor flags from MSR 0x17 */ | |
160 | rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]); | |
d45de409 | 161 | csig->pf = 1 << ((val[1] >> 18) & 7); |
1da177e4 LT |
162 | } |
163 | ||
164 | wrmsr(MSR_IA32_UCODE_REV, 0, 0); | |
245067d1 | 165 | /* see notes above for revision 1.07. Apparent chip bug */ |
487472bc | 166 | sync_core(); |
1da177e4 | 167 | /* get the current revision from MSR 0x8B */ |
d45de409 | 168 | rdmsr(MSR_IA32_UCODE_REV, val[0], csig->rev); |
280a9ca5 | 169 | |
f58e1f53 JP |
170 | pr_info("CPU%d sig=0x%x, pf=0x%x, revision=0x%x\n", |
171 | cpu_num, csig->sig, csig->pf, csig->rev); | |
d45de409 DA |
172 | |
173 | return 0; | |
1da177e4 LT |
174 | } |
175 | ||
a0a29b62 | 176 | static inline int update_match_cpu(struct cpu_signature *csig, int sig, int pf) |
1da177e4 | 177 | { |
a0a29b62 DA |
178 | return (!sigmatch(sig, csig->sig, pf, csig->pf)) ? 0 : 1; |
179 | } | |
1da177e4 | 180 | |
dd3feda7 | 181 | static inline int |
4bae1967 | 182 | update_match_revision(struct microcode_header_intel *mc_header, int rev) |
a0a29b62 DA |
183 | { |
184 | return (mc_header->rev <= rev) ? 0 : 1; | |
1da177e4 LT |
185 | } |
186 | ||
8d86f390 | 187 | static int microcode_sanity_check(void *mc) |
1da177e4 | 188 | { |
4bae1967 | 189 | unsigned long total_size, data_size, ext_table_size; |
d4ee3668 | 190 | struct microcode_header_intel *mc_header = mc; |
9a3110bf | 191 | struct extended_sigtable *ext_header = NULL; |
9a3110bf | 192 | int sum, orig_sum, ext_sigcount = 0, i; |
4bae1967 | 193 | struct extended_signature *ext_sig; |
9a3110bf SL |
194 | |
195 | total_size = get_totalsize(mc_header); | |
196 | data_size = get_datasize(mc_header); | |
4bae1967 | 197 | |
bd8e39f9 | 198 | if (data_size + MC_HEADER_SIZE > total_size) { |
f58e1f53 | 199 | pr_err("error! Bad data size in microcode data file\n"); |
9a3110bf SL |
200 | return -EINVAL; |
201 | } | |
1da177e4 | 202 | |
9a3110bf | 203 | if (mc_header->ldrver != 1 || mc_header->hdrver != 1) { |
f58e1f53 | 204 | pr_err("error! Unknown microcode update format\n"); |
9a3110bf SL |
205 | return -EINVAL; |
206 | } | |
207 | ext_table_size = total_size - (MC_HEADER_SIZE + data_size); | |
208 | if (ext_table_size) { | |
209 | if ((ext_table_size < EXT_HEADER_SIZE) | |
210 | || ((ext_table_size - EXT_HEADER_SIZE) % EXT_SIGNATURE_SIZE)) { | |
f58e1f53 | 211 | pr_err("error! Small exttable size in microcode data file\n"); |
9a3110bf | 212 | return -EINVAL; |
1da177e4 | 213 | } |
9a3110bf SL |
214 | ext_header = mc + MC_HEADER_SIZE + data_size; |
215 | if (ext_table_size != exttable_size(ext_header)) { | |
f58e1f53 | 216 | pr_err("error! Bad exttable size in microcode data file\n"); |
9a3110bf | 217 | return -EFAULT; |
1da177e4 | 218 | } |
9a3110bf SL |
219 | ext_sigcount = ext_header->count; |
220 | } | |
1da177e4 | 221 | |
9a3110bf SL |
222 | /* check extended table checksum */ |
223 | if (ext_table_size) { | |
224 | int ext_table_sum = 0; | |
9a4b9efa | 225 | int *ext_tablep = (int *)ext_header; |
9a3110bf SL |
226 | |
227 | i = ext_table_size / DWSIZE; | |
228 | while (i--) | |
229 | ext_table_sum += ext_tablep[i]; | |
230 | if (ext_table_sum) { | |
f58e1f53 | 231 | pr_warning("aborting, bad extended signature table checksum\n"); |
9a3110bf | 232 | return -EINVAL; |
1da177e4 | 233 | } |
9a3110bf | 234 | } |
1da177e4 | 235 | |
9a3110bf SL |
236 | /* calculate the checksum */ |
237 | orig_sum = 0; | |
238 | i = (MC_HEADER_SIZE + data_size) / DWSIZE; | |
239 | while (i--) | |
240 | orig_sum += ((int *)mc)[i]; | |
241 | if (orig_sum) { | |
f58e1f53 | 242 | pr_err("aborting, bad checksum\n"); |
9a3110bf SL |
243 | return -EINVAL; |
244 | } | |
245 | if (!ext_table_size) | |
246 | return 0; | |
247 | /* check extended signature checksum */ | |
248 | for (i = 0; i < ext_sigcount; i++) { | |
ade1af77 JE |
249 | ext_sig = (void *)ext_header + EXT_HEADER_SIZE + |
250 | EXT_SIGNATURE_SIZE * i; | |
9a3110bf SL |
251 | sum = orig_sum |
252 | - (mc_header->sig + mc_header->pf + mc_header->cksum) | |
253 | + (ext_sig->sig + ext_sig->pf + ext_sig->cksum); | |
254 | if (sum) { | |
f58e1f53 | 255 | pr_err("aborting, bad checksum\n"); |
9a3110bf | 256 | return -EINVAL; |
1da177e4 | 257 | } |
9a3110bf SL |
258 | } |
259 | return 0; | |
260 | } | |
5cf6c541 | 261 | |
9a3110bf SL |
262 | /* |
263 | * return 0 - no update found | |
264 | * return 1 - found update | |
9a3110bf | 265 | */ |
a0a29b62 DA |
266 | static int |
267 | get_matching_microcode(struct cpu_signature *cpu_sig, void *mc, int rev) | |
9a3110bf | 268 | { |
d4ee3668 | 269 | struct microcode_header_intel *mc_header = mc; |
9a3110bf SL |
270 | struct extended_sigtable *ext_header; |
271 | unsigned long total_size = get_totalsize(mc_header); | |
272 | int ext_sigcount, i; | |
273 | struct extended_signature *ext_sig; | |
9a3110bf | 274 | |
a0a29b62 DA |
275 | if (!update_match_revision(mc_header, rev)) |
276 | return 0; | |
277 | ||
278 | if (update_match_cpu(cpu_sig, mc_header->sig, mc_header->pf)) | |
279 | return 1; | |
9a3110bf | 280 | |
a0a29b62 | 281 | /* Look for ext. headers: */ |
9a3110bf SL |
282 | if (total_size <= get_datasize(mc_header) + MC_HEADER_SIZE) |
283 | return 0; | |
284 | ||
ade1af77 | 285 | ext_header = mc + get_datasize(mc_header) + MC_HEADER_SIZE; |
9a3110bf | 286 | ext_sigcount = ext_header->count; |
ade1af77 | 287 | ext_sig = (void *)ext_header + EXT_HEADER_SIZE; |
a0a29b62 | 288 | |
9a3110bf | 289 | for (i = 0; i < ext_sigcount; i++) { |
a0a29b62 DA |
290 | if (update_match_cpu(cpu_sig, ext_sig->sig, ext_sig->pf)) |
291 | return 1; | |
9a3110bf SL |
292 | ext_sig++; |
293 | } | |
294 | return 0; | |
1da177e4 LT |
295 | } |
296 | ||
871b72dd | 297 | static int apply_microcode(int cpu) |
1da177e4 | 298 | { |
4bae1967 IM |
299 | struct microcode_intel *mc_intel; |
300 | struct ucode_cpu_info *uci; | |
1da177e4 | 301 | unsigned int val[2]; |
4bae1967 IM |
302 | int cpu_num; |
303 | ||
304 | cpu_num = raw_smp_processor_id(); | |
305 | uci = ucode_cpu_info + cpu; | |
306 | mc_intel = uci->mc; | |
1da177e4 | 307 | |
9a3110bf SL |
308 | /* We should bind the task to the CPU */ |
309 | BUG_ON(cpu_num != cpu); | |
310 | ||
18dbc916 | 311 | if (mc_intel == NULL) |
871b72dd | 312 | return 0; |
1da177e4 LT |
313 | |
314 | /* write microcode via MSR 0x79 */ | |
315 | wrmsr(MSR_IA32_UCODE_WRITE, | |
18dbc916 DA |
316 | (unsigned long) mc_intel->bits, |
317 | (unsigned long) mc_intel->bits >> 16 >> 16); | |
1da177e4 LT |
318 | wrmsr(MSR_IA32_UCODE_REV, 0, 0); |
319 | ||
245067d1 | 320 | /* see notes above for revision 1.07. Apparent chip bug */ |
487472bc | 321 | sync_core(); |
245067d1 | 322 | |
1da177e4 LT |
323 | /* get the current revision from MSR 0x8B */ |
324 | rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]); | |
325 | ||
18dbc916 | 326 | if (val[1] != mc_intel->hdr.rev) { |
f58e1f53 JP |
327 | pr_err("CPU%d update to revision 0x%x failed\n", |
328 | cpu_num, mc_intel->hdr.rev); | |
871b72dd | 329 | return -1; |
9a3110bf | 330 | } |
3235dc3f | 331 | pr_info("CPU%d updated to revision 0x%x, date = %04x-%02x-%02x\n", |
871b72dd | 332 | cpu_num, val[1], |
18dbc916 DA |
333 | mc_intel->hdr.date & 0xffff, |
334 | mc_intel->hdr.date >> 24, | |
335 | (mc_intel->hdr.date >> 16) & 0xff); | |
4bae1967 | 336 | |
d45de409 | 337 | uci->cpu_sig.rev = val[1]; |
871b72dd DA |
338 | |
339 | return 0; | |
1da177e4 LT |
340 | } |
341 | ||
871b72dd DA |
342 | static enum ucode_state generic_load_microcode(int cpu, void *data, size_t size, |
343 | int (*get_ucode_data)(void *, const void *, size_t)) | |
9a3110bf | 344 | { |
a0a29b62 | 345 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; |
938179b4 | 346 | u8 *ucode_ptr = data, *new_mc = NULL, *mc = NULL; |
a0a29b62 DA |
347 | int new_rev = uci->cpu_sig.rev; |
348 | unsigned int leftover = size; | |
871b72dd | 349 | enum ucode_state state = UCODE_OK; |
938179b4 | 350 | unsigned int curr_mc_size = 0; |
9a3110bf | 351 | |
a0a29b62 DA |
352 | while (leftover) { |
353 | struct microcode_header_intel mc_header; | |
354 | unsigned int mc_size; | |
9a3110bf | 355 | |
a0a29b62 DA |
356 | if (get_ucode_data(&mc_header, ucode_ptr, sizeof(mc_header))) |
357 | break; | |
a30a6a2c | 358 | |
a0a29b62 DA |
359 | mc_size = get_totalsize(&mc_header); |
360 | if (!mc_size || mc_size > leftover) { | |
f58e1f53 | 361 | pr_err("error! Bad data in microcode data file\n"); |
a0a29b62 DA |
362 | break; |
363 | } | |
a30a6a2c | 364 | |
938179b4 DS |
365 | /* For performance reasons, reuse mc area when possible */ |
366 | if (!mc || mc_size > curr_mc_size) { | |
5cdd2de0 | 367 | vfree(mc); |
938179b4 DS |
368 | mc = vmalloc(mc_size); |
369 | if (!mc) | |
370 | break; | |
371 | curr_mc_size = mc_size; | |
372 | } | |
a0a29b62 DA |
373 | |
374 | if (get_ucode_data(mc, ucode_ptr, mc_size) || | |
375 | microcode_sanity_check(mc) < 0) { | |
a0a29b62 DA |
376 | break; |
377 | } | |
378 | ||
379 | if (get_matching_microcode(&uci->cpu_sig, mc, new_rev)) { | |
5cdd2de0 | 380 | vfree(new_mc); |
a0a29b62 DA |
381 | new_rev = mc_header.rev; |
382 | new_mc = mc; | |
938179b4 DS |
383 | mc = NULL; /* trigger new vmalloc */ |
384 | } | |
a0a29b62 DA |
385 | |
386 | ucode_ptr += mc_size; | |
387 | leftover -= mc_size; | |
a30a6a2c SL |
388 | } |
389 | ||
5cdd2de0 | 390 | vfree(mc); |
938179b4 | 391 | |
871b72dd | 392 | if (leftover) { |
5cdd2de0 | 393 | vfree(new_mc); |
871b72dd | 394 | state = UCODE_ERROR; |
4bae1967 | 395 | goto out; |
871b72dd | 396 | } |
4bae1967 | 397 | |
871b72dd DA |
398 | if (!new_mc) { |
399 | state = UCODE_NFOUND; | |
4bae1967 | 400 | goto out; |
a30a6a2c | 401 | } |
a0a29b62 | 402 | |
5cdd2de0 | 403 | vfree(uci->mc); |
4bae1967 IM |
404 | uci->mc = (struct microcode_intel *)new_mc; |
405 | ||
f58e1f53 JP |
406 | pr_debug("CPU%d found a matching microcode update with version 0x%x (current=0x%x)\n", |
407 | cpu, new_rev, uci->cpu_sig.rev); | |
871b72dd DA |
408 | out: |
409 | return state; | |
a30a6a2c SL |
410 | } |
411 | ||
a0a29b62 DA |
412 | static int get_ucode_fw(void *to, const void *from, size_t n) |
413 | { | |
414 | memcpy(to, from, n); | |
415 | return 0; | |
416 | } | |
a30a6a2c | 417 | |
871b72dd | 418 | static enum ucode_state request_microcode_fw(int cpu, struct device *device) |
a30a6a2c SL |
419 | { |
420 | char name[30]; | |
92cb7612 | 421 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
a30a6a2c | 422 | const struct firmware *firmware; |
871b72dd | 423 | enum ucode_state ret; |
a30a6a2c | 424 | |
3e135d88 | 425 | sprintf(name, "intel-ucode/%02x-%02x-%02x", |
a30a6a2c | 426 | c->x86, c->x86_model, c->x86_mask); |
871b72dd DA |
427 | |
428 | if (request_firmware(&firmware, name, device)) { | |
f58e1f53 | 429 | pr_debug("data file %s load failed\n", name); |
871b72dd | 430 | return UCODE_NFOUND; |
a30a6a2c | 431 | } |
a0a29b62 | 432 | |
dd3feda7 JSR |
433 | ret = generic_load_microcode(cpu, (void *)firmware->data, |
434 | firmware->size, &get_ucode_fw); | |
a0a29b62 | 435 | |
a30a6a2c SL |
436 | release_firmware(firmware); |
437 | ||
a0a29b62 DA |
438 | return ret; |
439 | } | |
440 | ||
441 | static int get_ucode_user(void *to, const void *from, size_t n) | |
442 | { | |
443 | return copy_from_user(to, from, n); | |
444 | } | |
445 | ||
871b72dd DA |
446 | static enum ucode_state |
447 | request_microcode_user(int cpu, const void __user *buf, size_t size) | |
a0a29b62 | 448 | { |
dd3feda7 | 449 | return generic_load_microcode(cpu, (void *)buf, size, &get_ucode_user); |
a30a6a2c SL |
450 | } |
451 | ||
8d86f390 | 452 | static void microcode_fini_cpu(int cpu) |
a30a6a2c SL |
453 | { |
454 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; | |
455 | ||
18dbc916 DA |
456 | vfree(uci->mc); |
457 | uci->mc = NULL; | |
a30a6a2c | 458 | } |
8d86f390 | 459 | |
4db646b1 | 460 | static struct microcode_ops microcode_intel_ops = { |
a0a29b62 DA |
461 | .request_microcode_user = request_microcode_user, |
462 | .request_microcode_fw = request_microcode_fw, | |
8d86f390 PO |
463 | .collect_cpu_info = collect_cpu_info, |
464 | .apply_microcode = apply_microcode, | |
465 | .microcode_fini_cpu = microcode_fini_cpu, | |
466 | }; | |
467 | ||
18dbc916 | 468 | struct microcode_ops * __init init_intel_microcode(void) |
8d86f390 | 469 | { |
18dbc916 | 470 | return µcode_intel_ops; |
8d86f390 PO |
471 | } |
472 |