Merge branch 'oprofile-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / arch / x86 / kernel / microcode_intel.c
CommitLineData
1da177e4
LT
1/*
2 * Intel CPU Microcode Update Driver for Linux
3 *
69688262 4 * Copyright (C) 2000-2006 Tigran Aivazian <tigran@aivazian.fsnet.co.uk>
9a3110bf 5 * 2006 Shaohua Li <shaohua.li@intel.com>
1da177e4
LT
6 *
7 * This driver allows to upgrade microcode on Intel processors
bc4e0f9a 8 * belonging to IA-32 family - PentiumPro, Pentium II,
1da177e4
LT
9 * Pentium III, Xeon, Pentium 4, etc.
10 *
bc4e0f9a
BC
11 * Reference: Section 8.11 of Volume 3a, IA-32 Intel? Architecture
12 * Software Developer's Manual
13 * Order Number 253668 or free download from:
14 *
15 * http://developer.intel.com/design/pentium4/manuals/253668.htm
1da177e4
LT
16 *
17 * For more information, go to http://www.urbanmyth.org/microcode
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version
22 * 2 of the License, or (at your option) any later version.
23 *
24 * 1.0 16 Feb 2000, Tigran Aivazian <tigran@sco.com>
25 * Initial release.
26 * 1.01 18 Feb 2000, Tigran Aivazian <tigran@sco.com>
27 * Added read() support + cleanups.
28 * 1.02 21 Feb 2000, Tigran Aivazian <tigran@sco.com>
29 * Added 'device trimming' support. open(O_WRONLY) zeroes
30 * and frees the saved copy of applied microcode.
31 * 1.03 29 Feb 2000, Tigran Aivazian <tigran@sco.com>
32 * Made to use devfs (/dev/cpu/microcode) + cleanups.
33 * 1.04 06 Jun 2000, Simon Trimmer <simon@veritas.com>
34 * Added misc device support (now uses both devfs and misc).
35 * Added MICROCODE_IOCFREE ioctl to clear memory.
36 * 1.05 09 Jun 2000, Simon Trimmer <simon@veritas.com>
37 * Messages for error cases (non Intel & no suitable microcode).
38 * 1.06 03 Aug 2000, Tigran Aivazian <tigran@veritas.com>
39 * Removed ->release(). Removed exclusive open and status bitmap.
40 * Added microcode_rwsem to serialize read()/write()/ioctl().
41 * Removed global kernel lock usage.
42 * 1.07 07 Sep 2000, Tigran Aivazian <tigran@veritas.com>
43 * Write 0 to 0x8B msr and then cpuid before reading revision,
44 * so that it works even if there were no update done by the
45 * BIOS. Otherwise, reading from 0x8B gives junk (which happened
46 * to be 0 on my machine which is why it worked even when I
47 * disabled update by the BIOS)
48 * Thanks to Eric W. Biederman <ebiederman@lnxi.com> for the fix.
49 * 1.08 11 Dec 2000, Richard Schaal <richard.schaal@intel.com> and
50 * Tigran Aivazian <tigran@veritas.com>
51 * Intel Pentium 4 processor support and bugfixes.
52 * 1.09 30 Oct 2001, Tigran Aivazian <tigran@veritas.com>
53 * Bugfix for HT (Hyper-Threading) enabled processors
54 * whereby processor resources are shared by all logical processors
55 * in a single CPU package.
56 * 1.10 28 Feb 2002 Asit K Mallick <asit.k.mallick@intel.com> and
57 * Tigran Aivazian <tigran@veritas.com>,
f516526f
PO
58 * Serialize updates as required on HT processors due to
59 * speculative nature of implementation.
1da177e4
LT
60 * 1.11 22 Mar 2002 Tigran Aivazian <tigran@veritas.com>
61 * Fix the panic when writing zero-length microcode chunk.
bc4e0f9a 62 * 1.12 29 Sep 2003 Nitin Kamble <nitin.a.kamble@intel.com>,
1da177e4
LT
63 * Jun Nakajima <jun.nakajima@intel.com>
64 * Support for the microcode updates in the new format.
65 * 1.13 10 Oct 2003 Tigran Aivazian <tigran@veritas.com>
66 * Removed ->read() method and obsoleted MICROCODE_IOCFREE ioctl
bc4e0f9a 67 * because we no longer hold a copy of applied microcode
1da177e4
LT
68 * in kernel memory.
69 * 1.14 25 Jun 2004 Tigran Aivazian <tigran@veritas.com>
70 * Fix sigmatch() macro to handle old CPUs with pf == 0.
71 * Thanks to Stuart Swales for pointing out this bug.
72 */
4bae1967 73#include <linux/firmware.h>
4bae1967 74#include <linux/uaccess.h>
4bae1967
IM
75#include <linux/kernel.h>
76#include <linux/module.h>
871b72dd 77#include <linux/vmalloc.h>
1da177e4 78
9a56a0f8 79#include <asm/microcode.h>
4bae1967
IM
80#include <asm/processor.h>
81#include <asm/msr.h>
1da177e4 82
3e135d88 83MODULE_DESCRIPTION("Microcode Update Driver");
69688262 84MODULE_AUTHOR("Tigran Aivazian <tigran@aivazian.fsnet.co.uk>");
1da177e4
LT
85MODULE_LICENSE("GPL");
86
18dbc916
DA
87struct microcode_header_intel {
88 unsigned int hdrver;
89 unsigned int rev;
90 unsigned int date;
91 unsigned int sig;
92 unsigned int cksum;
93 unsigned int ldrver;
94 unsigned int pf;
95 unsigned int datasize;
96 unsigned int totalsize;
97 unsigned int reserved[3];
98};
99
100struct microcode_intel {
101 struct microcode_header_intel hdr;
102 unsigned int bits[0];
103};
104
105/* microcode format is extended from prescott processors */
106struct extended_signature {
107 unsigned int sig;
108 unsigned int pf;
109 unsigned int cksum;
110};
111
112struct extended_sigtable {
113 unsigned int count;
114 unsigned int cksum;
115 unsigned int reserved[3];
116 struct extended_signature sigs[0];
117};
118
4bae1967 119#define DEFAULT_UCODE_DATASIZE (2000)
f516526f
PO
120#define MC_HEADER_SIZE (sizeof(struct microcode_header_intel))
121#define DEFAULT_UCODE_TOTALSIZE (DEFAULT_UCODE_DATASIZE + MC_HEADER_SIZE)
122#define EXT_HEADER_SIZE (sizeof(struct extended_sigtable))
123#define EXT_SIGNATURE_SIZE (sizeof(struct extended_signature))
3e135d88 124#define DWSIZE (sizeof(u32))
4bae1967 125
1da177e4 126#define get_totalsize(mc) \
d4ee3668
PO
127 (((struct microcode_intel *)mc)->hdr.totalsize ? \
128 ((struct microcode_intel *)mc)->hdr.totalsize : \
129 DEFAULT_UCODE_TOTALSIZE)
130
1da177e4 131#define get_datasize(mc) \
d4ee3668
PO
132 (((struct microcode_intel *)mc)->hdr.datasize ? \
133 ((struct microcode_intel *)mc)->hdr.datasize : DEFAULT_UCODE_DATASIZE)
1da177e4
LT
134
135#define sigmatch(s1, s2, p1, p2) \
136 (((s1) == (s2)) && (((p1) & (p2)) || (((p1) == 0) && ((p2) == 0))))
137
138#define exttable_size(et) ((et)->count * EXT_SIGNATURE_SIZE + EXT_HEADER_SIZE)
139
d45de409 140static int collect_cpu_info(int cpu_num, struct cpu_signature *csig)
1da177e4 141{
92cb7612 142 struct cpuinfo_x86 *c = &cpu_data(cpu_num);
1da177e4
LT
143 unsigned int val[2];
144
d45de409 145 memset(csig, 0, sizeof(*csig));
1da177e4
LT
146
147 if (c->x86_vendor != X86_VENDOR_INTEL || c->x86 < 6 ||
3e135d88 148 cpu_has(c, X86_FEATURE_IA64)) {
9a3110bf
SL
149 printk(KERN_ERR "microcode: CPU%d not a capable Intel "
150 "processor\n", cpu_num);
d45de409 151 return -1;
9a3110bf 152 }
1da177e4 153
d45de409 154 csig->sig = cpuid_eax(0x00000001);
9a3110bf
SL
155
156 if ((c->x86_model >= 5) || (c->x86 > 6)) {
157 /* get processor flags from MSR 0x17 */
158 rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]);
d45de409 159 csig->pf = 1 << ((val[1] >> 18) & 7);
1da177e4
LT
160 }
161
162 wrmsr(MSR_IA32_UCODE_REV, 0, 0);
245067d1 163 /* see notes above for revision 1.07. Apparent chip bug */
487472bc 164 sync_core();
1da177e4 165 /* get the current revision from MSR 0x8B */
d45de409 166 rdmsr(MSR_IA32_UCODE_REV, val[0], csig->rev);
280a9ca5 167
871b72dd
DA
168 printk(KERN_INFO "microcode: CPU%d sig=0x%x, pf=0x%x, revision=0x%x\n",
169 cpu_num, csig->sig, csig->pf, csig->rev);
d45de409
DA
170
171 return 0;
1da177e4
LT
172}
173
a0a29b62 174static inline int update_match_cpu(struct cpu_signature *csig, int sig, int pf)
1da177e4 175{
a0a29b62
DA
176 return (!sigmatch(sig, csig->sig, pf, csig->pf)) ? 0 : 1;
177}
1da177e4 178
dd3feda7 179static inline int
4bae1967 180update_match_revision(struct microcode_header_intel *mc_header, int rev)
a0a29b62
DA
181{
182 return (mc_header->rev <= rev) ? 0 : 1;
1da177e4
LT
183}
184
8d86f390 185static int microcode_sanity_check(void *mc)
1da177e4 186{
4bae1967 187 unsigned long total_size, data_size, ext_table_size;
d4ee3668 188 struct microcode_header_intel *mc_header = mc;
9a3110bf 189 struct extended_sigtable *ext_header = NULL;
9a3110bf 190 int sum, orig_sum, ext_sigcount = 0, i;
4bae1967 191 struct extended_signature *ext_sig;
9a3110bf
SL
192
193 total_size = get_totalsize(mc_header);
194 data_size = get_datasize(mc_header);
4bae1967 195
bd8e39f9 196 if (data_size + MC_HEADER_SIZE > total_size) {
9a3110bf 197 printk(KERN_ERR "microcode: error! "
4bae1967 198 "Bad data size in microcode data file\n");
9a3110bf
SL
199 return -EINVAL;
200 }
1da177e4 201
9a3110bf
SL
202 if (mc_header->ldrver != 1 || mc_header->hdrver != 1) {
203 printk(KERN_ERR "microcode: error! "
4bae1967 204 "Unknown microcode update format\n");
9a3110bf
SL
205 return -EINVAL;
206 }
207 ext_table_size = total_size - (MC_HEADER_SIZE + data_size);
208 if (ext_table_size) {
209 if ((ext_table_size < EXT_HEADER_SIZE)
210 || ((ext_table_size - EXT_HEADER_SIZE) % EXT_SIGNATURE_SIZE)) {
211 printk(KERN_ERR "microcode: error! "
212 "Small exttable size in microcode data file\n");
213 return -EINVAL;
1da177e4 214 }
9a3110bf
SL
215 ext_header = mc + MC_HEADER_SIZE + data_size;
216 if (ext_table_size != exttable_size(ext_header)) {
217 printk(KERN_ERR "microcode: error! "
218 "Bad exttable size in microcode data file\n");
219 return -EFAULT;
1da177e4 220 }
9a3110bf
SL
221 ext_sigcount = ext_header->count;
222 }
1da177e4 223
9a3110bf
SL
224 /* check extended table checksum */
225 if (ext_table_size) {
226 int ext_table_sum = 0;
9a4b9efa 227 int *ext_tablep = (int *)ext_header;
9a3110bf
SL
228
229 i = ext_table_size / DWSIZE;
230 while (i--)
231 ext_table_sum += ext_tablep[i];
232 if (ext_table_sum) {
233 printk(KERN_WARNING "microcode: aborting, "
234 "bad extended signature table checksum\n");
235 return -EINVAL;
1da177e4 236 }
9a3110bf 237 }
1da177e4 238
9a3110bf
SL
239 /* calculate the checksum */
240 orig_sum = 0;
241 i = (MC_HEADER_SIZE + data_size) / DWSIZE;
242 while (i--)
243 orig_sum += ((int *)mc)[i];
244 if (orig_sum) {
245 printk(KERN_ERR "microcode: aborting, bad checksum\n");
246 return -EINVAL;
247 }
248 if (!ext_table_size)
249 return 0;
250 /* check extended signature checksum */
251 for (i = 0; i < ext_sigcount; i++) {
ade1af77
JE
252 ext_sig = (void *)ext_header + EXT_HEADER_SIZE +
253 EXT_SIGNATURE_SIZE * i;
9a3110bf
SL
254 sum = orig_sum
255 - (mc_header->sig + mc_header->pf + mc_header->cksum)
256 + (ext_sig->sig + ext_sig->pf + ext_sig->cksum);
257 if (sum) {
258 printk(KERN_ERR "microcode: aborting, bad checksum\n");
259 return -EINVAL;
1da177e4 260 }
9a3110bf
SL
261 }
262 return 0;
263}
5cf6c541 264
9a3110bf
SL
265/*
266 * return 0 - no update found
267 * return 1 - found update
9a3110bf 268 */
a0a29b62
DA
269static int
270get_matching_microcode(struct cpu_signature *cpu_sig, void *mc, int rev)
9a3110bf 271{
d4ee3668 272 struct microcode_header_intel *mc_header = mc;
9a3110bf
SL
273 struct extended_sigtable *ext_header;
274 unsigned long total_size = get_totalsize(mc_header);
275 int ext_sigcount, i;
276 struct extended_signature *ext_sig;
9a3110bf 277
a0a29b62
DA
278 if (!update_match_revision(mc_header, rev))
279 return 0;
280
281 if (update_match_cpu(cpu_sig, mc_header->sig, mc_header->pf))
282 return 1;
9a3110bf 283
a0a29b62 284 /* Look for ext. headers: */
9a3110bf
SL
285 if (total_size <= get_datasize(mc_header) + MC_HEADER_SIZE)
286 return 0;
287
ade1af77 288 ext_header = mc + get_datasize(mc_header) + MC_HEADER_SIZE;
9a3110bf 289 ext_sigcount = ext_header->count;
ade1af77 290 ext_sig = (void *)ext_header + EXT_HEADER_SIZE;
a0a29b62 291
9a3110bf 292 for (i = 0; i < ext_sigcount; i++) {
a0a29b62
DA
293 if (update_match_cpu(cpu_sig, ext_sig->sig, ext_sig->pf))
294 return 1;
9a3110bf
SL
295 ext_sig++;
296 }
297 return 0;
1da177e4
LT
298}
299
871b72dd 300static int apply_microcode(int cpu)
1da177e4 301{
4bae1967
IM
302 struct microcode_intel *mc_intel;
303 struct ucode_cpu_info *uci;
1da177e4 304 unsigned int val[2];
4bae1967
IM
305 int cpu_num;
306
307 cpu_num = raw_smp_processor_id();
308 uci = ucode_cpu_info + cpu;
309 mc_intel = uci->mc;
1da177e4 310
9a3110bf
SL
311 /* We should bind the task to the CPU */
312 BUG_ON(cpu_num != cpu);
313
18dbc916 314 if (mc_intel == NULL)
871b72dd 315 return 0;
1da177e4
LT
316
317 /* write microcode via MSR 0x79 */
318 wrmsr(MSR_IA32_UCODE_WRITE,
18dbc916
DA
319 (unsigned long) mc_intel->bits,
320 (unsigned long) mc_intel->bits >> 16 >> 16);
1da177e4
LT
321 wrmsr(MSR_IA32_UCODE_REV, 0, 0);
322
245067d1 323 /* see notes above for revision 1.07. Apparent chip bug */
487472bc 324 sync_core();
245067d1 325
1da177e4
LT
326 /* get the current revision from MSR 0x8B */
327 rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]);
328
18dbc916 329 if (val[1] != mc_intel->hdr.rev) {
871b72dd
DA
330 printk(KERN_ERR "microcode: CPU%d update "
331 "to revision 0x%x failed\n",
332 cpu_num, mc_intel->hdr.rev);
333 return -1;
9a3110bf 334 }
871b72dd
DA
335 printk(KERN_INFO "microcode: CPU%d updated to revision "
336 "0x%x, date = %04x-%02x-%02x \n",
337 cpu_num, val[1],
18dbc916
DA
338 mc_intel->hdr.date & 0xffff,
339 mc_intel->hdr.date >> 24,
340 (mc_intel->hdr.date >> 16) & 0xff);
4bae1967 341
d45de409 342 uci->cpu_sig.rev = val[1];
871b72dd
DA
343
344 return 0;
1da177e4
LT
345}
346
871b72dd
DA
347static enum ucode_state generic_load_microcode(int cpu, void *data, size_t size,
348 int (*get_ucode_data)(void *, const void *, size_t))
9a3110bf 349{
a0a29b62
DA
350 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
351 u8 *ucode_ptr = data, *new_mc = NULL, *mc;
352 int new_rev = uci->cpu_sig.rev;
353 unsigned int leftover = size;
871b72dd 354 enum ucode_state state = UCODE_OK;
9a3110bf 355
a0a29b62
DA
356 while (leftover) {
357 struct microcode_header_intel mc_header;
358 unsigned int mc_size;
9a3110bf 359
a0a29b62
DA
360 if (get_ucode_data(&mc_header, ucode_ptr, sizeof(mc_header)))
361 break;
a30a6a2c 362
a0a29b62
DA
363 mc_size = get_totalsize(&mc_header);
364 if (!mc_size || mc_size > leftover) {
365 printk(KERN_ERR "microcode: error!"
366 "Bad data in microcode data file\n");
367 break;
368 }
a30a6a2c 369
a0a29b62
DA
370 mc = vmalloc(mc_size);
371 if (!mc)
372 break;
373
374 if (get_ucode_data(mc, ucode_ptr, mc_size) ||
375 microcode_sanity_check(mc) < 0) {
376 vfree(mc);
377 break;
378 }
379
380 if (get_matching_microcode(&uci->cpu_sig, mc, new_rev)) {
a1c75cc5
IM
381 if (new_mc)
382 vfree(new_mc);
a0a29b62
DA
383 new_rev = mc_header.rev;
384 new_mc = mc;
385 } else
386 vfree(mc);
387
388 ucode_ptr += mc_size;
389 leftover -= mc_size;
a30a6a2c
SL
390 }
391
871b72dd
DA
392 if (leftover) {
393 if (new_mc)
394 vfree(new_mc);
395 state = UCODE_ERROR;
4bae1967 396 goto out;
871b72dd 397 }
4bae1967 398
871b72dd
DA
399 if (!new_mc) {
400 state = UCODE_NFOUND;
4bae1967 401 goto out;
a30a6a2c 402 }
a0a29b62 403
4bae1967
IM
404 if (uci->mc)
405 vfree(uci->mc);
406 uci->mc = (struct microcode_intel *)new_mc;
407
408 pr_debug("microcode: CPU%d found a matching microcode update with"
409 " version 0x%x (current=0x%x)\n",
410 cpu, new_rev, uci->cpu_sig.rev);
871b72dd
DA
411out:
412 return state;
a30a6a2c
SL
413}
414
a0a29b62
DA
415static int get_ucode_fw(void *to, const void *from, size_t n)
416{
417 memcpy(to, from, n);
418 return 0;
419}
a30a6a2c 420
871b72dd 421static enum ucode_state request_microcode_fw(int cpu, struct device *device)
a30a6a2c
SL
422{
423 char name[30];
92cb7612 424 struct cpuinfo_x86 *c = &cpu_data(cpu);
a30a6a2c 425 const struct firmware *firmware;
871b72dd 426 enum ucode_state ret;
a30a6a2c 427
3e135d88 428 sprintf(name, "intel-ucode/%02x-%02x-%02x",
a30a6a2c 429 c->x86, c->x86_model, c->x86_mask);
871b72dd
DA
430
431 if (request_firmware(&firmware, name, device)) {
bc4e0f9a 432 pr_debug("microcode: data file %s load failed\n", name);
871b72dd 433 return UCODE_NFOUND;
a30a6a2c 434 }
a0a29b62 435
dd3feda7
JSR
436 ret = generic_load_microcode(cpu, (void *)firmware->data,
437 firmware->size, &get_ucode_fw);
a0a29b62 438
a30a6a2c
SL
439 release_firmware(firmware);
440
a0a29b62
DA
441 return ret;
442}
443
444static int get_ucode_user(void *to, const void *from, size_t n)
445{
446 return copy_from_user(to, from, n);
447}
448
871b72dd
DA
449static enum ucode_state
450request_microcode_user(int cpu, const void __user *buf, size_t size)
a0a29b62 451{
dd3feda7 452 return generic_load_microcode(cpu, (void *)buf, size, &get_ucode_user);
a30a6a2c
SL
453}
454
8d86f390 455static void microcode_fini_cpu(int cpu)
a30a6a2c
SL
456{
457 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
458
18dbc916
DA
459 vfree(uci->mc);
460 uci->mc = NULL;
a30a6a2c 461}
8d86f390 462
4db646b1 463static struct microcode_ops microcode_intel_ops = {
a0a29b62
DA
464 .request_microcode_user = request_microcode_user,
465 .request_microcode_fw = request_microcode_fw,
8d86f390
PO
466 .collect_cpu_info = collect_cpu_info,
467 .apply_microcode = apply_microcode,
468 .microcode_fini_cpu = microcode_fini_cpu,
469};
470
18dbc916 471struct microcode_ops * __init init_intel_microcode(void)
8d86f390 472{
18dbc916 473 return &microcode_intel_ops;
8d86f390
PO
474}
475
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