Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Intel Multiprocessor Specification 1.1 and 1.4 | |
3 | * compliant MP-table parsing routines. | |
4 | * | |
5 | * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> | |
6 | * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
7 | * | |
8 | * Fixes | |
9 | * Erich Boleyn : MP v1.4 and additional changes. | |
10 | * Alan Cox : Added EBDA scanning | |
11 | * Ingo Molnar : various cleanups and rewrites | |
12 | * Maciej W. Rozycki: Bits for default MP configurations | |
13 | * Paul Diefenbaugh: Added full ACPI support | |
14 | */ | |
15 | ||
16 | #include <linux/mm.h> | |
1da177e4 LT |
17 | #include <linux/init.h> |
18 | #include <linux/acpi.h> | |
19 | #include <linux/delay.h> | |
1da177e4 | 20 | #include <linux/bootmem.h> |
1da177e4 LT |
21 | #include <linux/kernel_stat.h> |
22 | #include <linux/mc146818rtc.h> | |
23 | #include <linux/bitops.h> | |
24 | ||
25 | #include <asm/smp.h> | |
26 | #include <asm/acpi.h> | |
27 | #include <asm/mtrr.h> | |
28 | #include <asm/mpspec.h> | |
29 | #include <asm/io_apic.h> | |
ce3fe6b2 | 30 | #include <asm/bios_ebda.h> |
1da177e4 LT |
31 | |
32 | #include <mach_apic.h> | |
874c4fe3 | 33 | #include <mach_apicdef.h> |
1da177e4 | 34 | #include <mach_mpparse.h> |
1da177e4 LT |
35 | |
36 | /* Have we found an MP table */ | |
37 | int smp_found_config; | |
1da177e4 LT |
38 | |
39 | /* | |
40 | * Various Linux-internal data structures created from the | |
41 | * MP-table. | |
42 | */ | |
c0a282c2 | 43 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
4ef81297 | 44 | int mp_bus_id_to_type[MAX_MP_BUSSES]; |
c0a282c2 | 45 | #endif |
a6333c3c | 46 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); |
4ef81297 | 47 | int mp_bus_id_to_pci_bus[MAX_MP_BUSSES] = {[0 ... MAX_MP_BUSSES - 1] = -1 }; |
1da177e4 LT |
48 | static int mp_current_pci_id; |
49 | ||
1da177e4 | 50 | int pic_mode; |
1da177e4 | 51 | |
1da177e4 LT |
52 | /* |
53 | * Intel MP BIOS table parsing routines: | |
54 | */ | |
55 | ||
1da177e4 LT |
56 | /* |
57 | * Checksum an MP configuration block. | |
58 | */ | |
59 | ||
60 | static int __init mpf_checksum(unsigned char *mp, int len) | |
61 | { | |
62 | int sum = 0; | |
63 | ||
64 | while (len--) | |
65 | sum += *mp++; | |
66 | ||
67 | return sum & 0xFF; | |
68 | } | |
69 | ||
86420506 | 70 | #ifdef CONFIG_X86_NUMAQ |
1da177e4 LT |
71 | /* |
72 | * Have to match translation table entries to main table entries by counter | |
73 | * hence the mpc_record variable .... can't see a less disgusting way of | |
74 | * doing this .... | |
75 | */ | |
76 | ||
4ef81297 AS |
77 | static int mpc_record; |
78 | static struct mpc_config_translation *translation_table[MAX_MPC_ENTRY] | |
79 | __cpuinitdata; | |
86420506 | 80 | #endif |
1da177e4 | 81 | |
c853c676 AS |
82 | static void __cpuinit MP_processor_info(struct mpc_config_processor *m) |
83 | { | |
84 | int apicid; | |
746f2244 | 85 | char *bootup_cpu = ""; |
c853c676 | 86 | |
7b1292e2 GC |
87 | if (!(m->mpc_cpuflag & CPU_ENABLED)) { |
88 | disabled_cpus++; | |
1da177e4 | 89 | return; |
7b1292e2 | 90 | } |
4655c7de | 91 | #ifdef CONFIG_X86_NUMAQ |
1da177e4 | 92 | apicid = mpc_apic_id(m, translation_table[mpc_record]); |
4655c7de | 93 | #else |
4655c7de AS |
94 | apicid = m->mpc_apicid; |
95 | #endif | |
1da177e4 | 96 | if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) { |
746f2244 | 97 | bootup_cpu = " (Bootup-CPU)"; |
1da177e4 | 98 | boot_cpu_physical_apicid = m->mpc_apicid; |
1da177e4 LT |
99 | } |
100 | ||
746f2244 | 101 | printk(KERN_INFO "Processor #%d%s\n", m->mpc_apicid, bootup_cpu); |
c853c676 | 102 | generic_processor_info(apicid, m->mpc_apicver); |
1da177e4 LT |
103 | } |
104 | ||
4ef81297 | 105 | static void __init MP_bus_info(struct mpc_config_bus *m) |
1da177e4 LT |
106 | { |
107 | char str[7]; | |
108 | ||
109 | memcpy(str, m->mpc_bustype, 6); | |
110 | str[6] = 0; | |
111 | ||
0ec153af | 112 | #ifdef CONFIG_X86_NUMAQ |
1da177e4 | 113 | mpc_oem_bus_info(m, str, translation_table[mpc_record]); |
0ec153af AS |
114 | #else |
115 | Dprintk("Bus #%d is %s\n", m->mpc_busid, str); | |
116 | #endif | |
1da177e4 | 117 | |
5e4edbb7 | 118 | #if MAX_MP_BUSSES < 256 |
c0ec31ad RD |
119 | if (m->mpc_busid >= MAX_MP_BUSSES) { |
120 | printk(KERN_WARNING "MP table busid value (%d) for bustype %s " | |
4ef81297 AS |
121 | " is too large, max. supported is %d\n", |
122 | m->mpc_busid, str, MAX_MP_BUSSES - 1); | |
c0ec31ad RD |
123 | return; |
124 | } | |
5e4edbb7 | 125 | #endif |
c0ec31ad | 126 | |
f8924e77 AS |
127 | if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA) - 1) == 0) { |
128 | set_bit(m->mpc_busid, mp_bus_not_pci); | |
129 | #if defined(CONFIG_EISA) || defined (CONFIG_MCA) | |
130 | mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA; | |
131 | #endif | |
132 | } else if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI) - 1) == 0) { | |
d285e338 | 133 | #ifdef CONFIG_X86_NUMAQ |
1da177e4 | 134 | mpc_oem_pci_bus(m, translation_table[mpc_record]); |
d285e338 | 135 | #endif |
a6333c3c | 136 | clear_bit(m->mpc_busid, mp_bus_not_pci); |
1da177e4 LT |
137 | mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id; |
138 | mp_current_pci_id++; | |
c0a282c2 AS |
139 | #if defined(CONFIG_EISA) || defined (CONFIG_MCA) |
140 | mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI; | |
4ef81297 | 141 | } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA) - 1) == 0) { |
9e0a2de2 | 142 | mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA; |
4ef81297 | 143 | } else if (strncmp(str, BUSTYPE_MCA, sizeof(BUSTYPE_MCA) - 1) == 0) { |
1da177e4 | 144 | mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA; |
c0a282c2 | 145 | #endif |
f8924e77 AS |
146 | } else |
147 | printk(KERN_WARNING "Unknown bustype %s - ignoring\n", str); | |
1da177e4 LT |
148 | } |
149 | ||
61048c63 AS |
150 | #ifdef CONFIG_X86_IO_APIC |
151 | ||
857033a6 AS |
152 | static int bad_ioapic(unsigned long address) |
153 | { | |
154 | if (nr_ioapics >= MAX_IO_APICS) { | |
155 | printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded " | |
156 | "(found %d)\n", MAX_IO_APICS, nr_ioapics); | |
157 | panic("Recompile kernel with bigger MAX_IO_APICS!\n"); | |
158 | } | |
159 | if (!address) { | |
160 | printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address" | |
161 | " found in table, skipping!\n"); | |
162 | return 1; | |
163 | } | |
164 | return 0; | |
165 | } | |
166 | ||
4ef81297 | 167 | static void __init MP_ioapic_info(struct mpc_config_ioapic *m) |
1da177e4 LT |
168 | { |
169 | if (!(m->mpc_flags & MPC_APIC_USABLE)) | |
170 | return; | |
171 | ||
64883ab0 | 172 | printk(KERN_INFO "I/O APIC #%d Version %d at 0x%X.\n", |
4ef81297 | 173 | m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr); |
857033a6 AS |
174 | |
175 | if (bad_ioapic(m->mpc_apicaddr)) | |
1da177e4 | 176 | return; |
857033a6 | 177 | |
1da177e4 LT |
178 | mp_ioapics[nr_ioapics] = *m; |
179 | nr_ioapics++; | |
180 | } | |
181 | ||
4ef81297 | 182 | static void __init MP_intsrc_info(struct mpc_config_intsrc *m) |
1da177e4 | 183 | { |
4ef81297 | 184 | mp_irqs[mp_irq_entries] = *m; |
1da177e4 LT |
185 | Dprintk("Int: type %d, pol %d, trig %d, bus %d," |
186 | " IRQ %02x, APIC ID %x, APIC INT %02x\n", | |
4ef81297 AS |
187 | m->mpc_irqtype, m->mpc_irqflag & 3, |
188 | (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus, | |
189 | m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq); | |
1da177e4 LT |
190 | if (++mp_irq_entries == MAX_IRQ_SOURCES) |
191 | panic("Max # of irq sources exceeded!!\n"); | |
192 | } | |
193 | ||
61048c63 AS |
194 | #endif |
195 | ||
4ef81297 | 196 | static void __init MP_lintsrc_info(struct mpc_config_lintsrc *m) |
1da177e4 LT |
197 | { |
198 | Dprintk("Lint: type %d, pol %d, trig %d, bus %d," | |
199 | " IRQ %02x, APIC ID %x, APIC LINT %02x\n", | |
4ef81297 AS |
200 | m->mpc_irqtype, m->mpc_irqflag & 3, |
201 | (m->mpc_irqflag >> 2) & 3, m->mpc_srcbusid, | |
202 | m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint); | |
1da177e4 LT |
203 | } |
204 | ||
205 | #ifdef CONFIG_X86_NUMAQ | |
4ef81297 | 206 | static void __init MP_translation_info(struct mpc_config_translation *m) |
1da177e4 | 207 | { |
4ef81297 AS |
208 | printk(KERN_INFO |
209 | "Translation: record %d, type %d, quad %d, global %d, local %d\n", | |
210 | mpc_record, m->trans_type, m->trans_quad, m->trans_global, | |
211 | m->trans_local); | |
1da177e4 | 212 | |
4ef81297 | 213 | if (mpc_record >= MAX_MPC_ENTRY) |
1da177e4 LT |
214 | printk(KERN_ERR "MAX_MPC_ENTRY exceeded!\n"); |
215 | else | |
4ef81297 | 216 | translation_table[mpc_record] = m; /* stash this for later */ |
1da177e4 LT |
217 | if (m->trans_quad < MAX_NUMNODES && !node_online(m->trans_quad)) |
218 | node_set_online(m->trans_quad); | |
219 | } | |
220 | ||
221 | /* | |
222 | * Read/parse the MPC oem tables | |
223 | */ | |
224 | ||
4ef81297 AS |
225 | static void __init smp_read_mpc_oem(struct mp_config_oemtable *oemtable, |
226 | unsigned short oemsize) | |
1da177e4 | 227 | { |
4ef81297 AS |
228 | int count = sizeof(*oemtable); /* the header size */ |
229 | unsigned char *oemptr = ((unsigned char *)oemtable) + count; | |
230 | ||
1da177e4 | 231 | mpc_record = 0; |
4ef81297 AS |
232 | printk(KERN_INFO "Found an OEM MPC table at %8p - parsing it ... \n", |
233 | oemtable); | |
234 | if (memcmp(oemtable->oem_signature, MPC_OEM_SIGNATURE, 4)) { | |
235 | printk(KERN_WARNING | |
236 | "SMP mpc oemtable: bad signature [%c%c%c%c]!\n", | |
237 | oemtable->oem_signature[0], oemtable->oem_signature[1], | |
238 | oemtable->oem_signature[2], oemtable->oem_signature[3]); | |
1da177e4 LT |
239 | return; |
240 | } | |
4ef81297 | 241 | if (mpf_checksum((unsigned char *)oemtable, oemtable->oem_length)) { |
1da177e4 LT |
242 | printk(KERN_WARNING "SMP oem mptable: checksum error!\n"); |
243 | return; | |
244 | } | |
245 | while (count < oemtable->oem_length) { | |
246 | switch (*oemptr) { | |
4ef81297 | 247 | case MP_TRANSLATION: |
1da177e4 | 248 | { |
4ef81297 AS |
249 | struct mpc_config_translation *m = |
250 | (struct mpc_config_translation *)oemptr; | |
1da177e4 LT |
251 | MP_translation_info(m); |
252 | oemptr += sizeof(*m); | |
253 | count += sizeof(*m); | |
254 | ++mpc_record; | |
255 | break; | |
256 | } | |
4ef81297 | 257 | default: |
1da177e4 | 258 | { |
4ef81297 AS |
259 | printk(KERN_WARNING |
260 | "Unrecognised OEM table entry type! - %d\n", | |
261 | (int)*oemptr); | |
1da177e4 LT |
262 | return; |
263 | } | |
264 | } | |
4ef81297 | 265 | } |
1da177e4 LT |
266 | } |
267 | ||
268 | static inline void mps_oem_check(struct mp_config_table *mpc, char *oem, | |
4ef81297 | 269 | char *productid) |
1da177e4 LT |
270 | { |
271 | if (strncmp(oem, "IBM NUMA", 8)) | |
272 | printk("Warning! May not be a NUMA-Q system!\n"); | |
273 | if (mpc->mpc_oemptr) | |
4ef81297 AS |
274 | smp_read_mpc_oem((struct mp_config_oemtable *)mpc->mpc_oemptr, |
275 | mpc->mpc_oemsize); | |
1da177e4 | 276 | } |
4ef81297 | 277 | #endif /* CONFIG_X86_NUMAQ */ |
1da177e4 LT |
278 | |
279 | /* | |
280 | * Read/parse the MPC | |
281 | */ | |
282 | ||
888032cd | 283 | static int __init smp_read_mpc(struct mp_config_table *mpc, unsigned early) |
1da177e4 LT |
284 | { |
285 | char str[16]; | |
286 | char oem[10]; | |
4ef81297 AS |
287 | int count = sizeof(*mpc); |
288 | unsigned char *mpt = ((unsigned char *)mpc) + count; | |
1da177e4 | 289 | |
4ef81297 | 290 | if (memcmp(mpc->mpc_signature, MPC_SIGNATURE, 4)) { |
1da177e4 | 291 | printk(KERN_ERR "SMP mptable: bad signature [0x%x]!\n", |
4ef81297 | 292 | *(u32 *) mpc->mpc_signature); |
1da177e4 LT |
293 | return 0; |
294 | } | |
4ef81297 | 295 | if (mpf_checksum((unsigned char *)mpc, mpc->mpc_length)) { |
1da177e4 LT |
296 | printk(KERN_ERR "SMP mptable: checksum error!\n"); |
297 | return 0; | |
298 | } | |
4ef81297 | 299 | if (mpc->mpc_spec != 0x01 && mpc->mpc_spec != 0x04) { |
1da177e4 | 300 | printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n", |
4ef81297 | 301 | mpc->mpc_spec); |
1da177e4 LT |
302 | return 0; |
303 | } | |
304 | if (!mpc->mpc_lapic) { | |
305 | printk(KERN_ERR "SMP mptable: null local APIC address!\n"); | |
306 | return 0; | |
307 | } | |
4ef81297 AS |
308 | memcpy(oem, mpc->mpc_oem, 8); |
309 | oem[8] = 0; | |
310 | printk(KERN_INFO "OEM ID: %s ", oem); | |
1da177e4 | 311 | |
4ef81297 AS |
312 | memcpy(str, mpc->mpc_productid, 12); |
313 | str[12] = 0; | |
314 | printk("Product ID: %s ", str); | |
1da177e4 LT |
315 | |
316 | mps_oem_check(mpc, oem, str); | |
317 | ||
64883ab0 | 318 | printk("APIC at: 0x%X\n", mpc->mpc_lapic); |
1da177e4 | 319 | |
64883ab0 | 320 | /* |
1da177e4 LT |
321 | * Save the local APIC address (it might be non-default) -- but only |
322 | * if we're not using ACPI. | |
323 | */ | |
324 | if (!acpi_lapic) | |
325 | mp_lapic_addr = mpc->mpc_lapic; | |
326 | ||
888032cd AS |
327 | if (early) |
328 | return 1; | |
329 | ||
1da177e4 | 330 | /* |
4ef81297 | 331 | * Now process the configuration blocks. |
1da177e4 | 332 | */ |
86420506 | 333 | #ifdef CONFIG_X86_NUMAQ |
1da177e4 | 334 | mpc_record = 0; |
86420506 | 335 | #endif |
1da177e4 | 336 | while (count < mpc->mpc_length) { |
4ef81297 AS |
337 | switch (*mpt) { |
338 | case MP_PROCESSOR: | |
1da177e4 | 339 | { |
4ef81297 AS |
340 | struct mpc_config_processor *m = |
341 | (struct mpc_config_processor *)mpt; | |
1da177e4 LT |
342 | /* ACPI may have already provided this data */ |
343 | if (!acpi_lapic) | |
344 | MP_processor_info(m); | |
345 | mpt += sizeof(*m); | |
346 | count += sizeof(*m); | |
347 | break; | |
348 | } | |
4ef81297 | 349 | case MP_BUS: |
1da177e4 | 350 | { |
4ef81297 AS |
351 | struct mpc_config_bus *m = |
352 | (struct mpc_config_bus *)mpt; | |
1da177e4 LT |
353 | MP_bus_info(m); |
354 | mpt += sizeof(*m); | |
355 | count += sizeof(*m); | |
356 | break; | |
357 | } | |
4ef81297 | 358 | case MP_IOAPIC: |
1da177e4 | 359 | { |
61048c63 | 360 | #ifdef CONFIG_X86_IO_APIC |
4ef81297 AS |
361 | struct mpc_config_ioapic *m = |
362 | (struct mpc_config_ioapic *)mpt; | |
1da177e4 | 363 | MP_ioapic_info(m); |
61048c63 | 364 | #endif |
4ef81297 AS |
365 | mpt += sizeof(struct mpc_config_ioapic); |
366 | count += sizeof(struct mpc_config_ioapic); | |
1da177e4 LT |
367 | break; |
368 | } | |
4ef81297 | 369 | case MP_INTSRC: |
1da177e4 | 370 | { |
61048c63 | 371 | #ifdef CONFIG_X86_IO_APIC |
4ef81297 AS |
372 | struct mpc_config_intsrc *m = |
373 | (struct mpc_config_intsrc *)mpt; | |
1da177e4 LT |
374 | |
375 | MP_intsrc_info(m); | |
61048c63 | 376 | #endif |
4ef81297 AS |
377 | mpt += sizeof(struct mpc_config_intsrc); |
378 | count += sizeof(struct mpc_config_intsrc); | |
1da177e4 LT |
379 | break; |
380 | } | |
4ef81297 | 381 | case MP_LINTSRC: |
1da177e4 | 382 | { |
4ef81297 AS |
383 | struct mpc_config_lintsrc *m = |
384 | (struct mpc_config_lintsrc *)mpt; | |
1da177e4 | 385 | MP_lintsrc_info(m); |
4ef81297 AS |
386 | mpt += sizeof(*m); |
387 | count += sizeof(*m); | |
1da177e4 LT |
388 | break; |
389 | } | |
4ef81297 | 390 | default: |
1da177e4 LT |
391 | { |
392 | count = mpc->mpc_length; | |
393 | break; | |
394 | } | |
395 | } | |
86420506 | 396 | #ifdef CONFIG_X86_NUMAQ |
1da177e4 | 397 | ++mpc_record; |
86420506 | 398 | #endif |
1da177e4 | 399 | } |
3c43f039 | 400 | setup_apic_routing(); |
1da177e4 LT |
401 | if (!num_processors) |
402 | printk(KERN_ERR "SMP mptable: no processors registered!\n"); | |
403 | return num_processors; | |
404 | } | |
405 | ||
61048c63 AS |
406 | #ifdef CONFIG_X86_IO_APIC |
407 | ||
1da177e4 LT |
408 | static int __init ELCR_trigger(unsigned int irq) |
409 | { | |
410 | unsigned int port; | |
411 | ||
412 | port = 0x4d0 + (irq >> 3); | |
413 | return (inb(port) >> (irq & 7)) & 1; | |
414 | } | |
415 | ||
416 | static void __init construct_default_ioirq_mptable(int mpc_default_type) | |
417 | { | |
418 | struct mpc_config_intsrc intsrc; | |
419 | int i; | |
420 | int ELCR_fallback = 0; | |
421 | ||
422 | intsrc.mpc_type = MP_INTSRC; | |
4ef81297 | 423 | intsrc.mpc_irqflag = 0; /* conforming */ |
1da177e4 LT |
424 | intsrc.mpc_srcbus = 0; |
425 | intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid; | |
426 | ||
427 | intsrc.mpc_irqtype = mp_INT; | |
428 | ||
429 | /* | |
430 | * If true, we have an ISA/PCI system with no IRQ entries | |
431 | * in the MP table. To prevent the PCI interrupts from being set up | |
432 | * incorrectly, we try to use the ELCR. The sanity check to see if | |
433 | * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can | |
434 | * never be level sensitive, so we simply see if the ELCR agrees. | |
435 | * If it does, we assume it's valid. | |
436 | */ | |
437 | if (mpc_default_type == 5) { | |
4ef81297 AS |
438 | printk(KERN_INFO |
439 | "ISA/PCI bus type with no IRQ information... falling back to ELCR\n"); | |
1da177e4 | 440 | |
4ef81297 AS |
441 | if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) |
442 | || ELCR_trigger(13)) | |
443 | printk(KERN_WARNING | |
444 | "ELCR contains invalid data... not using ELCR\n"); | |
1da177e4 | 445 | else { |
4ef81297 AS |
446 | printk(KERN_INFO |
447 | "Using ELCR to identify PCI interrupts\n"); | |
1da177e4 LT |
448 | ELCR_fallback = 1; |
449 | } | |
450 | } | |
451 | ||
452 | for (i = 0; i < 16; i++) { | |
453 | switch (mpc_default_type) { | |
454 | case 2: | |
455 | if (i == 0 || i == 13) | |
456 | continue; /* IRQ0 & IRQ13 not connected */ | |
457 | /* fall through */ | |
458 | default: | |
459 | if (i == 2) | |
460 | continue; /* IRQ2 is never connected */ | |
461 | } | |
462 | ||
463 | if (ELCR_fallback) { | |
464 | /* | |
465 | * If the ELCR indicates a level-sensitive interrupt, we | |
466 | * copy that information over to the MP table in the | |
467 | * irqflag field (level sensitive, active high polarity). | |
468 | */ | |
469 | if (ELCR_trigger(i)) | |
470 | intsrc.mpc_irqflag = 13; | |
471 | else | |
472 | intsrc.mpc_irqflag = 0; | |
473 | } | |
474 | ||
475 | intsrc.mpc_srcbusirq = i; | |
4ef81297 | 476 | intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */ |
1da177e4 LT |
477 | MP_intsrc_info(&intsrc); |
478 | } | |
479 | ||
480 | intsrc.mpc_irqtype = mp_ExtINT; | |
481 | intsrc.mpc_srcbusirq = 0; | |
4ef81297 | 482 | intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */ |
1da177e4 LT |
483 | MP_intsrc_info(&intsrc); |
484 | } | |
485 | ||
61048c63 AS |
486 | #endif |
487 | ||
1da177e4 LT |
488 | static inline void __init construct_default_ISA_mptable(int mpc_default_type) |
489 | { | |
490 | struct mpc_config_processor processor; | |
491 | struct mpc_config_bus bus; | |
61048c63 | 492 | #ifdef CONFIG_X86_IO_APIC |
1da177e4 | 493 | struct mpc_config_ioapic ioapic; |
61048c63 | 494 | #endif |
1da177e4 LT |
495 | struct mpc_config_lintsrc lintsrc; |
496 | int linttypes[2] = { mp_ExtINT, mp_NMI }; | |
497 | int i; | |
498 | ||
499 | /* | |
500 | * local APIC has default address | |
501 | */ | |
502 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
503 | ||
504 | /* | |
505 | * 2 CPUs, numbered 0 & 1. | |
506 | */ | |
507 | processor.mpc_type = MP_PROCESSOR; | |
508 | /* Either an integrated APIC or a discrete 82489DX. */ | |
509 | processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01; | |
510 | processor.mpc_cpuflag = CPU_ENABLED; | |
511 | processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) | | |
4ef81297 | 512 | (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask; |
1da177e4 LT |
513 | processor.mpc_featureflag = boot_cpu_data.x86_capability[0]; |
514 | processor.mpc_reserved[0] = 0; | |
515 | processor.mpc_reserved[1] = 0; | |
516 | for (i = 0; i < 2; i++) { | |
517 | processor.mpc_apicid = i; | |
518 | MP_processor_info(&processor); | |
519 | } | |
520 | ||
521 | bus.mpc_type = MP_BUS; | |
522 | bus.mpc_busid = 0; | |
523 | switch (mpc_default_type) { | |
4ef81297 AS |
524 | default: |
525 | printk("???\n"); | |
526 | printk(KERN_ERR "Unknown standard configuration %d\n", | |
527 | mpc_default_type); | |
528 | /* fall through */ | |
529 | case 1: | |
530 | case 5: | |
531 | memcpy(bus.mpc_bustype, "ISA ", 6); | |
532 | break; | |
533 | case 2: | |
534 | case 6: | |
535 | case 3: | |
536 | memcpy(bus.mpc_bustype, "EISA ", 6); | |
537 | break; | |
538 | case 4: | |
539 | case 7: | |
540 | memcpy(bus.mpc_bustype, "MCA ", 6); | |
1da177e4 LT |
541 | } |
542 | MP_bus_info(&bus); | |
543 | if (mpc_default_type > 4) { | |
544 | bus.mpc_busid = 1; | |
545 | memcpy(bus.mpc_bustype, "PCI ", 6); | |
546 | MP_bus_info(&bus); | |
547 | } | |
548 | ||
61048c63 | 549 | #ifdef CONFIG_X86_IO_APIC |
1da177e4 LT |
550 | ioapic.mpc_type = MP_IOAPIC; |
551 | ioapic.mpc_apicid = 2; | |
552 | ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01; | |
553 | ioapic.mpc_flags = MPC_APIC_USABLE; | |
554 | ioapic.mpc_apicaddr = 0xFEC00000; | |
555 | MP_ioapic_info(&ioapic); | |
556 | ||
557 | /* | |
558 | * We set up most of the low 16 IO-APIC pins according to MPS rules. | |
559 | */ | |
560 | construct_default_ioirq_mptable(mpc_default_type); | |
61048c63 | 561 | #endif |
1da177e4 | 562 | lintsrc.mpc_type = MP_LINTSRC; |
4ef81297 | 563 | lintsrc.mpc_irqflag = 0; /* conforming */ |
1da177e4 LT |
564 | lintsrc.mpc_srcbusid = 0; |
565 | lintsrc.mpc_srcbusirq = 0; | |
566 | lintsrc.mpc_destapic = MP_APIC_ALL; | |
567 | for (i = 0; i < 2; i++) { | |
568 | lintsrc.mpc_irqtype = linttypes[i]; | |
569 | lintsrc.mpc_destapiclint = i; | |
570 | MP_lintsrc_info(&lintsrc); | |
571 | } | |
572 | } | |
573 | ||
574 | static struct intel_mp_floating *mpf_found; | |
575 | ||
576 | /* | |
577 | * Scan the memory blocks for an SMP configuration block. | |
578 | */ | |
888032cd | 579 | static void __init __get_smp_config(unsigned early) |
1da177e4 LT |
580 | { |
581 | struct intel_mp_floating *mpf = mpf_found; | |
582 | ||
888032cd AS |
583 | if (acpi_lapic && early) |
584 | return; | |
585 | ||
1da177e4 | 586 | /* |
4ef81297 | 587 | * ACPI supports both logical (e.g. Hyper-Threading) and physical |
1da177e4 LT |
588 | * processors, where MPS only supports physical. |
589 | */ | |
590 | if (acpi_lapic && acpi_ioapic) { | |
4ef81297 AS |
591 | printk(KERN_INFO |
592 | "Using ACPI (MADT) for SMP configuration information\n"); | |
1da177e4 | 593 | return; |
4ef81297 AS |
594 | } else if (acpi_lapic) |
595 | printk(KERN_INFO | |
596 | "Using ACPI for processor (LAPIC) configuration information\n"); | |
1da177e4 | 597 | |
4ef81297 AS |
598 | printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n", |
599 | mpf->mpf_specification); | |
600 | if (mpf->mpf_feature2 & (1 << 7)) { | |
1da177e4 LT |
601 | printk(KERN_INFO " IMCR and PIC compatibility mode.\n"); |
602 | pic_mode = 1; | |
603 | } else { | |
604 | printk(KERN_INFO " Virtual Wire compatibility mode.\n"); | |
605 | pic_mode = 0; | |
606 | } | |
607 | ||
608 | /* | |
609 | * Now see if we need to read further. | |
610 | */ | |
611 | if (mpf->mpf_feature1 != 0) { | |
888032cd AS |
612 | if (early) { |
613 | /* | |
614 | * local APIC has default address | |
615 | */ | |
616 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
617 | return; | |
618 | } | |
1da177e4 | 619 | |
4ef81297 AS |
620 | printk(KERN_INFO "Default MP configuration #%d\n", |
621 | mpf->mpf_feature1); | |
1da177e4 LT |
622 | construct_default_ISA_mptable(mpf->mpf_feature1); |
623 | ||
624 | } else if (mpf->mpf_physptr) { | |
625 | ||
626 | /* | |
627 | * Read the physical hardware table. Anything here will | |
628 | * override the defaults. | |
629 | */ | |
888032cd | 630 | if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr), early)) { |
1da177e4 | 631 | smp_found_config = 0; |
4ef81297 AS |
632 | printk(KERN_ERR |
633 | "BIOS bug, MP table errors detected!...\n"); | |
634 | printk(KERN_ERR | |
635 | "... disabling SMP support. (tell your hw vendor)\n"); | |
1da177e4 LT |
636 | return; |
637 | } | |
61048c63 | 638 | |
888032cd AS |
639 | if (early) |
640 | return; | |
61048c63 | 641 | #ifdef CONFIG_X86_IO_APIC |
1da177e4 LT |
642 | /* |
643 | * If there are no explicit MP IRQ entries, then we are | |
644 | * broken. We set up most of the low 16 IO-APIC pins to | |
645 | * ISA defaults and hope it will work. | |
646 | */ | |
647 | if (!mp_irq_entries) { | |
648 | struct mpc_config_bus bus; | |
649 | ||
4ef81297 AS |
650 | printk(KERN_ERR |
651 | "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n"); | |
1da177e4 LT |
652 | |
653 | bus.mpc_type = MP_BUS; | |
654 | bus.mpc_busid = 0; | |
655 | memcpy(bus.mpc_bustype, "ISA ", 6); | |
656 | MP_bus_info(&bus); | |
657 | ||
658 | construct_default_ioirq_mptable(0); | |
659 | } | |
61048c63 | 660 | #endif |
1da177e4 LT |
661 | } else |
662 | BUG(); | |
663 | ||
888032cd AS |
664 | if (!early) |
665 | printk(KERN_INFO "Processors: %d\n", num_processors); | |
1da177e4 LT |
666 | /* |
667 | * Only use the first configuration found. | |
668 | */ | |
669 | } | |
670 | ||
888032cd AS |
671 | void __init early_get_smp_config(void) |
672 | { | |
673 | __get_smp_config(1); | |
674 | } | |
675 | ||
676 | void __init get_smp_config(void) | |
677 | { | |
678 | __get_smp_config(0); | |
679 | } | |
680 | ||
681 | static int __init smp_scan_config(unsigned long base, unsigned long length, | |
682 | unsigned reserve) | |
1da177e4 LT |
683 | { |
684 | unsigned long *bp = phys_to_virt(base); | |
685 | struct intel_mp_floating *mpf; | |
686 | ||
4ef81297 | 687 | printk(KERN_INFO "Scan SMP from %p for %ld bytes.\n", bp, length); |
1da177e4 LT |
688 | if (sizeof(*mpf) != 16) |
689 | printk("Error: MPF size\n"); | |
690 | ||
691 | while (length > 0) { | |
692 | mpf = (struct intel_mp_floating *)bp; | |
693 | if ((*bp == SMP_MAGIC_IDENT) && | |
4ef81297 AS |
694 | (mpf->mpf_length == 1) && |
695 | !mpf_checksum((unsigned char *)bp, 16) && | |
696 | ((mpf->mpf_specification == 1) | |
697 | || (mpf->mpf_specification == 4))) { | |
1da177e4 LT |
698 | |
699 | smp_found_config = 1; | |
e91a3b43 | 700 | printk(KERN_INFO "found SMP MP-table at [%p] %08lx\n", |
4ef81297 | 701 | mpf, virt_to_phys(mpf)); |
72a7fe39 BW |
702 | reserve_bootmem(virt_to_phys(mpf), PAGE_SIZE, |
703 | BOOTMEM_DEFAULT); | |
1da177e4 LT |
704 | if (mpf->mpf_physptr) { |
705 | /* | |
706 | * We cannot access to MPC table to compute | |
707 | * table size yet, as only few megabytes from | |
708 | * the bottom is mapped now. | |
709 | * PC-9800's MPC table places on the very last | |
710 | * of physical memory; so that simply reserving | |
711 | * PAGE_SIZE from mpg->mpf_physptr yields BUG() | |
712 | * in reserve_bootmem. | |
713 | */ | |
714 | unsigned long size = PAGE_SIZE; | |
715 | unsigned long end = max_low_pfn * PAGE_SIZE; | |
716 | if (mpf->mpf_physptr + size > end) | |
717 | size = end - mpf->mpf_physptr; | |
72a7fe39 BW |
718 | reserve_bootmem(mpf->mpf_physptr, size, |
719 | BOOTMEM_DEFAULT); | |
1da177e4 LT |
720 | } |
721 | ||
722 | mpf_found = mpf; | |
723 | return 1; | |
724 | } | |
725 | bp += 4; | |
726 | length -= 16; | |
727 | } | |
728 | return 0; | |
729 | } | |
730 | ||
888032cd | 731 | static void __init __find_smp_config(unsigned reserve) |
1da177e4 LT |
732 | { |
733 | unsigned int address; | |
734 | ||
735 | /* | |
736 | * FIXME: Linux assumes you have 640K of base ram.. | |
737 | * this continues the error... | |
738 | * | |
739 | * 1) Scan the bottom 1K for a signature | |
740 | * 2) Scan the top 1K of base RAM | |
741 | * 3) Scan the 64K of bios | |
742 | */ | |
888032cd AS |
743 | if (smp_scan_config(0x0, 0x400, reserve) || |
744 | smp_scan_config(639 * 0x400, 0x400, reserve) || | |
745 | smp_scan_config(0xF0000, 0x10000, reserve)) | |
1da177e4 LT |
746 | return; |
747 | /* | |
748 | * If it is an SMP machine we should know now, unless the | |
749 | * configuration is in an EISA/MCA bus machine with an | |
750 | * extended bios data area. | |
751 | * | |
752 | * there is a real-mode segmented pointer pointing to the | |
753 | * 4K EBDA area at 0x40E, calculate and scan it here. | |
754 | * | |
755 | * NOTE! There are Linux loaders that will corrupt the EBDA | |
756 | * area, and as such this kind of SMP config may be less | |
757 | * trustworthy, simply because the SMP table may have been | |
758 | * stomped on during early boot. These loaders are buggy and | |
759 | * should be fixed. | |
760 | * | |
761 | * MP1.4 SPEC states to only scan first 1K of 4K EBDA. | |
762 | */ | |
763 | ||
764 | address = get_bios_ebda(); | |
765 | if (address) | |
888032cd AS |
766 | smp_scan_config(address, 0x400, reserve); |
767 | } | |
768 | ||
769 | void __init early_find_smp_config(void) | |
770 | { | |
771 | __find_smp_config(0); | |
772 | } | |
773 | ||
774 | void __init find_smp_config(void) | |
775 | { | |
776 | __find_smp_config(1); | |
1da177e4 LT |
777 | } |
778 | ||
779 | /* -------------------------------------------------------------------------- | |
780 | ACPI-based MP Configuration | |
781 | -------------------------------------------------------------------------- */ | |
782 | ||
888ba6c6 | 783 | #ifdef CONFIG_ACPI |
1da177e4 | 784 | |
8466361a | 785 | #ifdef CONFIG_X86_IO_APIC |
1da177e4 LT |
786 | |
787 | #define MP_ISA_BUS 0 | |
788 | #define MP_MAX_IOAPIC_PIN 127 | |
789 | ||
9e5c5f1d | 790 | extern struct mp_ioapic_routing mp_ioapic_routing[MAX_IO_APICS]; |
1da177e4 | 791 | |
4ef81297 | 792 | static int mp_find_ioapic(int gsi) |
1da177e4 | 793 | { |
19f03ffe | 794 | int i = 0; |
1da177e4 LT |
795 | |
796 | /* Find the IOAPIC that manages this GSI. */ | |
797 | for (i = 0; i < nr_ioapics; i++) { | |
798 | if ((gsi >= mp_ioapic_routing[i].gsi_base) | |
4ef81297 | 799 | && (gsi <= mp_ioapic_routing[i].gsi_end)) |
1da177e4 LT |
800 | return i; |
801 | } | |
802 | ||
803 | printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); | |
804 | ||
805 | return -1; | |
806 | } | |
1da177e4 | 807 | |
e3e3ffa2 AS |
808 | static u8 uniq_ioapic_id(u8 id) |
809 | { | |
810 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && | |
811 | !APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
812 | return io_apic_get_unique_id(nr_ioapics, id); | |
813 | else | |
814 | return id; | |
815 | } | |
816 | ||
a65d1d64 | 817 | void __init mp_register_ioapic(int id, u32 address, u32 gsi_base) |
1da177e4 | 818 | { |
19f03ffe | 819 | int idx = 0; |
1da177e4 | 820 | |
857033a6 | 821 | if (bad_ioapic(address)) |
1da177e4 | 822 | return; |
1da177e4 | 823 | |
e3e3ffa2 | 824 | idx = nr_ioapics; |
1da177e4 LT |
825 | |
826 | mp_ioapics[idx].mpc_type = MP_IOAPIC; | |
827 | mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE; | |
828 | mp_ioapics[idx].mpc_apicaddr = address; | |
829 | ||
830 | set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); | |
e3e3ffa2 | 831 | mp_ioapics[idx].mpc_apicid = uniq_ioapic_id(id); |
1da177e4 | 832 | mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx); |
4ef81297 AS |
833 | |
834 | /* | |
1da177e4 LT |
835 | * Build basic GSI lookup table to facilitate gsi->io_apic lookups |
836 | * and to prevent reprogramming of IOAPIC pins (PCI GSIs). | |
837 | */ | |
838 | mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid; | |
839 | mp_ioapic_routing[idx].gsi_base = gsi_base; | |
64883ab0 | 840 | mp_ioapic_routing[idx].gsi_end = gsi_base + |
4ef81297 | 841 | io_apic_get_redir_entries(idx); |
1da177e4 | 842 | |
64883ab0 TG |
843 | printk("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, " |
844 | "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid, | |
e3e3ffa2 AS |
845 | mp_ioapics[idx].mpc_apicver, |
846 | mp_ioapics[idx].mpc_apicaddr, | |
4ef81297 | 847 | mp_ioapic_routing[idx].gsi_base, mp_ioapic_routing[idx].gsi_end); |
e3e3ffa2 AS |
848 | |
849 | nr_ioapics++; | |
1da177e4 LT |
850 | } |
851 | ||
4ef81297 | 852 | void __init mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi) |
1da177e4 LT |
853 | { |
854 | struct mpc_config_intsrc intsrc; | |
4ef81297 AS |
855 | int ioapic = -1; |
856 | int pin = -1; | |
1da177e4 | 857 | |
4ef81297 | 858 | /* |
1da177e4 LT |
859 | * Convert 'gsi' to 'ioapic.pin'. |
860 | */ | |
861 | ioapic = mp_find_ioapic(gsi); | |
862 | if (ioapic < 0) | |
863 | return; | |
864 | pin = gsi - mp_ioapic_routing[ioapic].gsi_base; | |
865 | ||
866 | /* | |
867 | * TBD: This check is for faulty timer entries, where the override | |
4ef81297 | 868 | * erroneously sets the trigger to level, resulting in a HUGE |
1da177e4 LT |
869 | * increase of timer interrupts! |
870 | */ | |
871 | if ((bus_irq == 0) && (trigger == 3)) | |
872 | trigger = 1; | |
873 | ||
874 | intsrc.mpc_type = MP_INTSRC; | |
875 | intsrc.mpc_irqtype = mp_INT; | |
876 | intsrc.mpc_irqflag = (trigger << 2) | polarity; | |
877 | intsrc.mpc_srcbus = MP_ISA_BUS; | |
4ef81297 AS |
878 | intsrc.mpc_srcbusirq = bus_irq; /* IRQ */ |
879 | intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */ | |
880 | intsrc.mpc_dstirq = pin; /* INTIN# */ | |
1da177e4 LT |
881 | |
882 | Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n", | |
4ef81297 AS |
883 | intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3, |
884 | (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus, | |
1da177e4 LT |
885 | intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq); |
886 | ||
887 | mp_irqs[mp_irq_entries] = intsrc; | |
888 | if (++mp_irq_entries == MAX_IRQ_SOURCES) | |
889 | panic("Max # of irq sources exceeded!\n"); | |
1da177e4 LT |
890 | } |
891 | ||
2df29726 AS |
892 | int es7000_plat; |
893 | ||
4ef81297 | 894 | void __init mp_config_acpi_legacy_irqs(void) |
1da177e4 LT |
895 | { |
896 | struct mpc_config_intsrc intsrc; | |
19f03ffe AK |
897 | int i = 0; |
898 | int ioapic = -1; | |
1da177e4 | 899 | |
c0a282c2 | 900 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
4ef81297 | 901 | /* |
1da177e4 LT |
902 | * Fabricate the legacy ISA bus (bus #31). |
903 | */ | |
904 | mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA; | |
c0a282c2 | 905 | #endif |
a6333c3c | 906 | set_bit(MP_ISA_BUS, mp_bus_not_pci); |
1da177e4 LT |
907 | Dprintk("Bus #%d is ISA\n", MP_ISA_BUS); |
908 | ||
909 | /* | |
910 | * Older generations of ES7000 have no legacy identity mappings | |
911 | */ | |
912 | if (es7000_plat == 1) | |
913 | return; | |
914 | ||
4ef81297 AS |
915 | /* |
916 | * Locate the IOAPIC that manages the ISA IRQs (0-15). | |
1da177e4 LT |
917 | */ |
918 | ioapic = mp_find_ioapic(0); | |
919 | if (ioapic < 0) | |
920 | return; | |
921 | ||
922 | intsrc.mpc_type = MP_INTSRC; | |
4ef81297 | 923 | intsrc.mpc_irqflag = 0; /* Conforming */ |
1da177e4 | 924 | intsrc.mpc_srcbus = MP_ISA_BUS; |
61048c63 | 925 | #ifdef CONFIG_X86_IO_APIC |
1da177e4 | 926 | intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; |
61048c63 | 927 | #endif |
4ef81297 | 928 | /* |
1da177e4 | 929 | * Use the default configuration for the IRQs 0-15. Unless |
27b46d76 | 930 | * overridden by (MADT) interrupt source override entries. |
1da177e4 LT |
931 | */ |
932 | for (i = 0; i < 16; i++) { | |
933 | int idx; | |
934 | ||
935 | for (idx = 0; idx < mp_irq_entries; idx++) { | |
936 | struct mpc_config_intsrc *irq = mp_irqs + idx; | |
937 | ||
938 | /* Do we already have a mapping for this ISA IRQ? */ | |
4ef81297 AS |
939 | if (irq->mpc_srcbus == MP_ISA_BUS |
940 | && irq->mpc_srcbusirq == i) | |
1da177e4 LT |
941 | break; |
942 | ||
943 | /* Do we already have a mapping for this IOAPIC pin */ | |
944 | if ((irq->mpc_dstapic == intsrc.mpc_dstapic) && | |
4ef81297 | 945 | (irq->mpc_dstirq == i)) |
1da177e4 LT |
946 | break; |
947 | } | |
948 | ||
949 | if (idx != mp_irq_entries) { | |
950 | printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i); | |
4ef81297 | 951 | continue; /* IRQ already used */ |
1da177e4 LT |
952 | } |
953 | ||
954 | intsrc.mpc_irqtype = mp_INT; | |
4ef81297 | 955 | intsrc.mpc_srcbusirq = i; /* Identity mapped */ |
1da177e4 LT |
956 | intsrc.mpc_dstirq = i; |
957 | ||
958 | Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, " | |
4ef81297 AS |
959 | "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3, |
960 | (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus, | |
961 | intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, | |
1da177e4 LT |
962 | intsrc.mpc_dstirq); |
963 | ||
964 | mp_irqs[mp_irq_entries] = intsrc; | |
965 | if (++mp_irq_entries == MAX_IRQ_SOURCES) | |
966 | panic("Max # of irq sources exceeded!\n"); | |
967 | } | |
968 | } | |
969 | ||
c434b7a6 | 970 | #define MAX_GSI_NUM 4096 |
2ba7deef | 971 | #define IRQ_COMPRESSION_START 64 |
c434b7a6 | 972 | |
19f03ffe | 973 | int mp_register_gsi(u32 gsi, int triggering, int polarity) |
1da177e4 | 974 | { |
19f03ffe AK |
975 | int ioapic = -1; |
976 | int ioapic_pin = 0; | |
977 | int idx, bit = 0; | |
2ba7deef | 978 | static int pci_irq = IRQ_COMPRESSION_START; |
c434b7a6 | 979 | /* |
ab4a574e | 980 | * Mapping between Global System Interrupts, which |
c434b7a6 NP |
981 | * represent all possible interrupts, and IRQs |
982 | * assigned to actual devices. | |
983 | */ | |
4ef81297 | 984 | static int gsi_to_irq[MAX_GSI_NUM]; |
1da177e4 | 985 | |
1da177e4 | 986 | /* Don't set up the ACPI SCI because it's already set up */ |
cee324b1 | 987 | if (acpi_gbl_FADT.sci_interrupt == gsi) |
1da177e4 | 988 | return gsi; |
1da177e4 LT |
989 | |
990 | ioapic = mp_find_ioapic(gsi); | |
991 | if (ioapic < 0) { | |
992 | printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi); | |
993 | return gsi; | |
994 | } | |
995 | ||
996 | ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base; | |
997 | ||
998 | if (ioapic_renumber_irq) | |
999 | gsi = ioapic_renumber_irq(ioapic, gsi); | |
1000 | ||
4ef81297 AS |
1001 | /* |
1002 | * Avoid pin reprogramming. PRTs typically include entries | |
1da177e4 LT |
1003 | * with redundant pin->gsi mappings (but unique PCI devices); |
1004 | * we only program the IOAPIC on the first. | |
1005 | */ | |
1006 | bit = ioapic_pin % 32; | |
1007 | idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32); | |
1008 | if (idx > 3) { | |
1009 | printk(KERN_ERR "Invalid reference to IOAPIC pin " | |
4ef81297 AS |
1010 | "%d-%d\n", mp_ioapic_routing[ioapic].apic_id, |
1011 | ioapic_pin); | |
1da177e4 LT |
1012 | return gsi; |
1013 | } | |
4ef81297 | 1014 | if ((1 << bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) { |
1da177e4 LT |
1015 | Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n", |
1016 | mp_ioapic_routing[ioapic].apic_id, ioapic_pin); | |
2ba7deef | 1017 | return (gsi < IRQ_COMPRESSION_START ? gsi : gsi_to_irq[gsi]); |
1da177e4 LT |
1018 | } |
1019 | ||
4ef81297 | 1020 | mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1 << bit); |
1da177e4 | 1021 | |
2ba7deef LB |
1022 | /* |
1023 | * For GSI >= 64, use IRQ compression | |
1024 | */ | |
1025 | if ((gsi >= IRQ_COMPRESSION_START) | |
4ef81297 | 1026 | && (triggering == ACPI_LEVEL_SENSITIVE)) { |
c434b7a6 NP |
1027 | /* |
1028 | * For PCI devices assign IRQs in order, avoiding gaps | |
1029 | * due to unused I/O APIC pins. | |
1030 | */ | |
1031 | int irq = gsi; | |
1032 | if (gsi < MAX_GSI_NUM) { | |
e0c1e9bf KM |
1033 | /* |
1034 | * Retain the VIA chipset work-around (gsi > 15), but | |
1035 | * avoid a problem where the 8254 timer (IRQ0) is setup | |
1036 | * via an override (so it's not on pin 0 of the ioapic), | |
1037 | * and at the same time, the pin 0 interrupt is a PCI | |
1038 | * type. The gsi > 15 test could cause these two pins | |
1039 | * to be shared as IRQ0, and they are not shareable. | |
1040 | * So test for this condition, and if necessary, avoid | |
1041 | * the pin collision. | |
1042 | */ | |
ede1389f | 1043 | gsi = pci_irq++; |
e1afc3f5 NP |
1044 | /* |
1045 | * Don't assign IRQ used by ACPI SCI | |
1046 | */ | |
cee324b1 | 1047 | if (gsi == acpi_gbl_FADT.sci_interrupt) |
e1afc3f5 | 1048 | gsi = pci_irq++; |
c434b7a6 NP |
1049 | gsi_to_irq[irq] = gsi; |
1050 | } else { | |
1051 | printk(KERN_ERR "GSI %u is too high\n", gsi); | |
1052 | return gsi; | |
1053 | } | |
1054 | } | |
1055 | ||
1da177e4 | 1056 | io_apic_set_pci_routing(ioapic, ioapic_pin, gsi, |
4ef81297 AS |
1057 | triggering == ACPI_EDGE_SENSITIVE ? 0 : 1, |
1058 | polarity == ACPI_ACTIVE_HIGH ? 0 : 1); | |
1da177e4 LT |
1059 | return gsi; |
1060 | } | |
1061 | ||
8466361a | 1062 | #endif /* CONFIG_X86_IO_APIC */ |
888ba6c6 | 1063 | #endif /* CONFIG_ACPI */ |