Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Intel Multiprocessor Specification 1.1 and 1.4 | |
3 | * compliant MP-table parsing routines. | |
4 | * | |
5 | * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> | |
6 | * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
7 | * | |
8 | * Fixes | |
9 | * Erich Boleyn : MP v1.4 and additional changes. | |
10 | * Alan Cox : Added EBDA scanning | |
11 | * Ingo Molnar : various cleanups and rewrites | |
12 | * Maciej W. Rozycki: Bits for default MP configurations | |
13 | * Paul Diefenbaugh: Added full ACPI support | |
14 | */ | |
15 | ||
16 | #include <linux/mm.h> | |
1da177e4 LT |
17 | #include <linux/init.h> |
18 | #include <linux/delay.h> | |
1da177e4 | 19 | #include <linux/bootmem.h> |
1da177e4 LT |
20 | #include <linux/kernel_stat.h> |
21 | #include <linux/mc146818rtc.h> | |
22 | #include <linux/acpi.h> | |
8c5a0908 | 23 | #include <linux/module.h> |
1da177e4 LT |
24 | |
25 | #include <asm/smp.h> | |
26 | #include <asm/mtrr.h> | |
27 | #include <asm/mpspec.h> | |
28 | #include <asm/pgalloc.h> | |
29 | #include <asm/io_apic.h> | |
30 | #include <asm/proto.h> | |
8d916406 | 31 | #include <asm/acpi.h> |
1da177e4 LT |
32 | |
33 | /* Have we found an MP table */ | |
34 | int smp_found_config; | |
1da177e4 | 35 | |
1da177e4 LT |
36 | /* |
37 | * Various Linux-internal data structures created from the | |
38 | * MP-table. | |
39 | */ | |
55f05ffa | 40 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); |
1da177e4 | 41 | int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 }; |
1da177e4 LT |
42 | |
43 | static int mp_current_pci_id = 0; | |
44 | /* I/O APIC entries */ | |
45 | struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS]; | |
46 | ||
47 | /* # of MP IRQ source entries */ | |
48 | struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES]; | |
49 | ||
50 | /* MP IRQ source entries */ | |
51 | int mp_irq_entries; | |
52 | ||
53 | int nr_ioapics; | |
1da177e4 LT |
54 | unsigned long mp_lapic_addr = 0; |
55 | ||
56 | ||
57 | ||
58 | /* Processor that is doing the boot up */ | |
59 | unsigned int boot_cpu_id = -1U; | |
60 | /* Internal processor count */ | |
43999d9e | 61 | unsigned int num_processors __cpuinitdata = 0; |
420f8f68 | 62 | |
43999d9e | 63 | unsigned disabled_cpus __cpuinitdata; |
1da177e4 LT |
64 | |
65 | /* Bitmask of physically existing CPUs */ | |
66 | physid_mask_t phys_cpu_present_map = PHYSID_MASK_NONE; | |
67 | ||
1da177e4 LT |
68 | u8 bios_cpu_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID }; |
69 | ||
70 | ||
71 | /* | |
72 | * Intel MP BIOS table parsing routines: | |
73 | */ | |
74 | ||
75 | /* | |
76 | * Checksum an MP configuration block. | |
77 | */ | |
78 | ||
79 | static int __init mpf_checksum(unsigned char *mp, int len) | |
80 | { | |
81 | int sum = 0; | |
82 | ||
83 | while (len--) | |
84 | sum += *mp++; | |
85 | ||
86 | return sum & 0xFF; | |
87 | } | |
88 | ||
51f62e18 | 89 | static void __cpuinit MP_processor_info (struct mpc_config_processor *m) |
1da177e4 | 90 | { |
8893166f | 91 | int cpu; |
51f62e18 | 92 | cpumask_t tmp_map; |
f2c2cca3 | 93 | char *bootup_cpu = ""; |
1da177e4 | 94 | |
420f8f68 AK |
95 | if (!(m->mpc_cpuflag & CPU_ENABLED)) { |
96 | disabled_cpus++; | |
1da177e4 | 97 | return; |
420f8f68 | 98 | } |
1da177e4 | 99 | if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) { |
f2c2cca3 | 100 | bootup_cpu = " (Bootup-CPU)"; |
1da177e4 LT |
101 | boot_cpu_id = m->mpc_apicid; |
102 | } | |
f2c2cca3 AK |
103 | |
104 | printk(KERN_INFO "Processor #%d%s\n", m->mpc_apicid, bootup_cpu); | |
105 | ||
1da177e4 LT |
106 | if (num_processors >= NR_CPUS) { |
107 | printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached." | |
108 | " Processor ignored.\n", NR_CPUS); | |
109 | return; | |
110 | } | |
1da177e4 | 111 | |
51f62e18 AR |
112 | num_processors++; |
113 | cpus_complement(tmp_map, cpu_present_map); | |
114 | cpu = first_cpu(tmp_map); | |
115 | ||
1da177e4 | 116 | physid_set(m->mpc_apicid, phys_cpu_present_map); |
18a2b647 AK |
117 | if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) { |
118 | /* | |
119 | * bios_cpu_apicid is required to have processors listed | |
120 | * in same order as logical cpu numbers. Hence the first | |
121 | * entry is BSP, and so on. | |
122 | */ | |
61b1b2d0 | 123 | cpu = 0; |
51f62e18 | 124 | } |
61b1b2d0 AK |
125 | bios_cpu_apicid[cpu] = m->mpc_apicid; |
126 | x86_cpu_to_apicid[cpu] = m->mpc_apicid; | |
127 | ||
128 | cpu_set(cpu, cpu_possible_map); | |
129 | cpu_set(cpu, cpu_present_map); | |
1da177e4 LT |
130 | } |
131 | ||
132 | static void __init MP_bus_info (struct mpc_config_bus *m) | |
133 | { | |
134 | char str[7]; | |
135 | ||
136 | memcpy(str, m->mpc_bustype, 6); | |
137 | str[6] = 0; | |
138 | Dprintk("Bus #%d is %s\n", m->mpc_busid, str); | |
139 | ||
140 | if (strncmp(str, "ISA", 3) == 0) { | |
55f05ffa | 141 | set_bit(m->mpc_busid, mp_bus_not_pci); |
1da177e4 | 142 | } else if (strncmp(str, "PCI", 3) == 0) { |
55f05ffa | 143 | clear_bit(m->mpc_busid, mp_bus_not_pci); |
1da177e4 LT |
144 | mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id; |
145 | mp_current_pci_id++; | |
1da177e4 LT |
146 | } else { |
147 | printk(KERN_ERR "Unknown bustype %s\n", str); | |
148 | } | |
149 | } | |
150 | ||
013bf2c5 AK |
151 | static int bad_ioapic(unsigned long address) |
152 | { | |
153 | if (nr_ioapics >= MAX_IO_APICS) { | |
154 | printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded " | |
155 | "(found %d)\n", MAX_IO_APICS, nr_ioapics); | |
156 | panic("Recompile kernel with bigger MAX_IO_APICS!\n"); | |
157 | } | |
158 | if (!address) { | |
159 | printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address" | |
160 | " found in table, skipping!\n"); | |
161 | return 1; | |
162 | } | |
163 | return 0; | |
164 | } | |
165 | ||
1da177e4 LT |
166 | static void __init MP_ioapic_info (struct mpc_config_ioapic *m) |
167 | { | |
168 | if (!(m->mpc_flags & MPC_APIC_USABLE)) | |
169 | return; | |
170 | ||
f2c2cca3 AK |
171 | printk("I/O APIC #%d at 0x%X.\n", |
172 | m->mpc_apicid, m->mpc_apicaddr); | |
013bf2c5 AK |
173 | |
174 | if (bad_ioapic(m->mpc_apicaddr)) | |
1da177e4 | 175 | return; |
013bf2c5 | 176 | |
1da177e4 LT |
177 | mp_ioapics[nr_ioapics] = *m; |
178 | nr_ioapics++; | |
179 | } | |
180 | ||
181 | static void __init MP_intsrc_info (struct mpc_config_intsrc *m) | |
182 | { | |
183 | mp_irqs [mp_irq_entries] = *m; | |
184 | Dprintk("Int: type %d, pol %d, trig %d, bus %d," | |
185 | " IRQ %02x, APIC ID %x, APIC INT %02x\n", | |
186 | m->mpc_irqtype, m->mpc_irqflag & 3, | |
187 | (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus, | |
188 | m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq); | |
6004e1b7 | 189 | if (++mp_irq_entries >= MAX_IRQ_SOURCES) |
1da177e4 LT |
190 | panic("Max # of irq sources exceeded!!\n"); |
191 | } | |
192 | ||
193 | static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m) | |
194 | { | |
195 | Dprintk("Lint: type %d, pol %d, trig %d, bus %d," | |
196 | " IRQ %02x, APIC ID %x, APIC LINT %02x\n", | |
197 | m->mpc_irqtype, m->mpc_irqflag & 3, | |
198 | (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid, | |
199 | m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint); | |
1da177e4 LT |
200 | } |
201 | ||
202 | /* | |
203 | * Read/parse the MPC | |
204 | */ | |
205 | ||
206 | static int __init smp_read_mpc(struct mp_config_table *mpc) | |
207 | { | |
208 | char str[16]; | |
209 | int count=sizeof(*mpc); | |
210 | unsigned char *mpt=((unsigned char *)mpc)+count; | |
211 | ||
212 | if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) { | |
aecc6361 | 213 | printk("MPTABLE: bad signature [%c%c%c%c]!\n", |
1da177e4 LT |
214 | mpc->mpc_signature[0], |
215 | mpc->mpc_signature[1], | |
216 | mpc->mpc_signature[2], | |
217 | mpc->mpc_signature[3]); | |
218 | return 0; | |
219 | } | |
220 | if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) { | |
aecc6361 | 221 | printk("MPTABLE: checksum error!\n"); |
1da177e4 LT |
222 | return 0; |
223 | } | |
224 | if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) { | |
aecc6361 | 225 | printk(KERN_ERR "MPTABLE: bad table version (%d)!!\n", |
1da177e4 LT |
226 | mpc->mpc_spec); |
227 | return 0; | |
228 | } | |
229 | if (!mpc->mpc_lapic) { | |
aecc6361 | 230 | printk(KERN_ERR "MPTABLE: null local APIC address!\n"); |
1da177e4 LT |
231 | return 0; |
232 | } | |
233 | memcpy(str,mpc->mpc_oem,8); | |
aecc6361 AK |
234 | str[8] = 0; |
235 | printk(KERN_INFO "MPTABLE: OEM ID: %s ",str); | |
1da177e4 LT |
236 | |
237 | memcpy(str,mpc->mpc_productid,12); | |
aecc6361 AK |
238 | str[12] = 0; |
239 | printk("MPTABLE: Product ID: %s ",str); | |
1da177e4 | 240 | |
aecc6361 | 241 | printk("MPTABLE: APIC at: 0x%X\n",mpc->mpc_lapic); |
1da177e4 LT |
242 | |
243 | /* save the local APIC address, it might be non-default */ | |
244 | if (!acpi_lapic) | |
aecc6361 | 245 | mp_lapic_addr = mpc->mpc_lapic; |
1da177e4 LT |
246 | |
247 | /* | |
248 | * Now process the configuration blocks. | |
249 | */ | |
250 | while (count < mpc->mpc_length) { | |
251 | switch(*mpt) { | |
252 | case MP_PROCESSOR: | |
253 | { | |
254 | struct mpc_config_processor *m= | |
255 | (struct mpc_config_processor *)mpt; | |
256 | if (!acpi_lapic) | |
aecc6361 | 257 | MP_processor_info(m); |
1da177e4 LT |
258 | mpt += sizeof(*m); |
259 | count += sizeof(*m); | |
260 | break; | |
261 | } | |
262 | case MP_BUS: | |
263 | { | |
264 | struct mpc_config_bus *m= | |
265 | (struct mpc_config_bus *)mpt; | |
266 | MP_bus_info(m); | |
267 | mpt += sizeof(*m); | |
268 | count += sizeof(*m); | |
269 | break; | |
270 | } | |
271 | case MP_IOAPIC: | |
272 | { | |
273 | struct mpc_config_ioapic *m= | |
274 | (struct mpc_config_ioapic *)mpt; | |
275 | MP_ioapic_info(m); | |
aecc6361 AK |
276 | mpt += sizeof(*m); |
277 | count += sizeof(*m); | |
1da177e4 LT |
278 | break; |
279 | } | |
280 | case MP_INTSRC: | |
281 | { | |
282 | struct mpc_config_intsrc *m= | |
283 | (struct mpc_config_intsrc *)mpt; | |
284 | ||
285 | MP_intsrc_info(m); | |
aecc6361 AK |
286 | mpt += sizeof(*m); |
287 | count += sizeof(*m); | |
1da177e4 LT |
288 | break; |
289 | } | |
290 | case MP_LINTSRC: | |
291 | { | |
292 | struct mpc_config_lintsrc *m= | |
293 | (struct mpc_config_lintsrc *)mpt; | |
294 | MP_lintsrc_info(m); | |
aecc6361 AK |
295 | mpt += sizeof(*m); |
296 | count += sizeof(*m); | |
1da177e4 LT |
297 | break; |
298 | } | |
299 | } | |
300 | } | |
3c43f039 | 301 | setup_apic_routing(); |
1da177e4 | 302 | if (!num_processors) |
aecc6361 | 303 | printk(KERN_ERR "MPTABLE: no processors registered!\n"); |
1da177e4 LT |
304 | return num_processors; |
305 | } | |
306 | ||
307 | static int __init ELCR_trigger(unsigned int irq) | |
308 | { | |
309 | unsigned int port; | |
310 | ||
311 | port = 0x4d0 + (irq >> 3); | |
312 | return (inb(port) >> (irq & 7)) & 1; | |
313 | } | |
314 | ||
315 | static void __init construct_default_ioirq_mptable(int mpc_default_type) | |
316 | { | |
317 | struct mpc_config_intsrc intsrc; | |
318 | int i; | |
319 | int ELCR_fallback = 0; | |
320 | ||
321 | intsrc.mpc_type = MP_INTSRC; | |
322 | intsrc.mpc_irqflag = 0; /* conforming */ | |
323 | intsrc.mpc_srcbus = 0; | |
324 | intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid; | |
325 | ||
326 | intsrc.mpc_irqtype = mp_INT; | |
327 | ||
328 | /* | |
329 | * If true, we have an ISA/PCI system with no IRQ entries | |
330 | * in the MP table. To prevent the PCI interrupts from being set up | |
331 | * incorrectly, we try to use the ELCR. The sanity check to see if | |
332 | * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can | |
333 | * never be level sensitive, so we simply see if the ELCR agrees. | |
334 | * If it does, we assume it's valid. | |
335 | */ | |
336 | if (mpc_default_type == 5) { | |
337 | printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n"); | |
338 | ||
339 | if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13)) | |
340 | printk(KERN_ERR "ELCR contains invalid data... not using ELCR\n"); | |
341 | else { | |
342 | printk(KERN_INFO "Using ELCR to identify PCI interrupts\n"); | |
343 | ELCR_fallback = 1; | |
344 | } | |
345 | } | |
346 | ||
347 | for (i = 0; i < 16; i++) { | |
348 | switch (mpc_default_type) { | |
349 | case 2: | |
350 | if (i == 0 || i == 13) | |
351 | continue; /* IRQ0 & IRQ13 not connected */ | |
352 | /* fall through */ | |
353 | default: | |
354 | if (i == 2) | |
355 | continue; /* IRQ2 is never connected */ | |
356 | } | |
357 | ||
358 | if (ELCR_fallback) { | |
359 | /* | |
360 | * If the ELCR indicates a level-sensitive interrupt, we | |
361 | * copy that information over to the MP table in the | |
362 | * irqflag field (level sensitive, active high polarity). | |
363 | */ | |
364 | if (ELCR_trigger(i)) | |
365 | intsrc.mpc_irqflag = 13; | |
366 | else | |
367 | intsrc.mpc_irqflag = 0; | |
368 | } | |
369 | ||
370 | intsrc.mpc_srcbusirq = i; | |
371 | intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */ | |
372 | MP_intsrc_info(&intsrc); | |
373 | } | |
374 | ||
375 | intsrc.mpc_irqtype = mp_ExtINT; | |
376 | intsrc.mpc_srcbusirq = 0; | |
377 | intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */ | |
378 | MP_intsrc_info(&intsrc); | |
379 | } | |
380 | ||
381 | static inline void __init construct_default_ISA_mptable(int mpc_default_type) | |
382 | { | |
383 | struct mpc_config_processor processor; | |
384 | struct mpc_config_bus bus; | |
385 | struct mpc_config_ioapic ioapic; | |
386 | struct mpc_config_lintsrc lintsrc; | |
387 | int linttypes[2] = { mp_ExtINT, mp_NMI }; | |
388 | int i; | |
389 | ||
390 | /* | |
391 | * local APIC has default address | |
392 | */ | |
393 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
394 | ||
395 | /* | |
396 | * 2 CPUs, numbered 0 & 1. | |
397 | */ | |
398 | processor.mpc_type = MP_PROCESSOR; | |
f2c2cca3 | 399 | processor.mpc_apicver = 0; |
1da177e4 | 400 | processor.mpc_cpuflag = CPU_ENABLED; |
f2c2cca3 AK |
401 | processor.mpc_cpufeature = 0; |
402 | processor.mpc_featureflag = 0; | |
1da177e4 LT |
403 | processor.mpc_reserved[0] = 0; |
404 | processor.mpc_reserved[1] = 0; | |
405 | for (i = 0; i < 2; i++) { | |
406 | processor.mpc_apicid = i; | |
407 | MP_processor_info(&processor); | |
408 | } | |
409 | ||
410 | bus.mpc_type = MP_BUS; | |
411 | bus.mpc_busid = 0; | |
412 | switch (mpc_default_type) { | |
413 | default: | |
414 | printk(KERN_ERR "???\nUnknown standard configuration %d\n", | |
415 | mpc_default_type); | |
416 | /* fall through */ | |
417 | case 1: | |
418 | case 5: | |
419 | memcpy(bus.mpc_bustype, "ISA ", 6); | |
420 | break; | |
1da177e4 LT |
421 | } |
422 | MP_bus_info(&bus); | |
423 | if (mpc_default_type > 4) { | |
424 | bus.mpc_busid = 1; | |
425 | memcpy(bus.mpc_bustype, "PCI ", 6); | |
426 | MP_bus_info(&bus); | |
427 | } | |
428 | ||
429 | ioapic.mpc_type = MP_IOAPIC; | |
430 | ioapic.mpc_apicid = 2; | |
f2c2cca3 | 431 | ioapic.mpc_apicver = 0; |
1da177e4 LT |
432 | ioapic.mpc_flags = MPC_APIC_USABLE; |
433 | ioapic.mpc_apicaddr = 0xFEC00000; | |
434 | MP_ioapic_info(&ioapic); | |
435 | ||
436 | /* | |
437 | * We set up most of the low 16 IO-APIC pins according to MPS rules. | |
438 | */ | |
439 | construct_default_ioirq_mptable(mpc_default_type); | |
440 | ||
441 | lintsrc.mpc_type = MP_LINTSRC; | |
442 | lintsrc.mpc_irqflag = 0; /* conforming */ | |
443 | lintsrc.mpc_srcbusid = 0; | |
444 | lintsrc.mpc_srcbusirq = 0; | |
445 | lintsrc.mpc_destapic = MP_APIC_ALL; | |
446 | for (i = 0; i < 2; i++) { | |
447 | lintsrc.mpc_irqtype = linttypes[i]; | |
448 | lintsrc.mpc_destapiclint = i; | |
449 | MP_lintsrc_info(&lintsrc); | |
450 | } | |
451 | } | |
452 | ||
453 | static struct intel_mp_floating *mpf_found; | |
454 | ||
455 | /* | |
456 | * Scan the memory blocks for an SMP configuration block. | |
457 | */ | |
458 | void __init get_smp_config (void) | |
459 | { | |
460 | struct intel_mp_floating *mpf = mpf_found; | |
461 | ||
462 | /* | |
1da177e4 LT |
463 | * ACPI supports both logical (e.g. Hyper-Threading) and physical |
464 | * processors, where MPS only supports physical. | |
465 | */ | |
466 | if (acpi_lapic && acpi_ioapic) { | |
467 | printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n"); | |
468 | return; | |
469 | } | |
470 | else if (acpi_lapic) | |
471 | printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n"); | |
472 | ||
473 | printk("Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification); | |
1da177e4 LT |
474 | |
475 | /* | |
476 | * Now see if we need to read further. | |
477 | */ | |
478 | if (mpf->mpf_feature1 != 0) { | |
479 | ||
480 | printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1); | |
481 | construct_default_ISA_mptable(mpf->mpf_feature1); | |
482 | ||
483 | } else if (mpf->mpf_physptr) { | |
484 | ||
485 | /* | |
486 | * Read the physical hardware table. Anything here will | |
487 | * override the defaults. | |
488 | */ | |
f6c2e333 | 489 | if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr))) { |
1da177e4 LT |
490 | smp_found_config = 0; |
491 | printk(KERN_ERR "BIOS bug, MP table errors detected!...\n"); | |
492 | printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n"); | |
493 | return; | |
494 | } | |
495 | /* | |
496 | * If there are no explicit MP IRQ entries, then we are | |
497 | * broken. We set up most of the low 16 IO-APIC pins to | |
498 | * ISA defaults and hope it will work. | |
499 | */ | |
500 | if (!mp_irq_entries) { | |
501 | struct mpc_config_bus bus; | |
502 | ||
503 | printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n"); | |
504 | ||
505 | bus.mpc_type = MP_BUS; | |
506 | bus.mpc_busid = 0; | |
507 | memcpy(bus.mpc_bustype, "ISA ", 6); | |
508 | MP_bus_info(&bus); | |
509 | ||
510 | construct_default_ioirq_mptable(0); | |
511 | } | |
512 | ||
513 | } else | |
514 | BUG(); | |
515 | ||
516 | printk(KERN_INFO "Processors: %d\n", num_processors); | |
517 | /* | |
518 | * Only use the first configuration found. | |
519 | */ | |
520 | } | |
521 | ||
522 | static int __init smp_scan_config (unsigned long base, unsigned long length) | |
523 | { | |
524 | extern void __bad_mpf_size(void); | |
525 | unsigned int *bp = phys_to_virt(base); | |
526 | struct intel_mp_floating *mpf; | |
527 | ||
528 | Dprintk("Scan SMP from %p for %ld bytes.\n", bp,length); | |
529 | if (sizeof(*mpf) != 16) | |
530 | __bad_mpf_size(); | |
531 | ||
532 | while (length > 0) { | |
533 | mpf = (struct intel_mp_floating *)bp; | |
534 | if ((*bp == SMP_MAGIC_IDENT) && | |
535 | (mpf->mpf_length == 1) && | |
536 | !mpf_checksum((unsigned char *)bp, 16) && | |
537 | ((mpf->mpf_specification == 1) | |
538 | || (mpf->mpf_specification == 4)) ) { | |
539 | ||
540 | smp_found_config = 1; | |
541 | reserve_bootmem_generic(virt_to_phys(mpf), PAGE_SIZE); | |
542 | if (mpf->mpf_physptr) | |
543 | reserve_bootmem_generic(mpf->mpf_physptr, PAGE_SIZE); | |
544 | mpf_found = mpf; | |
545 | return 1; | |
546 | } | |
547 | bp += 4; | |
548 | length -= 16; | |
549 | } | |
550 | return 0; | |
551 | } | |
552 | ||
a01fd3ba | 553 | void __init find_smp_config(void) |
1da177e4 LT |
554 | { |
555 | unsigned int address; | |
556 | ||
557 | /* | |
558 | * FIXME: Linux assumes you have 640K of base ram.. | |
559 | * this continues the error... | |
560 | * | |
561 | * 1) Scan the bottom 1K for a signature | |
562 | * 2) Scan the top 1K of base RAM | |
563 | * 3) Scan the 64K of bios | |
564 | */ | |
565 | if (smp_scan_config(0x0,0x400) || | |
566 | smp_scan_config(639*0x400,0x400) || | |
567 | smp_scan_config(0xF0000,0x10000)) | |
568 | return; | |
569 | /* | |
e5099134 | 570 | * If it is an SMP machine we should know now. |
1da177e4 LT |
571 | * |
572 | * there is a real-mode segmented pointer pointing to the | |
573 | * 4K EBDA area at 0x40E, calculate and scan it here. | |
574 | * | |
575 | * NOTE! There are Linux loaders that will corrupt the EBDA | |
576 | * area, and as such this kind of SMP config may be less | |
577 | * trustworthy, simply because the SMP table may have been | |
578 | * stomped on during early boot. These loaders are buggy and | |
579 | * should be fixed. | |
580 | */ | |
581 | ||
582 | address = *(unsigned short *)phys_to_virt(0x40E); | |
583 | address <<= 4; | |
584 | if (smp_scan_config(address, 0x1000)) | |
585 | return; | |
586 | ||
587 | /* If we have come this far, we did not find an MP table */ | |
588 | printk(KERN_INFO "No mptable found.\n"); | |
589 | } | |
590 | ||
1da177e4 LT |
591 | /* -------------------------------------------------------------------------- |
592 | ACPI-based MP Configuration | |
593 | -------------------------------------------------------------------------- */ | |
594 | ||
888ba6c6 | 595 | #ifdef CONFIG_ACPI |
1da177e4 | 596 | |
efec3b9a | 597 | void __init mp_register_lapic_address(u64 address) |
1da177e4 LT |
598 | { |
599 | mp_lapic_addr = (unsigned long) address; | |
1da177e4 | 600 | set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr); |
1da177e4 LT |
601 | if (boot_cpu_id == -1U) |
602 | boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID)); | |
1da177e4 LT |
603 | } |
604 | ||
efec3b9a | 605 | void __cpuinit mp_register_lapic (u8 id, u8 enabled) |
1da177e4 LT |
606 | { |
607 | struct mpc_config_processor processor; | |
608 | int boot_cpu = 0; | |
609 | ||
e4251e13 | 610 | if (id == boot_cpu_id) |
1da177e4 LT |
611 | boot_cpu = 1; |
612 | ||
613 | processor.mpc_type = MP_PROCESSOR; | |
614 | processor.mpc_apicid = id; | |
f2c2cca3 | 615 | processor.mpc_apicver = 0; |
1da177e4 LT |
616 | processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0); |
617 | processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0); | |
f2c2cca3 AK |
618 | processor.mpc_cpufeature = 0; |
619 | processor.mpc_featureflag = 0; | |
1da177e4 LT |
620 | processor.mpc_reserved[0] = 0; |
621 | processor.mpc_reserved[1] = 0; | |
622 | ||
623 | MP_processor_info(&processor); | |
624 | } | |
625 | ||
1da177e4 LT |
626 | #define MP_ISA_BUS 0 |
627 | #define MP_MAX_IOAPIC_PIN 127 | |
628 | ||
629 | static struct mp_ioapic_routing { | |
630 | int apic_id; | |
631 | int gsi_start; | |
632 | int gsi_end; | |
633 | u32 pin_programmed[4]; | |
634 | } mp_ioapic_routing[MAX_IO_APICS]; | |
635 | ||
efec3b9a | 636 | static int mp_find_ioapic(int gsi) |
1da177e4 | 637 | { |
efec3b9a | 638 | int i = 0; |
1da177e4 LT |
639 | |
640 | /* Find the IOAPIC that manages this GSI. */ | |
641 | for (i = 0; i < nr_ioapics; i++) { | |
642 | if ((gsi >= mp_ioapic_routing[i].gsi_start) | |
643 | && (gsi <= mp_ioapic_routing[i].gsi_end)) | |
644 | return i; | |
645 | } | |
646 | ||
647 | printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); | |
1da177e4 LT |
648 | return -1; |
649 | } | |
1da177e4 | 650 | |
78b599ae AK |
651 | static u8 uniq_ioapic_id(u8 id) |
652 | { | |
653 | int i; | |
654 | DECLARE_BITMAP(used, 256); | |
655 | bitmap_zero(used, 256); | |
656 | for (i = 0; i < nr_ioapics; i++) { | |
657 | struct mpc_config_ioapic *ia = &mp_ioapics[i]; | |
658 | __set_bit(ia->mpc_apicid, used); | |
659 | } | |
660 | if (!test_bit(id, used)) | |
661 | return id; | |
662 | return find_first_zero_bit(used, 256); | |
663 | } | |
664 | ||
efec3b9a | 665 | void __init mp_register_ioapic(u8 id, u32 address, u32 gsi_base) |
1da177e4 | 666 | { |
efec3b9a | 667 | int idx = 0; |
1da177e4 | 668 | |
013bf2c5 | 669 | if (bad_ioapic(address)) |
1da177e4 | 670 | return; |
1da177e4 | 671 | |
78b599ae | 672 | idx = nr_ioapics; |
1da177e4 LT |
673 | |
674 | mp_ioapics[idx].mpc_type = MP_IOAPIC; | |
675 | mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE; | |
676 | mp_ioapics[idx].mpc_apicaddr = address; | |
677 | ||
678 | set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); | |
78b599ae | 679 | mp_ioapics[idx].mpc_apicid = uniq_ioapic_id(id); |
f2c2cca3 | 680 | mp_ioapics[idx].mpc_apicver = 0; |
1da177e4 LT |
681 | |
682 | /* | |
683 | * Build basic IRQ lookup table to facilitate gsi->io_apic lookups | |
684 | * and to prevent reprogramming of IOAPIC pins (PCI IRQs). | |
685 | */ | |
686 | mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid; | |
687 | mp_ioapic_routing[idx].gsi_start = gsi_base; | |
688 | mp_ioapic_routing[idx].gsi_end = gsi_base + | |
689 | io_apic_get_redir_entries(idx); | |
690 | ||
f2c2cca3 | 691 | printk(KERN_INFO "IOAPIC[%d]: apic_id %d, address 0x%x, " |
1da177e4 | 692 | "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid, |
f2c2cca3 | 693 | mp_ioapics[idx].mpc_apicaddr, |
1da177e4 LT |
694 | mp_ioapic_routing[idx].gsi_start, |
695 | mp_ioapic_routing[idx].gsi_end); | |
78b599ae AK |
696 | |
697 | nr_ioapics++; | |
1da177e4 LT |
698 | } |
699 | ||
efec3b9a AK |
700 | void __init |
701 | mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi) | |
1da177e4 LT |
702 | { |
703 | struct mpc_config_intsrc intsrc; | |
704 | int ioapic = -1; | |
705 | int pin = -1; | |
706 | ||
707 | /* | |
708 | * Convert 'gsi' to 'ioapic.pin'. | |
709 | */ | |
710 | ioapic = mp_find_ioapic(gsi); | |
711 | if (ioapic < 0) | |
712 | return; | |
713 | pin = gsi - mp_ioapic_routing[ioapic].gsi_start; | |
714 | ||
715 | /* | |
716 | * TBD: This check is for faulty timer entries, where the override | |
717 | * erroneously sets the trigger to level, resulting in a HUGE | |
718 | * increase of timer interrupts! | |
719 | */ | |
720 | if ((bus_irq == 0) && (trigger == 3)) | |
721 | trigger = 1; | |
722 | ||
723 | intsrc.mpc_type = MP_INTSRC; | |
724 | intsrc.mpc_irqtype = mp_INT; | |
725 | intsrc.mpc_irqflag = (trigger << 2) | polarity; | |
726 | intsrc.mpc_srcbus = MP_ISA_BUS; | |
727 | intsrc.mpc_srcbusirq = bus_irq; /* IRQ */ | |
728 | intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */ | |
729 | intsrc.mpc_dstirq = pin; /* INTIN# */ | |
730 | ||
731 | Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n", | |
732 | intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3, | |
733 | (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus, | |
734 | intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq); | |
735 | ||
736 | mp_irqs[mp_irq_entries] = intsrc; | |
737 | if (++mp_irq_entries == MAX_IRQ_SOURCES) | |
738 | panic("Max # of irq sources exceeded!\n"); | |
1da177e4 LT |
739 | } |
740 | ||
efec3b9a | 741 | void __init mp_config_acpi_legacy_irqs(void) |
1da177e4 LT |
742 | { |
743 | struct mpc_config_intsrc intsrc; | |
efec3b9a AK |
744 | int i = 0; |
745 | int ioapic = -1; | |
1da177e4 LT |
746 | |
747 | /* | |
748 | * Fabricate the legacy ISA bus (bus #31). | |
749 | */ | |
55f05ffa | 750 | set_bit(MP_ISA_BUS, mp_bus_not_pci); |
1da177e4 LT |
751 | |
752 | /* | |
753 | * Locate the IOAPIC that manages the ISA IRQs (0-15). | |
754 | */ | |
755 | ioapic = mp_find_ioapic(0); | |
756 | if (ioapic < 0) | |
757 | return; | |
758 | ||
759 | intsrc.mpc_type = MP_INTSRC; | |
760 | intsrc.mpc_irqflag = 0; /* Conforming */ | |
761 | intsrc.mpc_srcbus = MP_ISA_BUS; | |
762 | intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; | |
763 | ||
764 | /* | |
765 | * Use the default configuration for the IRQs 0-15. Unless | |
766 | * overridden by (MADT) interrupt source override entries. | |
767 | */ | |
768 | for (i = 0; i < 16; i++) { | |
769 | int idx; | |
770 | ||
771 | for (idx = 0; idx < mp_irq_entries; idx++) { | |
772 | struct mpc_config_intsrc *irq = mp_irqs + idx; | |
773 | ||
774 | /* Do we already have a mapping for this ISA IRQ? */ | |
775 | if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i) | |
776 | break; | |
777 | ||
778 | /* Do we already have a mapping for this IOAPIC pin */ | |
779 | if ((irq->mpc_dstapic == intsrc.mpc_dstapic) && | |
780 | (irq->mpc_dstirq == i)) | |
781 | break; | |
782 | } | |
783 | ||
784 | if (idx != mp_irq_entries) { | |
785 | printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i); | |
786 | continue; /* IRQ already used */ | |
787 | } | |
788 | ||
789 | intsrc.mpc_irqtype = mp_INT; | |
790 | intsrc.mpc_srcbusirq = i; /* Identity mapped */ | |
791 | intsrc.mpc_dstirq = i; | |
792 | ||
793 | Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, " | |
794 | "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3, | |
795 | (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus, | |
796 | intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, | |
797 | intsrc.mpc_dstirq); | |
798 | ||
799 | mp_irqs[mp_irq_entries] = intsrc; | |
800 | if (++mp_irq_entries == MAX_IRQ_SOURCES) | |
801 | panic("Max # of irq sources exceeded!\n"); | |
802 | } | |
1da177e4 LT |
803 | } |
804 | ||
50eca3eb | 805 | int mp_register_gsi(u32 gsi, int triggering, int polarity) |
1da177e4 | 806 | { |
efec3b9a AK |
807 | int ioapic = -1; |
808 | int ioapic_pin = 0; | |
809 | int idx, bit = 0; | |
1da177e4 LT |
810 | |
811 | if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC) | |
812 | return gsi; | |
813 | ||
1da177e4 | 814 | /* Don't set up the ACPI SCI because it's already set up */ |
cee324b1 | 815 | if (acpi_gbl_FADT.sci_interrupt == gsi) |
1da177e4 | 816 | return gsi; |
1da177e4 LT |
817 | |
818 | ioapic = mp_find_ioapic(gsi); | |
819 | if (ioapic < 0) { | |
820 | printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi); | |
821 | return gsi; | |
822 | } | |
823 | ||
824 | ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_start; | |
825 | ||
826 | /* | |
827 | * Avoid pin reprogramming. PRTs typically include entries | |
828 | * with redundant pin->gsi mappings (but unique PCI devices); | |
829 | * we only program the IOAPIC on the first. | |
830 | */ | |
831 | bit = ioapic_pin % 32; | |
832 | idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32); | |
833 | if (idx > 3) { | |
834 | printk(KERN_ERR "Invalid reference to IOAPIC pin " | |
835 | "%d-%d\n", mp_ioapic_routing[ioapic].apic_id, | |
836 | ioapic_pin); | |
837 | return gsi; | |
838 | } | |
839 | if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) { | |
840 | Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n", | |
841 | mp_ioapic_routing[ioapic].apic_id, ioapic_pin); | |
cd1182f5 | 842 | return gsi; |
1da177e4 LT |
843 | } |
844 | ||
845 | mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit); | |
846 | ||
847 | io_apic_set_pci_routing(ioapic, ioapic_pin, gsi, | |
50eca3eb BM |
848 | triggering == ACPI_EDGE_SENSITIVE ? 0 : 1, |
849 | polarity == ACPI_ACTIVE_HIGH ? 0 : 1); | |
1da177e4 LT |
850 | return gsi; |
851 | } | |
888ba6c6 | 852 | #endif /*CONFIG_ACPI*/ |