Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Intel Multiprocessor Specification 1.1 and 1.4 | |
3 | * compliant MP-table parsing routines. | |
4 | * | |
5 | * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> | |
6 | * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
7 | * | |
8 | * Fixes | |
9 | * Erich Boleyn : MP v1.4 and additional changes. | |
10 | * Alan Cox : Added EBDA scanning | |
11 | * Ingo Molnar : various cleanups and rewrites | |
12 | * Maciej W. Rozycki: Bits for default MP configurations | |
13 | * Paul Diefenbaugh: Added full ACPI support | |
14 | */ | |
15 | ||
16 | #include <linux/mm.h> | |
1da177e4 LT |
17 | #include <linux/init.h> |
18 | #include <linux/delay.h> | |
1da177e4 | 19 | #include <linux/bootmem.h> |
1da177e4 LT |
20 | #include <linux/kernel_stat.h> |
21 | #include <linux/mc146818rtc.h> | |
22 | #include <linux/acpi.h> | |
8c5a0908 | 23 | #include <linux/module.h> |
1da177e4 LT |
24 | |
25 | #include <asm/smp.h> | |
26 | #include <asm/mtrr.h> | |
27 | #include <asm/mpspec.h> | |
28 | #include <asm/pgalloc.h> | |
29 | #include <asm/io_apic.h> | |
30 | #include <asm/proto.h> | |
8d916406 | 31 | #include <asm/acpi.h> |
ce3fe6b2 | 32 | #include <asm/bios_ebda.h> |
1da177e4 | 33 | |
f6bc4029 GOC |
34 | #include <mach_apic.h> |
35 | ||
1da177e4 LT |
36 | /* Have we found an MP table */ |
37 | int smp_found_config; | |
1da177e4 | 38 | |
1da177e4 LT |
39 | /* |
40 | * Various Linux-internal data structures created from the | |
41 | * MP-table. | |
42 | */ | |
55f05ffa | 43 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); |
d2953315 | 44 | int mp_bus_id_to_pci_bus[MAX_MP_BUSSES] = {[0 ... MAX_MP_BUSSES - 1] = -1 }; |
1da177e4 LT |
45 | |
46 | static int mp_current_pci_id = 0; | |
1da177e4 | 47 | |
1da177e4 LT |
48 | /* |
49 | * Intel MP BIOS table parsing routines: | |
50 | */ | |
51 | ||
52 | /* | |
53 | * Checksum an MP configuration block. | |
54 | */ | |
55 | ||
56 | static int __init mpf_checksum(unsigned char *mp, int len) | |
57 | { | |
58 | int sum = 0; | |
59 | ||
60 | while (len--) | |
61 | sum += *mp++; | |
62 | ||
63 | return sum & 0xFF; | |
64 | } | |
65 | ||
0e01c00c AS |
66 | static void __cpuinit MP_processor_info(struct mpc_config_processor *m) |
67 | { | |
68 | char *bootup_cpu = ""; | |
69 | ||
70 | if (!(m->mpc_cpuflag & CPU_ENABLED)) { | |
71 | disabled_cpus++; | |
72 | return; | |
73 | } | |
74 | if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) { | |
75 | bootup_cpu = " (Bootup-CPU)"; | |
76 | boot_cpu_physical_apicid = m->mpc_apicid; | |
77 | } | |
78 | ||
79 | printk(KERN_INFO "Processor #%d%s\n", m->mpc_apicid, bootup_cpu); | |
80 | generic_processor_info(m->mpc_apicid, 0); | |
81 | } | |
82 | ||
d2953315 | 83 | static void __init MP_bus_info(struct mpc_config_bus *m) |
1da177e4 LT |
84 | { |
85 | char str[7]; | |
86 | ||
87 | memcpy(str, m->mpc_bustype, 6); | |
88 | str[6] = 0; | |
89 | Dprintk("Bus #%d is %s\n", m->mpc_busid, str); | |
90 | ||
91 | if (strncmp(str, "ISA", 3) == 0) { | |
55f05ffa | 92 | set_bit(m->mpc_busid, mp_bus_not_pci); |
1da177e4 | 93 | } else if (strncmp(str, "PCI", 3) == 0) { |
55f05ffa | 94 | clear_bit(m->mpc_busid, mp_bus_not_pci); |
1da177e4 LT |
95 | mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id; |
96 | mp_current_pci_id++; | |
1da177e4 LT |
97 | } else { |
98 | printk(KERN_ERR "Unknown bustype %s\n", str); | |
99 | } | |
100 | } | |
101 | ||
013bf2c5 AK |
102 | static int bad_ioapic(unsigned long address) |
103 | { | |
104 | if (nr_ioapics >= MAX_IO_APICS) { | |
105 | printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded " | |
d2953315 | 106 | "(found %d)\n", MAX_IO_APICS, nr_ioapics); |
013bf2c5 AK |
107 | panic("Recompile kernel with bigger MAX_IO_APICS!\n"); |
108 | } | |
109 | if (!address) { | |
110 | printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address" | |
d2953315 | 111 | " found in table, skipping!\n"); |
013bf2c5 AK |
112 | return 1; |
113 | } | |
114 | return 0; | |
115 | } | |
116 | ||
d2953315 | 117 | static void __init MP_ioapic_info(struct mpc_config_ioapic *m) |
1da177e4 LT |
118 | { |
119 | if (!(m->mpc_flags & MPC_APIC_USABLE)) | |
120 | return; | |
121 | ||
d2953315 AS |
122 | printk(KERN_INFO "I/O APIC #%d at 0x%X.\n", m->mpc_apicid, |
123 | m->mpc_apicaddr); | |
013bf2c5 AK |
124 | |
125 | if (bad_ioapic(m->mpc_apicaddr)) | |
1da177e4 | 126 | return; |
013bf2c5 | 127 | |
1da177e4 LT |
128 | mp_ioapics[nr_ioapics] = *m; |
129 | nr_ioapics++; | |
130 | } | |
131 | ||
d2953315 | 132 | static void __init MP_intsrc_info(struct mpc_config_intsrc *m) |
1da177e4 | 133 | { |
d2953315 | 134 | mp_irqs[mp_irq_entries] = *m; |
1da177e4 LT |
135 | Dprintk("Int: type %d, pol %d, trig %d, bus %d," |
136 | " IRQ %02x, APIC ID %x, APIC INT %02x\n", | |
d2953315 AS |
137 | m->mpc_irqtype, m->mpc_irqflag & 3, |
138 | (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus, | |
139 | m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq); | |
6004e1b7 | 140 | if (++mp_irq_entries >= MAX_IRQ_SOURCES) |
1da177e4 LT |
141 | panic("Max # of irq sources exceeded!!\n"); |
142 | } | |
143 | ||
d2953315 | 144 | static void __init MP_lintsrc_info(struct mpc_config_lintsrc *m) |
1da177e4 LT |
145 | { |
146 | Dprintk("Lint: type %d, pol %d, trig %d, bus %d," | |
147 | " IRQ %02x, APIC ID %x, APIC LINT %02x\n", | |
d2953315 AS |
148 | m->mpc_irqtype, m->mpc_irqflag & 3, |
149 | (m->mpc_irqflag >> 2) & 3, m->mpc_srcbusid, | |
150 | m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint); | |
1da177e4 LT |
151 | } |
152 | ||
153 | /* | |
154 | * Read/parse the MPC | |
155 | */ | |
8643f9d0 | 156 | static int __init smp_read_mpc(struct mp_config_table *mpc, unsigned early) |
1da177e4 LT |
157 | { |
158 | char str[16]; | |
d2953315 AS |
159 | int count = sizeof(*mpc); |
160 | unsigned char *mpt = ((unsigned char *)mpc) + count; | |
161 | ||
162 | if (memcmp(mpc->mpc_signature, MPC_SIGNATURE, 4)) { | |
163 | printk(KERN_ERR "MPTABLE: bad signature [%c%c%c%c]!\n", | |
164 | mpc->mpc_signature[0], | |
165 | mpc->mpc_signature[1], | |
166 | mpc->mpc_signature[2], mpc->mpc_signature[3]); | |
1da177e4 LT |
167 | return 0; |
168 | } | |
d2953315 AS |
169 | if (mpf_checksum((unsigned char *)mpc, mpc->mpc_length)) { |
170 | printk(KERN_ERR "MPTABLE: checksum error!\n"); | |
1da177e4 LT |
171 | return 0; |
172 | } | |
d2953315 | 173 | if (mpc->mpc_spec != 0x01 && mpc->mpc_spec != 0x04) { |
aecc6361 | 174 | printk(KERN_ERR "MPTABLE: bad table version (%d)!!\n", |
d2953315 | 175 | mpc->mpc_spec); |
1da177e4 LT |
176 | return 0; |
177 | } | |
178 | if (!mpc->mpc_lapic) { | |
aecc6361 | 179 | printk(KERN_ERR "MPTABLE: null local APIC address!\n"); |
1da177e4 LT |
180 | return 0; |
181 | } | |
d2953315 | 182 | memcpy(str, mpc->mpc_oem, 8); |
aecc6361 | 183 | str[8] = 0; |
d2953315 | 184 | printk(KERN_INFO "MPTABLE: OEM ID: %s ", str); |
1da177e4 | 185 | |
d2953315 | 186 | memcpy(str, mpc->mpc_productid, 12); |
aecc6361 | 187 | str[12] = 0; |
d2953315 | 188 | printk(KERN_INFO "MPTABLE: Product ID: %s ", str); |
1da177e4 | 189 | |
d2953315 | 190 | printk(KERN_INFO "MPTABLE: APIC at: 0x%X\n", mpc->mpc_lapic); |
1da177e4 LT |
191 | |
192 | /* save the local APIC address, it might be non-default */ | |
193 | if (!acpi_lapic) | |
aecc6361 | 194 | mp_lapic_addr = mpc->mpc_lapic; |
1da177e4 | 195 | |
8643f9d0 YL |
196 | if (early) |
197 | return 1; | |
198 | ||
1da177e4 | 199 | /* |
d2953315 | 200 | * Now process the configuration blocks. |
1da177e4 LT |
201 | */ |
202 | while (count < mpc->mpc_length) { | |
d2953315 AS |
203 | switch (*mpt) { |
204 | case MP_PROCESSOR: | |
1da177e4 | 205 | { |
d2953315 AS |
206 | struct mpc_config_processor *m = |
207 | (struct mpc_config_processor *)mpt; | |
1da177e4 | 208 | if (!acpi_lapic) |
aecc6361 | 209 | MP_processor_info(m); |
1da177e4 LT |
210 | mpt += sizeof(*m); |
211 | count += sizeof(*m); | |
212 | break; | |
213 | } | |
d2953315 | 214 | case MP_BUS: |
1da177e4 | 215 | { |
d2953315 AS |
216 | struct mpc_config_bus *m = |
217 | (struct mpc_config_bus *)mpt; | |
1da177e4 LT |
218 | MP_bus_info(m); |
219 | mpt += sizeof(*m); | |
220 | count += sizeof(*m); | |
221 | break; | |
222 | } | |
d2953315 | 223 | case MP_IOAPIC: |
1da177e4 | 224 | { |
d2953315 AS |
225 | struct mpc_config_ioapic *m = |
226 | (struct mpc_config_ioapic *)mpt; | |
1da177e4 | 227 | MP_ioapic_info(m); |
aecc6361 AK |
228 | mpt += sizeof(*m); |
229 | count += sizeof(*m); | |
1da177e4 LT |
230 | break; |
231 | } | |
d2953315 | 232 | case MP_INTSRC: |
1da177e4 | 233 | { |
d2953315 AS |
234 | struct mpc_config_intsrc *m = |
235 | (struct mpc_config_intsrc *)mpt; | |
1da177e4 LT |
236 | |
237 | MP_intsrc_info(m); | |
aecc6361 AK |
238 | mpt += sizeof(*m); |
239 | count += sizeof(*m); | |
1da177e4 LT |
240 | break; |
241 | } | |
d2953315 | 242 | case MP_LINTSRC: |
1da177e4 | 243 | { |
d2953315 AS |
244 | struct mpc_config_lintsrc *m = |
245 | (struct mpc_config_lintsrc *)mpt; | |
1da177e4 | 246 | MP_lintsrc_info(m); |
aecc6361 AK |
247 | mpt += sizeof(*m); |
248 | count += sizeof(*m); | |
1da177e4 LT |
249 | break; |
250 | } | |
251 | } | |
252 | } | |
3c43f039 | 253 | setup_apic_routing(); |
1da177e4 | 254 | if (!num_processors) |
aecc6361 | 255 | printk(KERN_ERR "MPTABLE: no processors registered!\n"); |
1da177e4 LT |
256 | return num_processors; |
257 | } | |
258 | ||
259 | static int __init ELCR_trigger(unsigned int irq) | |
260 | { | |
261 | unsigned int port; | |
262 | ||
263 | port = 0x4d0 + (irq >> 3); | |
264 | return (inb(port) >> (irq & 7)) & 1; | |
265 | } | |
266 | ||
267 | static void __init construct_default_ioirq_mptable(int mpc_default_type) | |
268 | { | |
269 | struct mpc_config_intsrc intsrc; | |
270 | int i; | |
271 | int ELCR_fallback = 0; | |
272 | ||
273 | intsrc.mpc_type = MP_INTSRC; | |
d2953315 | 274 | intsrc.mpc_irqflag = 0; /* conforming */ |
1da177e4 LT |
275 | intsrc.mpc_srcbus = 0; |
276 | intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid; | |
277 | ||
278 | intsrc.mpc_irqtype = mp_INT; | |
279 | ||
280 | /* | |
281 | * If true, we have an ISA/PCI system with no IRQ entries | |
282 | * in the MP table. To prevent the PCI interrupts from being set up | |
283 | * incorrectly, we try to use the ELCR. The sanity check to see if | |
284 | * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can | |
285 | * never be level sensitive, so we simply see if the ELCR agrees. | |
286 | * If it does, we assume it's valid. | |
287 | */ | |
288 | if (mpc_default_type == 5) { | |
d2953315 AS |
289 | printk(KERN_INFO "ISA/PCI bus type with no IRQ information... " |
290 | "falling back to ELCR\n"); | |
1da177e4 | 291 | |
d2953315 AS |
292 | if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || |
293 | ELCR_trigger(13)) | |
294 | printk(KERN_ERR "ELCR contains invalid data... " | |
295 | "not using ELCR\n"); | |
1da177e4 | 296 | else { |
d2953315 AS |
297 | printk(KERN_INFO |
298 | "Using ELCR to identify PCI interrupts\n"); | |
1da177e4 LT |
299 | ELCR_fallback = 1; |
300 | } | |
301 | } | |
302 | ||
303 | for (i = 0; i < 16; i++) { | |
304 | switch (mpc_default_type) { | |
305 | case 2: | |
306 | if (i == 0 || i == 13) | |
307 | continue; /* IRQ0 & IRQ13 not connected */ | |
308 | /* fall through */ | |
309 | default: | |
310 | if (i == 2) | |
311 | continue; /* IRQ2 is never connected */ | |
312 | } | |
313 | ||
314 | if (ELCR_fallback) { | |
315 | /* | |
316 | * If the ELCR indicates a level-sensitive interrupt, we | |
317 | * copy that information over to the MP table in the | |
318 | * irqflag field (level sensitive, active high polarity). | |
319 | */ | |
320 | if (ELCR_trigger(i)) | |
321 | intsrc.mpc_irqflag = 13; | |
322 | else | |
323 | intsrc.mpc_irqflag = 0; | |
324 | } | |
325 | ||
326 | intsrc.mpc_srcbusirq = i; | |
d2953315 | 327 | intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */ |
1da177e4 LT |
328 | MP_intsrc_info(&intsrc); |
329 | } | |
330 | ||
331 | intsrc.mpc_irqtype = mp_ExtINT; | |
332 | intsrc.mpc_srcbusirq = 0; | |
d2953315 | 333 | intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */ |
1da177e4 LT |
334 | MP_intsrc_info(&intsrc); |
335 | } | |
336 | ||
337 | static inline void __init construct_default_ISA_mptable(int mpc_default_type) | |
338 | { | |
339 | struct mpc_config_processor processor; | |
340 | struct mpc_config_bus bus; | |
341 | struct mpc_config_ioapic ioapic; | |
342 | struct mpc_config_lintsrc lintsrc; | |
343 | int linttypes[2] = { mp_ExtINT, mp_NMI }; | |
344 | int i; | |
345 | ||
346 | /* | |
347 | * local APIC has default address | |
348 | */ | |
349 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
350 | ||
351 | /* | |
352 | * 2 CPUs, numbered 0 & 1. | |
353 | */ | |
354 | processor.mpc_type = MP_PROCESSOR; | |
f2c2cca3 | 355 | processor.mpc_apicver = 0; |
1da177e4 | 356 | processor.mpc_cpuflag = CPU_ENABLED; |
f2c2cca3 AK |
357 | processor.mpc_cpufeature = 0; |
358 | processor.mpc_featureflag = 0; | |
1da177e4 LT |
359 | processor.mpc_reserved[0] = 0; |
360 | processor.mpc_reserved[1] = 0; | |
361 | for (i = 0; i < 2; i++) { | |
362 | processor.mpc_apicid = i; | |
363 | MP_processor_info(&processor); | |
364 | } | |
365 | ||
366 | bus.mpc_type = MP_BUS; | |
367 | bus.mpc_busid = 0; | |
368 | switch (mpc_default_type) { | |
d2953315 AS |
369 | default: |
370 | printk(KERN_ERR "???\nUnknown standard configuration %d\n", | |
371 | mpc_default_type); | |
372 | /* fall through */ | |
373 | case 1: | |
374 | case 5: | |
375 | memcpy(bus.mpc_bustype, "ISA ", 6); | |
376 | break; | |
1da177e4 LT |
377 | } |
378 | MP_bus_info(&bus); | |
379 | if (mpc_default_type > 4) { | |
380 | bus.mpc_busid = 1; | |
381 | memcpy(bus.mpc_bustype, "PCI ", 6); | |
382 | MP_bus_info(&bus); | |
383 | } | |
384 | ||
385 | ioapic.mpc_type = MP_IOAPIC; | |
386 | ioapic.mpc_apicid = 2; | |
f2c2cca3 | 387 | ioapic.mpc_apicver = 0; |
1da177e4 LT |
388 | ioapic.mpc_flags = MPC_APIC_USABLE; |
389 | ioapic.mpc_apicaddr = 0xFEC00000; | |
390 | MP_ioapic_info(&ioapic); | |
391 | ||
392 | /* | |
393 | * We set up most of the low 16 IO-APIC pins according to MPS rules. | |
394 | */ | |
395 | construct_default_ioirq_mptable(mpc_default_type); | |
396 | ||
397 | lintsrc.mpc_type = MP_LINTSRC; | |
d2953315 | 398 | lintsrc.mpc_irqflag = 0; /* conforming */ |
1da177e4 LT |
399 | lintsrc.mpc_srcbusid = 0; |
400 | lintsrc.mpc_srcbusirq = 0; | |
401 | lintsrc.mpc_destapic = MP_APIC_ALL; | |
402 | for (i = 0; i < 2; i++) { | |
403 | lintsrc.mpc_irqtype = linttypes[i]; | |
404 | lintsrc.mpc_destapiclint = i; | |
405 | MP_lintsrc_info(&lintsrc); | |
406 | } | |
407 | } | |
408 | ||
409 | static struct intel_mp_floating *mpf_found; | |
410 | ||
411 | /* | |
412 | * Scan the memory blocks for an SMP configuration block. | |
413 | */ | |
8643f9d0 | 414 | static void __init __get_smp_config(unsigned early) |
1da177e4 LT |
415 | { |
416 | struct intel_mp_floating *mpf = mpf_found; | |
417 | ||
8643f9d0 YL |
418 | if (acpi_lapic && early) |
419 | return; | |
1da177e4 | 420 | /* |
8643f9d0 YL |
421 | * ACPI supports both logical (e.g. Hyper-Threading) and physical |
422 | * processors, where MPS only supports physical. | |
423 | */ | |
424 | if (acpi_lapic && acpi_ioapic) { | |
425 | printk(KERN_INFO "Using ACPI (MADT) for SMP configuration " | |
d2953315 | 426 | "information\n"); |
8643f9d0 YL |
427 | return; |
428 | } else if (acpi_lapic) | |
429 | printk(KERN_INFO "Using ACPI for processor (LAPIC) " | |
d2953315 | 430 | "configuration information\n"); |
1da177e4 | 431 | |
8643f9d0 | 432 | printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n", |
d2953315 | 433 | mpf->mpf_specification); |
1da177e4 LT |
434 | |
435 | /* | |
436 | * Now see if we need to read further. | |
437 | */ | |
438 | if (mpf->mpf_feature1 != 0) { | |
8643f9d0 YL |
439 | if (early) { |
440 | /* | |
441 | * local APIC has default address | |
442 | */ | |
443 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
444 | return; | |
445 | } | |
1da177e4 | 446 | |
d2953315 AS |
447 | printk(KERN_INFO "Default MP configuration #%d\n", |
448 | mpf->mpf_feature1); | |
1da177e4 LT |
449 | construct_default_ISA_mptable(mpf->mpf_feature1); |
450 | ||
451 | } else if (mpf->mpf_physptr) { | |
452 | ||
453 | /* | |
454 | * Read the physical hardware table. Anything here will | |
455 | * override the defaults. | |
456 | */ | |
8643f9d0 | 457 | if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr), early)) { |
1da177e4 | 458 | smp_found_config = 0; |
d2953315 AS |
459 | printk(KERN_ERR |
460 | "BIOS bug, MP table errors detected!...\n"); | |
461 | printk(KERN_ERR "... disabling SMP support. " | |
462 | "(tell your hw vendor)\n"); | |
1da177e4 LT |
463 | return; |
464 | } | |
8643f9d0 YL |
465 | |
466 | if (early) | |
467 | return; | |
1da177e4 LT |
468 | /* |
469 | * If there are no explicit MP IRQ entries, then we are | |
470 | * broken. We set up most of the low 16 IO-APIC pins to | |
471 | * ISA defaults and hope it will work. | |
472 | */ | |
473 | if (!mp_irq_entries) { | |
474 | struct mpc_config_bus bus; | |
475 | ||
d2953315 AS |
476 | printk(KERN_ERR "BIOS bug, no explicit IRQ entries, " |
477 | "using default mptable. " | |
478 | "(tell your hw vendor)\n"); | |
1da177e4 LT |
479 | |
480 | bus.mpc_type = MP_BUS; | |
481 | bus.mpc_busid = 0; | |
482 | memcpy(bus.mpc_bustype, "ISA ", 6); | |
483 | MP_bus_info(&bus); | |
484 | ||
485 | construct_default_ioirq_mptable(0); | |
486 | } | |
487 | ||
488 | } else | |
489 | BUG(); | |
490 | ||
8643f9d0 YL |
491 | if (!early) |
492 | printk(KERN_INFO "Processors: %d\n", num_processors); | |
1da177e4 LT |
493 | /* |
494 | * Only use the first configuration found. | |
495 | */ | |
496 | } | |
497 | ||
8643f9d0 YL |
498 | void __init early_get_smp_config(void) |
499 | { | |
500 | __get_smp_config(1); | |
501 | } | |
502 | ||
503 | void __init get_smp_config(void) | |
504 | { | |
505 | __get_smp_config(0); | |
506 | } | |
507 | ||
508 | static int __init smp_scan_config(unsigned long base, unsigned long length, | |
509 | unsigned reserve) | |
1da177e4 | 510 | { |
d2953315 | 511 | extern void __bad_mpf_size(void); |
1da177e4 LT |
512 | unsigned int *bp = phys_to_virt(base); |
513 | struct intel_mp_floating *mpf; | |
514 | ||
d2953315 | 515 | Dprintk("Scan SMP from %p for %ld bytes.\n", bp, length); |
1da177e4 LT |
516 | if (sizeof(*mpf) != 16) |
517 | __bad_mpf_size(); | |
518 | ||
519 | while (length > 0) { | |
520 | mpf = (struct intel_mp_floating *)bp; | |
521 | if ((*bp == SMP_MAGIC_IDENT) && | |
d2953315 AS |
522 | (mpf->mpf_length == 1) && |
523 | !mpf_checksum((unsigned char *)bp, 16) && | |
524 | ((mpf->mpf_specification == 1) | |
525 | || (mpf->mpf_specification == 4))) { | |
1da177e4 LT |
526 | |
527 | smp_found_config = 1; | |
8643f9d0 YL |
528 | mpf_found = mpf; |
529 | ||
530 | if (!reserve) | |
531 | return 1; | |
532 | ||
1da177e4 LT |
533 | reserve_bootmem_generic(virt_to_phys(mpf), PAGE_SIZE); |
534 | if (mpf->mpf_physptr) | |
8643f9d0 YL |
535 | reserve_bootmem_generic(mpf->mpf_physptr, |
536 | PAGE_SIZE); | |
1da177e4 LT |
537 | return 1; |
538 | } | |
539 | bp += 4; | |
540 | length -= 16; | |
541 | } | |
542 | return 0; | |
543 | } | |
544 | ||
8643f9d0 | 545 | static void __init __find_smp_config(unsigned reserve) |
1da177e4 LT |
546 | { |
547 | unsigned int address; | |
548 | ||
549 | /* | |
550 | * FIXME: Linux assumes you have 640K of base ram.. | |
551 | * this continues the error... | |
552 | * | |
553 | * 1) Scan the bottom 1K for a signature | |
554 | * 2) Scan the top 1K of base RAM | |
555 | * 3) Scan the 64K of bios | |
556 | */ | |
8643f9d0 | 557 | if (smp_scan_config(0x0, 0x400, reserve) || |
d2953315 AS |
558 | smp_scan_config(639 * 0x400, 0x400, reserve) || |
559 | smp_scan_config(0xF0000, 0x10000, reserve)) | |
1da177e4 LT |
560 | return; |
561 | /* | |
e5099134 | 562 | * If it is an SMP machine we should know now. |
1da177e4 LT |
563 | * |
564 | * there is a real-mode segmented pointer pointing to the | |
565 | * 4K EBDA area at 0x40E, calculate and scan it here. | |
566 | * | |
567 | * NOTE! There are Linux loaders that will corrupt the EBDA | |
568 | * area, and as such this kind of SMP config may be less | |
569 | * trustworthy, simply because the SMP table may have been | |
570 | * stomped on during early boot. These loaders are buggy and | |
571 | * should be fixed. | |
85e46035 AS |
572 | * |
573 | * MP1.4 SPEC states to only scan first 1K of 4K EBDA. | |
1da177e4 LT |
574 | */ |
575 | ||
ce3fe6b2 AS |
576 | address = get_bios_ebda(); |
577 | if (address) | |
85e46035 | 578 | smp_scan_config(address, 0x400, reserve); |
1da177e4 LT |
579 | } |
580 | ||
8643f9d0 YL |
581 | void __init early_find_smp_config(void) |
582 | { | |
583 | __find_smp_config(0); | |
584 | } | |
585 | ||
586 | void __init find_smp_config(void) | |
587 | { | |
588 | __find_smp_config(1); | |
589 | } | |
590 | ||
1da177e4 LT |
591 | /* -------------------------------------------------------------------------- |
592 | ACPI-based MP Configuration | |
593 | -------------------------------------------------------------------------- */ | |
594 | ||
888ba6c6 | 595 | #ifdef CONFIG_ACPI |
1da177e4 | 596 | |
1da177e4 LT |
597 | #define MP_ISA_BUS 0 |
598 | #define MP_MAX_IOAPIC_PIN 127 | |
599 | ||
9e5c5f1d | 600 | extern struct mp_ioapic_routing mp_ioapic_routing[MAX_IO_APICS]; |
1da177e4 | 601 | |
efec3b9a | 602 | static int mp_find_ioapic(int gsi) |
1da177e4 | 603 | { |
efec3b9a | 604 | int i = 0; |
1da177e4 LT |
605 | |
606 | /* Find the IOAPIC that manages this GSI. */ | |
607 | for (i = 0; i < nr_ioapics; i++) { | |
555b0764 | 608 | if ((gsi >= mp_ioapic_routing[i].gsi_base) |
d2953315 | 609 | && (gsi <= mp_ioapic_routing[i].gsi_end)) |
1da177e4 LT |
610 | return i; |
611 | } | |
612 | ||
613 | printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); | |
1da177e4 LT |
614 | return -1; |
615 | } | |
1da177e4 | 616 | |
78b599ae AK |
617 | static u8 uniq_ioapic_id(u8 id) |
618 | { | |
619 | int i; | |
620 | DECLARE_BITMAP(used, 256); | |
621 | bitmap_zero(used, 256); | |
622 | for (i = 0; i < nr_ioapics; i++) { | |
623 | struct mpc_config_ioapic *ia = &mp_ioapics[i]; | |
624 | __set_bit(ia->mpc_apicid, used); | |
625 | } | |
626 | if (!test_bit(id, used)) | |
627 | return id; | |
628 | return find_first_zero_bit(used, 256); | |
629 | } | |
630 | ||
a65d1d64 | 631 | void __init mp_register_ioapic(int id, u32 address, u32 gsi_base) |
1da177e4 | 632 | { |
efec3b9a | 633 | int idx = 0; |
1da177e4 | 634 | |
013bf2c5 | 635 | if (bad_ioapic(address)) |
1da177e4 | 636 | return; |
1da177e4 | 637 | |
78b599ae | 638 | idx = nr_ioapics; |
1da177e4 LT |
639 | |
640 | mp_ioapics[idx].mpc_type = MP_IOAPIC; | |
641 | mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE; | |
642 | mp_ioapics[idx].mpc_apicaddr = address; | |
643 | ||
644 | set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); | |
78b599ae | 645 | mp_ioapics[idx].mpc_apicid = uniq_ioapic_id(id); |
f2c2cca3 | 646 | mp_ioapics[idx].mpc_apicver = 0; |
d2953315 | 647 | |
1da177e4 LT |
648 | /* |
649 | * Build basic IRQ lookup table to facilitate gsi->io_apic lookups | |
650 | * and to prevent reprogramming of IOAPIC pins (PCI IRQs). | |
651 | */ | |
652 | mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid; | |
555b0764 | 653 | mp_ioapic_routing[idx].gsi_base = gsi_base; |
d2953315 AS |
654 | mp_ioapic_routing[idx].gsi_end = gsi_base + |
655 | io_apic_get_redir_entries(idx); | |
1da177e4 | 656 | |
f2c2cca3 | 657 | printk(KERN_INFO "IOAPIC[%d]: apic_id %d, address 0x%x, " |
d2953315 AS |
658 | "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid, |
659 | mp_ioapics[idx].mpc_apicaddr, | |
555b0764 | 660 | mp_ioapic_routing[idx].gsi_base, |
d2953315 | 661 | mp_ioapic_routing[idx].gsi_end); |
78b599ae AK |
662 | |
663 | nr_ioapics++; | |
1da177e4 LT |
664 | } |
665 | ||
d2953315 | 666 | void __init mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi) |
1da177e4 LT |
667 | { |
668 | struct mpc_config_intsrc intsrc; | |
d2953315 AS |
669 | int ioapic = -1; |
670 | int pin = -1; | |
1da177e4 LT |
671 | |
672 | /* | |
673 | * Convert 'gsi' to 'ioapic.pin'. | |
674 | */ | |
675 | ioapic = mp_find_ioapic(gsi); | |
676 | if (ioapic < 0) | |
677 | return; | |
555b0764 | 678 | pin = gsi - mp_ioapic_routing[ioapic].gsi_base; |
1da177e4 LT |
679 | |
680 | /* | |
681 | * TBD: This check is for faulty timer entries, where the override | |
682 | * erroneously sets the trigger to level, resulting in a HUGE | |
683 | * increase of timer interrupts! | |
684 | */ | |
685 | if ((bus_irq == 0) && (trigger == 3)) | |
686 | trigger = 1; | |
687 | ||
688 | intsrc.mpc_type = MP_INTSRC; | |
689 | intsrc.mpc_irqtype = mp_INT; | |
690 | intsrc.mpc_irqflag = (trigger << 2) | polarity; | |
691 | intsrc.mpc_srcbus = MP_ISA_BUS; | |
d2953315 AS |
692 | intsrc.mpc_srcbusirq = bus_irq; /* IRQ */ |
693 | intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */ | |
694 | intsrc.mpc_dstirq = pin; /* INTIN# */ | |
1da177e4 | 695 | |
d2953315 AS |
696 | Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n", |
697 | intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3, | |
698 | (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus, | |
1da177e4 LT |
699 | intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq); |
700 | ||
701 | mp_irqs[mp_irq_entries] = intsrc; | |
702 | if (++mp_irq_entries == MAX_IRQ_SOURCES) | |
703 | panic("Max # of irq sources exceeded!\n"); | |
1da177e4 LT |
704 | } |
705 | ||
efec3b9a | 706 | void __init mp_config_acpi_legacy_irqs(void) |
1da177e4 LT |
707 | { |
708 | struct mpc_config_intsrc intsrc; | |
efec3b9a AK |
709 | int i = 0; |
710 | int ioapic = -1; | |
1da177e4 LT |
711 | |
712 | /* | |
713 | * Fabricate the legacy ISA bus (bus #31). | |
714 | */ | |
55f05ffa | 715 | set_bit(MP_ISA_BUS, mp_bus_not_pci); |
1da177e4 LT |
716 | |
717 | /* | |
718 | * Locate the IOAPIC that manages the ISA IRQs (0-15). | |
719 | */ | |
720 | ioapic = mp_find_ioapic(0); | |
721 | if (ioapic < 0) | |
722 | return; | |
723 | ||
724 | intsrc.mpc_type = MP_INTSRC; | |
d2953315 | 725 | intsrc.mpc_irqflag = 0; /* Conforming */ |
1da177e4 LT |
726 | intsrc.mpc_srcbus = MP_ISA_BUS; |
727 | intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; | |
728 | ||
729 | /* | |
730 | * Use the default configuration for the IRQs 0-15. Unless | |
731 | * overridden by (MADT) interrupt source override entries. | |
732 | */ | |
733 | for (i = 0; i < 16; i++) { | |
734 | int idx; | |
735 | ||
736 | for (idx = 0; idx < mp_irq_entries; idx++) { | |
737 | struct mpc_config_intsrc *irq = mp_irqs + idx; | |
738 | ||
739 | /* Do we already have a mapping for this ISA IRQ? */ | |
d2953315 AS |
740 | if (irq->mpc_srcbus == MP_ISA_BUS |
741 | && irq->mpc_srcbusirq == i) | |
1da177e4 LT |
742 | break; |
743 | ||
744 | /* Do we already have a mapping for this IOAPIC pin */ | |
745 | if ((irq->mpc_dstapic == intsrc.mpc_dstapic) && | |
d2953315 | 746 | (irq->mpc_dstirq == i)) |
1da177e4 LT |
747 | break; |
748 | } | |
749 | ||
750 | if (idx != mp_irq_entries) { | |
751 | printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i); | |
d2953315 | 752 | continue; /* IRQ already used */ |
1da177e4 LT |
753 | } |
754 | ||
755 | intsrc.mpc_irqtype = mp_INT; | |
d2953315 | 756 | intsrc.mpc_srcbusirq = i; /* Identity mapped */ |
1da177e4 LT |
757 | intsrc.mpc_dstirq = i; |
758 | ||
759 | Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, " | |
d2953315 AS |
760 | "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3, |
761 | (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus, | |
762 | intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, | |
1da177e4 LT |
763 | intsrc.mpc_dstirq); |
764 | ||
765 | mp_irqs[mp_irq_entries] = intsrc; | |
766 | if (++mp_irq_entries == MAX_IRQ_SOURCES) | |
767 | panic("Max # of irq sources exceeded!\n"); | |
768 | } | |
1da177e4 LT |
769 | } |
770 | ||
50eca3eb | 771 | int mp_register_gsi(u32 gsi, int triggering, int polarity) |
1da177e4 | 772 | { |
efec3b9a AK |
773 | int ioapic = -1; |
774 | int ioapic_pin = 0; | |
775 | int idx, bit = 0; | |
1da177e4 LT |
776 | |
777 | if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC) | |
778 | return gsi; | |
779 | ||
1da177e4 | 780 | /* Don't set up the ACPI SCI because it's already set up */ |
cee324b1 | 781 | if (acpi_gbl_FADT.sci_interrupt == gsi) |
1da177e4 | 782 | return gsi; |
1da177e4 LT |
783 | |
784 | ioapic = mp_find_ioapic(gsi); | |
785 | if (ioapic < 0) { | |
786 | printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi); | |
787 | return gsi; | |
788 | } | |
789 | ||
555b0764 | 790 | ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base; |
1da177e4 LT |
791 | |
792 | /* | |
793 | * Avoid pin reprogramming. PRTs typically include entries | |
794 | * with redundant pin->gsi mappings (but unique PCI devices); | |
795 | * we only program the IOAPIC on the first. | |
796 | */ | |
797 | bit = ioapic_pin % 32; | |
798 | idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32); | |
799 | if (idx > 3) { | |
800 | printk(KERN_ERR "Invalid reference to IOAPIC pin " | |
d2953315 AS |
801 | "%d-%d\n", mp_ioapic_routing[ioapic].apic_id, |
802 | ioapic_pin); | |
1da177e4 LT |
803 | return gsi; |
804 | } | |
d2953315 | 805 | if ((1 << bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) { |
1da177e4 LT |
806 | Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n", |
807 | mp_ioapic_routing[ioapic].apic_id, ioapic_pin); | |
cd1182f5 | 808 | return gsi; |
1da177e4 LT |
809 | } |
810 | ||
d2953315 | 811 | mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1 << bit); |
1da177e4 LT |
812 | |
813 | io_apic_set_pci_routing(ioapic, ioapic_pin, gsi, | |
d2953315 AS |
814 | triggering == ACPI_EDGE_SENSITIVE ? 0 : 1, |
815 | polarity == ACPI_ACTIVE_HIGH ? 0 : 1); | |
1da177e4 LT |
816 | return gsi; |
817 | } | |
d2953315 | 818 | #endif /* CONFIG_ACPI */ |