Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Intel Multiprocessor Specification 1.1 and 1.4 | |
3 | * compliant MP-table parsing routines. | |
4 | * | |
5 | * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> | |
6 | * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
7 | * | |
8 | * Fixes | |
9 | * Erich Boleyn : MP v1.4 and additional changes. | |
10 | * Alan Cox : Added EBDA scanning | |
11 | * Ingo Molnar : various cleanups and rewrites | |
12 | * Maciej W. Rozycki: Bits for default MP configurations | |
13 | * Paul Diefenbaugh: Added full ACPI support | |
14 | */ | |
15 | ||
16 | #include <linux/mm.h> | |
1da177e4 LT |
17 | #include <linux/init.h> |
18 | #include <linux/delay.h> | |
1da177e4 | 19 | #include <linux/bootmem.h> |
1da177e4 LT |
20 | #include <linux/kernel_stat.h> |
21 | #include <linux/mc146818rtc.h> | |
22 | #include <linux/acpi.h> | |
8c5a0908 | 23 | #include <linux/module.h> |
1da177e4 LT |
24 | |
25 | #include <asm/smp.h> | |
26 | #include <asm/mtrr.h> | |
27 | #include <asm/mpspec.h> | |
28 | #include <asm/pgalloc.h> | |
29 | #include <asm/io_apic.h> | |
30 | #include <asm/proto.h> | |
8d916406 | 31 | #include <asm/acpi.h> |
ce3fe6b2 | 32 | #include <asm/bios_ebda.h> |
1da177e4 | 33 | |
f6bc4029 GOC |
34 | #include <mach_apic.h> |
35 | ||
1da177e4 LT |
36 | /* Have we found an MP table */ |
37 | int smp_found_config; | |
1da177e4 | 38 | |
1da177e4 LT |
39 | /* |
40 | * Various Linux-internal data structures created from the | |
41 | * MP-table. | |
42 | */ | |
55f05ffa | 43 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); |
d2953315 | 44 | int mp_bus_id_to_pci_bus[MAX_MP_BUSSES] = {[0 ... MAX_MP_BUSSES - 1] = -1 }; |
1da177e4 LT |
45 | |
46 | static int mp_current_pci_id = 0; | |
1da177e4 | 47 | |
e937fcf2 IM |
48 | /* Make it easy to share the UP and SMP code: */ |
49 | #ifndef CONFIG_X86_SMP | |
50 | unsigned int num_processors; | |
51 | unsigned disabled_cpus __cpuinitdata; | |
52 | #ifndef CONFIG_X86_LOCAL_APIC | |
53 | unsigned int boot_cpu_physical_apicid = -1U; | |
54 | #endif | |
55 | #endif | |
56 | ||
1da177e4 LT |
57 | /* |
58 | * Intel MP BIOS table parsing routines: | |
59 | */ | |
60 | ||
61 | /* | |
62 | * Checksum an MP configuration block. | |
63 | */ | |
64 | ||
65 | static int __init mpf_checksum(unsigned char *mp, int len) | |
66 | { | |
67 | int sum = 0; | |
68 | ||
69 | while (len--) | |
70 | sum += *mp++; | |
71 | ||
72 | return sum & 0xFF; | |
73 | } | |
74 | ||
0e01c00c AS |
75 | static void __cpuinit MP_processor_info(struct mpc_config_processor *m) |
76 | { | |
77 | char *bootup_cpu = ""; | |
78 | ||
79 | if (!(m->mpc_cpuflag & CPU_ENABLED)) { | |
80 | disabled_cpus++; | |
81 | return; | |
82 | } | |
83 | if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) { | |
84 | bootup_cpu = " (Bootup-CPU)"; | |
85 | boot_cpu_physical_apicid = m->mpc_apicid; | |
86 | } | |
87 | ||
88 | printk(KERN_INFO "Processor #%d%s\n", m->mpc_apicid, bootup_cpu); | |
89 | generic_processor_info(m->mpc_apicid, 0); | |
90 | } | |
91 | ||
d2953315 | 92 | static void __init MP_bus_info(struct mpc_config_bus *m) |
1da177e4 LT |
93 | { |
94 | char str[7]; | |
95 | ||
96 | memcpy(str, m->mpc_bustype, 6); | |
97 | str[6] = 0; | |
98 | Dprintk("Bus #%d is %s\n", m->mpc_busid, str); | |
99 | ||
100 | if (strncmp(str, "ISA", 3) == 0) { | |
55f05ffa | 101 | set_bit(m->mpc_busid, mp_bus_not_pci); |
1da177e4 | 102 | } else if (strncmp(str, "PCI", 3) == 0) { |
55f05ffa | 103 | clear_bit(m->mpc_busid, mp_bus_not_pci); |
1da177e4 LT |
104 | mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id; |
105 | mp_current_pci_id++; | |
1da177e4 LT |
106 | } else { |
107 | printk(KERN_ERR "Unknown bustype %s\n", str); | |
108 | } | |
109 | } | |
110 | ||
013bf2c5 AK |
111 | static int bad_ioapic(unsigned long address) |
112 | { | |
113 | if (nr_ioapics >= MAX_IO_APICS) { | |
114 | printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded " | |
d2953315 | 115 | "(found %d)\n", MAX_IO_APICS, nr_ioapics); |
013bf2c5 AK |
116 | panic("Recompile kernel with bigger MAX_IO_APICS!\n"); |
117 | } | |
118 | if (!address) { | |
119 | printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address" | |
d2953315 | 120 | " found in table, skipping!\n"); |
013bf2c5 AK |
121 | return 1; |
122 | } | |
123 | return 0; | |
124 | } | |
125 | ||
d2953315 | 126 | static void __init MP_ioapic_info(struct mpc_config_ioapic *m) |
1da177e4 LT |
127 | { |
128 | if (!(m->mpc_flags & MPC_APIC_USABLE)) | |
129 | return; | |
130 | ||
d2953315 AS |
131 | printk(KERN_INFO "I/O APIC #%d at 0x%X.\n", m->mpc_apicid, |
132 | m->mpc_apicaddr); | |
013bf2c5 AK |
133 | |
134 | if (bad_ioapic(m->mpc_apicaddr)) | |
1da177e4 | 135 | return; |
013bf2c5 | 136 | |
1da177e4 LT |
137 | mp_ioapics[nr_ioapics] = *m; |
138 | nr_ioapics++; | |
139 | } | |
140 | ||
d2953315 | 141 | static void __init MP_intsrc_info(struct mpc_config_intsrc *m) |
1da177e4 | 142 | { |
d2953315 | 143 | mp_irqs[mp_irq_entries] = *m; |
1da177e4 LT |
144 | Dprintk("Int: type %d, pol %d, trig %d, bus %d," |
145 | " IRQ %02x, APIC ID %x, APIC INT %02x\n", | |
d2953315 AS |
146 | m->mpc_irqtype, m->mpc_irqflag & 3, |
147 | (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus, | |
148 | m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq); | |
6004e1b7 | 149 | if (++mp_irq_entries >= MAX_IRQ_SOURCES) |
1da177e4 LT |
150 | panic("Max # of irq sources exceeded!!\n"); |
151 | } | |
152 | ||
d2953315 | 153 | static void __init MP_lintsrc_info(struct mpc_config_lintsrc *m) |
1da177e4 LT |
154 | { |
155 | Dprintk("Lint: type %d, pol %d, trig %d, bus %d," | |
156 | " IRQ %02x, APIC ID %x, APIC LINT %02x\n", | |
d2953315 AS |
157 | m->mpc_irqtype, m->mpc_irqflag & 3, |
158 | (m->mpc_irqflag >> 2) & 3, m->mpc_srcbusid, | |
159 | m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint); | |
1da177e4 LT |
160 | } |
161 | ||
162 | /* | |
163 | * Read/parse the MPC | |
164 | */ | |
8643f9d0 | 165 | static int __init smp_read_mpc(struct mp_config_table *mpc, unsigned early) |
1da177e4 LT |
166 | { |
167 | char str[16]; | |
d2953315 AS |
168 | int count = sizeof(*mpc); |
169 | unsigned char *mpt = ((unsigned char *)mpc) + count; | |
170 | ||
171 | if (memcmp(mpc->mpc_signature, MPC_SIGNATURE, 4)) { | |
172 | printk(KERN_ERR "MPTABLE: bad signature [%c%c%c%c]!\n", | |
173 | mpc->mpc_signature[0], | |
174 | mpc->mpc_signature[1], | |
175 | mpc->mpc_signature[2], mpc->mpc_signature[3]); | |
1da177e4 LT |
176 | return 0; |
177 | } | |
d2953315 AS |
178 | if (mpf_checksum((unsigned char *)mpc, mpc->mpc_length)) { |
179 | printk(KERN_ERR "MPTABLE: checksum error!\n"); | |
1da177e4 LT |
180 | return 0; |
181 | } | |
d2953315 | 182 | if (mpc->mpc_spec != 0x01 && mpc->mpc_spec != 0x04) { |
aecc6361 | 183 | printk(KERN_ERR "MPTABLE: bad table version (%d)!!\n", |
d2953315 | 184 | mpc->mpc_spec); |
1da177e4 LT |
185 | return 0; |
186 | } | |
187 | if (!mpc->mpc_lapic) { | |
aecc6361 | 188 | printk(KERN_ERR "MPTABLE: null local APIC address!\n"); |
1da177e4 LT |
189 | return 0; |
190 | } | |
d2953315 | 191 | memcpy(str, mpc->mpc_oem, 8); |
aecc6361 | 192 | str[8] = 0; |
d2953315 | 193 | printk(KERN_INFO "MPTABLE: OEM ID: %s ", str); |
1da177e4 | 194 | |
d2953315 | 195 | memcpy(str, mpc->mpc_productid, 12); |
aecc6361 | 196 | str[12] = 0; |
d2953315 | 197 | printk(KERN_INFO "MPTABLE: Product ID: %s ", str); |
1da177e4 | 198 | |
d2953315 | 199 | printk(KERN_INFO "MPTABLE: APIC at: 0x%X\n", mpc->mpc_lapic); |
1da177e4 LT |
200 | |
201 | /* save the local APIC address, it might be non-default */ | |
202 | if (!acpi_lapic) | |
aecc6361 | 203 | mp_lapic_addr = mpc->mpc_lapic; |
1da177e4 | 204 | |
8643f9d0 YL |
205 | if (early) |
206 | return 1; | |
207 | ||
1da177e4 | 208 | /* |
d2953315 | 209 | * Now process the configuration blocks. |
1da177e4 LT |
210 | */ |
211 | while (count < mpc->mpc_length) { | |
d2953315 AS |
212 | switch (*mpt) { |
213 | case MP_PROCESSOR: | |
1da177e4 | 214 | { |
d2953315 AS |
215 | struct mpc_config_processor *m = |
216 | (struct mpc_config_processor *)mpt; | |
1da177e4 | 217 | if (!acpi_lapic) |
aecc6361 | 218 | MP_processor_info(m); |
1da177e4 LT |
219 | mpt += sizeof(*m); |
220 | count += sizeof(*m); | |
221 | break; | |
222 | } | |
d2953315 | 223 | case MP_BUS: |
1da177e4 | 224 | { |
d2953315 AS |
225 | struct mpc_config_bus *m = |
226 | (struct mpc_config_bus *)mpt; | |
1da177e4 LT |
227 | MP_bus_info(m); |
228 | mpt += sizeof(*m); | |
229 | count += sizeof(*m); | |
230 | break; | |
231 | } | |
d2953315 | 232 | case MP_IOAPIC: |
1da177e4 | 233 | { |
d2953315 AS |
234 | struct mpc_config_ioapic *m = |
235 | (struct mpc_config_ioapic *)mpt; | |
1da177e4 | 236 | MP_ioapic_info(m); |
aecc6361 AK |
237 | mpt += sizeof(*m); |
238 | count += sizeof(*m); | |
1da177e4 LT |
239 | break; |
240 | } | |
d2953315 | 241 | case MP_INTSRC: |
1da177e4 | 242 | { |
d2953315 AS |
243 | struct mpc_config_intsrc *m = |
244 | (struct mpc_config_intsrc *)mpt; | |
1da177e4 LT |
245 | |
246 | MP_intsrc_info(m); | |
aecc6361 AK |
247 | mpt += sizeof(*m); |
248 | count += sizeof(*m); | |
1da177e4 LT |
249 | break; |
250 | } | |
d2953315 | 251 | case MP_LINTSRC: |
1da177e4 | 252 | { |
d2953315 AS |
253 | struct mpc_config_lintsrc *m = |
254 | (struct mpc_config_lintsrc *)mpt; | |
1da177e4 | 255 | MP_lintsrc_info(m); |
aecc6361 AK |
256 | mpt += sizeof(*m); |
257 | count += sizeof(*m); | |
1da177e4 LT |
258 | break; |
259 | } | |
260 | } | |
261 | } | |
3c43f039 | 262 | setup_apic_routing(); |
1da177e4 | 263 | if (!num_processors) |
aecc6361 | 264 | printk(KERN_ERR "MPTABLE: no processors registered!\n"); |
1da177e4 LT |
265 | return num_processors; |
266 | } | |
267 | ||
268 | static int __init ELCR_trigger(unsigned int irq) | |
269 | { | |
270 | unsigned int port; | |
271 | ||
272 | port = 0x4d0 + (irq >> 3); | |
273 | return (inb(port) >> (irq & 7)) & 1; | |
274 | } | |
275 | ||
276 | static void __init construct_default_ioirq_mptable(int mpc_default_type) | |
277 | { | |
278 | struct mpc_config_intsrc intsrc; | |
279 | int i; | |
280 | int ELCR_fallback = 0; | |
281 | ||
282 | intsrc.mpc_type = MP_INTSRC; | |
d2953315 | 283 | intsrc.mpc_irqflag = 0; /* conforming */ |
1da177e4 LT |
284 | intsrc.mpc_srcbus = 0; |
285 | intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid; | |
286 | ||
287 | intsrc.mpc_irqtype = mp_INT; | |
288 | ||
289 | /* | |
290 | * If true, we have an ISA/PCI system with no IRQ entries | |
291 | * in the MP table. To prevent the PCI interrupts from being set up | |
292 | * incorrectly, we try to use the ELCR. The sanity check to see if | |
293 | * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can | |
294 | * never be level sensitive, so we simply see if the ELCR agrees. | |
295 | * If it does, we assume it's valid. | |
296 | */ | |
297 | if (mpc_default_type == 5) { | |
d2953315 AS |
298 | printk(KERN_INFO "ISA/PCI bus type with no IRQ information... " |
299 | "falling back to ELCR\n"); | |
1da177e4 | 300 | |
d2953315 AS |
301 | if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || |
302 | ELCR_trigger(13)) | |
303 | printk(KERN_ERR "ELCR contains invalid data... " | |
304 | "not using ELCR\n"); | |
1da177e4 | 305 | else { |
d2953315 AS |
306 | printk(KERN_INFO |
307 | "Using ELCR to identify PCI interrupts\n"); | |
1da177e4 LT |
308 | ELCR_fallback = 1; |
309 | } | |
310 | } | |
311 | ||
312 | for (i = 0; i < 16; i++) { | |
313 | switch (mpc_default_type) { | |
314 | case 2: | |
315 | if (i == 0 || i == 13) | |
316 | continue; /* IRQ0 & IRQ13 not connected */ | |
317 | /* fall through */ | |
318 | default: | |
319 | if (i == 2) | |
320 | continue; /* IRQ2 is never connected */ | |
321 | } | |
322 | ||
323 | if (ELCR_fallback) { | |
324 | /* | |
325 | * If the ELCR indicates a level-sensitive interrupt, we | |
326 | * copy that information over to the MP table in the | |
327 | * irqflag field (level sensitive, active high polarity). | |
328 | */ | |
329 | if (ELCR_trigger(i)) | |
330 | intsrc.mpc_irqflag = 13; | |
331 | else | |
332 | intsrc.mpc_irqflag = 0; | |
333 | } | |
334 | ||
335 | intsrc.mpc_srcbusirq = i; | |
d2953315 | 336 | intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */ |
1da177e4 LT |
337 | MP_intsrc_info(&intsrc); |
338 | } | |
339 | ||
340 | intsrc.mpc_irqtype = mp_ExtINT; | |
341 | intsrc.mpc_srcbusirq = 0; | |
d2953315 | 342 | intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */ |
1da177e4 LT |
343 | MP_intsrc_info(&intsrc); |
344 | } | |
345 | ||
346 | static inline void __init construct_default_ISA_mptable(int mpc_default_type) | |
347 | { | |
348 | struct mpc_config_processor processor; | |
349 | struct mpc_config_bus bus; | |
350 | struct mpc_config_ioapic ioapic; | |
351 | struct mpc_config_lintsrc lintsrc; | |
352 | int linttypes[2] = { mp_ExtINT, mp_NMI }; | |
353 | int i; | |
354 | ||
355 | /* | |
356 | * local APIC has default address | |
357 | */ | |
358 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
359 | ||
360 | /* | |
361 | * 2 CPUs, numbered 0 & 1. | |
362 | */ | |
363 | processor.mpc_type = MP_PROCESSOR; | |
f2c2cca3 | 364 | processor.mpc_apicver = 0; |
1da177e4 | 365 | processor.mpc_cpuflag = CPU_ENABLED; |
f2c2cca3 AK |
366 | processor.mpc_cpufeature = 0; |
367 | processor.mpc_featureflag = 0; | |
1da177e4 LT |
368 | processor.mpc_reserved[0] = 0; |
369 | processor.mpc_reserved[1] = 0; | |
370 | for (i = 0; i < 2; i++) { | |
371 | processor.mpc_apicid = i; | |
372 | MP_processor_info(&processor); | |
373 | } | |
374 | ||
375 | bus.mpc_type = MP_BUS; | |
376 | bus.mpc_busid = 0; | |
377 | switch (mpc_default_type) { | |
d2953315 AS |
378 | default: |
379 | printk(KERN_ERR "???\nUnknown standard configuration %d\n", | |
380 | mpc_default_type); | |
381 | /* fall through */ | |
382 | case 1: | |
383 | case 5: | |
384 | memcpy(bus.mpc_bustype, "ISA ", 6); | |
385 | break; | |
1da177e4 LT |
386 | } |
387 | MP_bus_info(&bus); | |
388 | if (mpc_default_type > 4) { | |
389 | bus.mpc_busid = 1; | |
390 | memcpy(bus.mpc_bustype, "PCI ", 6); | |
391 | MP_bus_info(&bus); | |
392 | } | |
393 | ||
394 | ioapic.mpc_type = MP_IOAPIC; | |
395 | ioapic.mpc_apicid = 2; | |
f2c2cca3 | 396 | ioapic.mpc_apicver = 0; |
1da177e4 LT |
397 | ioapic.mpc_flags = MPC_APIC_USABLE; |
398 | ioapic.mpc_apicaddr = 0xFEC00000; | |
399 | MP_ioapic_info(&ioapic); | |
400 | ||
401 | /* | |
402 | * We set up most of the low 16 IO-APIC pins according to MPS rules. | |
403 | */ | |
404 | construct_default_ioirq_mptable(mpc_default_type); | |
405 | ||
406 | lintsrc.mpc_type = MP_LINTSRC; | |
d2953315 | 407 | lintsrc.mpc_irqflag = 0; /* conforming */ |
1da177e4 LT |
408 | lintsrc.mpc_srcbusid = 0; |
409 | lintsrc.mpc_srcbusirq = 0; | |
410 | lintsrc.mpc_destapic = MP_APIC_ALL; | |
411 | for (i = 0; i < 2; i++) { | |
412 | lintsrc.mpc_irqtype = linttypes[i]; | |
413 | lintsrc.mpc_destapiclint = i; | |
414 | MP_lintsrc_info(&lintsrc); | |
415 | } | |
416 | } | |
417 | ||
418 | static struct intel_mp_floating *mpf_found; | |
419 | ||
420 | /* | |
421 | * Scan the memory blocks for an SMP configuration block. | |
422 | */ | |
8643f9d0 | 423 | static void __init __get_smp_config(unsigned early) |
1da177e4 LT |
424 | { |
425 | struct intel_mp_floating *mpf = mpf_found; | |
426 | ||
8643f9d0 YL |
427 | if (acpi_lapic && early) |
428 | return; | |
1da177e4 | 429 | /* |
8643f9d0 YL |
430 | * ACPI supports both logical (e.g. Hyper-Threading) and physical |
431 | * processors, where MPS only supports physical. | |
432 | */ | |
433 | if (acpi_lapic && acpi_ioapic) { | |
434 | printk(KERN_INFO "Using ACPI (MADT) for SMP configuration " | |
d2953315 | 435 | "information\n"); |
8643f9d0 YL |
436 | return; |
437 | } else if (acpi_lapic) | |
438 | printk(KERN_INFO "Using ACPI for processor (LAPIC) " | |
d2953315 | 439 | "configuration information\n"); |
1da177e4 | 440 | |
8643f9d0 | 441 | printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n", |
d2953315 | 442 | mpf->mpf_specification); |
1da177e4 LT |
443 | |
444 | /* | |
445 | * Now see if we need to read further. | |
446 | */ | |
447 | if (mpf->mpf_feature1 != 0) { | |
8643f9d0 YL |
448 | if (early) { |
449 | /* | |
450 | * local APIC has default address | |
451 | */ | |
452 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
453 | return; | |
454 | } | |
1da177e4 | 455 | |
d2953315 AS |
456 | printk(KERN_INFO "Default MP configuration #%d\n", |
457 | mpf->mpf_feature1); | |
1da177e4 LT |
458 | construct_default_ISA_mptable(mpf->mpf_feature1); |
459 | ||
460 | } else if (mpf->mpf_physptr) { | |
461 | ||
462 | /* | |
463 | * Read the physical hardware table. Anything here will | |
464 | * override the defaults. | |
465 | */ | |
8643f9d0 | 466 | if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr), early)) { |
1da177e4 | 467 | smp_found_config = 0; |
d2953315 AS |
468 | printk(KERN_ERR |
469 | "BIOS bug, MP table errors detected!...\n"); | |
470 | printk(KERN_ERR "... disabling SMP support. " | |
471 | "(tell your hw vendor)\n"); | |
1da177e4 LT |
472 | return; |
473 | } | |
8643f9d0 YL |
474 | |
475 | if (early) | |
476 | return; | |
1da177e4 LT |
477 | /* |
478 | * If there are no explicit MP IRQ entries, then we are | |
479 | * broken. We set up most of the low 16 IO-APIC pins to | |
480 | * ISA defaults and hope it will work. | |
481 | */ | |
482 | if (!mp_irq_entries) { | |
483 | struct mpc_config_bus bus; | |
484 | ||
d2953315 AS |
485 | printk(KERN_ERR "BIOS bug, no explicit IRQ entries, " |
486 | "using default mptable. " | |
487 | "(tell your hw vendor)\n"); | |
1da177e4 LT |
488 | |
489 | bus.mpc_type = MP_BUS; | |
490 | bus.mpc_busid = 0; | |
491 | memcpy(bus.mpc_bustype, "ISA ", 6); | |
492 | MP_bus_info(&bus); | |
493 | ||
494 | construct_default_ioirq_mptable(0); | |
495 | } | |
496 | ||
497 | } else | |
498 | BUG(); | |
499 | ||
8643f9d0 YL |
500 | if (!early) |
501 | printk(KERN_INFO "Processors: %d\n", num_processors); | |
1da177e4 LT |
502 | /* |
503 | * Only use the first configuration found. | |
504 | */ | |
505 | } | |
506 | ||
8643f9d0 YL |
507 | void __init early_get_smp_config(void) |
508 | { | |
509 | __get_smp_config(1); | |
510 | } | |
511 | ||
512 | void __init get_smp_config(void) | |
513 | { | |
514 | __get_smp_config(0); | |
515 | } | |
516 | ||
517 | static int __init smp_scan_config(unsigned long base, unsigned long length, | |
518 | unsigned reserve) | |
1da177e4 | 519 | { |
d2953315 | 520 | extern void __bad_mpf_size(void); |
1da177e4 LT |
521 | unsigned int *bp = phys_to_virt(base); |
522 | struct intel_mp_floating *mpf; | |
523 | ||
d2953315 | 524 | Dprintk("Scan SMP from %p for %ld bytes.\n", bp, length); |
1da177e4 LT |
525 | if (sizeof(*mpf) != 16) |
526 | __bad_mpf_size(); | |
527 | ||
528 | while (length > 0) { | |
529 | mpf = (struct intel_mp_floating *)bp; | |
530 | if ((*bp == SMP_MAGIC_IDENT) && | |
d2953315 AS |
531 | (mpf->mpf_length == 1) && |
532 | !mpf_checksum((unsigned char *)bp, 16) && | |
533 | ((mpf->mpf_specification == 1) | |
534 | || (mpf->mpf_specification == 4))) { | |
1da177e4 LT |
535 | |
536 | smp_found_config = 1; | |
8643f9d0 YL |
537 | mpf_found = mpf; |
538 | ||
539 | if (!reserve) | |
540 | return 1; | |
541 | ||
1da177e4 LT |
542 | reserve_bootmem_generic(virt_to_phys(mpf), PAGE_SIZE); |
543 | if (mpf->mpf_physptr) | |
8643f9d0 YL |
544 | reserve_bootmem_generic(mpf->mpf_physptr, |
545 | PAGE_SIZE); | |
1da177e4 LT |
546 | return 1; |
547 | } | |
548 | bp += 4; | |
549 | length -= 16; | |
550 | } | |
551 | return 0; | |
552 | } | |
553 | ||
8643f9d0 | 554 | static void __init __find_smp_config(unsigned reserve) |
1da177e4 LT |
555 | { |
556 | unsigned int address; | |
557 | ||
558 | /* | |
559 | * FIXME: Linux assumes you have 640K of base ram.. | |
560 | * this continues the error... | |
561 | * | |
562 | * 1) Scan the bottom 1K for a signature | |
563 | * 2) Scan the top 1K of base RAM | |
564 | * 3) Scan the 64K of bios | |
565 | */ | |
8643f9d0 | 566 | if (smp_scan_config(0x0, 0x400, reserve) || |
d2953315 AS |
567 | smp_scan_config(639 * 0x400, 0x400, reserve) || |
568 | smp_scan_config(0xF0000, 0x10000, reserve)) | |
1da177e4 LT |
569 | return; |
570 | /* | |
e5099134 | 571 | * If it is an SMP machine we should know now. |
1da177e4 LT |
572 | * |
573 | * there is a real-mode segmented pointer pointing to the | |
574 | * 4K EBDA area at 0x40E, calculate and scan it here. | |
575 | * | |
576 | * NOTE! There are Linux loaders that will corrupt the EBDA | |
577 | * area, and as such this kind of SMP config may be less | |
578 | * trustworthy, simply because the SMP table may have been | |
579 | * stomped on during early boot. These loaders are buggy and | |
580 | * should be fixed. | |
85e46035 AS |
581 | * |
582 | * MP1.4 SPEC states to only scan first 1K of 4K EBDA. | |
1da177e4 LT |
583 | */ |
584 | ||
ce3fe6b2 AS |
585 | address = get_bios_ebda(); |
586 | if (address) | |
85e46035 | 587 | smp_scan_config(address, 0x400, reserve); |
1da177e4 LT |
588 | } |
589 | ||
8643f9d0 YL |
590 | void __init early_find_smp_config(void) |
591 | { | |
592 | __find_smp_config(0); | |
593 | } | |
594 | ||
595 | void __init find_smp_config(void) | |
596 | { | |
597 | __find_smp_config(1); | |
598 | } | |
599 | ||
1da177e4 LT |
600 | /* -------------------------------------------------------------------------- |
601 | ACPI-based MP Configuration | |
602 | -------------------------------------------------------------------------- */ | |
603 | ||
888ba6c6 | 604 | #ifdef CONFIG_ACPI |
1da177e4 | 605 | |
efec3b9a | 606 | void __init mp_register_lapic_address(u64 address) |
1da177e4 | 607 | { |
d2953315 | 608 | mp_lapic_addr = (unsigned long)address; |
1da177e4 | 609 | set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr); |
c70dcb74 | 610 | if (boot_cpu_physical_apicid == -1U) |
05f2d12c | 611 | boot_cpu_physical_apicid = GET_APIC_ID(read_apic_id()); |
1da177e4 | 612 | } |
a65d1d64 | 613 | void __cpuinit mp_register_lapic(int id, u8 enabled) |
1da177e4 | 614 | { |
8ccab29c AS |
615 | if (!enabled) { |
616 | ++disabled_cpus; | |
617 | return; | |
618 | } | |
1da177e4 | 619 | |
468e85b9 | 620 | generic_processor_info(id, 0); |
1da177e4 LT |
621 | } |
622 | ||
be8a5685 | 623 | |
1da177e4 LT |
624 | #define MP_ISA_BUS 0 |
625 | #define MP_MAX_IOAPIC_PIN 127 | |
626 | ||
9e5c5f1d | 627 | extern struct mp_ioapic_routing mp_ioapic_routing[MAX_IO_APICS]; |
1da177e4 | 628 | |
efec3b9a | 629 | static int mp_find_ioapic(int gsi) |
1da177e4 | 630 | { |
efec3b9a | 631 | int i = 0; |
1da177e4 LT |
632 | |
633 | /* Find the IOAPIC that manages this GSI. */ | |
634 | for (i = 0; i < nr_ioapics; i++) { | |
555b0764 | 635 | if ((gsi >= mp_ioapic_routing[i].gsi_base) |
d2953315 | 636 | && (gsi <= mp_ioapic_routing[i].gsi_end)) |
1da177e4 LT |
637 | return i; |
638 | } | |
639 | ||
640 | printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); | |
1da177e4 LT |
641 | return -1; |
642 | } | |
1da177e4 | 643 | |
78b599ae AK |
644 | static u8 uniq_ioapic_id(u8 id) |
645 | { | |
646 | int i; | |
647 | DECLARE_BITMAP(used, 256); | |
648 | bitmap_zero(used, 256); | |
649 | for (i = 0; i < nr_ioapics; i++) { | |
650 | struct mpc_config_ioapic *ia = &mp_ioapics[i]; | |
651 | __set_bit(ia->mpc_apicid, used); | |
652 | } | |
653 | if (!test_bit(id, used)) | |
654 | return id; | |
655 | return find_first_zero_bit(used, 256); | |
656 | } | |
657 | ||
a65d1d64 | 658 | void __init mp_register_ioapic(int id, u32 address, u32 gsi_base) |
1da177e4 | 659 | { |
efec3b9a | 660 | int idx = 0; |
1da177e4 | 661 | |
013bf2c5 | 662 | if (bad_ioapic(address)) |
1da177e4 | 663 | return; |
1da177e4 | 664 | |
78b599ae | 665 | idx = nr_ioapics; |
1da177e4 LT |
666 | |
667 | mp_ioapics[idx].mpc_type = MP_IOAPIC; | |
668 | mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE; | |
669 | mp_ioapics[idx].mpc_apicaddr = address; | |
670 | ||
671 | set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); | |
78b599ae | 672 | mp_ioapics[idx].mpc_apicid = uniq_ioapic_id(id); |
f2c2cca3 | 673 | mp_ioapics[idx].mpc_apicver = 0; |
d2953315 | 674 | |
1da177e4 LT |
675 | /* |
676 | * Build basic IRQ lookup table to facilitate gsi->io_apic lookups | |
677 | * and to prevent reprogramming of IOAPIC pins (PCI IRQs). | |
678 | */ | |
679 | mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid; | |
555b0764 | 680 | mp_ioapic_routing[idx].gsi_base = gsi_base; |
d2953315 AS |
681 | mp_ioapic_routing[idx].gsi_end = gsi_base + |
682 | io_apic_get_redir_entries(idx); | |
1da177e4 | 683 | |
f2c2cca3 | 684 | printk(KERN_INFO "IOAPIC[%d]: apic_id %d, address 0x%x, " |
d2953315 AS |
685 | "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid, |
686 | mp_ioapics[idx].mpc_apicaddr, | |
555b0764 | 687 | mp_ioapic_routing[idx].gsi_base, |
d2953315 | 688 | mp_ioapic_routing[idx].gsi_end); |
78b599ae AK |
689 | |
690 | nr_ioapics++; | |
1da177e4 LT |
691 | } |
692 | ||
d2953315 | 693 | void __init mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi) |
1da177e4 LT |
694 | { |
695 | struct mpc_config_intsrc intsrc; | |
d2953315 AS |
696 | int ioapic = -1; |
697 | int pin = -1; | |
1da177e4 LT |
698 | |
699 | /* | |
700 | * Convert 'gsi' to 'ioapic.pin'. | |
701 | */ | |
702 | ioapic = mp_find_ioapic(gsi); | |
703 | if (ioapic < 0) | |
704 | return; | |
555b0764 | 705 | pin = gsi - mp_ioapic_routing[ioapic].gsi_base; |
1da177e4 LT |
706 | |
707 | /* | |
708 | * TBD: This check is for faulty timer entries, where the override | |
709 | * erroneously sets the trigger to level, resulting in a HUGE | |
710 | * increase of timer interrupts! | |
711 | */ | |
712 | if ((bus_irq == 0) && (trigger == 3)) | |
713 | trigger = 1; | |
714 | ||
715 | intsrc.mpc_type = MP_INTSRC; | |
716 | intsrc.mpc_irqtype = mp_INT; | |
717 | intsrc.mpc_irqflag = (trigger << 2) | polarity; | |
718 | intsrc.mpc_srcbus = MP_ISA_BUS; | |
d2953315 AS |
719 | intsrc.mpc_srcbusirq = bus_irq; /* IRQ */ |
720 | intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */ | |
721 | intsrc.mpc_dstirq = pin; /* INTIN# */ | |
1da177e4 | 722 | |
d2953315 AS |
723 | Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n", |
724 | intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3, | |
725 | (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus, | |
1da177e4 LT |
726 | intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq); |
727 | ||
728 | mp_irqs[mp_irq_entries] = intsrc; | |
729 | if (++mp_irq_entries == MAX_IRQ_SOURCES) | |
730 | panic("Max # of irq sources exceeded!\n"); | |
1da177e4 LT |
731 | } |
732 | ||
efec3b9a | 733 | void __init mp_config_acpi_legacy_irqs(void) |
1da177e4 LT |
734 | { |
735 | struct mpc_config_intsrc intsrc; | |
efec3b9a AK |
736 | int i = 0; |
737 | int ioapic = -1; | |
1da177e4 LT |
738 | |
739 | /* | |
740 | * Fabricate the legacy ISA bus (bus #31). | |
741 | */ | |
55f05ffa | 742 | set_bit(MP_ISA_BUS, mp_bus_not_pci); |
1da177e4 LT |
743 | |
744 | /* | |
745 | * Locate the IOAPIC that manages the ISA IRQs (0-15). | |
746 | */ | |
747 | ioapic = mp_find_ioapic(0); | |
748 | if (ioapic < 0) | |
749 | return; | |
750 | ||
751 | intsrc.mpc_type = MP_INTSRC; | |
d2953315 | 752 | intsrc.mpc_irqflag = 0; /* Conforming */ |
1da177e4 LT |
753 | intsrc.mpc_srcbus = MP_ISA_BUS; |
754 | intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; | |
755 | ||
756 | /* | |
757 | * Use the default configuration for the IRQs 0-15. Unless | |
758 | * overridden by (MADT) interrupt source override entries. | |
759 | */ | |
760 | for (i = 0; i < 16; i++) { | |
761 | int idx; | |
762 | ||
763 | for (idx = 0; idx < mp_irq_entries; idx++) { | |
764 | struct mpc_config_intsrc *irq = mp_irqs + idx; | |
765 | ||
766 | /* Do we already have a mapping for this ISA IRQ? */ | |
d2953315 AS |
767 | if (irq->mpc_srcbus == MP_ISA_BUS |
768 | && irq->mpc_srcbusirq == i) | |
1da177e4 LT |
769 | break; |
770 | ||
771 | /* Do we already have a mapping for this IOAPIC pin */ | |
772 | if ((irq->mpc_dstapic == intsrc.mpc_dstapic) && | |
d2953315 | 773 | (irq->mpc_dstirq == i)) |
1da177e4 LT |
774 | break; |
775 | } | |
776 | ||
777 | if (idx != mp_irq_entries) { | |
778 | printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i); | |
d2953315 | 779 | continue; /* IRQ already used */ |
1da177e4 LT |
780 | } |
781 | ||
782 | intsrc.mpc_irqtype = mp_INT; | |
d2953315 | 783 | intsrc.mpc_srcbusirq = i; /* Identity mapped */ |
1da177e4 LT |
784 | intsrc.mpc_dstirq = i; |
785 | ||
786 | Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, " | |
d2953315 AS |
787 | "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3, |
788 | (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus, | |
789 | intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, | |
1da177e4 LT |
790 | intsrc.mpc_dstirq); |
791 | ||
792 | mp_irqs[mp_irq_entries] = intsrc; | |
793 | if (++mp_irq_entries == MAX_IRQ_SOURCES) | |
794 | panic("Max # of irq sources exceeded!\n"); | |
795 | } | |
1da177e4 LT |
796 | } |
797 | ||
50eca3eb | 798 | int mp_register_gsi(u32 gsi, int triggering, int polarity) |
1da177e4 | 799 | { |
efec3b9a AK |
800 | int ioapic = -1; |
801 | int ioapic_pin = 0; | |
802 | int idx, bit = 0; | |
1da177e4 LT |
803 | |
804 | if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC) | |
805 | return gsi; | |
806 | ||
1da177e4 | 807 | /* Don't set up the ACPI SCI because it's already set up */ |
cee324b1 | 808 | if (acpi_gbl_FADT.sci_interrupt == gsi) |
1da177e4 | 809 | return gsi; |
1da177e4 LT |
810 | |
811 | ioapic = mp_find_ioapic(gsi); | |
812 | if (ioapic < 0) { | |
813 | printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi); | |
814 | return gsi; | |
815 | } | |
816 | ||
555b0764 | 817 | ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base; |
1da177e4 LT |
818 | |
819 | /* | |
820 | * Avoid pin reprogramming. PRTs typically include entries | |
821 | * with redundant pin->gsi mappings (but unique PCI devices); | |
822 | * we only program the IOAPIC on the first. | |
823 | */ | |
824 | bit = ioapic_pin % 32; | |
825 | idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32); | |
826 | if (idx > 3) { | |
827 | printk(KERN_ERR "Invalid reference to IOAPIC pin " | |
d2953315 AS |
828 | "%d-%d\n", mp_ioapic_routing[ioapic].apic_id, |
829 | ioapic_pin); | |
1da177e4 LT |
830 | return gsi; |
831 | } | |
d2953315 | 832 | if ((1 << bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) { |
1da177e4 LT |
833 | Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n", |
834 | mp_ioapic_routing[ioapic].apic_id, ioapic_pin); | |
cd1182f5 | 835 | return gsi; |
1da177e4 LT |
836 | } |
837 | ||
d2953315 | 838 | mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1 << bit); |
1da177e4 LT |
839 | |
840 | io_apic_set_pci_routing(ioapic, ioapic_pin, gsi, | |
d2953315 AS |
841 | triggering == ACPI_EDGE_SENSITIVE ? 0 : 1, |
842 | polarity == ACPI_ACTIVE_HIGH ? 0 : 1); | |
1da177e4 LT |
843 | return gsi; |
844 | } | |
d2953315 | 845 | #endif /* CONFIG_ACPI */ |