Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Intel Multiprocessor Specification 1.1 and 1.4 | |
3 | * compliant MP-table parsing routines. | |
4 | * | |
5 | * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> | |
6 | * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
7 | * | |
8 | * Fixes | |
9 | * Erich Boleyn : MP v1.4 and additional changes. | |
10 | * Alan Cox : Added EBDA scanning | |
11 | * Ingo Molnar : various cleanups and rewrites | |
12 | * Maciej W. Rozycki: Bits for default MP configurations | |
13 | * Paul Diefenbaugh: Added full ACPI support | |
14 | */ | |
15 | ||
16 | #include <linux/mm.h> | |
1da177e4 LT |
17 | #include <linux/init.h> |
18 | #include <linux/delay.h> | |
1da177e4 | 19 | #include <linux/bootmem.h> |
1da177e4 LT |
20 | #include <linux/kernel_stat.h> |
21 | #include <linux/mc146818rtc.h> | |
22 | #include <linux/acpi.h> | |
8c5a0908 | 23 | #include <linux/module.h> |
1da177e4 LT |
24 | |
25 | #include <asm/smp.h> | |
26 | #include <asm/mtrr.h> | |
27 | #include <asm/mpspec.h> | |
28 | #include <asm/pgalloc.h> | |
29 | #include <asm/io_apic.h> | |
30 | #include <asm/proto.h> | |
8d916406 | 31 | #include <asm/acpi.h> |
ce3fe6b2 | 32 | #include <asm/bios_ebda.h> |
1da177e4 | 33 | |
f6bc4029 GOC |
34 | #include <mach_apic.h> |
35 | ||
1da177e4 LT |
36 | /* Have we found an MP table */ |
37 | int smp_found_config; | |
1da177e4 | 38 | |
1da177e4 LT |
39 | /* |
40 | * Various Linux-internal data structures created from the | |
41 | * MP-table. | |
42 | */ | |
55f05ffa | 43 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); |
d2953315 | 44 | int mp_bus_id_to_pci_bus[MAX_MP_BUSSES] = {[0 ... MAX_MP_BUSSES - 1] = -1 }; |
1da177e4 LT |
45 | |
46 | static int mp_current_pci_id = 0; | |
1da177e4 | 47 | |
1da177e4 LT |
48 | /* |
49 | * Intel MP BIOS table parsing routines: | |
50 | */ | |
51 | ||
52 | /* | |
53 | * Checksum an MP configuration block. | |
54 | */ | |
55 | ||
56 | static int __init mpf_checksum(unsigned char *mp, int len) | |
57 | { | |
58 | int sum = 0; | |
59 | ||
60 | while (len--) | |
61 | sum += *mp++; | |
62 | ||
63 | return sum & 0xFF; | |
64 | } | |
65 | ||
0e01c00c AS |
66 | static void __cpuinit MP_processor_info(struct mpc_config_processor *m) |
67 | { | |
746f2244 | 68 | int apicid; |
0e01c00c AS |
69 | char *bootup_cpu = ""; |
70 | ||
71 | if (!(m->mpc_cpuflag & CPU_ENABLED)) { | |
72 | disabled_cpus++; | |
73 | return; | |
74 | } | |
746f2244 AS |
75 | #ifdef CONFIG_X86_NUMAQ |
76 | apicid = mpc_apic_id(m, translation_table[mpc_record]); | |
77 | #else | |
78 | apicid = m->mpc_apicid; | |
79 | #endif | |
0e01c00c AS |
80 | if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) { |
81 | bootup_cpu = " (Bootup-CPU)"; | |
82 | boot_cpu_physical_apicid = m->mpc_apicid; | |
83 | } | |
84 | ||
85 | printk(KERN_INFO "Processor #%d%s\n", m->mpc_apicid, bootup_cpu); | |
746f2244 | 86 | generic_processor_info(apicid, m->mpc_apicver); |
0e01c00c AS |
87 | } |
88 | ||
d2953315 | 89 | static void __init MP_bus_info(struct mpc_config_bus *m) |
1da177e4 LT |
90 | { |
91 | char str[7]; | |
92 | ||
93 | memcpy(str, m->mpc_bustype, 6); | |
94 | str[6] = 0; | |
95 | Dprintk("Bus #%d is %s\n", m->mpc_busid, str); | |
96 | ||
97 | if (strncmp(str, "ISA", 3) == 0) { | |
55f05ffa | 98 | set_bit(m->mpc_busid, mp_bus_not_pci); |
1da177e4 | 99 | } else if (strncmp(str, "PCI", 3) == 0) { |
55f05ffa | 100 | clear_bit(m->mpc_busid, mp_bus_not_pci); |
1da177e4 LT |
101 | mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id; |
102 | mp_current_pci_id++; | |
1da177e4 LT |
103 | } else { |
104 | printk(KERN_ERR "Unknown bustype %s\n", str); | |
105 | } | |
106 | } | |
107 | ||
013bf2c5 AK |
108 | static int bad_ioapic(unsigned long address) |
109 | { | |
110 | if (nr_ioapics >= MAX_IO_APICS) { | |
111 | printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded " | |
d2953315 | 112 | "(found %d)\n", MAX_IO_APICS, nr_ioapics); |
013bf2c5 AK |
113 | panic("Recompile kernel with bigger MAX_IO_APICS!\n"); |
114 | } | |
115 | if (!address) { | |
116 | printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address" | |
d2953315 | 117 | " found in table, skipping!\n"); |
013bf2c5 AK |
118 | return 1; |
119 | } | |
120 | return 0; | |
121 | } | |
122 | ||
d2953315 | 123 | static void __init MP_ioapic_info(struct mpc_config_ioapic *m) |
1da177e4 LT |
124 | { |
125 | if (!(m->mpc_flags & MPC_APIC_USABLE)) | |
126 | return; | |
127 | ||
d2953315 AS |
128 | printk(KERN_INFO "I/O APIC #%d at 0x%X.\n", m->mpc_apicid, |
129 | m->mpc_apicaddr); | |
013bf2c5 AK |
130 | |
131 | if (bad_ioapic(m->mpc_apicaddr)) | |
1da177e4 | 132 | return; |
013bf2c5 | 133 | |
1da177e4 LT |
134 | mp_ioapics[nr_ioapics] = *m; |
135 | nr_ioapics++; | |
136 | } | |
137 | ||
d2953315 | 138 | static void __init MP_intsrc_info(struct mpc_config_intsrc *m) |
1da177e4 | 139 | { |
d2953315 | 140 | mp_irqs[mp_irq_entries] = *m; |
1da177e4 LT |
141 | Dprintk("Int: type %d, pol %d, trig %d, bus %d," |
142 | " IRQ %02x, APIC ID %x, APIC INT %02x\n", | |
d2953315 AS |
143 | m->mpc_irqtype, m->mpc_irqflag & 3, |
144 | (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus, | |
145 | m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq); | |
6004e1b7 | 146 | if (++mp_irq_entries >= MAX_IRQ_SOURCES) |
1da177e4 LT |
147 | panic("Max # of irq sources exceeded!!\n"); |
148 | } | |
149 | ||
d2953315 | 150 | static void __init MP_lintsrc_info(struct mpc_config_lintsrc *m) |
1da177e4 LT |
151 | { |
152 | Dprintk("Lint: type %d, pol %d, trig %d, bus %d," | |
153 | " IRQ %02x, APIC ID %x, APIC LINT %02x\n", | |
d2953315 AS |
154 | m->mpc_irqtype, m->mpc_irqflag & 3, |
155 | (m->mpc_irqflag >> 2) & 3, m->mpc_srcbusid, | |
156 | m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint); | |
1da177e4 LT |
157 | } |
158 | ||
159 | /* | |
160 | * Read/parse the MPC | |
161 | */ | |
8643f9d0 | 162 | static int __init smp_read_mpc(struct mp_config_table *mpc, unsigned early) |
1da177e4 LT |
163 | { |
164 | char str[16]; | |
d2953315 AS |
165 | int count = sizeof(*mpc); |
166 | unsigned char *mpt = ((unsigned char *)mpc) + count; | |
167 | ||
168 | if (memcmp(mpc->mpc_signature, MPC_SIGNATURE, 4)) { | |
169 | printk(KERN_ERR "MPTABLE: bad signature [%c%c%c%c]!\n", | |
170 | mpc->mpc_signature[0], | |
171 | mpc->mpc_signature[1], | |
172 | mpc->mpc_signature[2], mpc->mpc_signature[3]); | |
1da177e4 LT |
173 | return 0; |
174 | } | |
d2953315 AS |
175 | if (mpf_checksum((unsigned char *)mpc, mpc->mpc_length)) { |
176 | printk(KERN_ERR "MPTABLE: checksum error!\n"); | |
1da177e4 LT |
177 | return 0; |
178 | } | |
d2953315 | 179 | if (mpc->mpc_spec != 0x01 && mpc->mpc_spec != 0x04) { |
aecc6361 | 180 | printk(KERN_ERR "MPTABLE: bad table version (%d)!!\n", |
d2953315 | 181 | mpc->mpc_spec); |
1da177e4 LT |
182 | return 0; |
183 | } | |
184 | if (!mpc->mpc_lapic) { | |
aecc6361 | 185 | printk(KERN_ERR "MPTABLE: null local APIC address!\n"); |
1da177e4 LT |
186 | return 0; |
187 | } | |
d2953315 | 188 | memcpy(str, mpc->mpc_oem, 8); |
aecc6361 | 189 | str[8] = 0; |
d2953315 | 190 | printk(KERN_INFO "MPTABLE: OEM ID: %s ", str); |
1da177e4 | 191 | |
d2953315 | 192 | memcpy(str, mpc->mpc_productid, 12); |
aecc6361 | 193 | str[12] = 0; |
d2953315 | 194 | printk(KERN_INFO "MPTABLE: Product ID: %s ", str); |
1da177e4 | 195 | |
d2953315 | 196 | printk(KERN_INFO "MPTABLE: APIC at: 0x%X\n", mpc->mpc_lapic); |
1da177e4 LT |
197 | |
198 | /* save the local APIC address, it might be non-default */ | |
199 | if (!acpi_lapic) | |
aecc6361 | 200 | mp_lapic_addr = mpc->mpc_lapic; |
1da177e4 | 201 | |
8643f9d0 YL |
202 | if (early) |
203 | return 1; | |
204 | ||
1da177e4 | 205 | /* |
d2953315 | 206 | * Now process the configuration blocks. |
1da177e4 LT |
207 | */ |
208 | while (count < mpc->mpc_length) { | |
d2953315 AS |
209 | switch (*mpt) { |
210 | case MP_PROCESSOR: | |
1da177e4 | 211 | { |
d2953315 AS |
212 | struct mpc_config_processor *m = |
213 | (struct mpc_config_processor *)mpt; | |
1da177e4 | 214 | if (!acpi_lapic) |
aecc6361 | 215 | MP_processor_info(m); |
1da177e4 LT |
216 | mpt += sizeof(*m); |
217 | count += sizeof(*m); | |
218 | break; | |
219 | } | |
d2953315 | 220 | case MP_BUS: |
1da177e4 | 221 | { |
d2953315 AS |
222 | struct mpc_config_bus *m = |
223 | (struct mpc_config_bus *)mpt; | |
1da177e4 LT |
224 | MP_bus_info(m); |
225 | mpt += sizeof(*m); | |
226 | count += sizeof(*m); | |
227 | break; | |
228 | } | |
d2953315 | 229 | case MP_IOAPIC: |
1da177e4 | 230 | { |
d2953315 AS |
231 | struct mpc_config_ioapic *m = |
232 | (struct mpc_config_ioapic *)mpt; | |
1da177e4 | 233 | MP_ioapic_info(m); |
aecc6361 AK |
234 | mpt += sizeof(*m); |
235 | count += sizeof(*m); | |
1da177e4 LT |
236 | break; |
237 | } | |
d2953315 | 238 | case MP_INTSRC: |
1da177e4 | 239 | { |
d2953315 AS |
240 | struct mpc_config_intsrc *m = |
241 | (struct mpc_config_intsrc *)mpt; | |
1da177e4 LT |
242 | |
243 | MP_intsrc_info(m); | |
aecc6361 AK |
244 | mpt += sizeof(*m); |
245 | count += sizeof(*m); | |
1da177e4 LT |
246 | break; |
247 | } | |
d2953315 | 248 | case MP_LINTSRC: |
1da177e4 | 249 | { |
d2953315 AS |
250 | struct mpc_config_lintsrc *m = |
251 | (struct mpc_config_lintsrc *)mpt; | |
1da177e4 | 252 | MP_lintsrc_info(m); |
aecc6361 AK |
253 | mpt += sizeof(*m); |
254 | count += sizeof(*m); | |
1da177e4 LT |
255 | break; |
256 | } | |
257 | } | |
258 | } | |
3c43f039 | 259 | setup_apic_routing(); |
1da177e4 | 260 | if (!num_processors) |
aecc6361 | 261 | printk(KERN_ERR "MPTABLE: no processors registered!\n"); |
1da177e4 LT |
262 | return num_processors; |
263 | } | |
264 | ||
265 | static int __init ELCR_trigger(unsigned int irq) | |
266 | { | |
267 | unsigned int port; | |
268 | ||
269 | port = 0x4d0 + (irq >> 3); | |
270 | return (inb(port) >> (irq & 7)) & 1; | |
271 | } | |
272 | ||
273 | static void __init construct_default_ioirq_mptable(int mpc_default_type) | |
274 | { | |
275 | struct mpc_config_intsrc intsrc; | |
276 | int i; | |
277 | int ELCR_fallback = 0; | |
278 | ||
279 | intsrc.mpc_type = MP_INTSRC; | |
d2953315 | 280 | intsrc.mpc_irqflag = 0; /* conforming */ |
1da177e4 LT |
281 | intsrc.mpc_srcbus = 0; |
282 | intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid; | |
283 | ||
284 | intsrc.mpc_irqtype = mp_INT; | |
285 | ||
286 | /* | |
287 | * If true, we have an ISA/PCI system with no IRQ entries | |
288 | * in the MP table. To prevent the PCI interrupts from being set up | |
289 | * incorrectly, we try to use the ELCR. The sanity check to see if | |
290 | * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can | |
291 | * never be level sensitive, so we simply see if the ELCR agrees. | |
292 | * If it does, we assume it's valid. | |
293 | */ | |
294 | if (mpc_default_type == 5) { | |
d2953315 AS |
295 | printk(KERN_INFO "ISA/PCI bus type with no IRQ information... " |
296 | "falling back to ELCR\n"); | |
1da177e4 | 297 | |
d2953315 AS |
298 | if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || |
299 | ELCR_trigger(13)) | |
300 | printk(KERN_ERR "ELCR contains invalid data... " | |
301 | "not using ELCR\n"); | |
1da177e4 | 302 | else { |
d2953315 AS |
303 | printk(KERN_INFO |
304 | "Using ELCR to identify PCI interrupts\n"); | |
1da177e4 LT |
305 | ELCR_fallback = 1; |
306 | } | |
307 | } | |
308 | ||
309 | for (i = 0; i < 16; i++) { | |
310 | switch (mpc_default_type) { | |
311 | case 2: | |
312 | if (i == 0 || i == 13) | |
313 | continue; /* IRQ0 & IRQ13 not connected */ | |
314 | /* fall through */ | |
315 | default: | |
316 | if (i == 2) | |
317 | continue; /* IRQ2 is never connected */ | |
318 | } | |
319 | ||
320 | if (ELCR_fallback) { | |
321 | /* | |
322 | * If the ELCR indicates a level-sensitive interrupt, we | |
323 | * copy that information over to the MP table in the | |
324 | * irqflag field (level sensitive, active high polarity). | |
325 | */ | |
326 | if (ELCR_trigger(i)) | |
327 | intsrc.mpc_irqflag = 13; | |
328 | else | |
329 | intsrc.mpc_irqflag = 0; | |
330 | } | |
331 | ||
332 | intsrc.mpc_srcbusirq = i; | |
d2953315 | 333 | intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */ |
1da177e4 LT |
334 | MP_intsrc_info(&intsrc); |
335 | } | |
336 | ||
337 | intsrc.mpc_irqtype = mp_ExtINT; | |
338 | intsrc.mpc_srcbusirq = 0; | |
d2953315 | 339 | intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */ |
1da177e4 LT |
340 | MP_intsrc_info(&intsrc); |
341 | } | |
342 | ||
343 | static inline void __init construct_default_ISA_mptable(int mpc_default_type) | |
344 | { | |
345 | struct mpc_config_processor processor; | |
346 | struct mpc_config_bus bus; | |
347 | struct mpc_config_ioapic ioapic; | |
348 | struct mpc_config_lintsrc lintsrc; | |
349 | int linttypes[2] = { mp_ExtINT, mp_NMI }; | |
350 | int i; | |
351 | ||
352 | /* | |
353 | * local APIC has default address | |
354 | */ | |
355 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
356 | ||
357 | /* | |
358 | * 2 CPUs, numbered 0 & 1. | |
359 | */ | |
360 | processor.mpc_type = MP_PROCESSOR; | |
f2c2cca3 | 361 | processor.mpc_apicver = 0; |
1da177e4 | 362 | processor.mpc_cpuflag = CPU_ENABLED; |
f2c2cca3 AK |
363 | processor.mpc_cpufeature = 0; |
364 | processor.mpc_featureflag = 0; | |
1da177e4 LT |
365 | processor.mpc_reserved[0] = 0; |
366 | processor.mpc_reserved[1] = 0; | |
367 | for (i = 0; i < 2; i++) { | |
368 | processor.mpc_apicid = i; | |
369 | MP_processor_info(&processor); | |
370 | } | |
371 | ||
372 | bus.mpc_type = MP_BUS; | |
373 | bus.mpc_busid = 0; | |
374 | switch (mpc_default_type) { | |
d2953315 AS |
375 | default: |
376 | printk(KERN_ERR "???\nUnknown standard configuration %d\n", | |
377 | mpc_default_type); | |
378 | /* fall through */ | |
379 | case 1: | |
380 | case 5: | |
381 | memcpy(bus.mpc_bustype, "ISA ", 6); | |
382 | break; | |
1da177e4 LT |
383 | } |
384 | MP_bus_info(&bus); | |
385 | if (mpc_default_type > 4) { | |
386 | bus.mpc_busid = 1; | |
387 | memcpy(bus.mpc_bustype, "PCI ", 6); | |
388 | MP_bus_info(&bus); | |
389 | } | |
390 | ||
391 | ioapic.mpc_type = MP_IOAPIC; | |
392 | ioapic.mpc_apicid = 2; | |
f2c2cca3 | 393 | ioapic.mpc_apicver = 0; |
1da177e4 LT |
394 | ioapic.mpc_flags = MPC_APIC_USABLE; |
395 | ioapic.mpc_apicaddr = 0xFEC00000; | |
396 | MP_ioapic_info(&ioapic); | |
397 | ||
398 | /* | |
399 | * We set up most of the low 16 IO-APIC pins according to MPS rules. | |
400 | */ | |
401 | construct_default_ioirq_mptable(mpc_default_type); | |
402 | ||
403 | lintsrc.mpc_type = MP_LINTSRC; | |
d2953315 | 404 | lintsrc.mpc_irqflag = 0; /* conforming */ |
1da177e4 LT |
405 | lintsrc.mpc_srcbusid = 0; |
406 | lintsrc.mpc_srcbusirq = 0; | |
407 | lintsrc.mpc_destapic = MP_APIC_ALL; | |
408 | for (i = 0; i < 2; i++) { | |
409 | lintsrc.mpc_irqtype = linttypes[i]; | |
410 | lintsrc.mpc_destapiclint = i; | |
411 | MP_lintsrc_info(&lintsrc); | |
412 | } | |
413 | } | |
414 | ||
415 | static struct intel_mp_floating *mpf_found; | |
416 | ||
417 | /* | |
418 | * Scan the memory blocks for an SMP configuration block. | |
419 | */ | |
8643f9d0 | 420 | static void __init __get_smp_config(unsigned early) |
1da177e4 LT |
421 | { |
422 | struct intel_mp_floating *mpf = mpf_found; | |
423 | ||
8643f9d0 YL |
424 | if (acpi_lapic && early) |
425 | return; | |
1da177e4 | 426 | /* |
8643f9d0 YL |
427 | * ACPI supports both logical (e.g. Hyper-Threading) and physical |
428 | * processors, where MPS only supports physical. | |
429 | */ | |
430 | if (acpi_lapic && acpi_ioapic) { | |
431 | printk(KERN_INFO "Using ACPI (MADT) for SMP configuration " | |
d2953315 | 432 | "information\n"); |
8643f9d0 YL |
433 | return; |
434 | } else if (acpi_lapic) | |
435 | printk(KERN_INFO "Using ACPI for processor (LAPIC) " | |
d2953315 | 436 | "configuration information\n"); |
1da177e4 | 437 | |
8643f9d0 | 438 | printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n", |
d2953315 | 439 | mpf->mpf_specification); |
1da177e4 LT |
440 | |
441 | /* | |
442 | * Now see if we need to read further. | |
443 | */ | |
444 | if (mpf->mpf_feature1 != 0) { | |
8643f9d0 YL |
445 | if (early) { |
446 | /* | |
447 | * local APIC has default address | |
448 | */ | |
449 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
450 | return; | |
451 | } | |
1da177e4 | 452 | |
d2953315 AS |
453 | printk(KERN_INFO "Default MP configuration #%d\n", |
454 | mpf->mpf_feature1); | |
1da177e4 LT |
455 | construct_default_ISA_mptable(mpf->mpf_feature1); |
456 | ||
457 | } else if (mpf->mpf_physptr) { | |
458 | ||
459 | /* | |
460 | * Read the physical hardware table. Anything here will | |
461 | * override the defaults. | |
462 | */ | |
8643f9d0 | 463 | if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr), early)) { |
1da177e4 | 464 | smp_found_config = 0; |
d2953315 AS |
465 | printk(KERN_ERR |
466 | "BIOS bug, MP table errors detected!...\n"); | |
467 | printk(KERN_ERR "... disabling SMP support. " | |
468 | "(tell your hw vendor)\n"); | |
1da177e4 LT |
469 | return; |
470 | } | |
8643f9d0 YL |
471 | |
472 | if (early) | |
473 | return; | |
1da177e4 LT |
474 | /* |
475 | * If there are no explicit MP IRQ entries, then we are | |
476 | * broken. We set up most of the low 16 IO-APIC pins to | |
477 | * ISA defaults and hope it will work. | |
478 | */ | |
479 | if (!mp_irq_entries) { | |
480 | struct mpc_config_bus bus; | |
481 | ||
d2953315 AS |
482 | printk(KERN_ERR "BIOS bug, no explicit IRQ entries, " |
483 | "using default mptable. " | |
484 | "(tell your hw vendor)\n"); | |
1da177e4 LT |
485 | |
486 | bus.mpc_type = MP_BUS; | |
487 | bus.mpc_busid = 0; | |
488 | memcpy(bus.mpc_bustype, "ISA ", 6); | |
489 | MP_bus_info(&bus); | |
490 | ||
491 | construct_default_ioirq_mptable(0); | |
492 | } | |
493 | ||
494 | } else | |
495 | BUG(); | |
496 | ||
8643f9d0 YL |
497 | if (!early) |
498 | printk(KERN_INFO "Processors: %d\n", num_processors); | |
1da177e4 LT |
499 | /* |
500 | * Only use the first configuration found. | |
501 | */ | |
502 | } | |
503 | ||
8643f9d0 YL |
504 | void __init early_get_smp_config(void) |
505 | { | |
506 | __get_smp_config(1); | |
507 | } | |
508 | ||
509 | void __init get_smp_config(void) | |
510 | { | |
511 | __get_smp_config(0); | |
512 | } | |
513 | ||
514 | static int __init smp_scan_config(unsigned long base, unsigned long length, | |
515 | unsigned reserve) | |
1da177e4 | 516 | { |
d2953315 | 517 | extern void __bad_mpf_size(void); |
1da177e4 LT |
518 | unsigned int *bp = phys_to_virt(base); |
519 | struct intel_mp_floating *mpf; | |
520 | ||
d2953315 | 521 | Dprintk("Scan SMP from %p for %ld bytes.\n", bp, length); |
1da177e4 LT |
522 | if (sizeof(*mpf) != 16) |
523 | __bad_mpf_size(); | |
524 | ||
525 | while (length > 0) { | |
526 | mpf = (struct intel_mp_floating *)bp; | |
527 | if ((*bp == SMP_MAGIC_IDENT) && | |
d2953315 AS |
528 | (mpf->mpf_length == 1) && |
529 | !mpf_checksum((unsigned char *)bp, 16) && | |
530 | ((mpf->mpf_specification == 1) | |
531 | || (mpf->mpf_specification == 4))) { | |
1da177e4 LT |
532 | |
533 | smp_found_config = 1; | |
8643f9d0 YL |
534 | mpf_found = mpf; |
535 | ||
536 | if (!reserve) | |
537 | return 1; | |
538 | ||
1da177e4 LT |
539 | reserve_bootmem_generic(virt_to_phys(mpf), PAGE_SIZE); |
540 | if (mpf->mpf_physptr) | |
8643f9d0 YL |
541 | reserve_bootmem_generic(mpf->mpf_physptr, |
542 | PAGE_SIZE); | |
1da177e4 LT |
543 | return 1; |
544 | } | |
545 | bp += 4; | |
546 | length -= 16; | |
547 | } | |
548 | return 0; | |
549 | } | |
550 | ||
8643f9d0 | 551 | static void __init __find_smp_config(unsigned reserve) |
1da177e4 LT |
552 | { |
553 | unsigned int address; | |
554 | ||
555 | /* | |
556 | * FIXME: Linux assumes you have 640K of base ram.. | |
557 | * this continues the error... | |
558 | * | |
559 | * 1) Scan the bottom 1K for a signature | |
560 | * 2) Scan the top 1K of base RAM | |
561 | * 3) Scan the 64K of bios | |
562 | */ | |
8643f9d0 | 563 | if (smp_scan_config(0x0, 0x400, reserve) || |
d2953315 AS |
564 | smp_scan_config(639 * 0x400, 0x400, reserve) || |
565 | smp_scan_config(0xF0000, 0x10000, reserve)) | |
1da177e4 LT |
566 | return; |
567 | /* | |
e5099134 | 568 | * If it is an SMP machine we should know now. |
1da177e4 LT |
569 | * |
570 | * there is a real-mode segmented pointer pointing to the | |
571 | * 4K EBDA area at 0x40E, calculate and scan it here. | |
572 | * | |
573 | * NOTE! There are Linux loaders that will corrupt the EBDA | |
574 | * area, and as such this kind of SMP config may be less | |
575 | * trustworthy, simply because the SMP table may have been | |
576 | * stomped on during early boot. These loaders are buggy and | |
577 | * should be fixed. | |
85e46035 AS |
578 | * |
579 | * MP1.4 SPEC states to only scan first 1K of 4K EBDA. | |
1da177e4 LT |
580 | */ |
581 | ||
ce3fe6b2 AS |
582 | address = get_bios_ebda(); |
583 | if (address) | |
85e46035 | 584 | smp_scan_config(address, 0x400, reserve); |
1da177e4 LT |
585 | } |
586 | ||
8643f9d0 YL |
587 | void __init early_find_smp_config(void) |
588 | { | |
589 | __find_smp_config(0); | |
590 | } | |
591 | ||
592 | void __init find_smp_config(void) | |
593 | { | |
594 | __find_smp_config(1); | |
595 | } | |
596 | ||
1da177e4 LT |
597 | /* -------------------------------------------------------------------------- |
598 | ACPI-based MP Configuration | |
599 | -------------------------------------------------------------------------- */ | |
600 | ||
888ba6c6 | 601 | #ifdef CONFIG_ACPI |
1da177e4 | 602 | |
1da177e4 LT |
603 | #define MP_ISA_BUS 0 |
604 | #define MP_MAX_IOAPIC_PIN 127 | |
605 | ||
9e5c5f1d | 606 | extern struct mp_ioapic_routing mp_ioapic_routing[MAX_IO_APICS]; |
1da177e4 | 607 | |
efec3b9a | 608 | static int mp_find_ioapic(int gsi) |
1da177e4 | 609 | { |
efec3b9a | 610 | int i = 0; |
1da177e4 LT |
611 | |
612 | /* Find the IOAPIC that manages this GSI. */ | |
613 | for (i = 0; i < nr_ioapics; i++) { | |
555b0764 | 614 | if ((gsi >= mp_ioapic_routing[i].gsi_base) |
d2953315 | 615 | && (gsi <= mp_ioapic_routing[i].gsi_end)) |
1da177e4 LT |
616 | return i; |
617 | } | |
618 | ||
619 | printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); | |
1da177e4 LT |
620 | return -1; |
621 | } | |
1da177e4 | 622 | |
78b599ae AK |
623 | static u8 uniq_ioapic_id(u8 id) |
624 | { | |
625 | int i; | |
626 | DECLARE_BITMAP(used, 256); | |
627 | bitmap_zero(used, 256); | |
628 | for (i = 0; i < nr_ioapics; i++) { | |
629 | struct mpc_config_ioapic *ia = &mp_ioapics[i]; | |
630 | __set_bit(ia->mpc_apicid, used); | |
631 | } | |
632 | if (!test_bit(id, used)) | |
633 | return id; | |
634 | return find_first_zero_bit(used, 256); | |
635 | } | |
636 | ||
a65d1d64 | 637 | void __init mp_register_ioapic(int id, u32 address, u32 gsi_base) |
1da177e4 | 638 | { |
efec3b9a | 639 | int idx = 0; |
1da177e4 | 640 | |
013bf2c5 | 641 | if (bad_ioapic(address)) |
1da177e4 | 642 | return; |
1da177e4 | 643 | |
78b599ae | 644 | idx = nr_ioapics; |
1da177e4 LT |
645 | |
646 | mp_ioapics[idx].mpc_type = MP_IOAPIC; | |
647 | mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE; | |
648 | mp_ioapics[idx].mpc_apicaddr = address; | |
649 | ||
650 | set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); | |
78b599ae | 651 | mp_ioapics[idx].mpc_apicid = uniq_ioapic_id(id); |
f2c2cca3 | 652 | mp_ioapics[idx].mpc_apicver = 0; |
d2953315 | 653 | |
1da177e4 LT |
654 | /* |
655 | * Build basic IRQ lookup table to facilitate gsi->io_apic lookups | |
656 | * and to prevent reprogramming of IOAPIC pins (PCI IRQs). | |
657 | */ | |
658 | mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid; | |
555b0764 | 659 | mp_ioapic_routing[idx].gsi_base = gsi_base; |
d2953315 AS |
660 | mp_ioapic_routing[idx].gsi_end = gsi_base + |
661 | io_apic_get_redir_entries(idx); | |
1da177e4 | 662 | |
f2c2cca3 | 663 | printk(KERN_INFO "IOAPIC[%d]: apic_id %d, address 0x%x, " |
d2953315 AS |
664 | "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid, |
665 | mp_ioapics[idx].mpc_apicaddr, | |
555b0764 | 666 | mp_ioapic_routing[idx].gsi_base, |
d2953315 | 667 | mp_ioapic_routing[idx].gsi_end); |
78b599ae AK |
668 | |
669 | nr_ioapics++; | |
1da177e4 LT |
670 | } |
671 | ||
d2953315 | 672 | void __init mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi) |
1da177e4 LT |
673 | { |
674 | struct mpc_config_intsrc intsrc; | |
d2953315 AS |
675 | int ioapic = -1; |
676 | int pin = -1; | |
1da177e4 LT |
677 | |
678 | /* | |
679 | * Convert 'gsi' to 'ioapic.pin'. | |
680 | */ | |
681 | ioapic = mp_find_ioapic(gsi); | |
682 | if (ioapic < 0) | |
683 | return; | |
555b0764 | 684 | pin = gsi - mp_ioapic_routing[ioapic].gsi_base; |
1da177e4 LT |
685 | |
686 | /* | |
687 | * TBD: This check is for faulty timer entries, where the override | |
688 | * erroneously sets the trigger to level, resulting in a HUGE | |
689 | * increase of timer interrupts! | |
690 | */ | |
691 | if ((bus_irq == 0) && (trigger == 3)) | |
692 | trigger = 1; | |
693 | ||
694 | intsrc.mpc_type = MP_INTSRC; | |
695 | intsrc.mpc_irqtype = mp_INT; | |
696 | intsrc.mpc_irqflag = (trigger << 2) | polarity; | |
697 | intsrc.mpc_srcbus = MP_ISA_BUS; | |
d2953315 AS |
698 | intsrc.mpc_srcbusirq = bus_irq; /* IRQ */ |
699 | intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */ | |
700 | intsrc.mpc_dstirq = pin; /* INTIN# */ | |
1da177e4 | 701 | |
d2953315 AS |
702 | Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n", |
703 | intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3, | |
704 | (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus, | |
1da177e4 LT |
705 | intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq); |
706 | ||
707 | mp_irqs[mp_irq_entries] = intsrc; | |
708 | if (++mp_irq_entries == MAX_IRQ_SOURCES) | |
709 | panic("Max # of irq sources exceeded!\n"); | |
1da177e4 LT |
710 | } |
711 | ||
efec3b9a | 712 | void __init mp_config_acpi_legacy_irqs(void) |
1da177e4 LT |
713 | { |
714 | struct mpc_config_intsrc intsrc; | |
efec3b9a AK |
715 | int i = 0; |
716 | int ioapic = -1; | |
1da177e4 LT |
717 | |
718 | /* | |
719 | * Fabricate the legacy ISA bus (bus #31). | |
720 | */ | |
55f05ffa | 721 | set_bit(MP_ISA_BUS, mp_bus_not_pci); |
1da177e4 LT |
722 | |
723 | /* | |
724 | * Locate the IOAPIC that manages the ISA IRQs (0-15). | |
725 | */ | |
726 | ioapic = mp_find_ioapic(0); | |
727 | if (ioapic < 0) | |
728 | return; | |
729 | ||
730 | intsrc.mpc_type = MP_INTSRC; | |
d2953315 | 731 | intsrc.mpc_irqflag = 0; /* Conforming */ |
1da177e4 LT |
732 | intsrc.mpc_srcbus = MP_ISA_BUS; |
733 | intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; | |
734 | ||
735 | /* | |
736 | * Use the default configuration for the IRQs 0-15. Unless | |
737 | * overridden by (MADT) interrupt source override entries. | |
738 | */ | |
739 | for (i = 0; i < 16; i++) { | |
740 | int idx; | |
741 | ||
742 | for (idx = 0; idx < mp_irq_entries; idx++) { | |
743 | struct mpc_config_intsrc *irq = mp_irqs + idx; | |
744 | ||
745 | /* Do we already have a mapping for this ISA IRQ? */ | |
d2953315 AS |
746 | if (irq->mpc_srcbus == MP_ISA_BUS |
747 | && irq->mpc_srcbusirq == i) | |
1da177e4 LT |
748 | break; |
749 | ||
750 | /* Do we already have a mapping for this IOAPIC pin */ | |
751 | if ((irq->mpc_dstapic == intsrc.mpc_dstapic) && | |
d2953315 | 752 | (irq->mpc_dstirq == i)) |
1da177e4 LT |
753 | break; |
754 | } | |
755 | ||
756 | if (idx != mp_irq_entries) { | |
757 | printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i); | |
d2953315 | 758 | continue; /* IRQ already used */ |
1da177e4 LT |
759 | } |
760 | ||
761 | intsrc.mpc_irqtype = mp_INT; | |
d2953315 | 762 | intsrc.mpc_srcbusirq = i; /* Identity mapped */ |
1da177e4 LT |
763 | intsrc.mpc_dstirq = i; |
764 | ||
765 | Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, " | |
d2953315 AS |
766 | "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3, |
767 | (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus, | |
768 | intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, | |
1da177e4 LT |
769 | intsrc.mpc_dstirq); |
770 | ||
771 | mp_irqs[mp_irq_entries] = intsrc; | |
772 | if (++mp_irq_entries == MAX_IRQ_SOURCES) | |
773 | panic("Max # of irq sources exceeded!\n"); | |
774 | } | |
1da177e4 LT |
775 | } |
776 | ||
50eca3eb | 777 | int mp_register_gsi(u32 gsi, int triggering, int polarity) |
1da177e4 | 778 | { |
efec3b9a AK |
779 | int ioapic = -1; |
780 | int ioapic_pin = 0; | |
781 | int idx, bit = 0; | |
1da177e4 LT |
782 | |
783 | if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC) | |
784 | return gsi; | |
785 | ||
1da177e4 | 786 | /* Don't set up the ACPI SCI because it's already set up */ |
cee324b1 | 787 | if (acpi_gbl_FADT.sci_interrupt == gsi) |
1da177e4 | 788 | return gsi; |
1da177e4 LT |
789 | |
790 | ioapic = mp_find_ioapic(gsi); | |
791 | if (ioapic < 0) { | |
792 | printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi); | |
793 | return gsi; | |
794 | } | |
795 | ||
555b0764 | 796 | ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base; |
1da177e4 LT |
797 | |
798 | /* | |
799 | * Avoid pin reprogramming. PRTs typically include entries | |
800 | * with redundant pin->gsi mappings (but unique PCI devices); | |
801 | * we only program the IOAPIC on the first. | |
802 | */ | |
803 | bit = ioapic_pin % 32; | |
804 | idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32); | |
805 | if (idx > 3) { | |
806 | printk(KERN_ERR "Invalid reference to IOAPIC pin " | |
d2953315 AS |
807 | "%d-%d\n", mp_ioapic_routing[ioapic].apic_id, |
808 | ioapic_pin); | |
1da177e4 LT |
809 | return gsi; |
810 | } | |
d2953315 | 811 | if ((1 << bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) { |
1da177e4 LT |
812 | Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n", |
813 | mp_ioapic_routing[ioapic].apic_id, ioapic_pin); | |
cd1182f5 | 814 | return gsi; |
1da177e4 LT |
815 | } |
816 | ||
d2953315 | 817 | mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1 << bit); |
1da177e4 LT |
818 | |
819 | io_apic_set_pci_routing(ioapic, ioapic_pin, gsi, | |
d2953315 AS |
820 | triggering == ACPI_EDGE_SENSITIVE ? 0 : 1, |
821 | polarity == ACPI_ACTIVE_HIGH ? 0 : 1); | |
1da177e4 LT |
822 | return gsi; |
823 | } | |
d2953315 | 824 | #endif /* CONFIG_ACPI */ |