Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Intel Multiprocessor Specification 1.1 and 1.4 | |
3 | * compliant MP-table parsing routines. | |
4 | * | |
5 | * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> | |
6 | * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
7 | * | |
8 | * Fixes | |
9 | * Erich Boleyn : MP v1.4 and additional changes. | |
10 | * Alan Cox : Added EBDA scanning | |
11 | * Ingo Molnar : various cleanups and rewrites | |
12 | * Maciej W. Rozycki: Bits for default MP configurations | |
13 | * Paul Diefenbaugh: Added full ACPI support | |
14 | */ | |
15 | ||
16 | #include <linux/mm.h> | |
1da177e4 LT |
17 | #include <linux/init.h> |
18 | #include <linux/delay.h> | |
1da177e4 | 19 | #include <linux/bootmem.h> |
1da177e4 LT |
20 | #include <linux/kernel_stat.h> |
21 | #include <linux/mc146818rtc.h> | |
22 | #include <linux/acpi.h> | |
8c5a0908 | 23 | #include <linux/module.h> |
1da177e4 LT |
24 | |
25 | #include <asm/smp.h> | |
26 | #include <asm/mtrr.h> | |
27 | #include <asm/mpspec.h> | |
28 | #include <asm/pgalloc.h> | |
29 | #include <asm/io_apic.h> | |
30 | #include <asm/proto.h> | |
8d916406 | 31 | #include <asm/acpi.h> |
ce3fe6b2 | 32 | #include <asm/bios_ebda.h> |
1da177e4 | 33 | |
f6bc4029 GOC |
34 | #include <mach_apic.h> |
35 | ||
1da177e4 LT |
36 | /* Have we found an MP table */ |
37 | int smp_found_config; | |
1da177e4 | 38 | |
1da177e4 LT |
39 | /* |
40 | * Various Linux-internal data structures created from the | |
41 | * MP-table. | |
42 | */ | |
55f05ffa | 43 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); |
d2953315 | 44 | int mp_bus_id_to_pci_bus[MAX_MP_BUSSES] = {[0 ... MAX_MP_BUSSES - 1] = -1 }; |
1da177e4 LT |
45 | |
46 | static int mp_current_pci_id = 0; | |
1da177e4 LT |
47 | |
48 | /* # of MP IRQ source entries */ | |
49 | struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES]; | |
50 | ||
51 | /* MP IRQ source entries */ | |
52 | int mp_irq_entries; | |
53 | ||
e937fcf2 IM |
54 | /* Make it easy to share the UP and SMP code: */ |
55 | #ifndef CONFIG_X86_SMP | |
56 | unsigned int num_processors; | |
57 | unsigned disabled_cpus __cpuinitdata; | |
58 | #ifndef CONFIG_X86_LOCAL_APIC | |
59 | unsigned int boot_cpu_physical_apicid = -1U; | |
60 | #endif | |
61 | #endif | |
62 | ||
1da177e4 LT |
63 | /* |
64 | * Intel MP BIOS table parsing routines: | |
65 | */ | |
66 | ||
67 | /* | |
68 | * Checksum an MP configuration block. | |
69 | */ | |
70 | ||
71 | static int __init mpf_checksum(unsigned char *mp, int len) | |
72 | { | |
73 | int sum = 0; | |
74 | ||
75 | while (len--) | |
76 | sum += *mp++; | |
77 | ||
78 | return sum & 0xFF; | |
79 | } | |
80 | ||
0e01c00c AS |
81 | static void __cpuinit MP_processor_info(struct mpc_config_processor *m) |
82 | { | |
83 | char *bootup_cpu = ""; | |
84 | ||
85 | if (!(m->mpc_cpuflag & CPU_ENABLED)) { | |
86 | disabled_cpus++; | |
87 | return; | |
88 | } | |
89 | if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) { | |
90 | bootup_cpu = " (Bootup-CPU)"; | |
91 | boot_cpu_physical_apicid = m->mpc_apicid; | |
92 | } | |
93 | ||
94 | printk(KERN_INFO "Processor #%d%s\n", m->mpc_apicid, bootup_cpu); | |
95 | generic_processor_info(m->mpc_apicid, 0); | |
96 | } | |
97 | ||
d2953315 | 98 | static void __init MP_bus_info(struct mpc_config_bus *m) |
1da177e4 LT |
99 | { |
100 | char str[7]; | |
101 | ||
102 | memcpy(str, m->mpc_bustype, 6); | |
103 | str[6] = 0; | |
104 | Dprintk("Bus #%d is %s\n", m->mpc_busid, str); | |
105 | ||
106 | if (strncmp(str, "ISA", 3) == 0) { | |
55f05ffa | 107 | set_bit(m->mpc_busid, mp_bus_not_pci); |
1da177e4 | 108 | } else if (strncmp(str, "PCI", 3) == 0) { |
55f05ffa | 109 | clear_bit(m->mpc_busid, mp_bus_not_pci); |
1da177e4 LT |
110 | mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id; |
111 | mp_current_pci_id++; | |
1da177e4 LT |
112 | } else { |
113 | printk(KERN_ERR "Unknown bustype %s\n", str); | |
114 | } | |
115 | } | |
116 | ||
013bf2c5 AK |
117 | static int bad_ioapic(unsigned long address) |
118 | { | |
119 | if (nr_ioapics >= MAX_IO_APICS) { | |
120 | printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded " | |
d2953315 | 121 | "(found %d)\n", MAX_IO_APICS, nr_ioapics); |
013bf2c5 AK |
122 | panic("Recompile kernel with bigger MAX_IO_APICS!\n"); |
123 | } | |
124 | if (!address) { | |
125 | printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address" | |
d2953315 | 126 | " found in table, skipping!\n"); |
013bf2c5 AK |
127 | return 1; |
128 | } | |
129 | return 0; | |
130 | } | |
131 | ||
d2953315 | 132 | static void __init MP_ioapic_info(struct mpc_config_ioapic *m) |
1da177e4 LT |
133 | { |
134 | if (!(m->mpc_flags & MPC_APIC_USABLE)) | |
135 | return; | |
136 | ||
d2953315 AS |
137 | printk(KERN_INFO "I/O APIC #%d at 0x%X.\n", m->mpc_apicid, |
138 | m->mpc_apicaddr); | |
013bf2c5 AK |
139 | |
140 | if (bad_ioapic(m->mpc_apicaddr)) | |
1da177e4 | 141 | return; |
013bf2c5 | 142 | |
1da177e4 LT |
143 | mp_ioapics[nr_ioapics] = *m; |
144 | nr_ioapics++; | |
145 | } | |
146 | ||
d2953315 | 147 | static void __init MP_intsrc_info(struct mpc_config_intsrc *m) |
1da177e4 | 148 | { |
d2953315 | 149 | mp_irqs[mp_irq_entries] = *m; |
1da177e4 LT |
150 | Dprintk("Int: type %d, pol %d, trig %d, bus %d," |
151 | " IRQ %02x, APIC ID %x, APIC INT %02x\n", | |
d2953315 AS |
152 | m->mpc_irqtype, m->mpc_irqflag & 3, |
153 | (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus, | |
154 | m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq); | |
6004e1b7 | 155 | if (++mp_irq_entries >= MAX_IRQ_SOURCES) |
1da177e4 LT |
156 | panic("Max # of irq sources exceeded!!\n"); |
157 | } | |
158 | ||
d2953315 | 159 | static void __init MP_lintsrc_info(struct mpc_config_lintsrc *m) |
1da177e4 LT |
160 | { |
161 | Dprintk("Lint: type %d, pol %d, trig %d, bus %d," | |
162 | " IRQ %02x, APIC ID %x, APIC LINT %02x\n", | |
d2953315 AS |
163 | m->mpc_irqtype, m->mpc_irqflag & 3, |
164 | (m->mpc_irqflag >> 2) & 3, m->mpc_srcbusid, | |
165 | m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint); | |
1da177e4 LT |
166 | } |
167 | ||
168 | /* | |
169 | * Read/parse the MPC | |
170 | */ | |
8643f9d0 | 171 | static int __init smp_read_mpc(struct mp_config_table *mpc, unsigned early) |
1da177e4 LT |
172 | { |
173 | char str[16]; | |
d2953315 AS |
174 | int count = sizeof(*mpc); |
175 | unsigned char *mpt = ((unsigned char *)mpc) + count; | |
176 | ||
177 | if (memcmp(mpc->mpc_signature, MPC_SIGNATURE, 4)) { | |
178 | printk(KERN_ERR "MPTABLE: bad signature [%c%c%c%c]!\n", | |
179 | mpc->mpc_signature[0], | |
180 | mpc->mpc_signature[1], | |
181 | mpc->mpc_signature[2], mpc->mpc_signature[3]); | |
1da177e4 LT |
182 | return 0; |
183 | } | |
d2953315 AS |
184 | if (mpf_checksum((unsigned char *)mpc, mpc->mpc_length)) { |
185 | printk(KERN_ERR "MPTABLE: checksum error!\n"); | |
1da177e4 LT |
186 | return 0; |
187 | } | |
d2953315 | 188 | if (mpc->mpc_spec != 0x01 && mpc->mpc_spec != 0x04) { |
aecc6361 | 189 | printk(KERN_ERR "MPTABLE: bad table version (%d)!!\n", |
d2953315 | 190 | mpc->mpc_spec); |
1da177e4 LT |
191 | return 0; |
192 | } | |
193 | if (!mpc->mpc_lapic) { | |
aecc6361 | 194 | printk(KERN_ERR "MPTABLE: null local APIC address!\n"); |
1da177e4 LT |
195 | return 0; |
196 | } | |
d2953315 | 197 | memcpy(str, mpc->mpc_oem, 8); |
aecc6361 | 198 | str[8] = 0; |
d2953315 | 199 | printk(KERN_INFO "MPTABLE: OEM ID: %s ", str); |
1da177e4 | 200 | |
d2953315 | 201 | memcpy(str, mpc->mpc_productid, 12); |
aecc6361 | 202 | str[12] = 0; |
d2953315 | 203 | printk(KERN_INFO "MPTABLE: Product ID: %s ", str); |
1da177e4 | 204 | |
d2953315 | 205 | printk(KERN_INFO "MPTABLE: APIC at: 0x%X\n", mpc->mpc_lapic); |
1da177e4 LT |
206 | |
207 | /* save the local APIC address, it might be non-default */ | |
208 | if (!acpi_lapic) | |
aecc6361 | 209 | mp_lapic_addr = mpc->mpc_lapic; |
1da177e4 | 210 | |
8643f9d0 YL |
211 | if (early) |
212 | return 1; | |
213 | ||
1da177e4 | 214 | /* |
d2953315 | 215 | * Now process the configuration blocks. |
1da177e4 LT |
216 | */ |
217 | while (count < mpc->mpc_length) { | |
d2953315 AS |
218 | switch (*mpt) { |
219 | case MP_PROCESSOR: | |
1da177e4 | 220 | { |
d2953315 AS |
221 | struct mpc_config_processor *m = |
222 | (struct mpc_config_processor *)mpt; | |
1da177e4 | 223 | if (!acpi_lapic) |
aecc6361 | 224 | MP_processor_info(m); |
1da177e4 LT |
225 | mpt += sizeof(*m); |
226 | count += sizeof(*m); | |
227 | break; | |
228 | } | |
d2953315 | 229 | case MP_BUS: |
1da177e4 | 230 | { |
d2953315 AS |
231 | struct mpc_config_bus *m = |
232 | (struct mpc_config_bus *)mpt; | |
1da177e4 LT |
233 | MP_bus_info(m); |
234 | mpt += sizeof(*m); | |
235 | count += sizeof(*m); | |
236 | break; | |
237 | } | |
d2953315 | 238 | case MP_IOAPIC: |
1da177e4 | 239 | { |
d2953315 AS |
240 | struct mpc_config_ioapic *m = |
241 | (struct mpc_config_ioapic *)mpt; | |
1da177e4 | 242 | MP_ioapic_info(m); |
aecc6361 AK |
243 | mpt += sizeof(*m); |
244 | count += sizeof(*m); | |
1da177e4 LT |
245 | break; |
246 | } | |
d2953315 | 247 | case MP_INTSRC: |
1da177e4 | 248 | { |
d2953315 AS |
249 | struct mpc_config_intsrc *m = |
250 | (struct mpc_config_intsrc *)mpt; | |
1da177e4 LT |
251 | |
252 | MP_intsrc_info(m); | |
aecc6361 AK |
253 | mpt += sizeof(*m); |
254 | count += sizeof(*m); | |
1da177e4 LT |
255 | break; |
256 | } | |
d2953315 | 257 | case MP_LINTSRC: |
1da177e4 | 258 | { |
d2953315 AS |
259 | struct mpc_config_lintsrc *m = |
260 | (struct mpc_config_lintsrc *)mpt; | |
1da177e4 | 261 | MP_lintsrc_info(m); |
aecc6361 AK |
262 | mpt += sizeof(*m); |
263 | count += sizeof(*m); | |
1da177e4 LT |
264 | break; |
265 | } | |
266 | } | |
267 | } | |
3c43f039 | 268 | setup_apic_routing(); |
1da177e4 | 269 | if (!num_processors) |
aecc6361 | 270 | printk(KERN_ERR "MPTABLE: no processors registered!\n"); |
1da177e4 LT |
271 | return num_processors; |
272 | } | |
273 | ||
274 | static int __init ELCR_trigger(unsigned int irq) | |
275 | { | |
276 | unsigned int port; | |
277 | ||
278 | port = 0x4d0 + (irq >> 3); | |
279 | return (inb(port) >> (irq & 7)) & 1; | |
280 | } | |
281 | ||
282 | static void __init construct_default_ioirq_mptable(int mpc_default_type) | |
283 | { | |
284 | struct mpc_config_intsrc intsrc; | |
285 | int i; | |
286 | int ELCR_fallback = 0; | |
287 | ||
288 | intsrc.mpc_type = MP_INTSRC; | |
d2953315 | 289 | intsrc.mpc_irqflag = 0; /* conforming */ |
1da177e4 LT |
290 | intsrc.mpc_srcbus = 0; |
291 | intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid; | |
292 | ||
293 | intsrc.mpc_irqtype = mp_INT; | |
294 | ||
295 | /* | |
296 | * If true, we have an ISA/PCI system with no IRQ entries | |
297 | * in the MP table. To prevent the PCI interrupts from being set up | |
298 | * incorrectly, we try to use the ELCR. The sanity check to see if | |
299 | * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can | |
300 | * never be level sensitive, so we simply see if the ELCR agrees. | |
301 | * If it does, we assume it's valid. | |
302 | */ | |
303 | if (mpc_default_type == 5) { | |
d2953315 AS |
304 | printk(KERN_INFO "ISA/PCI bus type with no IRQ information... " |
305 | "falling back to ELCR\n"); | |
1da177e4 | 306 | |
d2953315 AS |
307 | if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || |
308 | ELCR_trigger(13)) | |
309 | printk(KERN_ERR "ELCR contains invalid data... " | |
310 | "not using ELCR\n"); | |
1da177e4 | 311 | else { |
d2953315 AS |
312 | printk(KERN_INFO |
313 | "Using ELCR to identify PCI interrupts\n"); | |
1da177e4 LT |
314 | ELCR_fallback = 1; |
315 | } | |
316 | } | |
317 | ||
318 | for (i = 0; i < 16; i++) { | |
319 | switch (mpc_default_type) { | |
320 | case 2: | |
321 | if (i == 0 || i == 13) | |
322 | continue; /* IRQ0 & IRQ13 not connected */ | |
323 | /* fall through */ | |
324 | default: | |
325 | if (i == 2) | |
326 | continue; /* IRQ2 is never connected */ | |
327 | } | |
328 | ||
329 | if (ELCR_fallback) { | |
330 | /* | |
331 | * If the ELCR indicates a level-sensitive interrupt, we | |
332 | * copy that information over to the MP table in the | |
333 | * irqflag field (level sensitive, active high polarity). | |
334 | */ | |
335 | if (ELCR_trigger(i)) | |
336 | intsrc.mpc_irqflag = 13; | |
337 | else | |
338 | intsrc.mpc_irqflag = 0; | |
339 | } | |
340 | ||
341 | intsrc.mpc_srcbusirq = i; | |
d2953315 | 342 | intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */ |
1da177e4 LT |
343 | MP_intsrc_info(&intsrc); |
344 | } | |
345 | ||
346 | intsrc.mpc_irqtype = mp_ExtINT; | |
347 | intsrc.mpc_srcbusirq = 0; | |
d2953315 | 348 | intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */ |
1da177e4 LT |
349 | MP_intsrc_info(&intsrc); |
350 | } | |
351 | ||
352 | static inline void __init construct_default_ISA_mptable(int mpc_default_type) | |
353 | { | |
354 | struct mpc_config_processor processor; | |
355 | struct mpc_config_bus bus; | |
356 | struct mpc_config_ioapic ioapic; | |
357 | struct mpc_config_lintsrc lintsrc; | |
358 | int linttypes[2] = { mp_ExtINT, mp_NMI }; | |
359 | int i; | |
360 | ||
361 | /* | |
362 | * local APIC has default address | |
363 | */ | |
364 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
365 | ||
366 | /* | |
367 | * 2 CPUs, numbered 0 & 1. | |
368 | */ | |
369 | processor.mpc_type = MP_PROCESSOR; | |
f2c2cca3 | 370 | processor.mpc_apicver = 0; |
1da177e4 | 371 | processor.mpc_cpuflag = CPU_ENABLED; |
f2c2cca3 AK |
372 | processor.mpc_cpufeature = 0; |
373 | processor.mpc_featureflag = 0; | |
1da177e4 LT |
374 | processor.mpc_reserved[0] = 0; |
375 | processor.mpc_reserved[1] = 0; | |
376 | for (i = 0; i < 2; i++) { | |
377 | processor.mpc_apicid = i; | |
378 | MP_processor_info(&processor); | |
379 | } | |
380 | ||
381 | bus.mpc_type = MP_BUS; | |
382 | bus.mpc_busid = 0; | |
383 | switch (mpc_default_type) { | |
d2953315 AS |
384 | default: |
385 | printk(KERN_ERR "???\nUnknown standard configuration %d\n", | |
386 | mpc_default_type); | |
387 | /* fall through */ | |
388 | case 1: | |
389 | case 5: | |
390 | memcpy(bus.mpc_bustype, "ISA ", 6); | |
391 | break; | |
1da177e4 LT |
392 | } |
393 | MP_bus_info(&bus); | |
394 | if (mpc_default_type > 4) { | |
395 | bus.mpc_busid = 1; | |
396 | memcpy(bus.mpc_bustype, "PCI ", 6); | |
397 | MP_bus_info(&bus); | |
398 | } | |
399 | ||
400 | ioapic.mpc_type = MP_IOAPIC; | |
401 | ioapic.mpc_apicid = 2; | |
f2c2cca3 | 402 | ioapic.mpc_apicver = 0; |
1da177e4 LT |
403 | ioapic.mpc_flags = MPC_APIC_USABLE; |
404 | ioapic.mpc_apicaddr = 0xFEC00000; | |
405 | MP_ioapic_info(&ioapic); | |
406 | ||
407 | /* | |
408 | * We set up most of the low 16 IO-APIC pins according to MPS rules. | |
409 | */ | |
410 | construct_default_ioirq_mptable(mpc_default_type); | |
411 | ||
412 | lintsrc.mpc_type = MP_LINTSRC; | |
d2953315 | 413 | lintsrc.mpc_irqflag = 0; /* conforming */ |
1da177e4 LT |
414 | lintsrc.mpc_srcbusid = 0; |
415 | lintsrc.mpc_srcbusirq = 0; | |
416 | lintsrc.mpc_destapic = MP_APIC_ALL; | |
417 | for (i = 0; i < 2; i++) { | |
418 | lintsrc.mpc_irqtype = linttypes[i]; | |
419 | lintsrc.mpc_destapiclint = i; | |
420 | MP_lintsrc_info(&lintsrc); | |
421 | } | |
422 | } | |
423 | ||
424 | static struct intel_mp_floating *mpf_found; | |
425 | ||
426 | /* | |
427 | * Scan the memory blocks for an SMP configuration block. | |
428 | */ | |
8643f9d0 | 429 | static void __init __get_smp_config(unsigned early) |
1da177e4 LT |
430 | { |
431 | struct intel_mp_floating *mpf = mpf_found; | |
432 | ||
8643f9d0 YL |
433 | if (acpi_lapic && early) |
434 | return; | |
1da177e4 | 435 | /* |
8643f9d0 YL |
436 | * ACPI supports both logical (e.g. Hyper-Threading) and physical |
437 | * processors, where MPS only supports physical. | |
438 | */ | |
439 | if (acpi_lapic && acpi_ioapic) { | |
440 | printk(KERN_INFO "Using ACPI (MADT) for SMP configuration " | |
d2953315 | 441 | "information\n"); |
8643f9d0 YL |
442 | return; |
443 | } else if (acpi_lapic) | |
444 | printk(KERN_INFO "Using ACPI for processor (LAPIC) " | |
d2953315 | 445 | "configuration information\n"); |
1da177e4 | 446 | |
8643f9d0 | 447 | printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n", |
d2953315 | 448 | mpf->mpf_specification); |
1da177e4 LT |
449 | |
450 | /* | |
451 | * Now see if we need to read further. | |
452 | */ | |
453 | if (mpf->mpf_feature1 != 0) { | |
8643f9d0 YL |
454 | if (early) { |
455 | /* | |
456 | * local APIC has default address | |
457 | */ | |
458 | mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; | |
459 | return; | |
460 | } | |
1da177e4 | 461 | |
d2953315 AS |
462 | printk(KERN_INFO "Default MP configuration #%d\n", |
463 | mpf->mpf_feature1); | |
1da177e4 LT |
464 | construct_default_ISA_mptable(mpf->mpf_feature1); |
465 | ||
466 | } else if (mpf->mpf_physptr) { | |
467 | ||
468 | /* | |
469 | * Read the physical hardware table. Anything here will | |
470 | * override the defaults. | |
471 | */ | |
8643f9d0 | 472 | if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr), early)) { |
1da177e4 | 473 | smp_found_config = 0; |
d2953315 AS |
474 | printk(KERN_ERR |
475 | "BIOS bug, MP table errors detected!...\n"); | |
476 | printk(KERN_ERR "... disabling SMP support. " | |
477 | "(tell your hw vendor)\n"); | |
1da177e4 LT |
478 | return; |
479 | } | |
8643f9d0 YL |
480 | |
481 | if (early) | |
482 | return; | |
1da177e4 LT |
483 | /* |
484 | * If there are no explicit MP IRQ entries, then we are | |
485 | * broken. We set up most of the low 16 IO-APIC pins to | |
486 | * ISA defaults and hope it will work. | |
487 | */ | |
488 | if (!mp_irq_entries) { | |
489 | struct mpc_config_bus bus; | |
490 | ||
d2953315 AS |
491 | printk(KERN_ERR "BIOS bug, no explicit IRQ entries, " |
492 | "using default mptable. " | |
493 | "(tell your hw vendor)\n"); | |
1da177e4 LT |
494 | |
495 | bus.mpc_type = MP_BUS; | |
496 | bus.mpc_busid = 0; | |
497 | memcpy(bus.mpc_bustype, "ISA ", 6); | |
498 | MP_bus_info(&bus); | |
499 | ||
500 | construct_default_ioirq_mptable(0); | |
501 | } | |
502 | ||
503 | } else | |
504 | BUG(); | |
505 | ||
8643f9d0 YL |
506 | if (!early) |
507 | printk(KERN_INFO "Processors: %d\n", num_processors); | |
1da177e4 LT |
508 | /* |
509 | * Only use the first configuration found. | |
510 | */ | |
511 | } | |
512 | ||
8643f9d0 YL |
513 | void __init early_get_smp_config(void) |
514 | { | |
515 | __get_smp_config(1); | |
516 | } | |
517 | ||
518 | void __init get_smp_config(void) | |
519 | { | |
520 | __get_smp_config(0); | |
521 | } | |
522 | ||
523 | static int __init smp_scan_config(unsigned long base, unsigned long length, | |
524 | unsigned reserve) | |
1da177e4 | 525 | { |
d2953315 | 526 | extern void __bad_mpf_size(void); |
1da177e4 LT |
527 | unsigned int *bp = phys_to_virt(base); |
528 | struct intel_mp_floating *mpf; | |
529 | ||
d2953315 | 530 | Dprintk("Scan SMP from %p for %ld bytes.\n", bp, length); |
1da177e4 LT |
531 | if (sizeof(*mpf) != 16) |
532 | __bad_mpf_size(); | |
533 | ||
534 | while (length > 0) { | |
535 | mpf = (struct intel_mp_floating *)bp; | |
536 | if ((*bp == SMP_MAGIC_IDENT) && | |
d2953315 AS |
537 | (mpf->mpf_length == 1) && |
538 | !mpf_checksum((unsigned char *)bp, 16) && | |
539 | ((mpf->mpf_specification == 1) | |
540 | || (mpf->mpf_specification == 4))) { | |
1da177e4 LT |
541 | |
542 | smp_found_config = 1; | |
8643f9d0 YL |
543 | mpf_found = mpf; |
544 | ||
545 | if (!reserve) | |
546 | return 1; | |
547 | ||
1da177e4 LT |
548 | reserve_bootmem_generic(virt_to_phys(mpf), PAGE_SIZE); |
549 | if (mpf->mpf_physptr) | |
8643f9d0 YL |
550 | reserve_bootmem_generic(mpf->mpf_physptr, |
551 | PAGE_SIZE); | |
1da177e4 LT |
552 | return 1; |
553 | } | |
554 | bp += 4; | |
555 | length -= 16; | |
556 | } | |
557 | return 0; | |
558 | } | |
559 | ||
8643f9d0 | 560 | static void __init __find_smp_config(unsigned reserve) |
1da177e4 LT |
561 | { |
562 | unsigned int address; | |
563 | ||
564 | /* | |
565 | * FIXME: Linux assumes you have 640K of base ram.. | |
566 | * this continues the error... | |
567 | * | |
568 | * 1) Scan the bottom 1K for a signature | |
569 | * 2) Scan the top 1K of base RAM | |
570 | * 3) Scan the 64K of bios | |
571 | */ | |
8643f9d0 | 572 | if (smp_scan_config(0x0, 0x400, reserve) || |
d2953315 AS |
573 | smp_scan_config(639 * 0x400, 0x400, reserve) || |
574 | smp_scan_config(0xF0000, 0x10000, reserve)) | |
1da177e4 LT |
575 | return; |
576 | /* | |
e5099134 | 577 | * If it is an SMP machine we should know now. |
1da177e4 LT |
578 | * |
579 | * there is a real-mode segmented pointer pointing to the | |
580 | * 4K EBDA area at 0x40E, calculate and scan it here. | |
581 | * | |
582 | * NOTE! There are Linux loaders that will corrupt the EBDA | |
583 | * area, and as such this kind of SMP config may be less | |
584 | * trustworthy, simply because the SMP table may have been | |
585 | * stomped on during early boot. These loaders are buggy and | |
586 | * should be fixed. | |
85e46035 AS |
587 | * |
588 | * MP1.4 SPEC states to only scan first 1K of 4K EBDA. | |
1da177e4 LT |
589 | */ |
590 | ||
ce3fe6b2 AS |
591 | address = get_bios_ebda(); |
592 | if (address) | |
85e46035 | 593 | smp_scan_config(address, 0x400, reserve); |
1da177e4 LT |
594 | } |
595 | ||
8643f9d0 YL |
596 | void __init early_find_smp_config(void) |
597 | { | |
598 | __find_smp_config(0); | |
599 | } | |
600 | ||
601 | void __init find_smp_config(void) | |
602 | { | |
603 | __find_smp_config(1); | |
604 | } | |
605 | ||
1da177e4 LT |
606 | /* -------------------------------------------------------------------------- |
607 | ACPI-based MP Configuration | |
608 | -------------------------------------------------------------------------- */ | |
609 | ||
888ba6c6 | 610 | #ifdef CONFIG_ACPI |
1da177e4 | 611 | |
efec3b9a | 612 | void __init mp_register_lapic_address(u64 address) |
1da177e4 | 613 | { |
d2953315 | 614 | mp_lapic_addr = (unsigned long)address; |
1da177e4 | 615 | set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr); |
c70dcb74 | 616 | if (boot_cpu_physical_apicid == -1U) |
05f2d12c | 617 | boot_cpu_physical_apicid = GET_APIC_ID(read_apic_id()); |
1da177e4 | 618 | } |
a65d1d64 | 619 | void __cpuinit mp_register_lapic(int id, u8 enabled) |
1da177e4 | 620 | { |
8ccab29c AS |
621 | if (!enabled) { |
622 | ++disabled_cpus; | |
623 | return; | |
624 | } | |
1da177e4 | 625 | |
468e85b9 | 626 | generic_processor_info(id, 0); |
1da177e4 LT |
627 | } |
628 | ||
be8a5685 | 629 | |
1da177e4 LT |
630 | #define MP_ISA_BUS 0 |
631 | #define MP_MAX_IOAPIC_PIN 127 | |
632 | ||
9e5c5f1d | 633 | extern struct mp_ioapic_routing mp_ioapic_routing[MAX_IO_APICS]; |
1da177e4 | 634 | |
efec3b9a | 635 | static int mp_find_ioapic(int gsi) |
1da177e4 | 636 | { |
efec3b9a | 637 | int i = 0; |
1da177e4 LT |
638 | |
639 | /* Find the IOAPIC that manages this GSI. */ | |
640 | for (i = 0; i < nr_ioapics; i++) { | |
555b0764 | 641 | if ((gsi >= mp_ioapic_routing[i].gsi_base) |
d2953315 | 642 | && (gsi <= mp_ioapic_routing[i].gsi_end)) |
1da177e4 LT |
643 | return i; |
644 | } | |
645 | ||
646 | printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); | |
1da177e4 LT |
647 | return -1; |
648 | } | |
1da177e4 | 649 | |
78b599ae AK |
650 | static u8 uniq_ioapic_id(u8 id) |
651 | { | |
652 | int i; | |
653 | DECLARE_BITMAP(used, 256); | |
654 | bitmap_zero(used, 256); | |
655 | for (i = 0; i < nr_ioapics; i++) { | |
656 | struct mpc_config_ioapic *ia = &mp_ioapics[i]; | |
657 | __set_bit(ia->mpc_apicid, used); | |
658 | } | |
659 | if (!test_bit(id, used)) | |
660 | return id; | |
661 | return find_first_zero_bit(used, 256); | |
662 | } | |
663 | ||
a65d1d64 | 664 | void __init mp_register_ioapic(int id, u32 address, u32 gsi_base) |
1da177e4 | 665 | { |
efec3b9a | 666 | int idx = 0; |
1da177e4 | 667 | |
013bf2c5 | 668 | if (bad_ioapic(address)) |
1da177e4 | 669 | return; |
1da177e4 | 670 | |
78b599ae | 671 | idx = nr_ioapics; |
1da177e4 LT |
672 | |
673 | mp_ioapics[idx].mpc_type = MP_IOAPIC; | |
674 | mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE; | |
675 | mp_ioapics[idx].mpc_apicaddr = address; | |
676 | ||
677 | set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); | |
78b599ae | 678 | mp_ioapics[idx].mpc_apicid = uniq_ioapic_id(id); |
f2c2cca3 | 679 | mp_ioapics[idx].mpc_apicver = 0; |
d2953315 | 680 | |
1da177e4 LT |
681 | /* |
682 | * Build basic IRQ lookup table to facilitate gsi->io_apic lookups | |
683 | * and to prevent reprogramming of IOAPIC pins (PCI IRQs). | |
684 | */ | |
685 | mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid; | |
555b0764 | 686 | mp_ioapic_routing[idx].gsi_base = gsi_base; |
d2953315 AS |
687 | mp_ioapic_routing[idx].gsi_end = gsi_base + |
688 | io_apic_get_redir_entries(idx); | |
1da177e4 | 689 | |
f2c2cca3 | 690 | printk(KERN_INFO "IOAPIC[%d]: apic_id %d, address 0x%x, " |
d2953315 AS |
691 | "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid, |
692 | mp_ioapics[idx].mpc_apicaddr, | |
555b0764 | 693 | mp_ioapic_routing[idx].gsi_base, |
d2953315 | 694 | mp_ioapic_routing[idx].gsi_end); |
78b599ae AK |
695 | |
696 | nr_ioapics++; | |
1da177e4 LT |
697 | } |
698 | ||
d2953315 | 699 | void __init mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi) |
1da177e4 LT |
700 | { |
701 | struct mpc_config_intsrc intsrc; | |
d2953315 AS |
702 | int ioapic = -1; |
703 | int pin = -1; | |
1da177e4 LT |
704 | |
705 | /* | |
706 | * Convert 'gsi' to 'ioapic.pin'. | |
707 | */ | |
708 | ioapic = mp_find_ioapic(gsi); | |
709 | if (ioapic < 0) | |
710 | return; | |
555b0764 | 711 | pin = gsi - mp_ioapic_routing[ioapic].gsi_base; |
1da177e4 LT |
712 | |
713 | /* | |
714 | * TBD: This check is for faulty timer entries, where the override | |
715 | * erroneously sets the trigger to level, resulting in a HUGE | |
716 | * increase of timer interrupts! | |
717 | */ | |
718 | if ((bus_irq == 0) && (trigger == 3)) | |
719 | trigger = 1; | |
720 | ||
721 | intsrc.mpc_type = MP_INTSRC; | |
722 | intsrc.mpc_irqtype = mp_INT; | |
723 | intsrc.mpc_irqflag = (trigger << 2) | polarity; | |
724 | intsrc.mpc_srcbus = MP_ISA_BUS; | |
d2953315 AS |
725 | intsrc.mpc_srcbusirq = bus_irq; /* IRQ */ |
726 | intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */ | |
727 | intsrc.mpc_dstirq = pin; /* INTIN# */ | |
1da177e4 | 728 | |
d2953315 AS |
729 | Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n", |
730 | intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3, | |
731 | (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus, | |
1da177e4 LT |
732 | intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq); |
733 | ||
734 | mp_irqs[mp_irq_entries] = intsrc; | |
735 | if (++mp_irq_entries == MAX_IRQ_SOURCES) | |
736 | panic("Max # of irq sources exceeded!\n"); | |
1da177e4 LT |
737 | } |
738 | ||
efec3b9a | 739 | void __init mp_config_acpi_legacy_irqs(void) |
1da177e4 LT |
740 | { |
741 | struct mpc_config_intsrc intsrc; | |
efec3b9a AK |
742 | int i = 0; |
743 | int ioapic = -1; | |
1da177e4 LT |
744 | |
745 | /* | |
746 | * Fabricate the legacy ISA bus (bus #31). | |
747 | */ | |
55f05ffa | 748 | set_bit(MP_ISA_BUS, mp_bus_not_pci); |
1da177e4 LT |
749 | |
750 | /* | |
751 | * Locate the IOAPIC that manages the ISA IRQs (0-15). | |
752 | */ | |
753 | ioapic = mp_find_ioapic(0); | |
754 | if (ioapic < 0) | |
755 | return; | |
756 | ||
757 | intsrc.mpc_type = MP_INTSRC; | |
d2953315 | 758 | intsrc.mpc_irqflag = 0; /* Conforming */ |
1da177e4 LT |
759 | intsrc.mpc_srcbus = MP_ISA_BUS; |
760 | intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; | |
761 | ||
762 | /* | |
763 | * Use the default configuration for the IRQs 0-15. Unless | |
764 | * overridden by (MADT) interrupt source override entries. | |
765 | */ | |
766 | for (i = 0; i < 16; i++) { | |
767 | int idx; | |
768 | ||
769 | for (idx = 0; idx < mp_irq_entries; idx++) { | |
770 | struct mpc_config_intsrc *irq = mp_irqs + idx; | |
771 | ||
772 | /* Do we already have a mapping for this ISA IRQ? */ | |
d2953315 AS |
773 | if (irq->mpc_srcbus == MP_ISA_BUS |
774 | && irq->mpc_srcbusirq == i) | |
1da177e4 LT |
775 | break; |
776 | ||
777 | /* Do we already have a mapping for this IOAPIC pin */ | |
778 | if ((irq->mpc_dstapic == intsrc.mpc_dstapic) && | |
d2953315 | 779 | (irq->mpc_dstirq == i)) |
1da177e4 LT |
780 | break; |
781 | } | |
782 | ||
783 | if (idx != mp_irq_entries) { | |
784 | printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i); | |
d2953315 | 785 | continue; /* IRQ already used */ |
1da177e4 LT |
786 | } |
787 | ||
788 | intsrc.mpc_irqtype = mp_INT; | |
d2953315 | 789 | intsrc.mpc_srcbusirq = i; /* Identity mapped */ |
1da177e4 LT |
790 | intsrc.mpc_dstirq = i; |
791 | ||
792 | Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, " | |
d2953315 AS |
793 | "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3, |
794 | (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus, | |
795 | intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, | |
1da177e4 LT |
796 | intsrc.mpc_dstirq); |
797 | ||
798 | mp_irqs[mp_irq_entries] = intsrc; | |
799 | if (++mp_irq_entries == MAX_IRQ_SOURCES) | |
800 | panic("Max # of irq sources exceeded!\n"); | |
801 | } | |
1da177e4 LT |
802 | } |
803 | ||
50eca3eb | 804 | int mp_register_gsi(u32 gsi, int triggering, int polarity) |
1da177e4 | 805 | { |
efec3b9a AK |
806 | int ioapic = -1; |
807 | int ioapic_pin = 0; | |
808 | int idx, bit = 0; | |
1da177e4 LT |
809 | |
810 | if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC) | |
811 | return gsi; | |
812 | ||
1da177e4 | 813 | /* Don't set up the ACPI SCI because it's already set up */ |
cee324b1 | 814 | if (acpi_gbl_FADT.sci_interrupt == gsi) |
1da177e4 | 815 | return gsi; |
1da177e4 LT |
816 | |
817 | ioapic = mp_find_ioapic(gsi); | |
818 | if (ioapic < 0) { | |
819 | printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi); | |
820 | return gsi; | |
821 | } | |
822 | ||
555b0764 | 823 | ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base; |
1da177e4 LT |
824 | |
825 | /* | |
826 | * Avoid pin reprogramming. PRTs typically include entries | |
827 | * with redundant pin->gsi mappings (but unique PCI devices); | |
828 | * we only program the IOAPIC on the first. | |
829 | */ | |
830 | bit = ioapic_pin % 32; | |
831 | idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32); | |
832 | if (idx > 3) { | |
833 | printk(KERN_ERR "Invalid reference to IOAPIC pin " | |
d2953315 AS |
834 | "%d-%d\n", mp_ioapic_routing[ioapic].apic_id, |
835 | ioapic_pin); | |
1da177e4 LT |
836 | return gsi; |
837 | } | |
d2953315 | 838 | if ((1 << bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) { |
1da177e4 LT |
839 | Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n", |
840 | mp_ioapic_routing[ioapic].apic_id, ioapic_pin); | |
cd1182f5 | 841 | return gsi; |
1da177e4 LT |
842 | } |
843 | ||
d2953315 | 844 | mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1 << bit); |
1da177e4 LT |
845 | |
846 | io_apic_set_pci_routing(ioapic, ioapic_pin, gsi, | |
d2953315 AS |
847 | triggering == ACPI_EDGE_SENSITIVE ? 0 : 1, |
848 | polarity == ACPI_ACTIVE_HIGH ? 0 : 1); | |
1da177e4 LT |
849 | return gsi; |
850 | } | |
d2953315 | 851 | #endif /* CONFIG_ACPI */ |