Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/ebiederm...
[deliverable/linux.git] / arch / x86 / kernel / msr.c
CommitLineData
1da177e4 1/* ----------------------------------------------------------------------- *
2b06ac86
PA
2 *
3 * Copyright 2000-2008 H. Peter Anvin - All Rights Reserved
ff55df53 4 * Copyright 2009 Intel Corporation; author: H. Peter Anvin
1da177e4
LT
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, Inc., 675 Mass Ave, Cambridge MA 02139,
9 * USA; either version 2 of the License, or (at your option) any later
10 * version; incorporated herein by reference.
11 *
12 * ----------------------------------------------------------------------- */
13
14/*
1da177e4
LT
15 * x86 MSR access device
16 *
17 * This device is accessed by lseek() to the appropriate register number
18 * and then read/write in chunks of 8 bytes. A larger size means multiple
19 * reads or writes of the same register.
20 *
21 * This driver uses /dev/cpu/%d/msr where %d is the minor number, and on
22 * an SMP box will direct the access to CPU %d.
23 */
24
951a18c6
FF
25#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26
1da177e4 27#include <linux/module.h>
1da177e4
LT
28
29#include <linux/types.h>
30#include <linux/errno.h>
31#include <linux/fcntl.h>
32#include <linux/init.h>
33#include <linux/poll.h>
34#include <linux/smp.h>
1da177e4
LT
35#include <linux/major.h>
36#include <linux/fs.h>
37#include <linux/device.h>
38#include <linux/cpu.h>
39#include <linux/notifier.h>
448dd2fa 40#include <linux/uaccess.h>
5a0e3ad6 41#include <linux/gfp.h>
1da177e4 42
cd4d09ec 43#include <asm/cpufeature.h>
1da177e4 44#include <asm/msr.h>
1da177e4 45
8874b414 46static struct class *msr_class;
1da177e4 47
94a9fa41
PC
48static ssize_t msr_read(struct file *file, char __user *buf,
49 size_t count, loff_t *ppos)
1da177e4
LT
50{
51 u32 __user *tmp = (u32 __user *) buf;
52 u32 data[2];
1da177e4 53 u32 reg = *ppos;
6131ffaa 54 int cpu = iminor(file_inode(file));
85f1cb60
PA
55 int err = 0;
56 ssize_t bytes = 0;
1da177e4
LT
57
58 if (count % 8)
59 return -EINVAL; /* Invalid chunk size */
60
6926d570 61 for (; count; count -= 8) {
78a62d2c 62 err = rdmsr_safe_on_cpu(cpu, reg, &data[0], &data[1]);
0cc0213e 63 if (err)
85f1cb60 64 break;
85f1cb60
PA
65 if (copy_to_user(tmp, &data, 8)) {
66 err = -EFAULT;
67 break;
c6f31932 68 }
1da177e4 69 tmp += 2;
85f1cb60 70 bytes += 8;
1da177e4
LT
71 }
72
85f1cb60 73 return bytes ? bytes : err;
1da177e4
LT
74}
75
76static ssize_t msr_write(struct file *file, const char __user *buf,
77 size_t count, loff_t *ppos)
78{
79 const u32 __user *tmp = (const u32 __user *)buf;
80 u32 data[2];
1da177e4 81 u32 reg = *ppos;
6131ffaa 82 int cpu = iminor(file_inode(file));
85f1cb60
PA
83 int err = 0;
84 ssize_t bytes = 0;
1da177e4
LT
85
86 if (count % 8)
87 return -EINVAL; /* Invalid chunk size */
88
f475ff35 89 for (; count; count -= 8) {
85f1cb60
PA
90 if (copy_from_user(&data, tmp, 8)) {
91 err = -EFAULT;
92 break;
93 }
78a62d2c 94 err = wrmsr_safe_on_cpu(cpu, reg, data[0], data[1]);
0cc0213e 95 if (err)
85f1cb60 96 break;
1da177e4 97 tmp += 2;
85f1cb60 98 bytes += 8;
1da177e4
LT
99 }
100
85f1cb60 101 return bytes ? bytes : err;
1da177e4
LT
102}
103
ff55df53
PA
104static long msr_ioctl(struct file *file, unsigned int ioc, unsigned long arg)
105{
106 u32 __user *uregs = (u32 __user *)arg;
107 u32 regs[8];
6131ffaa 108 int cpu = iminor(file_inode(file));
ff55df53
PA
109 int err;
110
111 switch (ioc) {
112 case X86_IOC_RDMSR_REGS:
113 if (!(file->f_mode & FMODE_READ)) {
114 err = -EBADF;
115 break;
116 }
117 if (copy_from_user(&regs, uregs, sizeof regs)) {
118 err = -EFAULT;
119 break;
120 }
121 err = rdmsr_safe_regs_on_cpu(cpu, regs);
122 if (err)
123 break;
124 if (copy_to_user(uregs, &regs, sizeof regs))
125 err = -EFAULT;
126 break;
127
128 case X86_IOC_WRMSR_REGS:
129 if (!(file->f_mode & FMODE_WRITE)) {
130 err = -EBADF;
131 break;
132 }
133 if (copy_from_user(&regs, uregs, sizeof regs)) {
134 err = -EFAULT;
135 break;
136 }
137 err = wrmsr_safe_regs_on_cpu(cpu, regs);
138 if (err)
139 break;
140 if (copy_to_user(uregs, &regs, sizeof regs))
141 err = -EFAULT;
142 break;
143
144 default:
145 err = -ENOTTY;
146 break;
147 }
148
149 return err;
150}
151
1da177e4
LT
152static int msr_open(struct inode *inode, struct file *file)
153{
6131ffaa 154 unsigned int cpu = iminor(file_inode(file));
494c2ebf 155 struct cpuinfo_x86 *c;
1da177e4 156
c903f045
AC
157 if (!capable(CAP_SYS_RAWIO))
158 return -EPERM;
159
d6c30405
FW
160 if (cpu >= nr_cpu_ids || !cpu_online(cpu))
161 return -ENXIO; /* No such CPU */
162
5119e92e
JC
163 c = &cpu_data(cpu);
164 if (!cpu_has(c, X86_FEATURE_MSR))
d6c30405
FW
165 return -EIO; /* MSR not supported */
166
167 return 0;
1da177e4
LT
168}
169
170/*
171 * File operations we support
172 */
5dfe4c96 173static const struct file_operations msr_fops = {
1da177e4 174 .owner = THIS_MODULE,
b25472f9 175 .llseek = no_seek_end_llseek,
1da177e4
LT
176 .read = msr_read,
177 .write = msr_write,
178 .open = msr_open,
ff55df53
PA
179 .unlocked_ioctl = msr_ioctl,
180 .compat_ioctl = msr_ioctl,
1da177e4
LT
181};
182
148f9bb8 183static int msr_device_create(int cpu)
1da177e4 184{
a271aaf1 185 struct device *dev;
1da177e4 186
a9b12619
GKH
187 dev = device_create(msr_class, NULL, MKDEV(MSR_MAJOR, cpu), NULL,
188 "msr%d", cpu);
cba0fdbc 189 return PTR_ERR_OR_ZERO(dev);
881a841f
AM
190}
191
192static void msr_device_destroy(int cpu)
193{
194 device_destroy(msr_class, MKDEV(MSR_MAJOR, cpu));
1da177e4
LT
195}
196
148f9bb8
PG
197static int msr_class_cpu_callback(struct notifier_block *nfb,
198 unsigned long action, void *hcpu)
1da177e4
LT
199{
200 unsigned int cpu = (unsigned long)hcpu;
881a841f 201 int err = 0;
1da177e4
LT
202
203 switch (action) {
881a841f 204 case CPU_UP_PREPARE:
881a841f 205 err = msr_device_create(cpu);
1da177e4 206 break;
881a841f 207 case CPU_UP_CANCELED:
b844eba2 208 case CPU_UP_CANCELED_FROZEN:
1da177e4 209 case CPU_DEAD:
881a841f 210 msr_device_destroy(cpu);
1da177e4
LT
211 break;
212 }
a94247e7 213 return notifier_from_errno(err);
1da177e4
LT
214}
215
c72258c7 216static struct notifier_block __refdata msr_class_cpu_notifier = {
1da177e4
LT
217 .notifier_call = msr_class_cpu_callback,
218};
219
2c9ede55 220static char *msr_devnode(struct device *dev, umode_t *mode)
07e9bb8e
KS
221{
222 return kasprintf(GFP_KERNEL, "cpu/%u/msr", MINOR(dev->devt));
223}
224
1da177e4
LT
225static int __init msr_init(void)
226{
227 int i, err = 0;
228 i = 0;
229
0b962d47 230 if (__register_chrdev(MSR_MAJOR, 0, NR_CPUS, "cpu/msr", &msr_fops)) {
951a18c6 231 pr_err("unable to get major %d for msr\n", MSR_MAJOR);
1da177e4
LT
232 err = -EBUSY;
233 goto out;
234 }
8874b414 235 msr_class = class_create(THIS_MODULE, "msr");
1da177e4
LT
236 if (IS_ERR(msr_class)) {
237 err = PTR_ERR(msr_class);
238 goto out_chrdev;
239 }
e454cea2 240 msr_class->devnode = msr_devnode;
de82a01b
SB
241
242 cpu_notifier_register_begin();
1da177e4 243 for_each_online_cpu(i) {
a271aaf1 244 err = msr_device_create(i);
1da177e4
LT
245 if (err != 0)
246 goto out_class;
247 }
de82a01b
SB
248 __register_hotcpu_notifier(&msr_class_cpu_notifier);
249 cpu_notifier_register_done();
1da177e4
LT
250
251 err = 0;
252 goto out;
253
254out_class:
255 i = 0;
256 for_each_online_cpu(i)
881a841f 257 msr_device_destroy(i);
de82a01b 258 cpu_notifier_register_done();
8874b414 259 class_destroy(msr_class);
1da177e4 260out_chrdev:
0b962d47 261 __unregister_chrdev(MSR_MAJOR, 0, NR_CPUS, "cpu/msr");
1da177e4
LT
262out:
263 return err;
264}
265
266static void __exit msr_exit(void)
267{
268 int cpu = 0;
de82a01b
SB
269
270 cpu_notifier_register_begin();
1da177e4 271 for_each_online_cpu(cpu)
881a841f 272 msr_device_destroy(cpu);
8874b414 273 class_destroy(msr_class);
da482474 274 __unregister_chrdev(MSR_MAJOR, 0, NR_CPUS, "cpu/msr");
de82a01b
SB
275 __unregister_hotcpu_notifier(&msr_class_cpu_notifier);
276 cpu_notifier_register_done();
1da177e4
LT
277}
278
279module_init(msr_init);
280module_exit(msr_exit)
281
282MODULE_AUTHOR("H. Peter Anvin <hpa@zytor.com>");
283MODULE_DESCRIPTION("x86 generic MSR driver");
284MODULE_LICENSE("GPL");
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