Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * NMI watchdog support on APIC systems |
3 | * | |
4 | * Started by Ingo Molnar <mingo@redhat.com> | |
5 | * | |
6 | * Fixes: | |
7 | * Mikael Pettersson : AMD K7 support for local APIC NMI watchdog. | |
8 | * Mikael Pettersson : Power Management for local APIC NMI watchdog. | |
1da177e4 | 9 | * Mikael Pettersson : Pentium 4 support for local APIC NMI watchdog. |
1da177e4 LT |
10 | * Pavel Machek and |
11 | * Mikael Pettersson : PM converted to driver model. Disable/enable API. | |
12 | */ | |
13 | ||
3d1ba1da IM |
14 | #include <asm/apic.h> |
15 | ||
bb81a09e | 16 | #include <linux/nmi.h> |
1da177e4 | 17 | #include <linux/mm.h> |
1da177e4 | 18 | #include <linux/delay.h> |
1da177e4 | 19 | #include <linux/interrupt.h> |
1da177e4 LT |
20 | #include <linux/module.h> |
21 | #include <linux/sysdev.h> | |
1da177e4 | 22 | #include <linux/sysctl.h> |
3e4ff115 | 23 | #include <linux/percpu.h> |
eddb6fb9 | 24 | #include <linux/kprobes.h> |
bb81a09e | 25 | #include <linux/cpumask.h> |
f8b5035b | 26 | #include <linux/kernel_stat.h> |
1eeb66a1 | 27 | #include <linux/kdebug.h> |
88ff0a47 | 28 | #include <linux/smp.h> |
1da177e4 | 29 | |
35542c5e MR |
30 | #include <asm/i8259.h> |
31 | #include <asm/io_apic.h> | |
1da177e4 | 32 | #include <asm/smp.h> |
1da177e4 | 33 | #include <asm/nmi.h> |
1da177e4 | 34 | #include <asm/proto.h> |
6e908947 | 35 | #include <asm/timer.h> |
1da177e4 | 36 | |
553f265f | 37 | #include <asm/mce.h> |
1da177e4 | 38 | |
e32ede19 GOC |
39 | #include <mach_traps.h> |
40 | ||
29cbc78b AK |
41 | int unknown_nmi_panic; |
42 | int nmi_watchdog_enabled; | |
29cbc78b | 43 | |
1714f9bf | 44 | static cpumask_t backtrace_mask = CPU_MASK_NONE; |
828f0afd | 45 | |
1da177e4 | 46 | /* nmi_active: |
f2802e7f DZ |
47 | * >0: the lapic NMI watchdog is active, but can be disabled |
48 | * <0: the lapic NMI watchdog has not been set up, and cannot | |
1da177e4 | 49 | * be enabled |
f2802e7f | 50 | * 0: the lapic NMI watchdog is disabled, but can be enabled |
1da177e4 | 51 | */ |
f2802e7f | 52 | atomic_t nmi_active = ATOMIC_INIT(0); /* oprofile uses this */ |
88ff0a47 | 53 | EXPORT_SYMBOL(nmi_active); |
1da177e4 | 54 | |
c376d454 | 55 | unsigned int nmi_watchdog = NMI_NONE; |
88ff0a47 HS |
56 | EXPORT_SYMBOL(nmi_watchdog); |
57 | ||
58 | static int panic_on_timeout; | |
1da177e4 | 59 | |
1798bc22 | 60 | static unsigned int nmi_hz = HZ; |
05cb007d | 61 | static DEFINE_PER_CPU(short, wd_enabled); |
88ff0a47 | 62 | static int endflag __initdata; |
92715e28 | 63 | |
fd5cea02 CG |
64 | static inline unsigned int get_nmi_count(int cpu) |
65 | { | |
1798bc22 CG |
66 | #ifdef CONFIG_X86_64 |
67 | return cpu_pda(cpu)->__nmi_count; | |
68 | #else | |
fd5cea02 | 69 | return nmi_count(cpu); |
1798bc22 | 70 | #endif |
fd5cea02 CG |
71 | } |
72 | ||
73 | static inline int mce_in_progress(void) | |
74 | { | |
b8e0418b | 75 | #if defined(CONFIG_X86_64) && defined(CONFIG_X86_MCE) |
1798bc22 CG |
76 | return atomic_read(&mce_entry) > 0; |
77 | #endif | |
fd5cea02 CG |
78 | return 0; |
79 | } | |
80 | ||
81 | /* | |
82 | * Take the local apic timer and PIT/HPET into account. We don't | |
83 | * know which one is active, when we have highres/dyntick on | |
84 | */ | |
85 | static inline unsigned int get_timer_irqs(int cpu) | |
86 | { | |
1798bc22 CG |
87 | #ifdef CONFIG_X86_64 |
88 | return read_pda(apic_timer_irqs) + read_pda(irq0_irqs); | |
89 | #else | |
fd5cea02 CG |
90 | return per_cpu(irq_stat, cpu).apic_timer_irqs + |
91 | per_cpu(irq_stat, cpu).irq0_irqs; | |
1798bc22 | 92 | #endif |
fd5cea02 | 93 | } |
1da177e4 | 94 | |
75152114 | 95 | #ifdef CONFIG_SMP |
1798bc22 CG |
96 | /* |
97 | * The performance counters used by NMI_LOCAL_APIC don't trigger when | |
75152114 AK |
98 | * the CPU is idle. To make sure the NMI watchdog really ticks on all |
99 | * CPUs during the test make them busy. | |
100 | */ | |
101 | static __init void nmi_cpu_busy(void *data) | |
1da177e4 | 102 | { |
366c7f55 | 103 | local_irq_enable_in_hardirq(); |
1798bc22 CG |
104 | /* |
105 | * Intentionally don't use cpu_relax here. This is | |
106 | * to make sure that the performance counter really ticks, | |
107 | * even if there is a simulator or similar that catches the | |
108 | * pause instruction. On a real HT machine this is fine because | |
109 | * all other CPUs are busy with "useless" delay loops and don't | |
110 | * care if they get somewhat less cycles. | |
111 | */ | |
92715e28 RT |
112 | while (endflag == 0) |
113 | mb(); | |
1da177e4 | 114 | } |
75152114 | 115 | #endif |
1da177e4 | 116 | |
416b7218 | 117 | int __init check_nmi_watchdog(void) |
1da177e4 | 118 | { |
29b70081 | 119 | unsigned int *prev_nmi_count; |
1da177e4 LT |
120 | int cpu; |
121 | ||
4de00436 | 122 | if (!nmi_watchdog_active() || !atomic_read(&nmi_active)) |
f2802e7f DZ |
123 | return 0; |
124 | ||
7496b606 | 125 | prev_nmi_count = kmalloc(nr_cpu_ids * sizeof(int), GFP_KERNEL); |
416b7218 | 126 | if (!prev_nmi_count) |
35542c5e | 127 | goto error; |
1da177e4 | 128 | |
416b7218 | 129 | printk(KERN_INFO "Testing NMI watchdog ... "); |
ac6b931c | 130 | |
7554c3f0 | 131 | #ifdef CONFIG_SMP |
75152114 | 132 | if (nmi_watchdog == NMI_LOCAL_APIC) |
8691e5a8 | 133 | smp_call_function(nmi_cpu_busy, (void *)&endflag, 0); |
7554c3f0 | 134 | #endif |
1da177e4 | 135 | |
c8912599 | 136 | for_each_possible_cpu(cpu) |
fd5cea02 | 137 | prev_nmi_count[cpu] = get_nmi_count(cpu); |
1da177e4 | 138 | local_irq_enable(); |
1798bc22 | 139 | mdelay((20 * 1000) / nmi_hz); /* wait 20 ticks */ |
1da177e4 | 140 | |
394e3902 | 141 | for_each_online_cpu(cpu) { |
05cb007d | 142 | if (!per_cpu(wd_enabled, cpu)) |
f2802e7f | 143 | continue; |
fd5cea02 | 144 | if (get_nmi_count(cpu) - prev_nmi_count[cpu] <= 5) { |
75bc122c | 145 | printk(KERN_WARNING "WARNING: CPU#%d: NMI " |
75bc122c | 146 | "appears to be stuck (%d->%d)!\n", |
416b7218 HS |
147 | cpu, |
148 | prev_nmi_count[cpu], | |
fd5cea02 | 149 | get_nmi_count(cpu)); |
05cb007d | 150 | per_cpu(wd_enabled, cpu) = 0; |
f2802e7f | 151 | atomic_dec(&nmi_active); |
1da177e4 LT |
152 | } |
153 | } | |
416b7218 | 154 | endflag = 1; |
f2802e7f | 155 | if (!atomic_read(&nmi_active)) { |
416b7218 | 156 | kfree(prev_nmi_count); |
f2802e7f | 157 | atomic_set(&nmi_active, -1); |
35542c5e | 158 | goto error; |
f2802e7f | 159 | } |
1da177e4 LT |
160 | printk("OK.\n"); |
161 | ||
1798bc22 CG |
162 | /* |
163 | * now that we know it works we can reduce NMI frequency to | |
164 | * something more reasonable; makes a difference in some configs | |
165 | */ | |
05cb007d AK |
166 | if (nmi_watchdog == NMI_LOCAL_APIC) |
167 | nmi_hz = lapic_adjust_nmi_hz(1); | |
1da177e4 | 168 | |
416b7218 | 169 | kfree(prev_nmi_count); |
1da177e4 | 170 | return 0; |
35542c5e MR |
171 | error: |
172 | if (nmi_watchdog == NMI_IO_APIC && !timer_through_8259) | |
173 | disable_8259A_irq(0); | |
5b4d2386 MR |
174 | #ifdef CONFIG_X86_32 |
175 | timer_ack = 0; | |
176 | #endif | |
35542c5e | 177 | return -1; |
1da177e4 LT |
178 | } |
179 | ||
867ab545 | 180 | static int __init setup_nmi_watchdog(char *str) |
1da177e4 | 181 | { |
2b6addad | 182 | unsigned int nmi; |
1da177e4 | 183 | |
d1b946b9 | 184 | if (!strncmp(str, "panic", 5)) { |
1da177e4 LT |
185 | panic_on_timeout = 1; |
186 | str = strchr(str, ','); | |
187 | if (!str) | |
188 | return 1; | |
189 | ++str; | |
190 | } | |
191 | ||
192 | get_option(&str, &nmi); | |
193 | ||
2b6addad | 194 | if (nmi >= NMI_INVALID) |
1da177e4 | 195 | return 0; |
f2802e7f | 196 | |
75152114 | 197 | nmi_watchdog = nmi; |
1da177e4 LT |
198 | return 1; |
199 | } | |
1da177e4 LT |
200 | __setup("nmi_watchdog=", setup_nmi_watchdog); |
201 | ||
1798bc22 CG |
202 | /* |
203 | * Suspend/resume support | |
204 | */ | |
1da177e4 LT |
205 | #ifdef CONFIG_PM |
206 | ||
207 | static int nmi_pm_active; /* nmi_active before suspend */ | |
208 | ||
829ca9a3 | 209 | static int lapic_nmi_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 | 210 | { |
4038f901 | 211 | /* only CPU0 goes here, other CPUs should be offline */ |
f2802e7f | 212 | nmi_pm_active = atomic_read(&nmi_active); |
4038f901 SL |
213 | stop_apic_nmi_watchdog(NULL); |
214 | BUG_ON(atomic_read(&nmi_active) != 0); | |
1da177e4 LT |
215 | return 0; |
216 | } | |
217 | ||
218 | static int lapic_nmi_resume(struct sys_device *dev) | |
219 | { | |
4038f901 SL |
220 | /* only CPU0 goes here, other CPUs should be offline */ |
221 | if (nmi_pm_active > 0) { | |
222 | setup_apic_nmi_watchdog(NULL); | |
223 | touch_nmi_watchdog(); | |
224 | } | |
1da177e4 LT |
225 | return 0; |
226 | } | |
227 | ||
228 | static struct sysdev_class nmi_sysclass = { | |
af5ca3f4 | 229 | .name = "lapic_nmi", |
1da177e4 LT |
230 | .resume = lapic_nmi_resume, |
231 | .suspend = lapic_nmi_suspend, | |
232 | }; | |
233 | ||
234 | static struct sys_device device_lapic_nmi = { | |
416b7218 | 235 | .id = 0, |
1da177e4 LT |
236 | .cls = &nmi_sysclass, |
237 | }; | |
238 | ||
239 | static int __init init_lapic_nmi_sysfs(void) | |
240 | { | |
241 | int error; | |
242 | ||
1798bc22 CG |
243 | /* |
244 | * should really be a BUG_ON but b/c this is an | |
f2802e7f DZ |
245 | * init call, it just doesn't work. -dcz |
246 | */ | |
247 | if (nmi_watchdog != NMI_LOCAL_APIC) | |
248 | return 0; | |
249 | ||
416b7218 | 250 | if (atomic_read(&nmi_active) < 0) |
1da177e4 LT |
251 | return 0; |
252 | ||
253 | error = sysdev_class_register(&nmi_sysclass); | |
254 | if (!error) | |
255 | error = sysdev_register(&device_lapic_nmi); | |
256 | return error; | |
257 | } | |
1798bc22 | 258 | |
1da177e4 LT |
259 | /* must come after the local APIC's device_initcall() */ |
260 | late_initcall(init_lapic_nmi_sysfs); | |
261 | ||
262 | #endif /* CONFIG_PM */ | |
263 | ||
416b7218 HS |
264 | static void __acpi_nmi_enable(void *__unused) |
265 | { | |
593f4a78 | 266 | apic_write(APIC_LVT0, APIC_DM_NMI); |
416b7218 HS |
267 | } |
268 | ||
269 | /* | |
270 | * Enable timer based NMIs on all CPUs: | |
271 | */ | |
272 | void acpi_nmi_enable(void) | |
273 | { | |
274 | if (atomic_read(&nmi_active) && nmi_watchdog == NMI_IO_APIC) | |
15c8b6c1 | 275 | on_each_cpu(__acpi_nmi_enable, NULL, 1); |
416b7218 HS |
276 | } |
277 | ||
278 | static void __acpi_nmi_disable(void *__unused) | |
279 | { | |
593f4a78 | 280 | apic_write(APIC_LVT0, APIC_DM_NMI | APIC_LVT_MASKED); |
416b7218 HS |
281 | } |
282 | ||
283 | /* | |
284 | * Disable timer based NMIs on all CPUs: | |
285 | */ | |
286 | void acpi_nmi_disable(void) | |
287 | { | |
288 | if (atomic_read(&nmi_active) && nmi_watchdog == NMI_IO_APIC) | |
15c8b6c1 | 289 | on_each_cpu(__acpi_nmi_disable, NULL, 1); |
416b7218 HS |
290 | } |
291 | ||
f2802e7f DZ |
292 | void setup_apic_nmi_watchdog(void *unused) |
293 | { | |
416b7218 | 294 | if (__get_cpu_var(wd_enabled)) |
4038f901 SL |
295 | return; |
296 | ||
297 | /* cheap hack to support suspend/resume */ | |
298 | /* if cpu0 is not active neither should the other cpus */ | |
1798bc22 | 299 | if (smp_processor_id() != 0 && atomic_read(&nmi_active) <= 0) |
4038f901 SL |
300 | return; |
301 | ||
05cb007d AK |
302 | switch (nmi_watchdog) { |
303 | case NMI_LOCAL_APIC: | |
1798bc22 | 304 | /* enable it before to avoid race with handler */ |
05cb007d AK |
305 | __get_cpu_var(wd_enabled) = 1; |
306 | if (lapic_watchdog_init(nmi_hz) < 0) { | |
307 | __get_cpu_var(wd_enabled) = 0; | |
75152114 | 308 | return; |
f2802e7f | 309 | } |
05cb007d AK |
310 | /* FALL THROUGH */ |
311 | case NMI_IO_APIC: | |
312 | __get_cpu_var(wd_enabled) = 1; | |
313 | atomic_inc(&nmi_active); | |
f2802e7f | 314 | } |
f2802e7f | 315 | } |
75152114 | 316 | |
4038f901 | 317 | void stop_apic_nmi_watchdog(void *unused) |
f2802e7f DZ |
318 | { |
319 | /* only support LOCAL and IO APICs for now */ | |
4de00436 | 320 | if (!nmi_watchdog_active()) |
1798bc22 | 321 | return; |
05cb007d | 322 | if (__get_cpu_var(wd_enabled) == 0) |
4038f901 | 323 | return; |
05cb007d AK |
324 | if (nmi_watchdog == NMI_LOCAL_APIC) |
325 | lapic_watchdog_stop(); | |
326 | __get_cpu_var(wd_enabled) = 0; | |
f2802e7f | 327 | atomic_dec(&nmi_active); |
1da177e4 LT |
328 | } |
329 | ||
330 | /* | |
331 | * the best way to detect whether a CPU has a 'hard lockup' problem | |
332 | * is to check it's local APIC timer IRQ counts. If they are not | |
333 | * changing then that CPU has some problem. | |
334 | * | |
335 | * as these watchdog NMI IRQs are generated on every CPU, we only | |
336 | * have to check the current processor. | |
1da177e4 LT |
337 | * |
338 | * since NMIs don't listen to _any_ locks, we have to be extremely | |
339 | * careful not to rely on unsafe variables. The printk might lock | |
340 | * up though, so we have to break up any console locks first ... | |
1798bc22 | 341 | * [when there will be more tty-related locks, break them up here too!] |
1da177e4 LT |
342 | */ |
343 | ||
75152114 AK |
344 | static DEFINE_PER_CPU(unsigned, last_irq_sum); |
345 | static DEFINE_PER_CPU(local_t, alert_counter); | |
346 | static DEFINE_PER_CPU(int, nmi_touch); | |
1da177e4 | 347 | |
567f3e42 | 348 | void touch_nmi_watchdog(void) |
1da177e4 | 349 | { |
4de00436 | 350 | if (nmi_watchdog_active()) { |
99019e91 | 351 | unsigned cpu; |
1da177e4 | 352 | |
99019e91 | 353 | /* |
f784946d | 354 | * Tell other CPUs to reset their alert counters. We cannot |
99019e91 JB |
355 | * do it ourselves because the alert count increase is not |
356 | * atomic. | |
357 | */ | |
567f3e42 AM |
358 | for_each_present_cpu(cpu) { |
359 | if (per_cpu(nmi_touch, cpu) != 1) | |
360 | per_cpu(nmi_touch, cpu) = 1; | |
361 | } | |
99019e91 | 362 | } |
8446f1d3 | 363 | |
8446f1d3 IM |
364 | /* |
365 | * Tickle the softlockup detector too: | |
366 | */ | |
416b7218 | 367 | touch_softlockup_watchdog(); |
1da177e4 | 368 | } |
416b7218 | 369 | EXPORT_SYMBOL(touch_nmi_watchdog); |
1da177e4 | 370 | |
5deb45e3 SR |
371 | notrace __kprobes int |
372 | nmi_watchdog_tick(struct pt_regs *regs, unsigned reason) | |
1da177e4 | 373 | { |
1da177e4 LT |
374 | /* |
375 | * Since current_thread_info()-> is always on the stack, and we | |
376 | * always switch the stack NMI-atomically, it's safe to use | |
377 | * smp_processor_id(). | |
378 | */ | |
b791ccef | 379 | unsigned int sum; |
75152114 | 380 | int touched = 0; |
bb81a09e | 381 | int cpu = smp_processor_id(); |
05cb007d | 382 | int rc = 0; |
f2802e7f DZ |
383 | |
384 | /* check for other users first */ | |
385 | if (notify_die(DIE_NMI, "nmi", regs, reason, 2, SIGINT) | |
386 | == NOTIFY_STOP) { | |
3adbbcce | 387 | rc = 1; |
f2802e7f DZ |
388 | touched = 1; |
389 | } | |
1da177e4 | 390 | |
fd5cea02 CG |
391 | sum = get_timer_irqs(cpu); |
392 | ||
75152114 AK |
393 | if (__get_cpu_var(nmi_touch)) { |
394 | __get_cpu_var(nmi_touch) = 0; | |
395 | touched = 1; | |
396 | } | |
f2802e7f | 397 | |
bb81a09e AM |
398 | if (cpu_isset(cpu, backtrace_mask)) { |
399 | static DEFINE_SPINLOCK(lock); /* Serialise the printks */ | |
400 | ||
401 | spin_lock(&lock); | |
88ff0a47 | 402 | printk(KERN_WARNING "NMI backtrace for cpu %d\n", cpu); |
bb81a09e AM |
403 | dump_stack(); |
404 | spin_unlock(&lock); | |
405 | cpu_clear(cpu, backtrace_mask); | |
406 | } | |
407 | ||
fd5cea02 CG |
408 | /* Could check oops_in_progress here too, but it's safer not to */ |
409 | if (mce_in_progress()) | |
553f265f | 410 | touched = 1; |
1da177e4 | 411 | |
f8b5035b | 412 | /* if the none of the timers isn't firing, this cpu isn't doing much */ |
75152114 | 413 | if (!touched && __get_cpu_var(last_irq_sum) == sum) { |
1da177e4 LT |
414 | /* |
415 | * Ayiee, looks like this CPU is stuck ... | |
416 | * wait a few IRQs (5 seconds) before doing the oops ... | |
417 | */ | |
75152114 | 418 | local_inc(&__get_cpu_var(alert_counter)); |
1798bc22 | 419 | if (local_read(&__get_cpu_var(alert_counter)) == 5 * nmi_hz) |
748f2edb GA |
420 | /* |
421 | * die_nmi will return ONLY if NOTIFY_STOP happens.. | |
422 | */ | |
ddca03c9 | 423 | die_nmi("BUG: NMI Watchdog detected LOCKUP", |
d1b946b9 | 424 | regs, panic_on_timeout); |
1da177e4 | 425 | } else { |
75152114 AK |
426 | __get_cpu_var(last_irq_sum) = sum; |
427 | local_set(&__get_cpu_var(alert_counter), 0); | |
1da177e4 | 428 | } |
f2802e7f DZ |
429 | |
430 | /* see if the nmi watchdog went off */ | |
05cb007d AK |
431 | if (!__get_cpu_var(wd_enabled)) |
432 | return rc; | |
433 | switch (nmi_watchdog) { | |
434 | case NMI_LOCAL_APIC: | |
435 | rc |= lapic_wd_event(nmi_hz); | |
436 | break; | |
437 | case NMI_IO_APIC: | |
1798bc22 CG |
438 | /* |
439 | * don't know how to accurately check for this. | |
05cb007d AK |
440 | * just assume it was a watchdog timer interrupt |
441 | * This matches the old behaviour. | |
442 | */ | |
443 | rc = 1; | |
444 | break; | |
75152114 | 445 | } |
3adbbcce | 446 | return rc; |
1da177e4 LT |
447 | } |
448 | ||
1da177e4 LT |
449 | #ifdef CONFIG_SYSCTL |
450 | ||
e3a61b0a | 451 | static int __init setup_unknown_nmi_panic(char *str) |
8f4e956b | 452 | { |
e3a61b0a SA |
453 | unknown_nmi_panic = 1; |
454 | return 1; | |
8f4e956b | 455 | } |
e3a61b0a | 456 | __setup("unknown_nmi_panic", setup_unknown_nmi_panic); |
1da177e4 LT |
457 | |
458 | static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu) | |
459 | { | |
460 | unsigned char reason = get_nmi_reason(); | |
461 | char buf[64]; | |
462 | ||
2fbe7b25 | 463 | sprintf(buf, "NMI received for unknown reason %02x\n", reason); |
6c8decdf | 464 | die_nmi(buf, regs, 1); /* Always panic here */ |
1da177e4 LT |
465 | return 0; |
466 | } | |
467 | ||
407984f1 DZ |
468 | /* |
469 | * proc handler for /proc/sys/kernel/nmi | |
470 | */ | |
471 | int proc_nmi_enabled(struct ctl_table *table, int write, struct file *file, | |
472 | void __user *buffer, size_t *length, loff_t *ppos) | |
473 | { | |
474 | int old_state; | |
475 | ||
476 | nmi_watchdog_enabled = (atomic_read(&nmi_active) > 0) ? 1 : 0; | |
477 | old_state = nmi_watchdog_enabled; | |
478 | proc_dointvec(table, write, file, buffer, length, ppos); | |
479 | if (!!old_state == !!nmi_watchdog_enabled) | |
480 | return 0; | |
481 | ||
4de00436 | 482 | if (atomic_read(&nmi_active) < 0 || !nmi_watchdog_active()) { |
1798bc22 CG |
483 | printk(KERN_WARNING |
484 | "NMI watchdog is permanently disabled\n"); | |
e33e89ab | 485 | return -EIO; |
407984f1 DZ |
486 | } |
487 | ||
e33e89ab | 488 | if (nmi_watchdog == NMI_LOCAL_APIC) { |
407984f1 DZ |
489 | if (nmi_watchdog_enabled) |
490 | enable_lapic_nmi_watchdog(); | |
491 | else | |
492 | disable_lapic_nmi_watchdog(); | |
407984f1 | 493 | } else { |
1798bc22 | 494 | printk(KERN_WARNING |
407984f1 DZ |
495 | "NMI watchdog doesn't know what hardware to touch\n"); |
496 | return -EIO; | |
497 | } | |
498 | return 0; | |
499 | } | |
500 | ||
1798bc22 | 501 | #endif /* CONFIG_SYSCTL */ |
1da177e4 | 502 | |
a062bae9 LZ |
503 | int do_nmi_callback(struct pt_regs *regs, int cpu) |
504 | { | |
505 | #ifdef CONFIG_SYSCTL | |
506 | if (unknown_nmi_panic) | |
507 | return unknown_nmi_panic_callback(regs, cpu); | |
508 | #endif | |
509 | return 0; | |
510 | } | |
511 | ||
bb81a09e AM |
512 | void __trigger_all_cpu_backtrace(void) |
513 | { | |
514 | int i; | |
515 | ||
516 | backtrace_mask = cpu_online_map; | |
517 | /* Wait for up to 10 seconds for all CPUs to do the backtrace */ | |
518 | for (i = 0; i < 10 * 1000; i++) { | |
519 | if (cpus_empty(backtrace_mask)) | |
520 | break; | |
521 | mdelay(1); | |
522 | } | |
523 | } |