[deliverable/linux.git] / arch / x86 / kernel / pci-dma.c

#include <linux/dma-mapping.h>
#include <linux/dmar.h>
#include <linux/bootmem.h>
#include <linux/pci.h>

#include <asm/proto.h>
#include <asm/dma.h>
#include <asm/iommu.h>
#include <asm/calgary.h>
#include <asm/amd_iommu.h>

static int forbid_dac __read_mostly;

struct dma_mapping_ops *dma_ops;
EXPORT_SYMBOL(dma_ops);

static int iommu_sac_force __read_mostly;

#ifdef CONFIG_IOMMU_DEBUG
int panic_on_overflow __read_mostly = 1;
int force_iommu __read_mostly = 1;
#else
int panic_on_overflow __read_mostly = 0;
int force_iommu __read_mostly = 0;
#endif

int iommu_merge __read_mostly = 0;

int no_iommu __read_mostly;
/* Set this to 1 if there is a HW IOMMU in the system */
int iommu_detected __read_mostly = 0;

/* This tells the BIO block layer to assume merging. Default to off
   because we cannot guarantee merging later. */
int iommu_bio_merge __read_mostly = 0;
EXPORT_SYMBOL(iommu_bio_merge);

dma_addr_t bad_dma_address __read_mostly = 0;
EXPORT_SYMBOL(bad_dma_address);

/* Dummy device used for NULL arguments (normally ISA). Better would
   be probably a smaller DMA mask, but this is bug-to-bug compatible
   to older i386. */
struct device x86_dma_fallback_dev = {
	.bus_id = "fallback device",
	.coherent_dma_mask = DMA_32BIT_MASK,
	.dma_mask = &x86_dma_fallback_dev.coherent_dma_mask,
};
EXPORT_SYMBOL(x86_dma_fallback_dev);

int dma_set_mask(struct device *dev, u64 mask)
{
	if (!dev->dma_mask || !dma_supported(dev, mask))
		return -EIO;

	*dev->dma_mask = mask;

	return 0;
}
EXPORT_SYMBOL(dma_set_mask);

#ifdef CONFIG_X86_64
static __initdata void *dma32_bootmem_ptr;
static unsigned long dma32_bootmem_size __initdata = (128ULL<<20);

static int __init parse_dma32_size_opt(char *p)
{
	if (!p)
		return -EINVAL;
	dma32_bootmem_size = memparse(p, &p);
	return 0;
}
early_param("dma32_size", parse_dma32_size_opt);

void __init dma32_reserve_bootmem(void)
{
	unsigned long size, align;
	if (max_pfn <= MAX_DMA32_PFN)
		return;

	/*
	 * check aperture_64.c allocate_aperture() for reason about
	 * using 512M as goal
	 */
	align = 64ULL<<20;
	size = roundup(dma32_bootmem_size, align);
	dma32_bootmem_ptr = __alloc_bootmem_nopanic(size, align,
				 512ULL<<20);
	if (dma32_bootmem_ptr)
		dma32_bootmem_size = size;
	else
		dma32_bootmem_size = 0;
}
static void __init dma32_free_bootmem(void)
{

	if (max_pfn <= MAX_DMA32_PFN)
		return;

	if (!dma32_bootmem_ptr)
		return;

	free_bootmem(__pa(dma32_bootmem_ptr), dma32_bootmem_size);

	dma32_bootmem_ptr = NULL;
	dma32_bootmem_size = 0;
}
#endif

void __init pci_iommu_alloc(void)
{
#ifdef CONFIG_X86_64
	/* free the range so iommu could get some range less than 4G */
	dma32_free_bootmem();
#endif

	/*
	 * The order of these functions is important for
	 * fall-back/fail-over reasons
	 */
	gart_iommu_hole_init();

	detect_calgary();

	detect_intel_iommu();

	amd_iommu_detect();

	pci_swiotlb_init();
}

void *dma_generic_alloc_coherent(struct device *dev, size_t size,
				 dma_addr_t *dma_addr, gfp_t flag)
{
	unsigned long dma_mask;
	struct page *page;
	dma_addr_t addr;

	dma_mask = dma_alloc_coherent_mask(dev, flag);

	flag |= __GFP_ZERO;
again:
	page = alloc_pages_node(dev_to_node(dev), flag, get_order(size));
	if (!page)
		return NULL;

	addr = page_to_phys(page);
	if (!is_buffer_dma_capable(dma_mask, addr, size)) {
		__free_pages(page, get_order(size));

		if (dma_mask < DMA_32BIT_MASK && !(flag & GFP_DMA)) {
			flag = (flag & ~GFP_DMA32) | GFP_DMA;
			goto again;
		}

		return NULL;
	}

	*dma_addr = addr;
	return page_address(page);
}

/*
 * See <Documentation/x86_64/boot-options.txt> for the iommu kernel parameter
 * documentation.
 */
static __init int iommu_setup(char *p)
{
	iommu_merge = 1;

	if (!p)
		return -EINVAL;

	while (*p) {
		if (!strncmp(p, "off", 3))
			no_iommu = 1;
		/* gart_parse_options has more force support */
		if (!strncmp(p, "force", 5))
			force_iommu = 1;
		if (!strncmp(p, "noforce", 7)) {
			iommu_merge = 0;
			force_iommu = 0;
		}

		if (!strncmp(p, "biomerge", 8)) {
			iommu_bio_merge = 4096;
			iommu_merge = 1;
			force_iommu = 1;
		}
		if (!strncmp(p, "panic", 5))
			panic_on_overflow = 1;
		if (!strncmp(p, "nopanic", 7))
			panic_on_overflow = 0;
		if (!strncmp(p, "merge", 5)) {
			iommu_merge = 1;
			force_iommu = 1;
		}
		if (!strncmp(p, "nomerge", 7))
			iommu_merge = 0;
		if (!strncmp(p, "forcesac", 8))
			iommu_sac_force = 1;
		if (!strncmp(p, "allowdac", 8))
			forbid_dac = 0;
		if (!strncmp(p, "nodac", 5))
			forbid_dac = -1;
		if (!strncmp(p, "usedac", 6)) {
			forbid_dac = -1;
			return 1;
		}
#ifdef CONFIG_SWIOTLB
		if (!strncmp(p, "soft", 4))
			swiotlb = 1;
#endif

		gart_parse_options(p);

#ifdef CONFIG_CALGARY_IOMMU
		if (!strncmp(p, "calgary", 7))
			use_calgary = 1;
#endif /* CONFIG_CALGARY_IOMMU */

		p += strcspn(p, ",");
		if (*p == ',')
			++p;
	}
	return 0;
}
early_param("iommu", iommu_setup);

int dma_supported(struct device *dev, u64 mask)
{
	struct dma_mapping_ops *ops = get_dma_ops(dev);

#ifdef CONFIG_PCI
	if (mask > 0xffffffff && forbid_dac > 0) {
		dev_info(dev, "PCI: Disallowing DAC for device\n");
		return 0;
	}
#endif

	if (ops->dma_supported)
		return ops->dma_supported(dev, mask);

	/* Copied from i386. Doesn't make much sense, because it will
	   only work for pci_alloc_coherent.
	   The caller just has to use GFP_DMA in this case. */
	if (mask < DMA_24BIT_MASK)
		return 0;

	/* Tell the device to use SAC when IOMMU force is on.  This
	   allows the driver to use cheaper accesses in some cases.

	   Problem with this is that if we overflow the IOMMU area and
	   return DAC as fallback address the device may not handle it
	   correctly.

	   As a special case some controllers have a 39bit address
	   mode that is as efficient as 32bit (aic79xx). Don't force
	   SAC for these.  Assume all masks <= 40 bits are of this
	   type. Normally this doesn't make any difference, but gives
	   more gentle handling of IOMMU overflow. */
	if (iommu_sac_force && (mask >= DMA_40BIT_MASK)) {
		dev_info(dev, "Force SAC with mask %Lx\n", mask);
		return 0;
	}

	return 1;
}
EXPORT_SYMBOL(dma_supported);

static int __init pci_iommu_init(void)
{
	calgary_iommu_init();

	intel_iommu_init();

	amd_iommu_init();

	gart_iommu_init();

	no_iommu_init();
	return 0;
}

void pci_iommu_shutdown(void)
{
	gart_iommu_shutdown();
}
/* Must execute after PCI subsystem */
fs_initcall(pci_iommu_init);

#ifdef CONFIG_PCI
/* Many VIA bridges seem to corrupt data for DAC. Disable it here */

static __devinit void via_no_dac(struct pci_dev *dev)
{
	if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI && forbid_dac == 0) {
		printk(KERN_INFO "PCI: VIA PCI bridge detected."
				 "Disabling DAC.\n");
		forbid_dac = 1;
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_ANY_ID, via_no_dac);
#endif
Commit	Line	Data
459121c9	1	#include <linux/dma-mapping.h>
cb5867a5	2	#include <linux/dmar.h>
116890d5	3	#include <linux/bootmem.h>
bca5c096	4	#include <linux/pci.h>
cb5867a5	5
116890d5 GC	6	#include <asm/proto.h>
116890d5 GC	7	#include <asm/dma.h>
46a7fa27	8	#include <asm/iommu.h>
cb5867a5	9	#include <asm/calgary.h>
a69ca340	10	#include <asm/amd_iommu.h>
459121c9	11
3b15e581 FY	12	static int forbid_dac __read_mostly;
3b15e581 FY	13
8d8bb39b	14	struct dma_mapping_ops *dma_ops;
85c246ee GC	15	EXPORT_SYMBOL(dma_ops);
85c246ee GC	16
b4cdc430	17	static int iommu_sac_force __read_mostly;
8e0c3797	18
f9c258de GC	19	#ifdef CONFIG_IOMMU_DEBUG
	20	int panic_on_overflow __read_mostly = 1;
	21	int force_iommu __read_mostly = 1;
	22	#else
	23	int panic_on_overflow __read_mostly = 0;
	24	int force_iommu __read_mostly = 0;
	25	#endif
	26
fae9a0d8 GC	27	int iommu_merge __read_mostly = 0;
	28
	29	int no_iommu __read_mostly;
	30	/* Set this to 1 if there is a HW IOMMU in the system */
	31	int iommu_detected __read_mostly = 0;
	32
	33	/* This tells the BIO block layer to assume merging. Default to off
	34	because we cannot guarantee merging later. */
	35	int iommu_bio_merge __read_mostly = 0;
	36	EXPORT_SYMBOL(iommu_bio_merge);
	37
cac67877 GC	38	dma_addr_t bad_dma_address __read_mostly = 0;
cac67877 GC	39	EXPORT_SYMBOL(bad_dma_address);
fae9a0d8	40
098cb7f2 GC	41	/* Dummy device used for NULL arguments (normally ISA). Better would
	42	be probably a smaller DMA mask, but this is bug-to-bug compatible
	43	to older i386. */
6c505ce3	44	struct device x86_dma_fallback_dev = {
098cb7f2 GC	45	.bus_id = "fallback device",
098cb7f2 GC	46	.coherent_dma_mask = DMA_32BIT_MASK,
6c505ce3	47	.dma_mask = &x86_dma_fallback_dev.coherent_dma_mask,
098cb7f2	48	};
6c505ce3	49	EXPORT_SYMBOL(x86_dma_fallback_dev);
098cb7f2	50
459121c9 GC	51	int dma_set_mask(struct device *dev, u64 mask)
	52	{
	53	if (!dev->dma_mask \|\| !dma_supported(dev, mask))
	54	return -EIO;
	55
	56	*dev->dma_mask = mask;
	57
	58	return 0;
	59	}
	60	EXPORT_SYMBOL(dma_set_mask);
	61
116890d5 GC	62	#ifdef CONFIG_X86_64
	63	static __initdata void *dma32_bootmem_ptr;
	64	static unsigned long dma32_bootmem_size __initdata = (128ULL<<20);
	65
	66	static int __init parse_dma32_size_opt(char *p)
	67	{
	68	if (!p)
	69	return -EINVAL;
	70	dma32_bootmem_size = memparse(p, &p);
	71	return 0;
	72	}
	73	early_param("dma32_size", parse_dma32_size_opt);
	74
	75	void __init dma32_reserve_bootmem(void)
	76	{
	77	unsigned long size, align;
c987d12f	78	if (max_pfn <= MAX_DMA32_PFN)
116890d5 GC	79	return;
116890d5 GC	80
7677b2ef YL	81	/*
	82	* check aperture_64.c allocate_aperture() for reason about
	83	* using 512M as goal
	84	*/
116890d5	85	align = 64ULL<<20;
1ddb5518	86	size = roundup(dma32_bootmem_size, align);
116890d5	87	dma32_bootmem_ptr = __alloc_bootmem_nopanic(size, align,
7677b2ef	88	512ULL<<20);
116890d5 GC	89	if (dma32_bootmem_ptr)
	90	dma32_bootmem_size = size;
	91	else
	92	dma32_bootmem_size = 0;
	93	}
	94	static void __init dma32_free_bootmem(void)
	95	{
116890d5	96
c987d12f	97	if (max_pfn <= MAX_DMA32_PFN)
116890d5 GC	98	return;
	99
	100	if (!dma32_bootmem_ptr)
	101	return;
	102
330fce23	103	free_bootmem(__pa(dma32_bootmem_ptr), dma32_bootmem_size);
116890d5 GC	104
	105	dma32_bootmem_ptr = NULL;
	106	dma32_bootmem_size = 0;
	107	}
cfb80c9e	108	#endif
116890d5 GC	109
	110	void __init pci_iommu_alloc(void)
	111	{
cfb80c9e	112	#ifdef CONFIG_X86_64
116890d5 GC	113	/* free the range so iommu could get some range less than 4G */
116890d5 GC	114	dma32_free_bootmem();
cfb80c9e JF	115	#endif
cfb80c9e JF	116
116890d5 GC	117	/*
	118	* The order of these functions is important for
	119	* fall-back/fail-over reasons
	120	*/
116890d5	121	gart_iommu_hole_init();
116890d5	122
116890d5	123	detect_calgary();
116890d5 GC	124
	125	detect_intel_iommu();
	126
a69ca340 JR	127	amd_iommu_detect();
a69ca340 JR	128
116890d5	129	pci_swiotlb_init();
116890d5	130	}
8978b742	131
9f6ac577 FT	132	void dma_generic_alloc_coherent(struct device dev, size_t size,
	133	dma_addr_t *dma_addr, gfp_t flag)
	134	{
	135	unsigned long dma_mask;
	136	struct page *page;
	137	dma_addr_t addr;
	138
	139	dma_mask = dma_alloc_coherent_mask(dev, flag);
	140
	141	flag \|= __GFP_ZERO;
	142	again:
	143	page = alloc_pages_node(dev_to_node(dev), flag, get_order(size));
	144	if (!page)
	145	return NULL;
	146
	147	addr = page_to_phys(page);
	148	if (!is_buffer_dma_capable(dma_mask, addr, size)) {
	149	__free_pages(page, get_order(size));
	150
	151	if (dma_mask < DMA_32BIT_MASK && !(flag & GFP_DMA)) {
	152	flag = (flag & ~GFP_DMA32) \| GFP_DMA;
	153	goto again;
	154	}
	155
	156	return NULL;
	157	}
	158
	159	*dma_addr = addr;
	160	return page_address(page);
	161	}
	162
fae9a0d8 GC	163	/*
	164	* See <Documentation/x86_64/boot-options.txt> for the iommu kernel parameter
	165	* documentation.
	166	*/
	167	static __init int iommu_setup(char *p)
	168	{
	169	iommu_merge = 1;
	170
	171	if (!p)
	172	return -EINVAL;
	173
	174	while (*p) {
	175	if (!strncmp(p, "off", 3))
	176	no_iommu = 1;
	177	/* gart_parse_options has more force support */
	178	if (!strncmp(p, "force", 5))
	179	force_iommu = 1;
	180	if (!strncmp(p, "noforce", 7)) {
	181	iommu_merge = 0;
	182	force_iommu = 0;
	183	}
	184
	185	if (!strncmp(p, "biomerge", 8)) {
	186	iommu_bio_merge = 4096;
	187	iommu_merge = 1;
	188	force_iommu = 1;
	189	}
	190	if (!strncmp(p, "panic", 5))
	191	panic_on_overflow = 1;
	192	if (!strncmp(p, "nopanic", 7))
	193	panic_on_overflow = 0;
	194	if (!strncmp(p, "merge", 5)) {
	195	iommu_merge = 1;
	196	force_iommu = 1;
	197	}
	198	if (!strncmp(p, "nomerge", 7))
	199	iommu_merge = 0;
	200	if (!strncmp(p, "forcesac", 8))
	201	iommu_sac_force = 1;
	202	if (!strncmp(p, "allowdac", 8))
	203	forbid_dac = 0;
	204	if (!strncmp(p, "nodac", 5))
	205	forbid_dac = -1;
	206	if (!strncmp(p, "usedac", 6)) {
	207	forbid_dac = -1;
	208	return 1;
	209	}
	210	#ifdef CONFIG_SWIOTLB
	211	if (!strncmp(p, "soft", 4))
	212	swiotlb = 1;
	213	#endif
	214
fae9a0d8	215	gart_parse_options(p);
fae9a0d8 GC	216
	217	#ifdef CONFIG_CALGARY_IOMMU
	218	if (!strncmp(p, "calgary", 7))
	219	use_calgary = 1;
	220	#endif /* CONFIG_CALGARY_IOMMU */
	221
	222	p += strcspn(p, ",");
	223	if (*p == ',')
	224	++p;
	225	}
	226	return 0;
	227	}
	228	early_param("iommu", iommu_setup);
	229
8e0c3797 GC	230	int dma_supported(struct device *dev, u64 mask)
8e0c3797 GC	231	{
8d8bb39b FT	232	struct dma_mapping_ops *ops = get_dma_ops(dev);
8d8bb39b FT	233
8e0c3797 GC	234	#ifdef CONFIG_PCI
8e0c3797 GC	235	if (mask > 0xffffffff && forbid_dac > 0) {
fc3a8828	236	dev_info(dev, "PCI: Disallowing DAC for device\n");
8e0c3797 GC	237	return 0;
	238	}
	239	#endif
	240
8d8bb39b FT	241	if (ops->dma_supported)
8d8bb39b FT	242	return ops->dma_supported(dev, mask);
8e0c3797 GC	243
	244	/* Copied from i386. Doesn't make much sense, because it will
	245	only work for pci_alloc_coherent.
	246	The caller just has to use GFP_DMA in this case. */
	247	if (mask < DMA_24BIT_MASK)
	248	return 0;
	249
	250	/* Tell the device to use SAC when IOMMU force is on. This
	251	allows the driver to use cheaper accesses in some cases.
	252
	253	Problem with this is that if we overflow the IOMMU area and
	254	return DAC as fallback address the device may not handle it
	255	correctly.
	256
	257	As a special case some controllers have a 39bit address
	258	mode that is as efficient as 32bit (aic79xx). Don't force
	259	SAC for these. Assume all masks <= 40 bits are of this
	260	type. Normally this doesn't make any difference, but gives
	261	more gentle handling of IOMMU overflow. */
	262	if (iommu_sac_force && (mask >= DMA_40BIT_MASK)) {
fc3a8828	263	dev_info(dev, "Force SAC with mask %Lx\n", mask);
8e0c3797 GC	264	return 0;
	265	}
	266
	267	return 1;
	268	}
	269	EXPORT_SYMBOL(dma_supported);
	270
cb5867a5 GC	271	static int __init pci_iommu_init(void)
cb5867a5 GC	272	{
cb5867a5	273	calgary_iommu_init();
cb5867a5 GC	274
	275	intel_iommu_init();
	276
a69ca340 JR	277	amd_iommu_init();
a69ca340 JR	278
cb5867a5	279	gart_iommu_init();
459121c9	280
cb5867a5 GC	281	no_iommu_init();
	282	return 0;
	283	}
	284
	285	void pci_iommu_shutdown(void)
	286	{
	287	gart_iommu_shutdown();
	288	}
	289	/* Must execute after PCI subsystem */
	290	fs_initcall(pci_iommu_init);
3b15e581 FY	291
	292	#ifdef CONFIG_PCI
	293	/* Many VIA bridges seem to corrupt data for DAC. Disable it here */
	294
	295	static __devinit void via_no_dac(struct pci_dev *dev)
	296	{
	297	if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI && forbid_dac == 0) {
	298	printk(KERN_INFO "PCI: VIA PCI bridge detected."
	299	"Disabling DAC.\n");
	300	forbid_dac = 1;
	301	}
	302	}
	303	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_ANY_ID, via_no_dac);
	304	#endif