Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Dynamic DMA mapping support for AMD Hammer. | |
05fccb0e | 3 | * |
1da177e4 LT |
4 | * Use the integrated AGP GART in the Hammer northbridge as an IOMMU for PCI. |
5 | * This allows to use PCI devices that only support 32bit addresses on systems | |
05fccb0e | 6 | * with more than 4GB. |
1da177e4 | 7 | * |
5872fb94 | 8 | * See Documentation/PCI/PCI-DMA-mapping.txt for the interface specification. |
05fccb0e | 9 | * |
1da177e4 | 10 | * Copyright 2002 Andi Kleen, SuSE Labs. |
ff7f3649 | 11 | * Subject to the GNU General Public License v2 only. |
1da177e4 LT |
12 | */ |
13 | ||
1da177e4 LT |
14 | #include <linux/types.h> |
15 | #include <linux/ctype.h> | |
16 | #include <linux/agp_backend.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/mm.h> | |
19 | #include <linux/string.h> | |
20 | #include <linux/spinlock.h> | |
21 | #include <linux/pci.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/topology.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/bitops.h> | |
1eeb66a1 | 26 | #include <linux/kdebug.h> |
9ee1bea4 | 27 | #include <linux/scatterlist.h> |
fde9a109 | 28 | #include <linux/iommu-helper.h> |
cd76374e | 29 | #include <linux/sysdev.h> |
237a6224 | 30 | #include <linux/io.h> |
1da177e4 | 31 | #include <asm/atomic.h> |
1da177e4 LT |
32 | #include <asm/mtrr.h> |
33 | #include <asm/pgtable.h> | |
34 | #include <asm/proto.h> | |
46a7fa27 | 35 | #include <asm/iommu.h> |
395624fc | 36 | #include <asm/gart.h> |
1da177e4 | 37 | #include <asm/cacheflush.h> |
17a941d8 MBY |
38 | #include <asm/swiotlb.h> |
39 | #include <asm/dma.h> | |
a32073bf | 40 | #include <asm/k8.h> |
1da177e4 | 41 | |
79da0874 | 42 | static unsigned long iommu_bus_base; /* GART remapping area (physical) */ |
05fccb0e | 43 | static unsigned long iommu_size; /* size of remapping area bytes */ |
1da177e4 LT |
44 | static unsigned long iommu_pages; /* .. and in pages */ |
45 | ||
05fccb0e | 46 | static u32 *iommu_gatt_base; /* Remapping table */ |
1da177e4 | 47 | |
05fccb0e IM |
48 | /* |
49 | * If this is disabled the IOMMU will use an optimized flushing strategy | |
50 | * of only flushing when an mapping is reused. With it true the GART is | |
51 | * flushed for every mapping. Problem is that doing the lazy flush seems | |
52 | * to trigger bugs with some popular PCI cards, in particular 3ware (but | |
53 | * has been also also seen with Qlogic at least). | |
54 | */ | |
c854c919 | 55 | static int iommu_fullflush = 1; |
1da177e4 | 56 | |
05fccb0e | 57 | /* Allocation bitmap for the remapping area: */ |
1da177e4 | 58 | static DEFINE_SPINLOCK(iommu_bitmap_lock); |
05fccb0e IM |
59 | /* Guarded by iommu_bitmap_lock: */ |
60 | static unsigned long *iommu_gart_bitmap; | |
1da177e4 | 61 | |
05fccb0e | 62 | static u32 gart_unmapped_entry; |
1da177e4 LT |
63 | |
64 | #define GPTE_VALID 1 | |
65 | #define GPTE_COHERENT 2 | |
66 | #define GPTE_ENCODE(x) \ | |
67 | (((x) & 0xfffff000) | (((x) >> 32) << 4) | GPTE_VALID | GPTE_COHERENT) | |
68 | #define GPTE_DECODE(x) (((x) & 0xfffff000) | (((u64)(x) & 0xff0) << 28)) | |
69 | ||
05fccb0e | 70 | #define EMERGENCY_PAGES 32 /* = 128KB */ |
1da177e4 LT |
71 | |
72 | #ifdef CONFIG_AGP | |
73 | #define AGPEXTERN extern | |
74 | #else | |
75 | #define AGPEXTERN | |
76 | #endif | |
77 | ||
78 | /* backdoor interface to AGP driver */ | |
79 | AGPEXTERN int agp_memory_reserved; | |
80 | AGPEXTERN __u32 *agp_gatt_table; | |
81 | ||
82 | static unsigned long next_bit; /* protected by iommu_bitmap_lock */ | |
3610f211 | 83 | static bool need_flush; /* global flush state. set for each gart wrap */ |
1da177e4 | 84 | |
7b22ff53 FT |
85 | static unsigned long alloc_iommu(struct device *dev, int size, |
86 | unsigned long align_mask) | |
05fccb0e | 87 | { |
1da177e4 | 88 | unsigned long offset, flags; |
fde9a109 FT |
89 | unsigned long boundary_size; |
90 | unsigned long base_index; | |
91 | ||
92 | base_index = ALIGN(iommu_bus_base & dma_get_seg_boundary(dev), | |
93 | PAGE_SIZE) >> PAGE_SHIFT; | |
05d3ed0a | 94 | boundary_size = ALIGN((unsigned long long)dma_get_seg_boundary(dev) + 1, |
fde9a109 | 95 | PAGE_SIZE) >> PAGE_SHIFT; |
1da177e4 | 96 | |
05fccb0e | 97 | spin_lock_irqsave(&iommu_bitmap_lock, flags); |
fde9a109 | 98 | offset = iommu_area_alloc(iommu_gart_bitmap, iommu_pages, next_bit, |
7b22ff53 | 99 | size, base_index, boundary_size, align_mask); |
1da177e4 | 100 | if (offset == -1) { |
3610f211 | 101 | need_flush = true; |
fde9a109 | 102 | offset = iommu_area_alloc(iommu_gart_bitmap, iommu_pages, 0, |
7b22ff53 FT |
103 | size, base_index, boundary_size, |
104 | align_mask); | |
1da177e4 | 105 | } |
05fccb0e | 106 | if (offset != -1) { |
05fccb0e IM |
107 | next_bit = offset+size; |
108 | if (next_bit >= iommu_pages) { | |
1da177e4 | 109 | next_bit = 0; |
3610f211 | 110 | need_flush = true; |
05fccb0e IM |
111 | } |
112 | } | |
1da177e4 | 113 | if (iommu_fullflush) |
3610f211 | 114 | need_flush = true; |
05fccb0e IM |
115 | spin_unlock_irqrestore(&iommu_bitmap_lock, flags); |
116 | ||
1da177e4 | 117 | return offset; |
05fccb0e | 118 | } |
1da177e4 LT |
119 | |
120 | static void free_iommu(unsigned long offset, int size) | |
05fccb0e | 121 | { |
1da177e4 | 122 | unsigned long flags; |
05fccb0e | 123 | |
1da177e4 | 124 | spin_lock_irqsave(&iommu_bitmap_lock, flags); |
fde9a109 | 125 | iommu_area_free(iommu_gart_bitmap, offset, size); |
70d7d357 JR |
126 | if (offset >= next_bit) |
127 | next_bit = offset + size; | |
1da177e4 | 128 | spin_unlock_irqrestore(&iommu_bitmap_lock, flags); |
05fccb0e | 129 | } |
1da177e4 | 130 | |
05fccb0e | 131 | /* |
1da177e4 LT |
132 | * Use global flush state to avoid races with multiple flushers. |
133 | */ | |
a32073bf | 134 | static void flush_gart(void) |
05fccb0e | 135 | { |
1da177e4 | 136 | unsigned long flags; |
05fccb0e | 137 | |
1da177e4 | 138 | spin_lock_irqsave(&iommu_bitmap_lock, flags); |
a32073bf AK |
139 | if (need_flush) { |
140 | k8_flush_garts(); | |
3610f211 | 141 | need_flush = false; |
05fccb0e | 142 | } |
1da177e4 | 143 | spin_unlock_irqrestore(&iommu_bitmap_lock, flags); |
05fccb0e | 144 | } |
1da177e4 | 145 | |
1da177e4 | 146 | #ifdef CONFIG_IOMMU_LEAK |
1da177e4 | 147 | /* Debugging aid for drivers that don't free their IOMMU tables */ |
1da177e4 | 148 | static int leak_trace; |
79da0874 | 149 | static int iommu_leak_pages = 20; |
05fccb0e | 150 | |
79da0874 | 151 | static void dump_leak(void) |
1da177e4 | 152 | { |
05fccb0e IM |
153 | static int dump; |
154 | ||
19c1a6f5 | 155 | if (dump) |
05fccb0e | 156 | return; |
1da177e4 | 157 | dump = 1; |
05fccb0e | 158 | |
19c1a6f5 FT |
159 | show_stack(NULL, NULL); |
160 | debug_dma_dump_mappings(NULL); | |
1da177e4 | 161 | } |
1da177e4 LT |
162 | #endif |
163 | ||
17a941d8 | 164 | static void iommu_full(struct device *dev, size_t size, int dir) |
1da177e4 | 165 | { |
05fccb0e | 166 | /* |
1da177e4 LT |
167 | * Ran out of IOMMU space for this operation. This is very bad. |
168 | * Unfortunately the drivers cannot handle this operation properly. | |
05fccb0e | 169 | * Return some non mapped prereserved space in the aperture and |
1da177e4 LT |
170 | * let the Northbridge deal with it. This will result in garbage |
171 | * in the IO operation. When the size exceeds the prereserved space | |
05fccb0e | 172 | * memory corruption will occur or random memory will be DMAed |
1da177e4 | 173 | * out. Hopefully no network devices use single mappings that big. |
05fccb0e IM |
174 | */ |
175 | ||
fc3a8828 | 176 | dev_err(dev, "PCI-DMA: Out of IOMMU space for %lu bytes\n", size); |
1da177e4 | 177 | |
17a941d8 | 178 | if (size > PAGE_SIZE*EMERGENCY_PAGES) { |
1da177e4 LT |
179 | if (dir == PCI_DMA_FROMDEVICE || dir == PCI_DMA_BIDIRECTIONAL) |
180 | panic("PCI-DMA: Memory would be corrupted\n"); | |
05fccb0e IM |
181 | if (dir == PCI_DMA_TODEVICE || dir == PCI_DMA_BIDIRECTIONAL) |
182 | panic(KERN_ERR | |
183 | "PCI-DMA: Random memory would be DMAed\n"); | |
184 | } | |
1da177e4 | 185 | #ifdef CONFIG_IOMMU_LEAK |
05fccb0e | 186 | dump_leak(); |
1da177e4 | 187 | #endif |
05fccb0e | 188 | } |
1da177e4 | 189 | |
05fccb0e IM |
190 | static inline int |
191 | need_iommu(struct device *dev, unsigned long addr, size_t size) | |
192 | { | |
a4c2baa6 | 193 | return force_iommu || !dma_capable(dev, addr, size); |
1da177e4 LT |
194 | } |
195 | ||
05fccb0e IM |
196 | static inline int |
197 | nonforced_iommu(struct device *dev, unsigned long addr, size_t size) | |
198 | { | |
a4c2baa6 | 199 | return !dma_capable(dev, addr, size); |
1da177e4 LT |
200 | } |
201 | ||
202 | /* Map a single continuous physical area into the IOMMU. | |
203 | * Caller needs to check if the iommu is needed and flush. | |
204 | */ | |
17a941d8 | 205 | static dma_addr_t dma_map_area(struct device *dev, dma_addr_t phys_mem, |
7b22ff53 | 206 | size_t size, int dir, unsigned long align_mask) |
05fccb0e | 207 | { |
1477b8e5 | 208 | unsigned long npages = iommu_num_pages(phys_mem, size, PAGE_SIZE); |
7b22ff53 | 209 | unsigned long iommu_page = alloc_iommu(dev, npages, align_mask); |
1da177e4 | 210 | int i; |
05fccb0e | 211 | |
1da177e4 LT |
212 | if (iommu_page == -1) { |
213 | if (!nonforced_iommu(dev, phys_mem, size)) | |
05fccb0e | 214 | return phys_mem; |
1da177e4 LT |
215 | if (panic_on_overflow) |
216 | panic("dma_map_area overflow %lu bytes\n", size); | |
17a941d8 | 217 | iommu_full(dev, size, dir); |
1da177e4 LT |
218 | return bad_dma_address; |
219 | } | |
220 | ||
221 | for (i = 0; i < npages; i++) { | |
222 | iommu_gatt_base[iommu_page + i] = GPTE_ENCODE(phys_mem); | |
1da177e4 LT |
223 | phys_mem += PAGE_SIZE; |
224 | } | |
225 | return iommu_bus_base + iommu_page*PAGE_SIZE + (phys_mem & ~PAGE_MASK); | |
226 | } | |
227 | ||
228 | /* Map a single area into the IOMMU */ | |
052aedbf FT |
229 | static dma_addr_t gart_map_page(struct device *dev, struct page *page, |
230 | unsigned long offset, size_t size, | |
231 | enum dma_data_direction dir, | |
232 | struct dma_attrs *attrs) | |
1da177e4 | 233 | { |
2be62149 | 234 | unsigned long bus; |
052aedbf | 235 | phys_addr_t paddr = page_to_phys(page) + offset; |
1da177e4 | 236 | |
1da177e4 | 237 | if (!dev) |
6c505ce3 | 238 | dev = &x86_dma_fallback_dev; |
1da177e4 | 239 | |
2be62149 IM |
240 | if (!need_iommu(dev, paddr, size)) |
241 | return paddr; | |
1da177e4 | 242 | |
7b22ff53 FT |
243 | bus = dma_map_area(dev, paddr, size, dir, 0); |
244 | flush_gart(); | |
05fccb0e IM |
245 | |
246 | return bus; | |
17a941d8 MBY |
247 | } |
248 | ||
7c2d9cd2 JM |
249 | /* |
250 | * Free a DMA mapping. | |
251 | */ | |
052aedbf FT |
252 | static void gart_unmap_page(struct device *dev, dma_addr_t dma_addr, |
253 | size_t size, enum dma_data_direction dir, | |
254 | struct dma_attrs *attrs) | |
7c2d9cd2 JM |
255 | { |
256 | unsigned long iommu_page; | |
257 | int npages; | |
258 | int i; | |
259 | ||
260 | if (dma_addr < iommu_bus_base + EMERGENCY_PAGES*PAGE_SIZE || | |
261 | dma_addr >= iommu_bus_base + iommu_size) | |
262 | return; | |
05fccb0e | 263 | |
7c2d9cd2 | 264 | iommu_page = (dma_addr - iommu_bus_base)>>PAGE_SHIFT; |
1477b8e5 | 265 | npages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
7c2d9cd2 JM |
266 | for (i = 0; i < npages; i++) { |
267 | iommu_gatt_base[iommu_page + i] = gart_unmapped_entry; | |
7c2d9cd2 JM |
268 | } |
269 | free_iommu(iommu_page, npages); | |
270 | } | |
271 | ||
17a941d8 MBY |
272 | /* |
273 | * Wrapper for pci_unmap_single working with scatterlists. | |
274 | */ | |
160c1d8e FT |
275 | static void gart_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, |
276 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
17a941d8 | 277 | { |
9ee1bea4 | 278 | struct scatterlist *s; |
17a941d8 MBY |
279 | int i; |
280 | ||
9ee1bea4 | 281 | for_each_sg(sg, s, nents, i) { |
60b08c67 | 282 | if (!s->dma_length || !s->length) |
17a941d8 | 283 | break; |
d7dff840 | 284 | gart_unmap_page(dev, s->dma_address, s->dma_length, dir, NULL); |
17a941d8 MBY |
285 | } |
286 | } | |
1da177e4 LT |
287 | |
288 | /* Fallback for dma_map_sg in case of overflow */ | |
289 | static int dma_map_sg_nonforce(struct device *dev, struct scatterlist *sg, | |
290 | int nents, int dir) | |
291 | { | |
9ee1bea4 | 292 | struct scatterlist *s; |
1da177e4 LT |
293 | int i; |
294 | ||
295 | #ifdef CONFIG_IOMMU_DEBUG | |
296 | printk(KERN_DEBUG "dma_map_sg overflow\n"); | |
297 | #endif | |
298 | ||
9ee1bea4 | 299 | for_each_sg(sg, s, nents, i) { |
58b053e4 | 300 | unsigned long addr = sg_phys(s); |
05fccb0e IM |
301 | |
302 | if (nonforced_iommu(dev, addr, s->length)) { | |
7b22ff53 | 303 | addr = dma_map_area(dev, addr, s->length, dir, 0); |
05fccb0e IM |
304 | if (addr == bad_dma_address) { |
305 | if (i > 0) | |
160c1d8e | 306 | gart_unmap_sg(dev, sg, i, dir, NULL); |
05fccb0e | 307 | nents = 0; |
1da177e4 LT |
308 | sg[0].dma_length = 0; |
309 | break; | |
310 | } | |
311 | } | |
312 | s->dma_address = addr; | |
313 | s->dma_length = s->length; | |
314 | } | |
a32073bf | 315 | flush_gart(); |
05fccb0e | 316 | |
1da177e4 LT |
317 | return nents; |
318 | } | |
319 | ||
320 | /* Map multiple scatterlist entries continuous into the first. */ | |
fde9a109 FT |
321 | static int __dma_map_cont(struct device *dev, struct scatterlist *start, |
322 | int nelems, struct scatterlist *sout, | |
323 | unsigned long pages) | |
1da177e4 | 324 | { |
7b22ff53 | 325 | unsigned long iommu_start = alloc_iommu(dev, pages, 0); |
05fccb0e | 326 | unsigned long iommu_page = iommu_start; |
9ee1bea4 | 327 | struct scatterlist *s; |
1da177e4 LT |
328 | int i; |
329 | ||
330 | if (iommu_start == -1) | |
331 | return -1; | |
9ee1bea4 JA |
332 | |
333 | for_each_sg(start, s, nelems, i) { | |
1da177e4 LT |
334 | unsigned long pages, addr; |
335 | unsigned long phys_addr = s->dma_address; | |
05fccb0e | 336 | |
9ee1bea4 JA |
337 | BUG_ON(s != start && s->offset); |
338 | if (s == start) { | |
1da177e4 LT |
339 | sout->dma_address = iommu_bus_base; |
340 | sout->dma_address += iommu_page*PAGE_SIZE + s->offset; | |
341 | sout->dma_length = s->length; | |
05fccb0e IM |
342 | } else { |
343 | sout->dma_length += s->length; | |
1da177e4 LT |
344 | } |
345 | ||
346 | addr = phys_addr; | |
1477b8e5 | 347 | pages = iommu_num_pages(s->offset, s->length, PAGE_SIZE); |
05fccb0e IM |
348 | while (pages--) { |
349 | iommu_gatt_base[iommu_page] = GPTE_ENCODE(addr); | |
1da177e4 LT |
350 | addr += PAGE_SIZE; |
351 | iommu_page++; | |
0d541064 | 352 | } |
05fccb0e IM |
353 | } |
354 | BUG_ON(iommu_page - iommu_start != pages); | |
355 | ||
1da177e4 LT |
356 | return 0; |
357 | } | |
358 | ||
05fccb0e | 359 | static inline int |
fde9a109 FT |
360 | dma_map_cont(struct device *dev, struct scatterlist *start, int nelems, |
361 | struct scatterlist *sout, unsigned long pages, int need) | |
1da177e4 | 362 | { |
9ee1bea4 JA |
363 | if (!need) { |
364 | BUG_ON(nelems != 1); | |
e88a39de | 365 | sout->dma_address = start->dma_address; |
9ee1bea4 | 366 | sout->dma_length = start->length; |
1da177e4 | 367 | return 0; |
9ee1bea4 | 368 | } |
fde9a109 | 369 | return __dma_map_cont(dev, start, nelems, sout, pages); |
1da177e4 | 370 | } |
05fccb0e | 371 | |
1da177e4 LT |
372 | /* |
373 | * DMA map all entries in a scatterlist. | |
05fccb0e | 374 | * Merge chunks that have page aligned sizes into a continuous mapping. |
1da177e4 | 375 | */ |
160c1d8e FT |
376 | static int gart_map_sg(struct device *dev, struct scatterlist *sg, int nents, |
377 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
1da177e4 | 378 | { |
9ee1bea4 | 379 | struct scatterlist *s, *ps, *start_sg, *sgmap; |
05fccb0e IM |
380 | int need = 0, nextneed, i, out, start; |
381 | unsigned long pages = 0; | |
42d00284 FT |
382 | unsigned int seg_size; |
383 | unsigned int max_seg_size; | |
1da177e4 | 384 | |
05fccb0e | 385 | if (nents == 0) |
1da177e4 LT |
386 | return 0; |
387 | ||
1da177e4 | 388 | if (!dev) |
6c505ce3 | 389 | dev = &x86_dma_fallback_dev; |
1da177e4 LT |
390 | |
391 | out = 0; | |
392 | start = 0; | |
9ee1bea4 | 393 | start_sg = sgmap = sg; |
42d00284 FT |
394 | seg_size = 0; |
395 | max_seg_size = dma_get_max_seg_size(dev); | |
9ee1bea4 JA |
396 | ps = NULL; /* shut up gcc */ |
397 | for_each_sg(sg, s, nents, i) { | |
58b053e4 | 398 | dma_addr_t addr = sg_phys(s); |
05fccb0e | 399 | |
1da177e4 | 400 | s->dma_address = addr; |
05fccb0e | 401 | BUG_ON(s->length == 0); |
1da177e4 | 402 | |
05fccb0e | 403 | nextneed = need_iommu(dev, addr, s->length); |
1da177e4 LT |
404 | |
405 | /* Handle the previous not yet processed entries */ | |
406 | if (i > start) { | |
05fccb0e IM |
407 | /* |
408 | * Can only merge when the last chunk ends on a | |
409 | * page boundary and the new one doesn't have an | |
410 | * offset. | |
411 | */ | |
1da177e4 | 412 | if (!iommu_merge || !nextneed || !need || s->offset || |
42d00284 | 413 | (s->length + seg_size > max_seg_size) || |
9ee1bea4 | 414 | (ps->offset + ps->length) % PAGE_SIZE) { |
fde9a109 FT |
415 | if (dma_map_cont(dev, start_sg, i - start, |
416 | sgmap, pages, need) < 0) | |
1da177e4 LT |
417 | goto error; |
418 | out++; | |
42d00284 | 419 | seg_size = 0; |
9ee1bea4 | 420 | sgmap = sg_next(sgmap); |
1da177e4 | 421 | pages = 0; |
9ee1bea4 JA |
422 | start = i; |
423 | start_sg = s; | |
1da177e4 LT |
424 | } |
425 | } | |
426 | ||
42d00284 | 427 | seg_size += s->length; |
1da177e4 | 428 | need = nextneed; |
1477b8e5 | 429 | pages += iommu_num_pages(s->offset, s->length, PAGE_SIZE); |
9ee1bea4 | 430 | ps = s; |
1da177e4 | 431 | } |
fde9a109 | 432 | if (dma_map_cont(dev, start_sg, i - start, sgmap, pages, need) < 0) |
1da177e4 LT |
433 | goto error; |
434 | out++; | |
a32073bf | 435 | flush_gart(); |
9ee1bea4 JA |
436 | if (out < nents) { |
437 | sgmap = sg_next(sgmap); | |
438 | sgmap->dma_length = 0; | |
439 | } | |
1da177e4 LT |
440 | return out; |
441 | ||
442 | error: | |
a32073bf | 443 | flush_gart(); |
160c1d8e | 444 | gart_unmap_sg(dev, sg, out, dir, NULL); |
05fccb0e | 445 | |
a1002a48 KV |
446 | /* When it was forced or merged try again in a dumb way */ |
447 | if (force_iommu || iommu_merge) { | |
448 | out = dma_map_sg_nonforce(dev, sg, nents, dir); | |
449 | if (out > 0) | |
450 | return out; | |
451 | } | |
1da177e4 LT |
452 | if (panic_on_overflow) |
453 | panic("dma_map_sg: overflow on %lu pages\n", pages); | |
05fccb0e | 454 | |
17a941d8 | 455 | iommu_full(dev, pages << PAGE_SHIFT, dir); |
9ee1bea4 JA |
456 | for_each_sg(sg, s, nents, i) |
457 | s->dma_address = bad_dma_address; | |
1da177e4 | 458 | return 0; |
05fccb0e | 459 | } |
1da177e4 | 460 | |
94581094 JR |
461 | /* allocate and map a coherent mapping */ |
462 | static void * | |
463 | gart_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_addr, | |
464 | gfp_t flag) | |
465 | { | |
f6a32a36 | 466 | dma_addr_t paddr; |
421076e2 | 467 | unsigned long align_mask; |
1d990882 FT |
468 | struct page *page; |
469 | ||
470 | if (force_iommu && !(flag & GFP_DMA)) { | |
471 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
472 | page = alloc_pages(flag | __GFP_ZERO, get_order(size)); | |
473 | if (!page) | |
474 | return NULL; | |
475 | ||
476 | align_mask = (1UL << get_order(size)) - 1; | |
477 | paddr = dma_map_area(dev, page_to_phys(page), size, | |
478 | DMA_BIDIRECTIONAL, align_mask); | |
479 | ||
480 | flush_gart(); | |
481 | if (paddr != bad_dma_address) { | |
482 | *dma_addr = paddr; | |
483 | return page_address(page); | |
484 | } | |
485 | __free_pages(page, get_order(size)); | |
486 | } else | |
487 | return dma_generic_alloc_coherent(dev, size, dma_addr, flag); | |
94581094 JR |
488 | |
489 | return NULL; | |
490 | } | |
491 | ||
43a5a5a0 JR |
492 | /* free a coherent mapping */ |
493 | static void | |
494 | gart_free_coherent(struct device *dev, size_t size, void *vaddr, | |
495 | dma_addr_t dma_addr) | |
496 | { | |
d7dff840 | 497 | gart_unmap_page(dev, dma_addr, size, DMA_BIDIRECTIONAL, NULL); |
43a5a5a0 JR |
498 | free_pages((unsigned long)vaddr, get_order(size)); |
499 | } | |
500 | ||
17a941d8 | 501 | static int no_agp; |
1da177e4 LT |
502 | |
503 | static __init unsigned long check_iommu_size(unsigned long aper, u64 aper_size) | |
05fccb0e IM |
504 | { |
505 | unsigned long a; | |
506 | ||
507 | if (!iommu_size) { | |
508 | iommu_size = aper_size; | |
509 | if (!no_agp) | |
510 | iommu_size /= 2; | |
511 | } | |
512 | ||
513 | a = aper + iommu_size; | |
31422c51 | 514 | iommu_size -= round_up(a, PMD_PAGE_SIZE) - a; |
1da177e4 | 515 | |
05fccb0e | 516 | if (iommu_size < 64*1024*1024) { |
1da177e4 | 517 | printk(KERN_WARNING |
05fccb0e IM |
518 | "PCI-DMA: Warning: Small IOMMU %luMB." |
519 | " Consider increasing the AGP aperture in BIOS\n", | |
520 | iommu_size >> 20); | |
521 | } | |
522 | ||
1da177e4 | 523 | return iommu_size; |
05fccb0e | 524 | } |
1da177e4 | 525 | |
05fccb0e IM |
526 | static __init unsigned read_aperture(struct pci_dev *dev, u32 *size) |
527 | { | |
528 | unsigned aper_size = 0, aper_base_32, aper_order; | |
1da177e4 | 529 | u64 aper_base; |
1da177e4 | 530 | |
3bb6fbf9 PM |
531 | pci_read_config_dword(dev, AMD64_GARTAPERTUREBASE, &aper_base_32); |
532 | pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &aper_order); | |
05fccb0e | 533 | aper_order = (aper_order >> 1) & 7; |
1da177e4 | 534 | |
05fccb0e | 535 | aper_base = aper_base_32 & 0x7fff; |
1da177e4 LT |
536 | aper_base <<= 25; |
537 | ||
05fccb0e IM |
538 | aper_size = (32 * 1024 * 1024) << aper_order; |
539 | if (aper_base + aper_size > 0x100000000UL || !aper_size) | |
1da177e4 LT |
540 | aper_base = 0; |
541 | ||
542 | *size = aper_size; | |
543 | return aper_base; | |
05fccb0e | 544 | } |
1da177e4 | 545 | |
6703f6d1 RW |
546 | static void enable_gart_translations(void) |
547 | { | |
548 | int i; | |
549 | ||
550 | for (i = 0; i < num_k8_northbridges; i++) { | |
551 | struct pci_dev *dev = k8_northbridges[i]; | |
552 | ||
553 | enable_gart_translation(dev, __pa(agp_gatt_table)); | |
554 | } | |
555 | } | |
556 | ||
557 | /* | |
558 | * If fix_up_north_bridges is set, the north bridges have to be fixed up on | |
559 | * resume in the same way as they are handled in gart_iommu_hole_init(). | |
560 | */ | |
561 | static bool fix_up_north_bridges; | |
562 | static u32 aperture_order; | |
563 | static u32 aperture_alloc; | |
564 | ||
565 | void set_up_gart_resume(u32 aper_order, u32 aper_alloc) | |
566 | { | |
567 | fix_up_north_bridges = true; | |
568 | aperture_order = aper_order; | |
569 | aperture_alloc = aper_alloc; | |
570 | } | |
571 | ||
cd76374e PM |
572 | static int gart_resume(struct sys_device *dev) |
573 | { | |
6703f6d1 RW |
574 | printk(KERN_INFO "PCI-DMA: Resuming GART IOMMU\n"); |
575 | ||
576 | if (fix_up_north_bridges) { | |
577 | int i; | |
578 | ||
579 | printk(KERN_INFO "PCI-DMA: Restoring GART aperture settings\n"); | |
580 | ||
581 | for (i = 0; i < num_k8_northbridges; i++) { | |
582 | struct pci_dev *dev = k8_northbridges[i]; | |
583 | ||
584 | /* | |
585 | * Don't enable translations just yet. That is the next | |
586 | * step. Restore the pre-suspend aperture settings. | |
587 | */ | |
588 | pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, | |
589 | aperture_order << 1); | |
590 | pci_write_config_dword(dev, AMD64_GARTAPERTUREBASE, | |
591 | aperture_alloc >> 25); | |
592 | } | |
593 | } | |
594 | ||
595 | enable_gart_translations(); | |
596 | ||
cd76374e PM |
597 | return 0; |
598 | } | |
599 | ||
600 | static int gart_suspend(struct sys_device *dev, pm_message_t state) | |
601 | { | |
6703f6d1 | 602 | return 0; |
cd76374e PM |
603 | } |
604 | ||
605 | static struct sysdev_class gart_sysdev_class = { | |
606 | .name = "gart", | |
607 | .suspend = gart_suspend, | |
608 | .resume = gart_resume, | |
609 | ||
610 | }; | |
611 | ||
612 | static struct sys_device device_gart = { | |
613 | .id = 0, | |
614 | .cls = &gart_sysdev_class, | |
615 | }; | |
616 | ||
05fccb0e | 617 | /* |
1da177e4 | 618 | * Private Northbridge GATT initialization in case we cannot use the |
05fccb0e | 619 | * AGP driver for some reason. |
1da177e4 LT |
620 | */ |
621 | static __init int init_k8_gatt(struct agp_kern_info *info) | |
05fccb0e IM |
622 | { |
623 | unsigned aper_size, gatt_size, new_aper_size; | |
624 | unsigned aper_base, new_aper_base; | |
1da177e4 LT |
625 | struct pci_dev *dev; |
626 | void *gatt; | |
cd76374e | 627 | int i, error; |
a32073bf | 628 | |
1da177e4 LT |
629 | printk(KERN_INFO "PCI-DMA: Disabling AGP.\n"); |
630 | aper_size = aper_base = info->aper_size = 0; | |
a32073bf AK |
631 | dev = NULL; |
632 | for (i = 0; i < num_k8_northbridges; i++) { | |
633 | dev = k8_northbridges[i]; | |
05fccb0e IM |
634 | new_aper_base = read_aperture(dev, &new_aper_size); |
635 | if (!new_aper_base) | |
636 | goto nommu; | |
637 | ||
638 | if (!aper_base) { | |
1da177e4 LT |
639 | aper_size = new_aper_size; |
640 | aper_base = new_aper_base; | |
05fccb0e IM |
641 | } |
642 | if (aper_size != new_aper_size || aper_base != new_aper_base) | |
1da177e4 LT |
643 | goto nommu; |
644 | } | |
645 | if (!aper_base) | |
05fccb0e | 646 | goto nommu; |
1da177e4 | 647 | info->aper_base = aper_base; |
05fccb0e | 648 | info->aper_size = aper_size >> 20; |
1da177e4 | 649 | |
05fccb0e | 650 | gatt_size = (aper_size >> PAGE_SHIFT) * sizeof(u32); |
0114267b JR |
651 | gatt = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
652 | get_order(gatt_size)); | |
05fccb0e | 653 | if (!gatt) |
cf6387da | 654 | panic("Cannot allocate GATT table"); |
6d238cc4 | 655 | if (set_memory_uc((unsigned long)gatt, gatt_size >> PAGE_SHIFT)) |
cf6387da | 656 | panic("Could not set GART PTEs to uncacheable pages"); |
cf6387da | 657 | |
1da177e4 | 658 | agp_gatt_table = gatt; |
a32073bf | 659 | |
cd76374e PM |
660 | error = sysdev_class_register(&gart_sysdev_class); |
661 | if (!error) | |
662 | error = sysdev_register(&device_gart); | |
663 | if (error) | |
237a6224 JR |
664 | panic("Could not register gart_sysdev -- " |
665 | "would corrupt data on next suspend"); | |
6703f6d1 | 666 | |
a32073bf | 667 | flush_gart(); |
05fccb0e IM |
668 | |
669 | printk(KERN_INFO "PCI-DMA: aperture base @ %x size %u KB\n", | |
670 | aper_base, aper_size>>10); | |
7ab073b6 | 671 | |
1da177e4 LT |
672 | return 0; |
673 | ||
674 | nommu: | |
05fccb0e | 675 | /* Should not happen anymore */ |
8f59610d | 676 | printk(KERN_WARNING "PCI-DMA: More than 4GB of RAM and no IOMMU\n" |
ad361c98 | 677 | "falling back to iommu=soft.\n"); |
05fccb0e IM |
678 | return -1; |
679 | } | |
1da177e4 | 680 | |
160c1d8e | 681 | static struct dma_map_ops gart_dma_ops = { |
05fccb0e IM |
682 | .map_sg = gart_map_sg, |
683 | .unmap_sg = gart_unmap_sg, | |
052aedbf FT |
684 | .map_page = gart_map_page, |
685 | .unmap_page = gart_unmap_page, | |
94581094 | 686 | .alloc_coherent = gart_alloc_coherent, |
43a5a5a0 | 687 | .free_coherent = gart_free_coherent, |
17a941d8 MBY |
688 | }; |
689 | ||
bc2cea6a YL |
690 | void gart_iommu_shutdown(void) |
691 | { | |
692 | struct pci_dev *dev; | |
693 | int i; | |
694 | ||
695 | if (no_agp && (dma_ops != &gart_dma_ops)) | |
696 | return; | |
697 | ||
05fccb0e IM |
698 | for (i = 0; i < num_k8_northbridges; i++) { |
699 | u32 ctl; | |
bc2cea6a | 700 | |
05fccb0e | 701 | dev = k8_northbridges[i]; |
3bb6fbf9 | 702 | pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl); |
bc2cea6a | 703 | |
3bb6fbf9 | 704 | ctl &= ~GARTEN; |
bc2cea6a | 705 | |
3bb6fbf9 | 706 | pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl); |
05fccb0e | 707 | } |
bc2cea6a YL |
708 | } |
709 | ||
0dc243ae | 710 | void __init gart_iommu_init(void) |
05fccb0e | 711 | { |
1da177e4 | 712 | struct agp_kern_info info; |
1da177e4 | 713 | unsigned long iommu_start; |
d99e9016 YL |
714 | unsigned long aper_base, aper_size; |
715 | unsigned long start_pfn, end_pfn; | |
1da177e4 LT |
716 | unsigned long scratch; |
717 | long i; | |
718 | ||
55aab5f4 | 719 | if (cache_k8_northbridges() < 0 || num_k8_northbridges == 0) |
0dc243ae | 720 | return; |
a32073bf | 721 | |
1da177e4 | 722 | #ifndef CONFIG_AGP_AMD64 |
05fccb0e | 723 | no_agp = 1; |
1da177e4 LT |
724 | #else |
725 | /* Makefile puts PCI initialization via subsys_initcall first. */ | |
726 | /* Add other K8 AGP bridge drivers here */ | |
05fccb0e IM |
727 | no_agp = no_agp || |
728 | (agp_amd64_init() < 0) || | |
1da177e4 | 729 | (agp_copy_info(agp_bridge, &info) < 0); |
05fccb0e | 730 | #endif |
1da177e4 | 731 | |
60b08c67 | 732 | if (swiotlb) |
0dc243ae | 733 | return; |
60b08c67 | 734 | |
8d4f6b93 | 735 | /* Did we detect a different HW IOMMU? */ |
0440d4c0 | 736 | if (iommu_detected && !gart_iommu_aperture) |
0dc243ae | 737 | return; |
8d4f6b93 | 738 | |
1da177e4 | 739 | if (no_iommu || |
c987d12f | 740 | (!force_iommu && max_pfn <= MAX_DMA32_PFN) || |
0440d4c0 | 741 | !gart_iommu_aperture || |
1da177e4 | 742 | (no_agp && init_k8_gatt(&info) < 0)) { |
c987d12f | 743 | if (max_pfn > MAX_DMA32_PFN) { |
8f59610d | 744 | printk(KERN_WARNING "More than 4GB of memory " |
237a6224 JR |
745 | "but GART IOMMU not available.\n"); |
746 | printk(KERN_WARNING "falling back to iommu=soft.\n"); | |
5b7b644c | 747 | } |
0dc243ae | 748 | return; |
1da177e4 LT |
749 | } |
750 | ||
d99e9016 YL |
751 | /* need to map that range */ |
752 | aper_size = info.aper_size << 20; | |
753 | aper_base = info.aper_base; | |
754 | end_pfn = (aper_base>>PAGE_SHIFT) + (aper_size>>PAGE_SHIFT); | |
755 | if (end_pfn > max_low_pfn_mapped) { | |
756 | start_pfn = (aper_base>>PAGE_SHIFT); | |
757 | init_memory_mapping(start_pfn<<PAGE_SHIFT, end_pfn<<PAGE_SHIFT); | |
758 | } | |
759 | ||
5b7b644c | 760 | printk(KERN_INFO "PCI-DMA: using GART IOMMU.\n"); |
05fccb0e IM |
761 | iommu_size = check_iommu_size(info.aper_base, aper_size); |
762 | iommu_pages = iommu_size >> PAGE_SHIFT; | |
763 | ||
0114267b | 764 | iommu_gart_bitmap = (void *) __get_free_pages(GFP_KERNEL | __GFP_ZERO, |
05fccb0e IM |
765 | get_order(iommu_pages/8)); |
766 | if (!iommu_gart_bitmap) | |
767 | panic("Cannot allocate iommu bitmap\n"); | |
1da177e4 LT |
768 | |
769 | #ifdef CONFIG_IOMMU_LEAK | |
05fccb0e | 770 | if (leak_trace) { |
19c1a6f5 FT |
771 | int ret; |
772 | ||
773 | ret = dma_debug_resize_entries(iommu_pages); | |
774 | if (ret) | |
05fccb0e | 775 | printk(KERN_DEBUG |
19c1a6f5 | 776 | "PCI-DMA: Cannot trace all the entries\n"); |
05fccb0e | 777 | } |
1da177e4 LT |
778 | #endif |
779 | ||
05fccb0e | 780 | /* |
1da177e4 | 781 | * Out of IOMMU space handling. |
05fccb0e IM |
782 | * Reserve some invalid pages at the beginning of the GART. |
783 | */ | |
d26dbc5c | 784 | iommu_area_reserve(iommu_gart_bitmap, 0, EMERGENCY_PAGES); |
1da177e4 | 785 | |
05fccb0e | 786 | agp_memory_reserved = iommu_size; |
1da177e4 LT |
787 | printk(KERN_INFO |
788 | "PCI-DMA: Reserving %luMB of IOMMU area in the AGP aperture\n", | |
05fccb0e | 789 | iommu_size >> 20); |
1da177e4 | 790 | |
05fccb0e IM |
791 | iommu_start = aper_size - iommu_size; |
792 | iommu_bus_base = info.aper_base + iommu_start; | |
1da177e4 LT |
793 | bad_dma_address = iommu_bus_base; |
794 | iommu_gatt_base = agp_gatt_table + (iommu_start>>PAGE_SHIFT); | |
795 | ||
05fccb0e | 796 | /* |
1da177e4 LT |
797 | * Unmap the IOMMU part of the GART. The alias of the page is |
798 | * always mapped with cache enabled and there is no full cache | |
799 | * coherency across the GART remapping. The unmapping avoids | |
800 | * automatic prefetches from the CPU allocating cache lines in | |
801 | * there. All CPU accesses are done via the direct mapping to | |
802 | * the backing memory. The GART address is only used by PCI | |
05fccb0e | 803 | * devices. |
1da177e4 | 804 | */ |
28d6ee41 AK |
805 | set_memory_np((unsigned long)__va(iommu_bus_base), |
806 | iommu_size >> PAGE_SHIFT); | |
184652eb IM |
807 | /* |
808 | * Tricky. The GART table remaps the physical memory range, | |
809 | * so the CPU wont notice potential aliases and if the memory | |
810 | * is remapped to UC later on, we might surprise the PCI devices | |
811 | * with a stray writeout of a cacheline. So play it sure and | |
812 | * do an explicit, full-scale wbinvd() _after_ having marked all | |
813 | * the pages as Not-Present: | |
814 | */ | |
815 | wbinvd(); | |
fe2245c9 ML |
816 | |
817 | /* | |
818 | * Now all caches are flushed and we can safely enable | |
819 | * GART hardware. Doing it early leaves the possibility | |
820 | * of stale cache entries that can lead to GART PTE | |
821 | * errors. | |
822 | */ | |
823 | enable_gart_translations(); | |
1da177e4 | 824 | |
05fccb0e | 825 | /* |
fa3d319a | 826 | * Try to workaround a bug (thanks to BenH): |
05fccb0e | 827 | * Set unmapped entries to a scratch page instead of 0. |
1da177e4 | 828 | * Any prefetches that hit unmapped entries won't get an bus abort |
fa3d319a | 829 | * then. (P2P bridge may be prefetching on DMA reads). |
1da177e4 | 830 | */ |
05fccb0e IM |
831 | scratch = get_zeroed_page(GFP_KERNEL); |
832 | if (!scratch) | |
1da177e4 LT |
833 | panic("Cannot allocate iommu scratch page"); |
834 | gart_unmapped_entry = GPTE_ENCODE(__pa(scratch)); | |
05fccb0e | 835 | for (i = EMERGENCY_PAGES; i < iommu_pages; i++) |
1da177e4 LT |
836 | iommu_gatt_base[i] = gart_unmapped_entry; |
837 | ||
a32073bf | 838 | flush_gart(); |
17a941d8 | 839 | dma_ops = &gart_dma_ops; |
05fccb0e | 840 | } |
1da177e4 | 841 | |
43999d9e | 842 | void __init gart_parse_options(char *p) |
17a941d8 MBY |
843 | { |
844 | int arg; | |
845 | ||
1da177e4 | 846 | #ifdef CONFIG_IOMMU_LEAK |
05fccb0e | 847 | if (!strncmp(p, "leak", 4)) { |
17a941d8 MBY |
848 | leak_trace = 1; |
849 | p += 4; | |
237a6224 JR |
850 | if (*p == '=') |
851 | ++p; | |
17a941d8 MBY |
852 | if (isdigit(*p) && get_option(&p, &arg)) |
853 | iommu_leak_pages = arg; | |
854 | } | |
1da177e4 | 855 | #endif |
17a941d8 MBY |
856 | if (isdigit(*p) && get_option(&p, &arg)) |
857 | iommu_size = arg; | |
05fccb0e | 858 | if (!strncmp(p, "fullflush", 8)) |
17a941d8 | 859 | iommu_fullflush = 1; |
05fccb0e | 860 | if (!strncmp(p, "nofullflush", 11)) |
17a941d8 | 861 | iommu_fullflush = 0; |
05fccb0e | 862 | if (!strncmp(p, "noagp", 5)) |
17a941d8 | 863 | no_agp = 1; |
05fccb0e | 864 | if (!strncmp(p, "noaperture", 10)) |
17a941d8 MBY |
865 | fix_aperture = 0; |
866 | /* duplicated from pci-dma.c */ | |
05fccb0e | 867 | if (!strncmp(p, "force", 5)) |
0440d4c0 | 868 | gart_iommu_aperture_allowed = 1; |
05fccb0e | 869 | if (!strncmp(p, "allowed", 7)) |
0440d4c0 | 870 | gart_iommu_aperture_allowed = 1; |
17a941d8 MBY |
871 | if (!strncmp(p, "memaper", 7)) { |
872 | fallback_aper_force = 1; | |
873 | p += 7; | |
874 | if (*p == '=') { | |
875 | ++p; | |
876 | if (get_option(&p, &arg)) | |
877 | fallback_aper_order = arg; | |
878 | } | |
879 | } | |
880 | } |